From db533523c0538da25983f4f1decf614a5096af76 Mon Sep 17 00:00:00 2001 From: Divya Singhatwaria Date: Tue, 11 Dec 2018 14:20:35 +0530 Subject: [PATCH] gpu: nvgpu: fix MISRA Rule 16.x violations in pmu MISRA Rule 16.4 emphasizes on having a non-empty default label for every switch case MISRA Rule 16.6 emphasizes that every switch statement shall have atleast two switch-clauses JIRA NVGPU-1545 JIRA NVGPU-1557 Change-Id: I2d124ac0d66d8c490c59d262ddc647045d455633 Signed-off-by: Divya Singhatwaria Reviewed-on: https://git-master.nvidia.com/r/1970216 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/common/pmu/pmu_perfmon.c | 2 ++ drivers/gpu/nvgpu/common/pmu/pmu_pg.c | 3 +++ drivers/gpu/nvgpu/lpwr/rppg.c | 13 ++++++++++--- 3 files changed, 15 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/nvgpu/common/pmu/pmu_perfmon.c b/drivers/gpu/nvgpu/common/pmu/pmu_perfmon.c index 742d6b426..b1450b69b 100644 --- a/drivers/gpu/nvgpu/common/pmu/pmu_perfmon.c +++ b/drivers/gpu/nvgpu/common/pmu/pmu_perfmon.c @@ -326,6 +326,8 @@ int nvgpu_pmu_handle_perfmon_event(struct nvgpu_pmu *pmu, nvgpu_pmu_dbg(g, "perfmon init event"); break; default: + nvgpu_pmu_dbg(g, "Invalid msgtype:%u for %s", + msg->msg_type, __func__); break; } diff --git a/drivers/gpu/nvgpu/common/pmu/pmu_pg.c b/drivers/gpu/nvgpu/common/pmu/pmu_pg.c index 535090c1e..1d66af1c8 100644 --- a/drivers/gpu/nvgpu/common/pmu/pmu_pg.c +++ b/drivers/gpu/nvgpu/common/pmu/pmu_pg.c @@ -387,6 +387,8 @@ static void pmu_handle_pg_stat_msg(struct gk20a *g, struct pmu_msg *msg, msg->msg.pg.stat.data; break; default: + nvgpu_err(g, "Invalid msg id:%u", + msg->msg.pg.stat.sub_msg_id); break; } } @@ -788,6 +790,7 @@ int nvgpu_aelpg_init_and_enable(struct gk20a *g, u8 ctrl_id) case PMU_AP_CTRL_ID_GRAPHICS: break; default: + nvgpu_err(g, "Invalid ctrl_id:%u for %s", ctrl_id, __func__); break; } diff --git a/drivers/gpu/nvgpu/lpwr/rppg.c b/drivers/gpu/nvgpu/lpwr/rppg.c index 02da21507..c58e5a0e7 100644 --- a/drivers/gpu/nvgpu/lpwr/rppg.c +++ b/drivers/gpu/nvgpu/lpwr/rppg.c @@ -39,11 +39,13 @@ static void pmu_handle_rppg_init_msg(struct gk20a *g, struct pmu_msg *msg, nvgpu_pmu_dbg(g, "RPPG is acknowledged from PMU %x", msg->msg.pg.msg_type); break; + default: + *success = 0; + nvgpu_err(g, "Invalid message ID:%u", + msg->msg.pg.rppg_msg.cmn.msg_id); + break; } } - - nvgpu_pmu_dbg(g, "RPPG is acknowledged from PMU %x", - msg->msg.pg.msg_type); } static int rppg_send_cmd(struct gk20a *g, struct nv_pmu_rppg_cmd *prppg_cmd) @@ -120,9 +122,14 @@ static int rppg_ctrl_init(struct gk20a *g, u8 ctrl_id) switch (ctrl_id) { case NV_PMU_RPPG_CTRL_ID_GR: + rppg_cmd.init_ctrl.domain_id = NV_PMU_RPPG_DOMAIN_ID_GFX; + break; case NV_PMU_RPPG_CTRL_ID_MS: rppg_cmd.init_ctrl.domain_id = NV_PMU_RPPG_DOMAIN_ID_GFX; break; + default: + nvgpu_err(g, "Invalid ctrl_id %u for %s", ctrl_id, __func__); + break; } return rppg_send_cmd(g, &rppg_cmd);