From db8522874886b270805f4640693d8943a6b0ec5a Mon Sep 17 00:00:00 2001 From: Mahantesh Kumbar Date: Mon, 8 Oct 2018 14:17:31 +0530 Subject: [PATCH] gpu: nvgpu: boardobj volt device IPC_VMIN support -Add support for volt device OPERATION_TYPE_IPC_VMIN support -Added defines required for ipc vmin operation support -Modified volt_get_voltage_device_table_1x_psv() to add check to support IPC_VMIN & assign pwm source based on operation type. JIRA NVGPU-1156 Change-Id: Ia168669ea6b5896916747fccde8c6a52c271c4e3 Signed-off-by: Mahantesh Kumbar Reviewed-on: https://git-master.nvidia.com/r/1921395 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/ctrl/ctrlvolt.h | 2 ++ drivers/gpu/nvgpu/include/nvgpu/bios.h | 2 ++ drivers/gpu/nvgpu/volt/volt_dev.c | 21 ++++++++++++++++++++- drivers/gpu/nvgpu/volt/volt_rail.c | 1 + 4 files changed, 25 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/nvgpu/ctrl/ctrlvolt.h b/drivers/gpu/nvgpu/ctrl/ctrlvolt.h index 84994eb69..633bff1ad 100644 --- a/drivers/gpu/nvgpu/ctrl/ctrlvolt.h +++ b/drivers/gpu/nvgpu/ctrl/ctrlvolt.h @@ -74,6 +74,8 @@ enum nv_pmu_pmgr_pwm_source { NV_PMU_PMGR_PWM_SOURCE_THERM_VID_PWM_1, NV_PMU_PMGR_PWM_SOURCE_RSVD_0 = 7, NV_PMU_PMGR_PWM_SOURCE_RSVD_1 = 8, + NV_PMU_PMGR_PWM_SOURCE_THERM_IPC_VMIN_VID_PWM_0 = 11U, + NV_PMU_PMGR_PWM_SOURCE_THERM_IPC_VMIN_VID_PWM_1 = 12U, }; /*! diff --git a/drivers/gpu/nvgpu/include/nvgpu/bios.h b/drivers/gpu/nvgpu/include/nvgpu/bios.h index de8916781..bcc15a715 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/bios.h +++ b/drivers/gpu/nvgpu/include/nvgpu/bios.h @@ -858,6 +858,8 @@ struct vbios_voltage_device_table_1x_entry { 0x01 #define NV_VBIOS_VDT_1X_ENTRY_PARAM1_PSV_OPERATION_TYPE_LPWR_SLEEP_STATE \ 0x02 +#define NV_VBIOS_VDT_1X_ENTRY_PARAM1_PSV_OPERATION_TYPE_IPC_VMIN \ + 0x03U #define NV_VBIOS_VDT_1X_ENTRY_PARAM2_PSV_VOLTAGE_MAXIMUM_MASK \ GENMASK(23, 0) #define NV_VBIOS_VDT_1X_ENTRY_PARAM2_PSV_VOLTAGE_MAXIMUM_SHIFT 0 diff --git a/drivers/gpu/nvgpu/volt/volt_dev.c b/drivers/gpu/nvgpu/volt/volt_dev.c index 750588280..c8f763a9d 100644 --- a/drivers/gpu/nvgpu/volt/volt_dev.c +++ b/drivers/gpu/nvgpu/volt/volt_dev.c @@ -176,6 +176,8 @@ static u8 volt_dev_operation_type_convert(u8 vbios_type) case NV_VBIOS_VDT_1X_ENTRY_PARAM1_PSV_OPERATION_TYPE_LPWR_SLEEP_STATE: return CTRL_VOLT_DEVICE_OPERATION_TYPE_LPWR_SLEEP_STATE; + case NV_VBIOS_VDT_1X_ENTRY_PARAM1_PSV_OPERATION_TYPE_IPC_VMIN: + return CTRL_VOLT_VOLT_DEVICE_OPERATION_TYPE_IPC_VMIN; } return CTRL_VOLT_DEVICE_OPERATION_TYPE_INVALID; @@ -272,7 +274,9 @@ static int volt_get_voltage_device_table_1x_psv(struct gk20a *g, } if (ptmp_dev->super.operation_type == - CTRL_VOLT_DEVICE_OPERATION_TYPE_DEFAULT) { + CTRL_VOLT_DEVICE_OPERATION_TYPE_DEFAULT || + ptmp_dev->super.operation_type == + CTRL_VOLT_VOLT_DEVICE_OPERATION_TYPE_IPC_VMIN) { if (volt_domain == CTRL_VOLT_DOMAIN_LOGIC) { ptmp_dev->source = NV_PMU_PMGR_PWM_SOURCE_THERM_VID_PWM_0; @@ -281,6 +285,21 @@ static int volt_get_voltage_device_table_1x_psv(struct gk20a *g, ptmp_dev->source = NV_PMU_PMGR_PWM_SOURCE_THERM_VID_PWM_1; } + + if (ptmp_dev->super.operation_type == + CTRL_VOLT_VOLT_DEVICE_OPERATION_TYPE_IPC_VMIN) { + if (ptmp_dev->source == + NV_PMU_PMGR_PWM_SOURCE_THERM_VID_PWM_0) { + ptmp_dev->source = + NV_PMU_PMGR_PWM_SOURCE_THERM_IPC_VMIN_VID_PWM_0; + } + + if (ptmp_dev->source == + NV_PMU_PMGR_PWM_SOURCE_THERM_VID_PWM_1) { + ptmp_dev->source = + NV_PMU_PMGR_PWM_SOURCE_THERM_IPC_VMIN_VID_PWM_1; + } + } ptmp_dev->raw_period = g->ops.clk.get_crystal_clk_hz(g) / frequency_hz; } else if (ptmp_dev->super.operation_type == diff --git a/drivers/gpu/nvgpu/volt/volt_rail.c b/drivers/gpu/nvgpu/volt/volt_rail.c index c81572de1..b62d9a613 100644 --- a/drivers/gpu/nvgpu/volt/volt_rail.c +++ b/drivers/gpu/nvgpu/volt/volt_rail.c @@ -104,6 +104,7 @@ static u32 volt_rail_state_init(struct gk20a *g, u32 i; pvolt_rail->volt_dev_idx_default = CTRL_BOARDOBJ_IDX_INVALID; + pvolt_rail->volt_dev_idx_ipc_vmin = CTRL_BOARDOBJ_IDX_INVALID; for (i = 0; i < CTRL_VOLT_RAIL_VOLT_DELTA_MAX_ENTRIES; i++) { pvolt_rail->volt_delta_uv[i] = (int)NV_PMU_VOLT_VALUE_0V_IN_UV;