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synced 2025-12-22 17:36:20 +03:00
gpu: nvgpu: use instance specific max subctx count
Store nvgpu_cdev pointer in struct tsg_private and assign it in nvgpu_ioctl_tsg_open. In gk20a_tsg_ioctl_bind_channel_ex(), extract gpu_instance_id from cdev pointer and then extract instance specific max VEID count from gpu_instance_id. Use this max veid count to validate subcontext id coming from user. Jira NVGPU-5648 Change-Id: I71cea5180e1ced1a72818d160f1a951c1c6ec770 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2438925 Reviewed-by: automaticguardword <automaticguardword@nvidia.com> Reviewed-by: Lakshmanan M <lm@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com> GVS: Gerrit_Virtual_Submit
This commit is contained in:
committed by
Alex Waterman
parent
dacdaf0778
commit
dbad874d9e
@@ -639,7 +639,7 @@ clean_up:
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return err;
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}
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static int gk20a_ctrl_open_tsg(struct gk20a *g,
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static int gk20a_ctrl_open_tsg(struct gk20a *g, struct nvgpu_cdev *cdev,
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struct nvgpu_gpu_open_tsg_args *args)
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{
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int err;
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@@ -660,7 +660,7 @@ static int gk20a_ctrl_open_tsg(struct gk20a *g,
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goto clean_up;
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}
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err = nvgpu_ioctl_tsg_open(g, file);
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err = nvgpu_ioctl_tsg_open(g, cdev, file);
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if (err)
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goto clean_up_file;
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@@ -2047,7 +2047,7 @@ long gk20a_ctrl_dev_ioctl(struct file *filp, unsigned int cmd, unsigned long arg
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(struct nvgpu_alloc_as_args *)buf);
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break;
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case NVGPU_GPU_IOCTL_OPEN_TSG:
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err = gk20a_ctrl_open_tsg(g,
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err = gk20a_ctrl_open_tsg(g, priv->cdev,
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(struct nvgpu_gpu_open_tsg_args *)buf);
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break;
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case NVGPU_GPU_IOCTL_GET_TPC_MASKS:
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@@ -33,6 +33,7 @@
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#include <nvgpu/tsg.h>
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#include <nvgpu/fifo.h>
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#include <nvgpu/nvgpu_init.h>
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#include <nvgpu/grmgr.h>
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#include "platform_gk20a.h"
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#include "ioctl_tsg.h"
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@@ -43,6 +44,7 @@
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struct tsg_private {
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struct gk20a *g;
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struct nvgpu_tsg *tsg;
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struct nvgpu_cdev *cdev;
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};
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extern const struct file_operations gk20a_tsg_ops;
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@@ -84,11 +86,14 @@ static int nvgpu_tsg_bind_channel_fd(struct nvgpu_tsg *tsg, int ch_fd)
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}
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static int gk20a_tsg_ioctl_bind_channel_ex(struct gk20a *g,
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struct nvgpu_tsg *tsg, struct nvgpu_tsg_bind_channel_ex_args *arg)
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struct tsg_private *priv, struct nvgpu_tsg_bind_channel_ex_args *arg)
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{
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struct nvgpu_tsg *tsg = priv->tsg;
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struct nvgpu_sched_ctrl *sched = &g->sched_ctrl;
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struct nvgpu_channel *ch;
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struct nvgpu_gr_config *gr_config = nvgpu_gr_get_config_ptr(g);
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u32 max_subctx_count;
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u32 gpu_instance_id;
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int err = 0;
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nvgpu_log(g, gpu_dbg_fn | gpu_dbg_sched, "tsgid=%u", tsg->tsgid);
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@@ -125,7 +130,12 @@ static int gk20a_tsg_ioctl_bind_channel_ex(struct gk20a *g,
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tsg->tpc_pg_enabled = false; nvgpu_log(g, gpu_dbg_info, "dynamic TPC-PG not enabled");
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}
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if (arg->subcontext_id < g->fifo.max_subctx_count) {
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gpu_instance_id = nvgpu_get_gpu_instance_id_from_cdev(g, priv->cdev);
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nvgpu_assert(gpu_instance_id < g->mig.num_gpu_instances);
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max_subctx_count = nvgpu_grmgr_get_gpu_instance_max_veid_count(g, gpu_instance_id);
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if (arg->subcontext_id < max_subctx_count) {
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ch->subctx_id = arg->subcontext_id;
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} else {
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err = -EINVAL;
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@@ -416,7 +426,8 @@ static int gk20a_tsg_event_id_ctrl(struct gk20a *g, struct nvgpu_tsg *tsg,
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}
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#endif /* CONFIG_NVGPU_CHANNEL_TSG_CONTROL */
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int nvgpu_ioctl_tsg_open(struct gk20a *g, struct file *filp)
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int nvgpu_ioctl_tsg_open(struct gk20a *g, struct nvgpu_cdev *cdev,
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struct file *filp)
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{
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struct tsg_private *priv;
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struct nvgpu_tsg *tsg;
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@@ -452,6 +463,7 @@ int nvgpu_ioctl_tsg_open(struct gk20a *g, struct file *filp)
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priv->g = g;
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priv->tsg = tsg;
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priv->cdev = cdev;
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filp->private_data = priv;
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gk20a_sched_ctrl_tsg_added(g, tsg);
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@@ -482,7 +494,7 @@ int nvgpu_ioctl_tsg_dev_open(struct inode *inode, struct file *filp)
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return ret;
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}
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ret = nvgpu_ioctl_tsg_open(g, filp);
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ret = nvgpu_ioctl_tsg_open(g, cdev, filp);
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gk20a_idle(g);
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nvgpu_log_fn(g, "done");
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@@ -675,7 +687,7 @@ long nvgpu_ioctl_tsg_dev_ioctl(struct file *filp, unsigned int cmd,
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case NVGPU_TSG_IOCTL_BIND_CHANNEL_EX:
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{
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err = gk20a_tsg_ioctl_bind_channel_ex(g, tsg,
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err = gk20a_tsg_ioctl_bind_channel_ex(g, priv,
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(struct nvgpu_tsg_bind_channel_ex_args *)buf);
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break;
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}
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@@ -17,12 +17,13 @@ struct inode;
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struct file;
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struct gk20a;
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struct nvgpu_ref;
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struct nvgpu_cdev;
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struct nvgpu_tsg *nvgpu_tsg_get_from_file(int fd);
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int nvgpu_ioctl_tsg_dev_release(struct inode *inode, struct file *filp);
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int nvgpu_ioctl_tsg_dev_open(struct inode *inode, struct file *filp);
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int nvgpu_ioctl_tsg_open(struct gk20a *g, struct file *filp);
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int nvgpu_ioctl_tsg_open(struct gk20a *g, struct nvgpu_cdev *cdev, struct file *filp);
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long nvgpu_ioctl_tsg_dev_ioctl(struct file *filp,
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unsigned int cmd, unsigned long arg);
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void nvgpu_ioctl_tsg_release(struct nvgpu_ref *ref);
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