gpu: nvgpu: move engine_status_dump functions to common.fifo.hal.engine_status

The functions gk20a_dump_eng_status and gv11b_dump_eng_status belongs
to engine_status HAL unit.

1) The corresponding declaration and definitions of the above functions
are moved from fifo_{arch} files to engine_status_{arch} files.

2) The corresponding HAL pointer .dump_eng_status is moved from
fifo to engine_status HAL unit.

3) gv11b_dump_eng_status is now based to gv100b_dump_eng_status

4) Small changes in the files for ENGINE_STATUS such as correction of
HEADER DEFINES etc

Jira NVGPU-1315

Change-Id: I7fc06eab97206bc3b78c6f5c7aa30fa2c034961c
Signed-off-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2033632
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

drivers/gpu/nvgpu/common/fifo/engine_status_gm20b.c

@@ -21,12 +21,14 @@
  */
 
 #include <nvgpu/io.h>
+#include <nvgpu/debug.h>
 #include <nvgpu/gk20a.h>
 #include <nvgpu/engine_status.h>
 
 #include <nvgpu/hw/gm20b/hw_fifo_gm20b.h>
 
 #include "engine_status_gm20b.h"
+#include "gk20a/fifo_gk20a.h"
 
 static void populate_invalid_ctxsw_status_info(
 		struct nvgpu_engine_status_info *status_info)
@@ -165,3 +167,41 @@ void gm20b_read_engine_status_info(struct gk20a *g, u32 engine_id,
 		populate_invalid_ctxsw_status_info(status);
 	}
 }
+
+void gm20b_dump_engine_status(struct gk20a *g, struct gk20a_debug_output *o)
+{
+	u32 i, host_num_engines;
+	struct nvgpu_engine_status_info engine_status;
+
+	host_num_engines = nvgpu_get_litter_value(g, GPU_LIT_HOST_NUM_ENGINES);
+
+	gk20a_debug_output(o, "Engine status - chip %-5s", g->name);
+	gk20a_debug_output(o, "--------------------------");
+
+	for (i = 0; i < host_num_engines; i++) {
+		g->ops.engine_status.read_engine_status_info(g, i, &engine_status);
+
+		gk20a_debug_output(o,
+			"Engine %d | "
+			"ID: %d - %-9s next_id: %d %-9s | status: %s",
+			i,
+			engine_status.ctx_id,
+			nvgpu_engine_status_is_ctx_type_tsg(
+				&engine_status) ?
+				"[tsg]" : "[channel]",
+			engine_status.ctx_next_id,
+			nvgpu_engine_status_is_next_ctx_type_tsg(
+				&engine_status) ?
+				"[tsg]" : "[channel]",
+			gk20a_decode_pbdma_chan_eng_ctx_status(
+				engine_status.ctxsw_state));
+
+		if (engine_status.is_faulted) {
+			gk20a_debug_output(o, "  State: faulted");
+		}
+		if (engine_status.is_busy) {
+			gk20a_debug_output(o, "  State: busy");
+		}
+	}
+	gk20a_debug_output(o, "\n");
+}

drivers/gpu/nvgpu/common/fifo/engine_status_gm20b.h

@@ -20,15 +20,18 @@
  * DEALINGS IN THE SOFTWARE.
  */
 
-#ifndef NVGPU_ENGINE_STATUS_GM20B
+#ifndef NVGPU_ENGINE_STATUS_GM20B_H
-#define NVGPU_ENGINE_STATUS_GM20B
+#define NVGPU_ENGINE_STATUS_GM20B_H
 
 #include <nvgpu/types.h>
 
 struct gk20a;
 struct nvgpu_engine_status_info;
+struct gk20a_debug_output;
 
 void gm20b_read_engine_status_info(struct gk20a *g, u32 engine_id,
 		struct nvgpu_engine_status_info *status);
 
-#endif /* NVGPU_ENGINE_STATUS_GM20B */
+void gm20b_dump_engine_status(struct gk20a *g, struct gk20a_debug_output *o);
+
+#endif /* NVGPU_ENGINE_STATUS_GM20B_H */

drivers/gpu/nvgpu/common/fifo/engine_status_gv100.c

@@ -21,6 +21,7 @@
  */
 
 #include <nvgpu/io.h>
+#include <nvgpu/debug.h>
 #include <nvgpu/gk20a.h>
 #include <nvgpu/engine_status.h>
 
@@ -28,8 +29,9 @@
 
 #include "engine_status_gm20b.h"
 #include "engine_status_gv100.h"
+#include "gk20a/fifo_gk20a.h"
 
-void read_engine_status_info_gv100(struct gk20a *g, u32 engine_id,
+void gv100_read_engine_status_info(struct gk20a *g, u32 engine_id,
 		struct nvgpu_engine_status_info *status)
 {
 	u32 engine_reg_data;
@@ -42,3 +44,41 @@ void read_engine_status_info_gv100(struct gk20a *g, u32 engine_id,
 
 	return;
 }
+
+void gv100_dump_engine_status(struct gk20a *g, struct gk20a_debug_output *o)
+{
+	u32 i, host_num_engines;
+	struct nvgpu_engine_status_info engine_status;
+
+	host_num_engines = nvgpu_get_litter_value(g, GPU_LIT_HOST_NUM_ENGINES);
+
+	for (i = 0; i < host_num_engines; i++) {
+		g->ops.engine_status.read_engine_status_info(g, i, &engine_status);
+
+		gk20a_debug_output(o, "%s eng %d: ", g->name, i);
+		gk20a_debug_output(o,
+			"id: %d (%s), next_id: %d (%s), ctx status: %s ",
+			engine_status.ctx_id,
+			nvgpu_engine_status_is_ctx_type_tsg(
+				&engine_status) ?
+				"tsg" : "channel",
+			engine_status.ctx_next_id,
+			nvgpu_engine_status_is_next_ctx_type_tsg(
+				&engine_status) ?
+				"tsg" : "channel",
+			gk20a_decode_pbdma_chan_eng_ctx_status(
+				engine_status.ctxsw_state));
+
+		if (engine_status.in_reload_status) {
+			gk20a_debug_output(o, "ctx_reload ");
+		}
+		if (engine_status.is_faulted) {
+			gk20a_debug_output(o, "faulted ");
+		}
+		if (engine_status.is_busy) {
+			gk20a_debug_output(o, "busy ");
+		}
+		gk20a_debug_output(o, "\n");
+	}
+	gk20a_debug_output(o, "\n");
+}

drivers/gpu/nvgpu/common/fifo/engine_status_gv100.h

@@ -20,15 +20,18 @@
  * DEALINGS IN THE SOFTWARE.
  */
 
-#ifndef NVGPU_ENGINE_STATUS_GV100
+#ifndef NVGPU_ENGINE_STATUS_GV100_H
-#define NVGPU_ENGINE_STATUS_GV100
+#define NVGPU_ENGINE_STATUS_GV100_H
 
 #include <nvgpu/types.h>
 
 struct gk20a;
 struct nvgpu_engine_status_info;
+struct gk20a_debug_output;
 
-void read_engine_status_info_gv100(struct gk20a *g, u32 engine_id,
+void gv100_read_engine_status_info(struct gk20a *g, u32 engine_id,
 		struct nvgpu_engine_status_info *status);
 
-#endif
+void gv100_dump_engine_status(struct gk20a *g, struct gk20a_debug_output *o);
+
+#endif /* NVGPU_ENGINE_STATUS_GV100_H */

drivers/gpu/nvgpu/common/vgpu/gp10b/vgpu_hal_gp10b.c

@@ -387,7 +387,6 @@ static const struct gpu_ops vgpu_gp10b_ops = {
 		.init_engine_info = vgpu_fifo_init_engine_info,
 		.get_engines_mask_on_id = NULL,
 		.dump_pbdma_status = NULL,
-		.dump_eng_status = NULL,
 		.dump_channel_status_ramfc = NULL,
 		.capture_channel_ram_dump = NULL,
 		.intr_0_error_mask = gk20a_fifo_intr_0_error_mask,
@@ -432,6 +431,7 @@ static const struct gpu_ops vgpu_gp10b_ops = {
 	},
 	.engine_status = {
 		.read_engine_status_info = NULL,
+		.dump_engine_status = NULL,
 	},
 	.pbdma_status = {
 		.read_pbdma_status_info = NULL,

drivers/gpu/nvgpu/common/vgpu/gv11b/vgpu_hal_gv11b.c

@@ -457,7 +457,6 @@ static const struct gpu_ops vgpu_gv11b_ops = {
 		.init_engine_info = vgpu_fifo_init_engine_info,
 		.get_engines_mask_on_id = NULL,
 		.dump_pbdma_status = NULL,
-		.dump_eng_status = NULL,
 		.dump_channel_status_ramfc = NULL,
 		.capture_channel_ram_dump = NULL,
 		.intr_0_error_mask = gv11b_fifo_intr_0_error_mask,
@@ -510,6 +509,7 @@ static const struct gpu_ops vgpu_gv11b_ops = {
 	},
 	.engine_status = {
 		.read_engine_status_info = NULL,
+		.dump_engine_status = NULL,
 	},
 	.pbdma_status = {
 		.read_pbdma_status_info = NULL,

drivers/gpu/nvgpu/gk20a/fifo_gk20a.c

@@ -2658,45 +2658,6 @@ void gk20a_dump_pbdma_status(struct gk20a *g,
 	gk20a_debug_output(o, " ");
 }
 
-void gk20a_dump_eng_status(struct gk20a *g,
-				 struct gk20a_debug_output *o)
-{
-	u32 i, host_num_engines;
-	struct nvgpu_engine_status_info engine_status;
-
-	host_num_engines = nvgpu_get_litter_value(g, GPU_LIT_HOST_NUM_ENGINES);
-
-	gk20a_debug_output(o, "Engine status - chip %-5s", g->name);
-	gk20a_debug_output(o, "--------------------------");
-
-	for (i = 0; i < host_num_engines; i++) {
-		g->ops.engine_status.read_engine_status_info(g, i, &engine_status);
-
-		gk20a_debug_output(o,
-			"Engine %d | "
-			"ID: %d - %-9s next_id: %d %-9s | status: %s",
-			i,
-			engine_status.ctx_id,
-			nvgpu_engine_status_is_ctx_type_tsg(
-				&engine_status) ?
-				"[tsg]" : "[channel]",
-			engine_status.ctx_next_id,
-			nvgpu_engine_status_is_next_ctx_type_tsg(
-				&engine_status) ?
-				"[tsg]" : "[channel]",
-			gk20a_decode_pbdma_chan_eng_ctx_status(
-				engine_status.ctxsw_state));
-
-		if (engine_status.is_faulted) {
-			gk20a_debug_output(o, "  State: faulted");
-		}
-		if (engine_status.is_busy) {
-			gk20a_debug_output(o, "  State: busy");
-		}
-	}
-	gk20a_debug_output(o, "\n");
-}
-
 static int gk20a_fifo_commit_userd(struct channel_gk20a *c)
 {
 	u32 addr_lo;

drivers/gpu/nvgpu/gk20a/fifo_gk20a.h

@@ -329,8 +329,6 @@ void gk20a_debug_dump_all_channel_status_ramfc(struct gk20a *g,
 		 struct gk20a_debug_output *o);
 void gk20a_dump_pbdma_status(struct gk20a *g,
 				 struct gk20a_debug_output *o);
-void gk20a_dump_eng_status(struct gk20a *g,
-				 struct gk20a_debug_output *o);
 const char *gk20a_decode_pbdma_chan_eng_ctx_status(u32 index);
 
 int gk20a_fifo_tsg_unbind_channel_verify_status(struct channel_gk20a *ch);

drivers/gpu/nvgpu/gm20b/hal_gm20b.c

@@ -521,7 +521,6 @@ static const struct gpu_ops gm20b_ops = {
 		.init_engine_info = gm20b_fifo_init_engine_info,
 		.get_engines_mask_on_id = gk20a_fifo_engines_on_id,
 		.dump_pbdma_status = gk20a_dump_pbdma_status,
-		.dump_eng_status = gk20a_dump_eng_status,
 		.dump_channel_status_ramfc = gk20a_dump_channel_status_ramfc,
 		.capture_channel_ram_dump = gk20a_capture_channel_ram_dump,
 		.intr_0_error_mask = gk20a_fifo_intr_0_error_mask,
@@ -573,6 +572,7 @@ static const struct gpu_ops gm20b_ops = {
 	.engine_status = {
 		.read_engine_status_info =
 			gm20b_read_engine_status_info,
+		.dump_engine_status = gm20b_dump_engine_status,
 	},
 	.pbdma_status = {
 		.read_pbdma_status_info =

drivers/gpu/nvgpu/gp10b/hal_gp10b.c

@@ -574,7 +574,6 @@ static const struct gpu_ops gp10b_ops = {
 		.init_engine_info = gm20b_fifo_init_engine_info,
 		.get_engines_mask_on_id = gk20a_fifo_engines_on_id,
 		.dump_pbdma_status = gk20a_dump_pbdma_status,
-		.dump_eng_status = gk20a_dump_eng_status,
 		.dump_channel_status_ramfc = gk20a_dump_channel_status_ramfc,
 		.capture_channel_ram_dump = gk20a_capture_channel_ram_dump,
 		.intr_0_error_mask = gk20a_fifo_intr_0_error_mask,
@@ -627,6 +626,7 @@ static const struct gpu_ops gp10b_ops = {
 	.engine_status = {
 		.read_engine_status_info =
 			gm20b_read_engine_status_info,
+		.dump_engine_status = gm20b_dump_engine_status,
 	},
 	.pbdma_status = {
 		.read_pbdma_status_info =

drivers/gpu/nvgpu/gv100/hal_gv100.c

@@ -742,7 +742,6 @@ static const struct gpu_ops gv100_ops = {
 		.init_engine_info = gm20b_fifo_init_engine_info,
 		.get_engines_mask_on_id = gk20a_fifo_engines_on_id,
 		.dump_pbdma_status = gk20a_dump_pbdma_status,
-		.dump_eng_status = gv11b_dump_eng_status,
 		.dump_channel_status_ramfc = gv11b_dump_channel_status_ramfc,
 		.capture_channel_ram_dump = gv11b_capture_channel_ram_dump,
 		.intr_0_error_mask = gv11b_fifo_intr_0_error_mask,
@@ -801,7 +800,8 @@ static const struct gpu_ops gv100_ops = {
 	},
 	.engine_status = {
 		.read_engine_status_info =
-			read_engine_status_info_gv100,
+			gv100_read_engine_status_info,
+		.dump_engine_status = gv100_dump_engine_status,
 	},
 	.pbdma_status = {
 		.read_pbdma_status_info =

drivers/gpu/nvgpu/gv11b/fifo_gv11b.c

@@ -292,45 +292,6 @@ void gv11b_dump_channel_status_ramfc(struct gk20a *g,
 	gk20a_debug_output(o, "\n");
 }
 
-void gv11b_dump_eng_status(struct gk20a *g,
-				 struct gk20a_debug_output *o)
-{
-	u32 i, host_num_engines;
-	struct nvgpu_engine_status_info engine_status;
-
-	host_num_engines = nvgpu_get_litter_value(g, GPU_LIT_HOST_NUM_ENGINES);
-
-	for (i = 0; i < host_num_engines; i++) {
-		g->ops.engine_status.read_engine_status_info(g, i, &engine_status);
-
-		gk20a_debug_output(o, "%s eng %d: ", g->name, i);
-		gk20a_debug_output(o,
-			"id: %d (%s), next_id: %d (%s), ctx status: %s ",
-			engine_status.ctx_id,
-			nvgpu_engine_status_is_ctx_type_tsg(
-				&engine_status) ?
-				"tsg" : "channel",
-			engine_status.ctx_next_id,
-			nvgpu_engine_status_is_next_ctx_type_tsg(
-				&engine_status) ?
-				"tsg" : "channel",
-			gk20a_decode_pbdma_chan_eng_ctx_status(
-				engine_status.ctxsw_state));
-
-		if (engine_status.in_reload_status) {
-			gk20a_debug_output(o, "ctx_reload ");
-		}
-		if (engine_status.is_faulted) {
-			gk20a_debug_output(o, "faulted ");
-		}
-		if (engine_status.is_busy) {
-			gk20a_debug_output(o, "busy ");
-		}
-		gk20a_debug_output(o, "\n");
-	}
-	gk20a_debug_output(o, "\n");
-}
-
 u32 gv11b_fifo_intr_0_error_mask(struct gk20a *g)
 {
 	u32 intr_0_error_mask =

drivers/gpu/nvgpu/gv11b/fifo_gv11b.h

@@ -72,8 +72,6 @@ void gv11b_dump_channel_status_ramfc(struct gk20a *g,
 void gv11b_capture_channel_ram_dump(struct gk20a *g,
 		struct channel_gk20a *ch,
 		struct nvgpu_channel_dump_info *info);
-void gv11b_dump_eng_status(struct gk20a *g,
-				 struct gk20a_debug_output *o);
 u32 gv11b_fifo_intr_0_error_mask(struct gk20a *g);
 int gv11b_fifo_is_preempt_pending(struct gk20a *g, u32 id,
 		 unsigned int id_type);

drivers/gpu/nvgpu/gv11b/hal_gv11b.c

@@ -695,7 +695,6 @@ static const struct gpu_ops gv11b_ops = {
 		.init_engine_info = gm20b_fifo_init_engine_info,
 		.get_engines_mask_on_id = gk20a_fifo_engines_on_id,
 		.dump_pbdma_status = gk20a_dump_pbdma_status,
-		.dump_eng_status = gv11b_dump_eng_status,
 		.dump_channel_status_ramfc = gv11b_dump_channel_status_ramfc,
 		.capture_channel_ram_dump = gv11b_capture_channel_ram_dump,
 		.intr_0_error_mask = gv11b_fifo_intr_0_error_mask,
@@ -755,7 +754,8 @@ static const struct gpu_ops gv11b_ops = {
 	},
 	.engine_status = {
 		.read_engine_status_info =
-			read_engine_status_info_gv100,
+			gv100_read_engine_status_info,
+		.dump_engine_status = gv100_dump_engine_status,
 	},
 	.pbdma_status = {
 		.read_pbdma_status_info =

drivers/gpu/nvgpu/include/nvgpu/gk20a.h

@@ -806,8 +806,6 @@ struct gpu_ops {
 		void (*free_channel_ctx_header)(struct channel_gk20a *ch);
 		void (*dump_pbdma_status)(struct gk20a *g,
 				struct gk20a_debug_output *o);
-		void (*dump_eng_status)(struct gk20a *g,
-				struct gk20a_debug_output *o);
 		void (*dump_channel_status_ramfc)(struct gk20a *g,
 				struct gk20a_debug_output *o,
 				struct nvgpu_channel_dump_info *info);
@@ -934,6 +932,8 @@ struct gpu_ops {
 	struct {
 		void (*read_engine_status_info) (struct gk20a *g,
 			u32 engine_id, struct nvgpu_engine_status_info *status);
+		void (*dump_engine_status)(struct gk20a *g,
+				struct gk20a_debug_output *o);
 	} engine_status;
 	struct {
 		void (*read_pbdma_status_info) (struct gk20a *g,

drivers/gpu/nvgpu/os/linux/debug.c

@@ -67,7 +67,7 @@ void gk20a_debug_show_dump(struct gk20a *g, struct gk20a_debug_output *o)
 {
 	gk20a_debug_dump_all_channel_status_ramfc(g, o);
 	g->ops.fifo.dump_pbdma_status(g, o);
-	g->ops.fifo.dump_eng_status(g, o);
+	g->ops.engine_status.dump_engine_status(g, o);
 }
 
 static int gk20a_gr_dump_regs(struct gk20a *g,

drivers/gpu/nvgpu/tu104/hal_tu104.c

@@ -771,7 +771,6 @@ static const struct gpu_ops tu104_ops = {
 		.init_engine_info = gm20b_fifo_init_engine_info,
 		.get_engines_mask_on_id = gk20a_fifo_engines_on_id,
 		.dump_pbdma_status = gk20a_dump_pbdma_status,
-		.dump_eng_status = gv11b_dump_eng_status,
 		.dump_channel_status_ramfc = gv11b_dump_channel_status_ramfc,
 		.capture_channel_ram_dump = gv11b_capture_channel_ram_dump,
 		.intr_0_error_mask = gv11b_fifo_intr_0_error_mask,
@@ -833,7 +832,8 @@ static const struct gpu_ops tu104_ops = {
 	},
 	.engine_status = {
 		.read_engine_status_info =
-			read_engine_status_info_gv100,
+			gv100_read_engine_status_info,
+		.dump_engine_status = gv100_dump_engine_status,
 	},
 	.pbdma_status = {
 		.read_pbdma_status_info =