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gpu: nvgpu: add SET_CTX_MMU_DEBUG_MODE ioctl

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Added NVGPU_DBG_GPU_IOCTL_SET_CTX_MMU_DEBUG_MODE ioctl to set MMU
debug mode for a given context.

Added gr.set_mmu_debug_mode HAL to change NV_PGPC_PRI_MMU_DEBUG_CTRL
for a given channel. HAL implementation for native case is
gm20b_gr_set_mmu_debug_mode. It internally uses regops, which directly
writes to the register if the context is resident, or writes to
gr context otherwise.

Added NVGPU_SUPPORT_SET_CTX_MMU_DEBUG_MODE to enable the feature.
NV_PGPC_PRI_MMU_DEBUG_CTRL has to be context switched in FECS ucode,
so the feature is only enabled on TU104 for now.

Bug 2515097
But 2713590

Change-Id: Ib4efaf06fc47a8539b4474f94c68c20ce225263f
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2110720
(cherry-picked from commit af2ccb811d)
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2208767
Reviewed-by: Kajetan Dutka <kdutka@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: Winnie Hsu <whsu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
Tested-by: Kajetan Dutka <kdutka@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Thomas Fleury
2019-04-30 17:19:51 -07:00
committed by mobile promotions
parent 6e91ecaae7
commit dc281d6a9e
15 changed files with 122 additions and 12 deletions
Download Patch File Download Diff File Expand all files Collapse all files

56
drivers/gpu/nvgpu/os/linux/ioctl_dbg.c
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@@ -1,7 +1,7 @@
/*
* Tegra GK20A GPU Debugger/Profiler Driver
*
* Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2017-2020, NVIDIA CORPORATION. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
@@ -117,6 +117,10 @@ static int nvgpu_dbg_gpu_ioctl_smpc_ctxsw_mode(struct dbg_session_gk20a *dbg_s,
static int nvgpu_dbg_gpu_ioctl_hwpm_ctxsw_mode(struct dbg_session_gk20a *dbg_s,
struct nvgpu_dbg_gpu_hwpm_ctxsw_mode_args *args);
static int nvgpu_dbg_gpu_ioctl_set_mmu_debug_mode(
struct dbg_session_gk20a *dbg_s,
struct nvgpu_dbg_gpu_set_ctx_mmu_debug_mode_args *args);
static int nvgpu_dbg_gpu_ioctl_suspend_resume_sm(
struct dbg_session_gk20a *dbg_s,
struct nvgpu_dbg_gpu_suspend_resume_all_sms_args *args);
@@ -1072,6 +1076,51 @@ static int nvgpu_dbg_gpu_ioctl_hwpm_ctxsw_mode(struct dbg_session_gk20a *dbg_s,
return err;
}
static int nvgpu_dbg_gpu_ioctl_set_mmu_debug_mode(
struct dbg_session_gk20a *dbg_s,
struct nvgpu_dbg_gpu_set_ctx_mmu_debug_mode_args *args)
{
int err;
struct gk20a *g = dbg_s->g;
struct channel_gk20a *ch;
bool enable = (args->mode == NVGPU_DBG_GPU_CTX_MMU_DEBUG_MODE_ENABLED);
nvgpu_log_fn(g, "mode=%u", args->mode);
if (args->reserved != 0U) {
return -EINVAL;
}
if (g->ops.gr.set_mmu_debug_mode == NULL) {
return -ENOSYS;
}
err = gk20a_busy(g);
if (err) {
nvgpu_err(g, "failed to poweron");
return err;
}
/* Take the global lock, since we'll be doing global regops */
nvgpu_mutex_acquire(&g->dbg_sessions_lock);
ch = nvgpu_dbg_gpu_get_session_channel(dbg_s);
if (!ch) {
nvgpu_err(g, "no bound channel for mmu debug mode");
goto clean_up;
}
err = g->ops.gr.set_mmu_debug_mode(g, ch, enable);
if (err) {
nvgpu_err(g, "set mmu debug mode failed, err=%d", err);
}
clean_up:
nvgpu_mutex_release(&g->dbg_sessions_lock);
gk20a_idle(g);
return err;
}
static int nvgpu_dbg_gpu_ioctl_suspend_resume_sm(
struct dbg_session_gk20a *dbg_s,
struct nvgpu_dbg_gpu_suspend_resume_all_sms_args *args)
@@ -2030,6 +2079,11 @@ long gk20a_dbg_gpu_dev_ioctl(struct file *filp, unsigned int cmd,
(struct nvgpu_dbg_gpu_set_sm_exception_type_mask_args *)buf);
break;
case NVGPU_DBG_GPU_IOCTL_SET_CTX_MMU_DEBUG_MODE:
err = nvgpu_dbg_gpu_ioctl_set_mmu_debug_mode(dbg_s,
(struct nvgpu_dbg_gpu_set_ctx_mmu_debug_mode_args *)buf);
break;
default:
nvgpu_err(g,
"unrecognized dbg gpu ioctl cmd: 0x%x",