gpu: nvgpu: MISRA fixes for composite expressions

MISRA rules 10.6, 10.7, and 10.8 prevent mixing of types in composite
expressions. Resolve these violations by casting variables/constants to
the appropriate types.

Jira NVGPU-850
Jira NVGPU-853
Jira NVGPU-851

Change-Id: If6db312187211bc428cf465929082118565dacf4
Signed-off-by: Adeel Raza <araza@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1931156
GVS: Gerrit_Virtual_Submit
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Adeel Raza
2018-10-23 13:24:39 -07:00
committed by mobile promotions
parent a733659f19
commit dc37ca4559
49 changed files with 184 additions and 150 deletions

View File

@@ -1351,8 +1351,10 @@ int nvgpu_buddy_allocator_init(struct gk20a *g, struct nvgpu_allocator *na,
* requirement is not necessary.
*/
if (is_gva_space) {
base_big_page = base & ((vm->big_page_size << 10U) - 1U);
size_big_page = size & ((vm->big_page_size << 10U) - 1U);
base_big_page = base &
((U64(vm->big_page_size) << U64(10)) - U64(1));
size_big_page = size &
((U64(vm->big_page_size) << U64(10)) - U64(1));
if (vm->big_pages &&
(base_big_page != 0ULL || size_big_page != 0ULL)) {
return -EINVAL;