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gpu: nvgpu: MISRA fixes for composite expressions

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MISRA rules 10.6, 10.7, and 10.8 prevent mixing of types in composite
expressions. Resolve these violations by casting variables/constants to
the appropriate types.

Jira NVGPU-850
Jira NVGPU-853
Jira NVGPU-851

Change-Id: If6db312187211bc428cf465929082118565dacf4
Signed-off-by: Adeel Raza <araza@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1931156
GVS: Gerrit_Virtual_Submit
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Adeel Raza
2018-10-23 13:24:39 -07:00
committed by mobile promotions
parent a733659f19
commit dc37ca4559
49 changed files with 184 additions and 150 deletions
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2
drivers/gpu/nvgpu/lpwr/lpwr.c
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@@ -145,7 +145,7 @@ static int get_lpwr_ms_table(struct gk20a *g)
pms_data->default_entry_idx = (u8)header.default_entry_idx;
pms_data->idle_threshold_us = (u32)(header.idle_threshold_us * 10);
pms_data->idle_threshold_us = U32(header.idle_threshold_us) * U32(10);
/* Parse the LPWR MS Table entries.*/
for (idx = 0; idx < header.entry_count; idx++) {