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gpu: nvgpu: unit: ltc: increase line/branch coverage
This increases the line and branch coverage for nvgpu.common.ltc unit test. Add testing for nvgpu.common.hal.ltc for gv11b. Also, add Targets tag for SWUTS/traceability. JIRA NVGPU-2219 Change-Id: Ic0e3772b6348ba7ce43fd869567467bc13b8943c Signed-off-by: Philip Elcan <pelcan@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2248093 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Philip Elcan
committed by
Alex Waterman
Alex Waterman
parent
b8c25a5a55
commit
dcb19f578a
@@ -28,11 +28,16 @@
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#include <nvgpu/gk20a.h>
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#include <nvgpu/posix/io.h>
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#include <nvgpu/posix/posix-fault-injection.h>
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#include <nvgpu/hal_init.h>
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#include <nvgpu/enabled.h>
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#include <nvgpu/hw/gm20b/hw_mc_gm20b.h>
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#include <nvgpu/hw/gv11b/hw_ltc_gv11b.h>
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#include <nvgpu/ltc.h>
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#include <nvgpu/nvgpu_mem.h>
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#include <nvgpu/ecc.h>
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#include <nvgpu/gr/gr.h>
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#include <hal/ltc/intr/ltc_intr_gv11b.h>
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#include "nvgpu-ltc.h"
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@@ -72,18 +77,38 @@ static struct nvgpu_posix_io_callbacks netlist_test_reg_callbacks = {
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.bar1_readl = readl_access_reg_fn,
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};
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#define NUM_LTC 2
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#define NUM_SLICES 2
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static u32 mock_enum_ltc(struct gk20a *g)
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{
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return NUM_LTC;
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}
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static int mock_ecc_init_fail(struct gk20a *g)
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{
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return -1;
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}
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int test_ltc_init_support(struct unit_module *m,
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struct gk20a *g, void *args)
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{
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int err = 0;
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void (*save_void_func)(struct gk20a *g);
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int (*save_ecc_func)(struct gk20a *g);
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struct nvgpu_ltc *save_ptr;
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struct nvgpu_posix_fault_inj *kmem_fi =
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nvgpu_kmem_get_fault_injection();
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nvgpu_posix_io_init_reg_space(g);
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if (nvgpu_posix_io_add_reg_space(g, mc_boot_0_r(), 0xfff) != 0) {
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unit_err(m, "%s: failed to create register space\n", __func__);
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return UNIT_FAIL;
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}
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if (nvgpu_posix_io_add_reg_space(g, ltc_pltcg_base_v(), 0x3ffff) != 0) {
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unit_err(m, "%s: failed to create register space\n", __func__);
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return UNIT_FAIL;
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}
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(void)nvgpu_posix_register_io(g, &netlist_test_reg_callbacks);
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@@ -93,6 +118,12 @@ int test_ltc_init_support(struct unit_module *m,
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g->params.gpu_arch = NV_PMC_BOOT_0_ARCHITECTURE_GV110;
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g->params.gpu_impl = NV_PMC_BOOT_0_IMPLEMENTATION_B;
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/*
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* Initialize slices in register
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*/
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nvgpu_posix_io_writel_reg_space(g, ltc_ltcs_ltss_cbc_param_r(),
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NUM_SLICES << 28);
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/*
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* HAL init required for getting
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* the falcon ops initialized.
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@@ -102,13 +133,195 @@ int test_ltc_init_support(struct unit_module *m,
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unit_return_fail(m, "nvgpu_init_hal failed\n");
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}
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/*
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* Init dependent ECC unit
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*/
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err = nvgpu_ecc_init_support(g);
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if (err != 0) {
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unit_return_fail(m, "ecc init failed\n");
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}
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/*
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* Override HALs
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*/
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g->ops.priv_ring.enum_ltc = mock_enum_ltc;
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err = nvgpu_init_ltc_support(g);
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if (err != 0) {
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unit_return_fail(m, "nvgpu_init_ltc_support failed\n");
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}
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/*
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* Call init again after init to get branch coverage.
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*/
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err = nvgpu_init_ltc_support(g);
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if (err != 0) {
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unit_return_fail(m, "nvgpu_init_ltc_support failed\n");
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}
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/*
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* Call init again with this HAL set to NULL for branch coverage.
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*/
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save_void_func = g->ops.ltc.init_fs_state;
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g->ops.ltc.init_fs_state = NULL;
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err = nvgpu_init_ltc_support(g);
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if (err != 0) {
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unit_return_fail(m, "nvgpu_init_ltc_support failed\n");
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}
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/* and restore the HAL */
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g->ops.ltc.init_fs_state = save_void_func;
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/*
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* Call init with this HAL set to NULL for branch coverage.
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*/
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save_void_func = g->ops.ltc.intr.configure;
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g->ops.ltc.intr.configure = NULL;
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err = nvgpu_init_ltc_support(g);
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if (err != 0) {
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unit_return_fail(m, "nvgpu_init_ltc_support failed\n");
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}
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/* and restore the HAL */
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g->ops.ltc.intr.configure = save_void_func;
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/*
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* Call init with ecc init HAL NULL for branch coverage.
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*/
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save_ecc_func = g->ops.ltc.ecc_init;
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g->ops.ltc.ecc_init = NULL;
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err = nvgpu_init_ltc_support(g);
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if (err != 0) {
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unit_return_fail(m, "nvgpu_init_ltc_support failed\n");
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}
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/*
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* Call init with a failure returned from ecc init. This frees the ltc
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* state in gk20a, so we'll need to init again.
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*/
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g->ops.ltc.ecc_init = mock_ecc_init_fail;
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err = nvgpu_init_ltc_support(g);
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if (err == 0) {
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unit_return_fail(m, "nvgpu_init_ltc_support failed\n");
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}
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/* and restore the HAL */
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g->ops.ltc.ecc_init = save_ecc_func;
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/*
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* Call init with ecc flag set to initialzed for branch coverage.
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*/
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g->ecc.initialized = true;
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err = nvgpu_init_ltc_support(g);
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if (err != 0) {
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unit_return_fail(m, "nvgpu_init_ltc_support failed\n");
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}
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g->ecc.initialized = false;
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/*
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* Call init with kmem fault inj enabled for branch coverage.
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*/
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save_ptr = g->ltc;
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g->ltc = NULL;
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nvgpu_posix_enable_fault_injection(kmem_fi, true, 0);
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err = nvgpu_init_ltc_support(g);
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if (err == 0) {
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unit_return_fail(m,
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"nvgpu_init_ltc_support incorrectly succeeded\n");
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}
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/* and restore everything */
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nvgpu_posix_enable_fault_injection(kmem_fi, false, 0);
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g->ltc = save_ptr;
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/*
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* Call init one final time to setup the state variable properly for
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* future tests.
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*/
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err = nvgpu_init_ltc_support(g);
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if (err != 0) {
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unit_return_fail(m, "nvgpu_init_ltc_support failed\n");
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}
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return UNIT_SUCCESS;
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}
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int test_ltc_ecc_init_free(struct unit_module *m, struct gk20a *g, void *args)
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{
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int ret = UNIT_SUCCESS;
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int err;
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struct nvgpu_ecc_stat **save_sec_ptr = g->ecc.ltc.ecc_sec_count;
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struct nvgpu_ecc_stat **save_ded_ptr = g->ecc.ltc.ecc_ded_count;
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struct nvgpu_posix_fault_inj *kmem_fi =
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nvgpu_kmem_get_fault_injection();
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err = nvgpu_gr_alloc(g);
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if (err != 0) {
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unit_return_fail(m, "failed to init gr\n");
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}
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g->ecc.ltc.ecc_sec_count = NULL;
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g->ecc.ltc.ecc_ded_count = NULL;
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/*
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* Call with failure on first kzalloc
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*/
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nvgpu_posix_enable_fault_injection(kmem_fi, true, 0);
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err = g->ops.ltc.ecc_init(g);
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if (err == 0) {
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unit_err(m, "nvgpu_ecc_counter_init_per_lts() failed to return error\n");
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ret = UNIT_FAIL;
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goto done;
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}
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/*
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* Call with failure on third kzalloc for the 2nd array dimension and to
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* validate unrolling.
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*/
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nvgpu_posix_enable_fault_injection(kmem_fi, true, 2);
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err = g->ops.ltc.ecc_init(g);
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if (err == 0) {
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unit_err(m, "nvgpu_ecc_counter_init_per_lts() failed to return error\n");
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ret = UNIT_FAIL;
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goto done;
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}
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/* Re-Init dependent ECC unit */
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err = nvgpu_ecc_init_support(g);
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if (err != 0) {
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unit_return_fail(m, "ecc init failed\n");
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}
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/*
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* Call with failure on 4th kzalloc for second stat and get more
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* branch/line coverage.
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*/
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nvgpu_posix_enable_fault_injection(kmem_fi, true, 4);
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err = g->ops.ltc.ecc_init(g);
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if (err == 0) {
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unit_err(m, "nvgpu_ecc_counter_init_per_lts() failed to return error\n");
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ret = UNIT_FAIL;
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goto done;
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}
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/* Re-Init dependent ECC unit */
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err = nvgpu_ecc_init_support(g);
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if (err != 0) {
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unit_return_fail(m, "ecc init failed\n");
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}
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nvgpu_posix_enable_fault_injection(kmem_fi, false, 0);
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err = g->ops.ltc.ecc_init(g);
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if (err != 0) {
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unit_err(m, "nvgpu_ecc_counter_init_per_lts() failed to init\n");
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ret = UNIT_FAIL;
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goto done;
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}
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nvgpu_ltc_ecc_free(g);
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done:
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nvgpu_posix_enable_fault_injection(kmem_fi, false, 0);
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g->ecc.ltc.ecc_sec_count = save_sec_ptr;
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g->ecc.ltc.ecc_ded_count = save_ded_ptr;
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nvgpu_gr_free(g);
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return ret;
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}
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int test_ltc_functionality_tests(struct unit_module *m,
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@@ -122,11 +335,11 @@ int test_ltc_functionality_tests(struct unit_module *m,
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nvgpu_ltc_sync_enabled(g);
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ltc_count = nvgpu_ltc_get_ltc_count(g);
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if (ltc_count != 0) {
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if (ltc_count != NUM_LTC) {
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unit_return_fail(m, "nvgpu_ltc_get_ltc_count failed\n");
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}
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slice_per_ltc = nvgpu_ltc_get_slices_per_ltc(g);
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if (slice_per_ltc != 0) {
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if (slice_per_ltc != NUM_SLICES) {
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unit_return_fail(m, "nvgpu_ltc_get_slices_per_ltc failed\n");
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}
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cacheline_size = nvgpu_ltc_get_cacheline_size(g);
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@@ -142,6 +355,8 @@ int test_ltc_negative_tests(struct unit_module *m,
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{
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int err = 0;
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g->mm.ltc_enabled_current = g->mm.ltc_enabled_target;
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nvgpu_ltc_sync_enabled(g);
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g->ops.ltc.set_enabled = NULL;
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nvgpu_ltc_sync_enabled(g);
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nvgpu_ltc_remove_support(g);
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@@ -162,10 +377,263 @@ int test_ltc_remove_support(struct unit_module *m,
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return UNIT_SUCCESS;
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}
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static int mock_l2_flush(struct gk20a *g, bool inv)
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{
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return 0;
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}
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int test_ltc_intr(struct unit_module *m, struct gk20a *g, void *args)
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{
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int err = UNIT_SUCCESS;
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u32 i;
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const u32 offset1 = nvgpu_get_litter_value(g, GPU_LIT_LTC_STRIDE) *
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nvgpu_get_litter_value(g, GPU_LIT_LTS_STRIDE);
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int (*save_func)(struct gk20a *g, bool inv);
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/* Init counter space */
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nvgpu_init_list_node(&g->ecc.stats_list);
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err = NVGPU_ECC_COUNTER_INIT_PER_LTS(ecc_sec_count);
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if (err != 0) {
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unit_err(m, "failed to init ecc_sec_count\n");
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err = UNIT_FAIL;
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goto done;
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}
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err = NVGPU_ECC_COUNTER_INIT_PER_LTS(ecc_ded_count);
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if (err != 0) {
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unit_err(m, "failed to init ecc_ded_count\n");
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err = UNIT_FAIL;
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goto done;
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}
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/* test with no intr pending */
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g->ops.ltc.intr.isr(g, 0);
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/* test with intr, but no corrected or uncorrected bits */
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nvgpu_posix_io_writel_reg_space(g, ltc_ltc0_lts0_intr3_r(),
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ltc_ltcs_ltss_intr3_ecc_uncorrected_m());
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g->ops.ltc.intr.isr(g, 0);
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/* set corrected & uncorrected overflow bits */
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nvgpu_posix_io_writel_reg_space(g, ltc_ltc0_lts0_l2_cache_ecc_status_r(),
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ltc_ltc0_lts0_l2_cache_ecc_status_corrected_err_total_counter_overflow_m() |
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ltc_ltc0_lts0_l2_cache_ecc_status_uncorrected_err_total_counter_overflow_m());
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nvgpu_posix_io_writel_reg_space(g, ltc_ltc0_lts0_intr3_r(),
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ltc_ltcs_ltss_intr3_ecc_uncorrected_m());
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g->ops.ltc.intr.isr(g, 0);
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/* set corrected & uncorrected overflow bits in second instance */
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nvgpu_posix_io_writel_reg_space(g,
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ltc_ltc0_lts0_l2_cache_ecc_status_r() + offset1,
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ltc_ltc0_lts0_l2_cache_ecc_status_corrected_err_total_counter_overflow_m() |
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ltc_ltc0_lts0_l2_cache_ecc_status_uncorrected_err_total_counter_overflow_m());
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nvgpu_posix_io_writel_reg_space(g, ltc_ltc0_lts0_intr3_r() + offset1,
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ltc_ltcs_ltss_intr3_ecc_uncorrected_m());
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g->ops.ltc.intr.isr(g, 0);
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/* set corrected overflow bit independently for branch coverage */
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nvgpu_posix_io_writel_reg_space(g, ltc_ltc0_lts0_l2_cache_ecc_status_r(),
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ltc_ltc0_lts0_l2_cache_ecc_status_corrected_err_total_counter_overflow_m());
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nvgpu_posix_io_writel_reg_space(g, ltc_ltc0_lts0_intr3_r(),
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ltc_ltcs_ltss_intr3_ecc_uncorrected_m());
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g->ops.ltc.intr.isr(g, 0);
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/* set uncorrected overflow bit independently for branch coverage */
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nvgpu_posix_io_writel_reg_space(g, ltc_ltc0_lts0_l2_cache_ecc_status_r(),
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ltc_ltc0_lts0_l2_cache_ecc_status_uncorrected_err_total_counter_overflow_m());
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nvgpu_posix_io_writel_reg_space(g, ltc_ltc0_lts0_intr3_r(),
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ltc_ltcs_ltss_intr3_ecc_uncorrected_m());
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g->ops.ltc.intr.isr(g, 0);
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/*
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* Clear the corrected & uncorrected overflow bits. And for branch
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* coverage, set the uncorrected & corrected err counts.
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*/
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nvgpu_posix_io_writel_reg_space(g, ltc_ltc0_lts0_l2_cache_ecc_status_r(), 0x0);
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nvgpu_posix_io_writel_reg_space(g, ltc_ltc0_lts0_l2_cache_ecc_corrected_err_count_r(),
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ltc_ltc0_lts0_l2_cache_ecc_corrected_err_count_total_m());
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nvgpu_posix_io_writel_reg_space(g, ltc_ltc0_lts0_l2_cache_ecc_uncorrected_err_count_r(),
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ltc_ltc0_lts0_l2_cache_ecc_uncorrected_err_count_total_m());
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nvgpu_posix_io_writel_reg_space(g, ltc_ltc0_lts0_intr3_r(),
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ltc_ltcs_ltss_intr3_ecc_uncorrected_m());
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g->ops.ltc.intr.isr(g, 0);
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/* set dstg bits with data RAM */
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nvgpu_posix_io_writel_reg_space(g, ltc_ltc0_lts0_l2_cache_ecc_status_r(),
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ltc_ltc0_lts0_l2_cache_ecc_status_corrected_err_dstg_m() |
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ltc_ltc0_lts0_l2_cache_ecc_status_uncorrected_err_dstg_m());
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nvgpu_posix_io_writel_reg_space(g, ltc_ltc0_lts0_intr3_r(),
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ltc_ltcs_ltss_intr3_ecc_uncorrected_m());
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g->ops.ltc.intr.isr(g, 0);
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/* set dstg bits with byte enable (BE) RAM */
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nvgpu_posix_io_writel_reg_space(g, ltc_ltc0_lts0_l2_cache_ecc_status_r(),
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ltc_ltc0_lts0_l2_cache_ecc_status_corrected_err_dstg_m() |
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ltc_ltc0_lts0_l2_cache_ecc_status_uncorrected_err_dstg_m());
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nvgpu_posix_io_writel_reg_space(g, ltc_ltc0_lts0_dstg_ecc_address_r(),
|
||||
ltc_ltc0_lts0_dstg_ecc_address_info_ram_m());
|
||||
nvgpu_posix_io_writel_reg_space(g, ltc_ltc0_lts0_intr3_r(),
|
||||
ltc_ltcs_ltss_intr3_ecc_uncorrected_m());
|
||||
g->ops.ltc.intr.isr(g, 0);
|
||||
|
||||
/* set tstg & rstg bits */
|
||||
nvgpu_posix_io_writel_reg_space(g, ltc_ltc0_lts0_l2_cache_ecc_status_r(),
|
||||
ltc_ltc0_lts0_l2_cache_ecc_status_corrected_err_tstg_m() |
|
||||
ltc_ltc0_lts0_l2_cache_ecc_status_uncorrected_err_tstg_m() |
|
||||
ltc_ltc0_lts0_l2_cache_ecc_status_corrected_err_rstg_m() |
|
||||
ltc_ltc0_lts0_l2_cache_ecc_status_uncorrected_err_rstg_m());
|
||||
nvgpu_posix_io_writel_reg_space(g, ltc_ltc0_lts0_intr3_r(),
|
||||
ltc_ltcs_ltss_intr3_ecc_uncorrected_m());
|
||||
g->ops.ltc.intr.isr(g, 0);
|
||||
|
||||
/* set sec & ded error bits */
|
||||
nvgpu_posix_io_writel_reg_space(g, ltc_ltc0_lts0_intr_r(),
|
||||
ltc_ltcs_ltss_intr_ecc_sec_error_pending_f() |
|
||||
ltc_ltcs_ltss_intr_ecc_ded_error_pending_f());
|
||||
nvgpu_posix_io_writel_reg_space(g, ltc_ltc0_lts0_intr3_r(),
|
||||
ltc_ltcs_ltss_intr3_ecc_uncorrected_m());
|
||||
g->ops.ltc.intr.isr(g, 0);
|
||||
|
||||
/* For branch coverage, set sec & ded error bits and make l2 flush succeed */
|
||||
save_func = g->ops.mm.cache.l2_flush;
|
||||
g->ops.mm.cache.l2_flush = mock_l2_flush;
|
||||
nvgpu_posix_io_writel_reg_space(g, ltc_ltc0_lts0_intr_r(),
|
||||
ltc_ltcs_ltss_intr_ecc_sec_error_pending_f() |
|
||||
ltc_ltcs_ltss_intr_ecc_ded_error_pending_f());
|
||||
nvgpu_posix_io_writel_reg_space(g, ltc_ltc0_lts0_intr3_r(),
|
||||
ltc_ltcs_ltss_intr3_ecc_uncorrected_m());
|
||||
g->ops.ltc.intr.isr(g, 0);
|
||||
g->ops.mm.cache.l2_flush = save_func;
|
||||
|
||||
done:
|
||||
for (i = 0; i < nvgpu_ltc_get_ltc_count(g); i++) {
|
||||
if (g->ecc.ltc.ecc_sec_count != NULL) {
|
||||
nvgpu_kfree(g, g->ecc.ltc.ecc_sec_count[i]);
|
||||
}
|
||||
|
||||
if (g->ecc.ltc.ecc_ded_count != NULL) {
|
||||
nvgpu_kfree(g, g->ecc.ltc.ecc_ded_count[i]);
|
||||
}
|
||||
}
|
||||
|
||||
return err;
|
||||
}
|
||||
|
||||
int test_ltc_intr_en_illegal_compstat(struct unit_module *m,
|
||||
struct gk20a *g, void *args)
|
||||
{
|
||||
u32 val;
|
||||
|
||||
/* clear the reg to be sure */
|
||||
nvgpu_posix_io_writel_reg_space(g, ltc_ltcs_ltss_intr_r(), 0);
|
||||
|
||||
g->ops.ltc.intr.en_illegal_compstat(g, true);
|
||||
val = nvgpu_posix_io_readl_reg_space(g, ltc_ltcs_ltss_intr_r());
|
||||
if ((val & ltc_ltcs_ltss_intr_en_illegal_compstat_m()) == 0) {
|
||||
unit_return_fail(m, "failed to enable illegal compstat\n");
|
||||
}
|
||||
|
||||
g->ops.ltc.intr.en_illegal_compstat(g, false);
|
||||
val = nvgpu_posix_io_readl_reg_space(g, ltc_ltcs_ltss_intr_r());
|
||||
if ((val & ltc_ltcs_ltss_intr_en_illegal_compstat_m()) != 0) {
|
||||
unit_return_fail(m, "failed to disable illegal compstat\n");
|
||||
}
|
||||
|
||||
return UNIT_SUCCESS;
|
||||
}
|
||||
|
||||
int test_ltc_intr_configure(struct unit_module *m,
|
||||
struct gk20a *g, void *args)
|
||||
{
|
||||
u32 val;
|
||||
void (*save_func)(struct gk20a *g, bool en);
|
||||
|
||||
g->ops.ltc.intr.configure(g);
|
||||
val = nvgpu_posix_io_readl_reg_space(g, ltc_ltcs_ltss_intr_r());
|
||||
if ((val & (ltc_ltcs_ltss_intr_en_ecc_sec_error_enabled_f() |
|
||||
ltc_ltcs_ltss_intr_en_ecc_ded_error_enabled_f())) !=
|
||||
(ltc_ltcs_ltss_intr_en_ecc_sec_error_enabled_f() |
|
||||
ltc_ltcs_ltss_intr_en_ecc_ded_error_enabled_f())) {
|
||||
unit_return_fail(m, "failed to configure intr\n");
|
||||
}
|
||||
|
||||
/* for branch coverage test case where this HAL isn't configured */
|
||||
save_func = g->ops.ltc.intr.en_illegal_compstat;
|
||||
g->ops.ltc.intr.en_illegal_compstat = NULL;
|
||||
g->ops.ltc.intr.configure(g);
|
||||
val = nvgpu_posix_io_readl_reg_space(g, ltc_ltcs_ltss_intr_r());
|
||||
if ((val & (ltc_ltcs_ltss_intr_en_ecc_sec_error_enabled_f() |
|
||||
ltc_ltcs_ltss_intr_en_ecc_ded_error_enabled_f())) !=
|
||||
(ltc_ltcs_ltss_intr_en_ecc_sec_error_enabled_f() |
|
||||
ltc_ltcs_ltss_intr_en_ecc_ded_error_enabled_f())) {
|
||||
unit_return_fail(m, "failed to configure intr\n");
|
||||
}
|
||||
g->ops.ltc.intr.en_illegal_compstat = save_func;
|
||||
|
||||
return UNIT_SUCCESS;
|
||||
}
|
||||
|
||||
int test_determine_L2_size_bytes(struct unit_module *m,
|
||||
struct gk20a *g, void *args)
|
||||
{
|
||||
const u32 slice_size = 2;
|
||||
const u32 slice_per_l2 = 2;
|
||||
const u64 expected_size = g->ltc->ltc_count * slice_size * 1024 * slice_per_l2;
|
||||
u64 val;
|
||||
|
||||
nvgpu_posix_io_writel_reg_space(g, ltc_ltc0_lts0_tstg_info_1_r(),
|
||||
(slice_size << 0) |
|
||||
(slice_per_l2 << 16));
|
||||
val = g->ops.ltc.determine_L2_size_bytes(g);
|
||||
if (val != expected_size) {
|
||||
unit_return_fail(m, "incorrect L2 size reported %lld, expected %lld\n",
|
||||
val, expected_size);
|
||||
}
|
||||
|
||||
return UNIT_SUCCESS;
|
||||
}
|
||||
|
||||
int test_ltc_set_enabled(struct unit_module *m, struct gk20a *g, void *args)
|
||||
{
|
||||
u32 val;
|
||||
|
||||
/* clear reg */
|
||||
nvgpu_posix_io_writel_reg_space(g, ltc_ltcs_ltss_tstg_set_mgmt_2_r(),
|
||||
0x0);
|
||||
g->ops.ltc.set_enabled(g, true);
|
||||
val = nvgpu_posix_io_readl_reg_space(g,
|
||||
ltc_ltcs_ltss_tstg_set_mgmt_2_r());
|
||||
/* enabling is actually disabling bypass, so logic seems backwards */
|
||||
if ((val & ltc_ltcs_ltss_tstg_set_mgmt_2_l2_bypass_mode_enabled_f())
|
||||
!= 0) {
|
||||
unit_return_fail(m, "not enabled\n");
|
||||
}
|
||||
|
||||
/* clear reg */
|
||||
nvgpu_posix_io_writel_reg_space(g, ltc_ltcs_ltss_tstg_set_mgmt_2_r(),
|
||||
0x0);
|
||||
g->ops.ltc.set_enabled(g, false);
|
||||
val = nvgpu_posix_io_readl_reg_space(g,
|
||||
ltc_ltcs_ltss_tstg_set_mgmt_2_r());
|
||||
/* enabling is actually disabling bypass, so logic seems backwards */
|
||||
if ((val & ltc_ltcs_ltss_tstg_set_mgmt_2_l2_bypass_mode_enabled_f())
|
||||
== 0) {
|
||||
unit_return_fail(m, "not disabled\n");
|
||||
}
|
||||
|
||||
return UNIT_SUCCESS;
|
||||
}
|
||||
|
||||
struct unit_module_test nvgpu_ltc_tests[] = {
|
||||
UNIT_TEST(ltc_init_support, test_ltc_init_support, NULL, 0),
|
||||
UNIT_TEST(ltc_ecc_init_free, test_ltc_ecc_init_free, NULL, 0),
|
||||
UNIT_TEST(ltc_functionality_tests, test_ltc_functionality_tests,
|
||||
NULL, 0),
|
||||
UNIT_TEST(ltc_intr, test_ltc_intr, NULL, 0),
|
||||
UNIT_TEST(ltc_intr_en_illegal_compstat,
|
||||
test_ltc_intr_en_illegal_compstat, NULL, 0),
|
||||
UNIT_TEST(ltc_intr_configure, test_ltc_intr_configure, NULL, 0),
|
||||
UNIT_TEST(ltc_determine_L2_size, test_determine_L2_size_bytes, NULL, 0),
|
||||
UNIT_TEST(ltc_set_enabled, test_ltc_set_enabled, NULL, 0),
|
||||
UNIT_TEST(ltc_negative_tests, test_ltc_negative_tests, NULL, 0),
|
||||
UNIT_TEST(ltc_remove_support, test_ltc_remove_support, NULL, 0),
|
||||
};
|
||||
|
||||
Reference in New Issue
Block a user