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gpu: nvgpu: Add GCC exception handling support

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Add support for per-chip handling of GCC exception.

JIRA GPUT19X-86

Change-Id: I76ea588dc76b5c821ae5b53529db6dd64b3a856a
Signed-off-by: Lakshmanan M <lm@nvidia.com>
Reviewed-on: http://git-master/r/1485836
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Lakshmanan M
2017-05-19 15:43:13 +05:30
committed by mobile promotions
parent d85aa0064b
commit dcb744acfb
7 changed files with 32 additions and 0 deletions
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3
drivers/gpu/nvgpu/gk20a/gk20a.h
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@@ -304,6 +304,9 @@ struct gpu_ops {
int (*handle_sm_exception)(struct gk20a *g, u32 gpc, u32 tpc,
bool *post_event, struct channel_gk20a *fault_ch,
u32 *hww_global_esr);
int (*handle_gcc_exception)(struct gk20a *g, u32 gpc, u32 tpc,
bool *post_event, struct channel_gk20a *fault_ch,
u32 *hww_global_esr);
int (*handle_tex_exception)(struct gk20a *g, u32 gpc, u32 tpc,
bool *post_event);
void (*enable_gpc_exceptions)(struct gk20a *g);

9
drivers/gpu/nvgpu/gk20a/gr_gk20a.c
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@@ -6348,6 +6348,15 @@ static int gk20a_gr_handle_gpc_exception(struct gk20a *g, bool *post_event,
* exceptions to be cleared */
gk20a_gr_clear_sm_hww(g, gpc, tpc, global_esr);
}
/* Handle GCC exception */
if(gr_gpc0_gpccs_gpc_exception_gcc_v(gpc_exception) &&
g->ops.gr.handle_gcc_exception) {
int gcc_ret = 0;
gcc_ret = g->ops.gr.handle_gcc_exception(g, gpc, tpc,
post_event, fault_ch, hww_global_esr);
ret = ret ? ret : gcc_ret;
}
}
return ret;

4
drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_gr_gk20a.h
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@@ -3066,6 +3066,10 @@ static inline u32 gr_gpc0_gpccs_gpc_exception_r(void)
{
return 0x00502c90;
}
static inline u32 gr_gpc0_gpccs_gpc_exception_gcc_v(u32 r)
{
return (r >> 2) & 0x1;
}
static inline u32 gr_gpc0_gpccs_gpc_exception_tpc_v(u32 r)
{
return (r >> 16) & 0xff;

4
drivers/gpu/nvgpu/include/nvgpu/hw/gm206/hw_gr_gm206.h
View File

@@ -3078,6 +3078,10 @@ static inline u32 gr_gpc0_gpccs_gpc_exception_r(void)
{
return 0x00502c90;
}
static inline u32 gr_gpc0_gpccs_gpc_exception_gcc_v(u32 r)
{
return (r >> 2) & 0x1;
}
static inline u32 gr_gpc0_gpccs_gpc_exception_tpc_v(u32 r)
{
return (r >> 16) & 0xff;

4
drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_gr_gm20b.h
View File

@@ -3138,6 +3138,10 @@ static inline u32 gr_gpc0_gpccs_gpc_exception_r(void)
{
return 0x00502c90;
}
static inline u32 gr_gpc0_gpccs_gpc_exception_gcc_v(u32 r)
{
return (r >> 2) & 0x1;
}
static inline u32 gr_gpc0_gpccs_gpc_exception_tpc_v(u32 r)
{
return (r >> 16) & 0xff;

4
drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_gr_gp106.h
View File

@@ -3382,6 +3382,10 @@ static inline u32 gr_gpc0_gpccs_gpc_exception_r(void)
{
return 0x00502c90;
}
static inline u32 gr_gpc0_gpccs_gpc_exception_gcc_v(u32 r)
{
return (r >> 2) & 0x1;
}
static inline u32 gr_gpc0_gpccs_gpc_exception_tpc_v(u32 r)
{
return (r >> 16) & 0xff;

4
drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_gr_gp10b.h
View File

@@ -3502,6 +3502,10 @@ static inline u32 gr_gpc0_gpccs_gpc_exception_r(void)
{
return 0x00502c90;
}
static inline u32 gr_gpc0_gpccs_gpc_exception_gcc_v(u32 r)
{
return (r >> 2) & 0x1;
}
static inline u32 gr_gpc0_gpccs_gpc_exception_tpc_v(u32 r)
{
return (r >> 16) & 0xff;