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gpu: nvgpu: Move PMU code to common/pmu
Move code interfacing with PMU tasks to common/pmu. JIRA NVGPU-961 Change-Id: Ie62611b0ffe1196d4bfdc740e03017e1894a834f Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1950991 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Terje Bergstrom
committed by
mobile promotions
mobile promotions
parent
e0e24ee091
commit
dce78f7332
321
drivers/gpu/nvgpu/common/pmu/pmgr/pwrdev.c
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321
drivers/gpu/nvgpu/common/pmu/pmgr/pwrdev.c
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/*
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* Copyright (c) 2016-2019, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#include <nvgpu/bios.h>
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#include <nvgpu/gk20a.h>
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#include <nvgpu/boardobjgrp.h>
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#include <nvgpu/boardobjgrp_e32.h>
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#include <nvgpu/string.h>
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#include "pwrdev.h"
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#include "pmgr.h"
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#include "gp106/bios_gp106.h"
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static int _pwr_device_pmudata_instget(struct gk20a *g,
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struct nv_pmu_boardobjgrp *pmuboardobjgrp,
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struct nv_pmu_boardobj **ppboardobjpmudata,
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u8 idx)
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{
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struct nv_pmu_pmgr_pwr_device_desc_table *ppmgrdevice =
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(struct nv_pmu_pmgr_pwr_device_desc_table *)pmuboardobjgrp;
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nvgpu_log_info(g, " ");
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/*check whether pmuboardobjgrp has a valid boardobj in index*/
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if (((u32)BIT(idx) &
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ppmgrdevice->hdr.data.super.obj_mask.super.data[0]) == 0U) {
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return -EINVAL;
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}
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*ppboardobjpmudata = (struct nv_pmu_boardobj *)
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&ppmgrdevice->devices[idx].data.board_obj;
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nvgpu_log_info(g, " Done");
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return 0;
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}
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static int _pwr_domains_pmudatainit_ina3221(struct gk20a *g,
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struct boardobj *board_obj_ptr,
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struct nv_pmu_boardobj *ppmudata)
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{
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struct nv_pmu_pmgr_pwr_device_desc_ina3221 *ina3221_desc;
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struct pwr_device_ina3221 *ina3221;
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int status = 0;
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u32 indx;
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status = boardobj_pmudatainit_super(g, board_obj_ptr, ppmudata);
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if (status != 0) {
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nvgpu_err(g,
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"error updating pmu boardobjgrp for pwr domain 0x%x",
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status);
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goto done;
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}
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ina3221 = (struct pwr_device_ina3221 *)board_obj_ptr;
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ina3221_desc = (struct nv_pmu_pmgr_pwr_device_desc_ina3221 *) ppmudata;
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ina3221_desc->super.power_corr_factor = ina3221->super.power_corr_factor;
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ina3221_desc->i2c_dev_idx = ina3221->super.i2c_dev_idx;
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ina3221_desc->configuration = ina3221->configuration;
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ina3221_desc->mask_enable = ina3221->mask_enable;
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/* configure NV_PMU_THERM_EVENT_EXT_OVERT */
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ina3221_desc->event_mask = BIT32(0);
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ina3221_desc->curr_correct_m = ina3221->curr_correct_m;
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ina3221_desc->curr_correct_b = ina3221->curr_correct_b;
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for (indx = 0; indx < NV_PMU_PMGR_PWR_DEVICE_INA3221_CH_NUM; indx++) {
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ina3221_desc->r_shuntm_ohm[indx] = ina3221->r_shuntm_ohm[indx];
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}
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done:
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return status;
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}
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static struct boardobj *construct_pwr_device(struct gk20a *g,
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void *pargs, u16 pargs_size, u8 type)
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{
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struct boardobj *board_obj_ptr = NULL;
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int status;
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u32 indx;
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struct pwr_device_ina3221 *pwrdev;
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struct pwr_device_ina3221 *ina3221 = (struct pwr_device_ina3221*)pargs;
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status = boardobj_construct_super(g, &board_obj_ptr,
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pargs_size, pargs);
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if (status != 0) {
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return NULL;
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}
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pwrdev = (struct pwr_device_ina3221*)board_obj_ptr;
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/* Set Super class interfaces */
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board_obj_ptr->pmudatainit = _pwr_domains_pmudatainit_ina3221;
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pwrdev->super.power_rail = ina3221->super.power_rail;
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pwrdev->super.i2c_dev_idx = ina3221->super.i2c_dev_idx;
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pwrdev->super.power_corr_factor = BIT32(12);
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pwrdev->super.bIs_inforom_config = false;
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/* Set INA3221-specific information */
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pwrdev->configuration = ina3221->configuration;
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pwrdev->mask_enable = ina3221->mask_enable;
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pwrdev->gpio_function = ina3221->gpio_function;
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pwrdev->curr_correct_m = ina3221->curr_correct_m;
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pwrdev->curr_correct_b = ina3221->curr_correct_b;
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for (indx = 0; indx < NV_PMU_PMGR_PWR_DEVICE_INA3221_CH_NUM; indx++) {
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pwrdev->r_shuntm_ohm[indx] = ina3221->r_shuntm_ohm[indx];
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}
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nvgpu_log_info(g, " Done");
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return board_obj_ptr;
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}
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static int devinit_get_pwr_device_table(struct gk20a *g,
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struct pwr_devices *ppwrdeviceobjs)
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{
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int status = 0;
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u8 *pwr_device_table_ptr = NULL;
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u8 *curr_pwr_device_table_ptr = NULL;
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struct boardobj *boardobj;
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struct pwr_sensors_2x_header pwr_sensor_table_header = { 0 };
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struct pwr_sensors_2x_entry pwr_sensor_table_entry = { 0 };
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u32 index;
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u32 obj_index = 0;
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u16 pwr_device_size;
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union {
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struct boardobj boardobj;
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struct pwr_device pwrdev;
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struct pwr_device_ina3221 ina3221;
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} pwr_device_data;
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nvgpu_log_info(g, " ");
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pwr_device_table_ptr = (u8 *)nvgpu_bios_get_perf_table_ptrs(g,
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g->bios.perf_token, POWER_SENSORS_TABLE);
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if (pwr_device_table_ptr == NULL) {
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status = -EINVAL;
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goto done;
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}
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nvgpu_memcpy((u8 *)&pwr_sensor_table_header, pwr_device_table_ptr,
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VBIOS_POWER_SENSORS_2X_HEADER_SIZE_08);
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if (pwr_sensor_table_header.version !=
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VBIOS_POWER_SENSORS_VERSION_2X) {
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status = -EINVAL;
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goto done;
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}
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if (pwr_sensor_table_header.header_size <
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VBIOS_POWER_SENSORS_2X_HEADER_SIZE_08) {
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status = -EINVAL;
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goto done;
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}
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if (pwr_sensor_table_header.table_entry_size !=
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VBIOS_POWER_SENSORS_2X_ENTRY_SIZE_15) {
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status = -EINVAL;
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goto done;
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}
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curr_pwr_device_table_ptr = (pwr_device_table_ptr +
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VBIOS_POWER_SENSORS_2X_HEADER_SIZE_08);
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for (index = 0; index < pwr_sensor_table_header.num_table_entries; index++) {
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bool use_fxp8_8 = false;
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u8 i2c_dev_idx;
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u8 device_type;
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curr_pwr_device_table_ptr += (pwr_sensor_table_header.table_entry_size * index);
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pwr_sensor_table_entry.flags0 = *curr_pwr_device_table_ptr;
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nvgpu_memcpy((u8 *)&pwr_sensor_table_entry.class_param0,
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(curr_pwr_device_table_ptr + 1),
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(VBIOS_POWER_SENSORS_2X_ENTRY_SIZE_15 - 1U));
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device_type = BIOS_GET_FIELD(u8, pwr_sensor_table_entry.flags0,
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NV_VBIOS_POWER_SENSORS_2X_ENTRY_FLAGS0_CLASS);
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if (device_type == NV_VBIOS_POWER_SENSORS_2X_ENTRY_FLAGS0_CLASS_I2C) {
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i2c_dev_idx = BIOS_GET_FIELD(u8,
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pwr_sensor_table_entry.class_param0,
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NV_VBIOS_POWER_SENSORS_2X_ENTRY_CLASS_PARAM0_I2C_INDEX);
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use_fxp8_8 = BIOS_GET_FIELD(bool,
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pwr_sensor_table_entry.class_param0,
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NV_VBIOS_POWER_SENSORS_2X_ENTRY_CLASS_PARAM0_I2C_USE_FXP8_8);
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pwr_device_data.ina3221.super.i2c_dev_idx = i2c_dev_idx;
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pwr_device_data.ina3221.r_shuntm_ohm[0].use_fxp8_8 = use_fxp8_8;
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pwr_device_data.ina3221.r_shuntm_ohm[1].use_fxp8_8 = use_fxp8_8;
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pwr_device_data.ina3221.r_shuntm_ohm[2].use_fxp8_8 = use_fxp8_8;
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pwr_device_data.ina3221.r_shuntm_ohm[0].rshunt_value =
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BIOS_GET_FIELD(u16,
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pwr_sensor_table_entry.sensor_param0,
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NV_VBIOS_POWER_SENSORS_2X_ENTRY_SENSOR_PARAM0_INA3221_RSHUNT0_MOHM);
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pwr_device_data.ina3221.r_shuntm_ohm[1].rshunt_value =
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BIOS_GET_FIELD(u16,
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pwr_sensor_table_entry.sensor_param0,
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NV_VBIOS_POWER_SENSORS_2X_ENTRY_SENSOR_PARAM0_INA3221_RSHUNT1_MOHM);
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pwr_device_data.ina3221.r_shuntm_ohm[2].rshunt_value =
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BIOS_GET_FIELD(u16,
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pwr_sensor_table_entry.sensor_param1,
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NV_VBIOS_POWER_SENSORS_2X_ENTRY_SENSOR_PARAM1_INA3221_RSHUNT2_MOHM);
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pwr_device_data.ina3221.configuration =
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BIOS_GET_FIELD(u16,
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pwr_sensor_table_entry.sensor_param1,
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NV_VBIOS_POWER_SENSORS_2X_ENTRY_SENSOR_PARAM1_INA3221_CONFIGURATION);
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pwr_device_data.ina3221.mask_enable =
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BIOS_GET_FIELD(u16,
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pwr_sensor_table_entry.sensor_param2,
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NV_VBIOS_POWER_SENSORS_2X_ENTRY_SENSOR_PARAM2_INA3221_MASKENABLE);
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pwr_device_data.ina3221.gpio_function =
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BIOS_GET_FIELD(u8,
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pwr_sensor_table_entry.sensor_param2,
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NV_VBIOS_POWER_SENSORS_2X_ENTRY_SENSOR_PARAM2_INA3221_GPIOFUNCTION);
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pwr_device_data.ina3221.curr_correct_m =
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BIOS_GET_FIELD(u16,
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pwr_sensor_table_entry.sensor_param3,
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NV_VBIOS_POWER_SENSORS_2X_ENTRY_SENSOR_PARAM3_INA3221_CURR_CORRECT_M);
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pwr_device_data.ina3221.curr_correct_b =
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BIOS_GET_FIELD(s16,
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pwr_sensor_table_entry.sensor_param3,
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NV_VBIOS_POWER_SENSORS_2X_ENTRY_SENSOR_PARAM3_INA3221_CURR_CORRECT_B);
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if (pwr_device_data.ina3221.curr_correct_m == 0U) {
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pwr_device_data.ina3221.curr_correct_m = BIT16(12);
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}
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pwr_device_size = sizeof(struct pwr_device_ina3221);
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} else {
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continue;
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}
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pwr_device_data.boardobj.type = CTRL_PMGR_PWR_DEVICE_TYPE_INA3221;
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pwr_device_data.pwrdev.power_rail = (u8)0;
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boardobj = construct_pwr_device(g, &pwr_device_data,
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pwr_device_size, pwr_device_data.boardobj.type);
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if (boardobj == NULL) {
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nvgpu_err(g,
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"unable to create pwr device for %d type %d", index, pwr_device_data.boardobj.type);
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status = -EINVAL;
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goto done;
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}
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status = boardobjgrp_objinsert(&ppwrdeviceobjs->super.super,
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boardobj, obj_index);
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if (status != 0) {
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nvgpu_err(g,
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"unable to insert pwr device boardobj for %d", index);
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status = -EINVAL;
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goto done;
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}
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++obj_index;
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}
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done:
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nvgpu_log_info(g, " done status %x", status);
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return status;
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}
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int pmgr_device_sw_setup(struct gk20a *g)
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{
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int status;
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struct boardobjgrp *pboardobjgrp = NULL;
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struct pwr_devices *ppwrdeviceobjs;
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/* Construct the Super Class and override the Interfaces */
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status = boardobjgrpconstruct_e32(g, &g->pmgr_pmu->pmgr_deviceobjs.super);
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if (status != 0) {
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nvgpu_err(g,
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"error creating boardobjgrp for pmgr devices, status - 0x%x",
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status);
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goto done;
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}
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pboardobjgrp = &g->pmgr_pmu->pmgr_deviceobjs.super.super;
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ppwrdeviceobjs = &(g->pmgr_pmu->pmgr_deviceobjs);
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/* Override the Interfaces */
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pboardobjgrp->pmudatainstget = _pwr_device_pmudata_instget;
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status = devinit_get_pwr_device_table(g, ppwrdeviceobjs);
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if (status != 0) {
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goto done;
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}
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done:
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nvgpu_log_info(g, " done status %x", status);
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return status;
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}
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