diff --git a/drivers/gpu/nvgpu/hal/gr/gr/gr_gk20a.c b/drivers/gpu/nvgpu/hal/gr/gr/gr_gk20a.c
index 21d2148bc..d46c2ce49 100644
--- a/drivers/gpu/nvgpu/hal/gr/gr/gr_gk20a.c
+++ b/drivers/gpu/nvgpu/hal/gr/gr/gr_gk20a.c
@@ -1212,7 +1212,8 @@ static int gr_gk20a_find_priv_offset_in_buffer(struct gk20a *g,
 	}
 
 	if ((addr_type == CTXSW_ADDR_TYPE_SYS) ||
-	    (addr_type == CTXSW_ADDR_TYPE_BE)) {
+	    (addr_type == CTXSW_ADDR_TYPE_BE) ||
+	    (addr_type == CTXSW_ADDR_TYPE_LTS_MAIN)) {
 		/* Find the offset in the FECS segment. */
 		offset_to_segment = sys_priv_offset * 256U;
 
diff --git a/drivers/gpu/nvgpu/hal/gr/gr/gr_pri_gk20a.h b/drivers/gpu/nvgpu/hal/gr/gr/gr_pri_gk20a.h
index c093dfc5b..90ae9671b 100644
--- a/drivers/gpu/nvgpu/hal/gr/gr/gr_pri_gk20a.h
+++ b/drivers/gpu/nvgpu/hal/gr/gr/gr_pri_gk20a.h
@@ -242,6 +242,7 @@ enum ctxsw_addr_type {
 	CTXSW_ADDR_TYPE_ETPC = 8,
 	CTXSW_ADDR_TYPE_ROP  = 9,
 	CTXSW_ADDR_TYPE_FBP  = 10,
+	CTXSW_ADDR_TYPE_LTS_MAIN  = 11,
 };
 
 #define PRI_BROADCAST_FLAGS_NONE		0U
diff --git a/drivers/gpu/nvgpu/include/nvgpu/gops_ltc.h b/drivers/gpu/nvgpu/include/nvgpu/gops_ltc.h
index 9e7fdbf0d..9ae279f2d 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/gops_ltc.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/gops_ltc.h
@@ -53,7 +53,7 @@ struct gops_ltc_intr {
 	void (*configure)(struct gk20a *g);
 	void (*en_illegal_compstat)(struct gk20a *g, bool enable);
 #if defined(CONFIG_NVGPU_HAL_NON_FUSA) && defined(CONFIG_NVGPU_NEXT)
-#include "include/nvgpu/nvgpu_next_gops_ltc.h"
+#include "include/nvgpu/nvgpu_next_gops_ltc_intr.h"
 #endif
 	/** @endcond DOXYGEN_SHOULD_SKIP_THIS */
 };
@@ -156,6 +156,9 @@ struct gops_ltc {
 	void (*split_ltc_broadcast_addr)(struct gk20a *g, u32 addr,
 						u32 *priv_addr_table,
 						u32 *priv_addr_table_index);
+#if defined(CONFIG_NVGPU_HAL_NON_FUSA) && defined(CONFIG_NVGPU_NEXT)
+#include "include/nvgpu/nvgpu_next_gops_ltc.h"
+#endif
 #endif
 	/** @endcond DOXYGEN_SHOULD_SKIP_THIS */