diff --git a/drivers/gpu/nvgpu/common/profiler/profiler.c b/drivers/gpu/nvgpu/common/profiler/profiler.c index 64dee3c18..150947867 100644 --- a/drivers/gpu/nvgpu/common/profiler/profiler.c +++ b/drivers/gpu/nvgpu/common/profiler/profiler.c @@ -303,10 +303,10 @@ static int nvgpu_profiler_bind_hwpm(struct nvgpu_profiler_object *prof, bool str if (prof->ctxsw[NVGPU_PROFILER_PM_RESOURCE_TYPE_HWPM_LEGACY]) { err = g->ops.gr.update_hwpm_ctxsw_mode(g, prof->tsg, 0, mode); } else { - if (g->ops.gr.reset_hwpm_pmm_registers != NULL) { - g->ops.gr.reset_hwpm_pmm_registers(g); + if (g->ops.perf.reset_hwpm_pmm_registers != NULL) { + g->ops.perf.reset_hwpm_pmm_registers(g); } - g->ops.gr.init_hwpm_pmm_register(g); + g->ops.perf.init_hwpm_pmm_register(g); } } else { err = g->ops.gr.update_hwpm_ctxsw_mode(g, prof->tsg, 0, mode); diff --git a/drivers/gpu/nvgpu/hal/gr/gr/gr_gk20a.c b/drivers/gpu/nvgpu/hal/gr/gr/gr_gk20a.c index ee114c214..8821c2fa3 100644 --- a/drivers/gpu/nvgpu/hal/gr/gr/gr_gk20a.c +++ b/drivers/gpu/nvgpu/hal/gr/gr/gr_gk20a.c @@ -105,8 +105,8 @@ int gr_gk20a_update_hwpm_ctxsw_mode(struct gk20a *g, } if ((mode == NVGPU_GR_CTX_HWPM_CTXSW_MODE_STREAM_OUT_CTXSW) && - (g->ops.gr.init_hwpm_pmm_register != NULL)) { - g->ops.gr.init_hwpm_pmm_register(g); + (g->ops.perf.init_hwpm_pmm_register != NULL)) { + g->ops.perf.init_hwpm_pmm_register(g); } } diff --git a/drivers/gpu/nvgpu/hal/gr/gr/gr_gv100.c b/drivers/gpu/nvgpu/hal/gr/gr/gr_gv100.c index d6fdafaa6..d6c380f98 100644 --- a/drivers/gpu/nvgpu/hal/gr/gr/gr_gv100.c +++ b/drivers/gpu/nvgpu/hal/gr/gr/gr_gv100.c @@ -38,7 +38,6 @@ #include "common/gr/gr_priv.h" #include -#include #ifdef CONFIG_NVGPU_TEGRA_FUSE void gr_gv100_set_gpc_tpc_mask(struct gk20a *g, u32 gpc_index) @@ -82,135 +81,3 @@ void gr_gv100_split_fbpa_broadcast_addr(struct gk20a *g, u32 addr, } } } - -void gr_gv100_set_pmm_register(struct gk20a *g, u32 offset, u32 val, - u32 num_chiplets, u32 chiplet_stride, u32 num_perfmons) -{ - u32 perfmon_index = 0; - u32 chiplet_index = 0; - u32 reg_offset = 0; - - for (chiplet_index = 0; chiplet_index < num_chiplets; chiplet_index++) { - for (perfmon_index = 0; perfmon_index < num_perfmons; - perfmon_index++) { - reg_offset = offset + perfmon_index * - perf_pmmsys_perdomain_offset_v() + - chiplet_index * chiplet_stride; - nvgpu_writel(g, reg_offset, val); - } - } -} - -void gr_gv100_get_num_hwpm_perfmon(struct gk20a *g, u32 *num_sys_perfmon, - u32 *num_fbp_perfmon, u32 *num_gpc_perfmon) -{ - int err; - u32 buf_offset_lo, buf_offset_addr, num_offsets; - u32 perfmon_index = 0; - - for (perfmon_index = 0; perfmon_index < - perf_pmmsys_engine_sel__size_1_v(); - perfmon_index++) { - err = gr_gk20a_get_pm_ctx_buffer_offsets(g, - perf_pmmsys_engine_sel_r(perfmon_index), - 1, - &buf_offset_lo, - &buf_offset_addr, - &num_offsets); - if (err != 0) { - break; - } - } - *num_sys_perfmon = perfmon_index; - - for (perfmon_index = 0; perfmon_index < - perf_pmmfbp_engine_sel__size_1_v(); - perfmon_index++) { - err = gr_gk20a_get_pm_ctx_buffer_offsets(g, - perf_pmmfbp_engine_sel_r(perfmon_index), - 1, - &buf_offset_lo, - &buf_offset_addr, - &num_offsets); - if (err != 0) { - break; - } - } - *num_fbp_perfmon = perfmon_index; - - for (perfmon_index = 0; perfmon_index < - perf_pmmgpc_engine_sel__size_1_v(); - perfmon_index++) { - err = gr_gk20a_get_pm_ctx_buffer_offsets(g, - perf_pmmgpc_engine_sel_r(perfmon_index), - 1, - &buf_offset_lo, - &buf_offset_addr, - &num_offsets); - if (err != 0) { - break; - } - } - *num_gpc_perfmon = perfmon_index; -} - -void gr_gv100_reset_hwpm_pmm_registers(struct gk20a *g) -{ - u32 count; - const u32 *perfmon_regs; - u32 i; - - if (g->num_sys_perfmon == 0U) { - g->ops.gr.get_num_hwpm_perfmon(g, &g->num_sys_perfmon, - &g->num_fbp_perfmon, &g->num_gpc_perfmon); - } - - perfmon_regs = g->ops.perf.get_hwpm_sys_perfmon_regs(&count); - - for (i = 0U; i < count; i++) { - g->ops.gr.set_pmm_register(g, perfmon_regs[i], 0U, 1U, - g->ops.perf.get_pmmsys_per_chiplet_offset(), - g->num_sys_perfmon); - } - - /* - * All the registers are broadcast ones so trigger - * g->ops.gr.set_pmm_register() only with 1 chiplet even for - * GPC and FBP chiplets. - */ - perfmon_regs = g->ops.perf.get_hwpm_fbp_perfmon_regs(&count); - - for (i = 0U; i < count; i++) { - g->ops.gr.set_pmm_register(g, perfmon_regs[i], 0U, 1U, - g->ops.perf.get_pmmfbp_per_chiplet_offset(), - g->num_fbp_perfmon); - } - - perfmon_regs = g->ops.perf.get_hwpm_gpc_perfmon_regs(&count); - - for (i = 0U; i < count; i++) { - g->ops.gr.set_pmm_register(g, perfmon_regs[i], 0U, 1U, - g->ops.perf.get_pmmgpc_per_chiplet_offset(), - g->num_gpc_perfmon); - } -} - -void gr_gv100_init_hwpm_pmm_register(struct gk20a *g) -{ - if (g->num_sys_perfmon == 0U) { - g->ops.gr.get_num_hwpm_perfmon(g, &g->num_sys_perfmon, - &g->num_fbp_perfmon, &g->num_gpc_perfmon); - } - - g->ops.gr.set_pmm_register(g, perf_pmmsys_engine_sel_r(0), 0xFFFFFFFFU, - 1U, g->ops.perf.get_pmmsys_per_chiplet_offset(), - g->num_sys_perfmon); - g->ops.gr.set_pmm_register(g, perf_pmmfbp_engine_sel_r(0), 0xFFFFFFFFU, - nvgpu_fbp_get_num_fbps(g->fbp), - g->ops.perf.get_pmmfbp_per_chiplet_offset(), - g->num_fbp_perfmon); - g->ops.gr.set_pmm_register(g, perf_pmmgpc_engine_sel_r(0), 0xFFFFFFFFU, - nvgpu_gr_config_get_gpc_count(g->gr->config), - g->ops.perf.get_pmmgpc_per_chiplet_offset(), - g->num_gpc_perfmon); -} diff --git a/drivers/gpu/nvgpu/hal/gr/gr/gr_gv100.h b/drivers/gpu/nvgpu/hal/gr/gr/gr_gv100.h index 1c6ca1108..32f9bd7ff 100644 --- a/drivers/gpu/nvgpu/hal/gr/gr/gr_gv100.h +++ b/drivers/gpu/nvgpu/hal/gr/gr/gr_gv100.h @@ -37,11 +37,5 @@ void gr_gv100_set_gpc_tpc_mask(struct gk20a *g, u32 gpc_index); void gr_gv100_split_fbpa_broadcast_addr(struct gk20a *g, u32 addr, u32 num_fbpas, u32 *priv_addr_table, u32 *t); -void gr_gv100_init_hwpm_pmm_register(struct gk20a *g); -void gr_gv100_reset_hwpm_pmm_registers(struct gk20a *g); -void gr_gv100_set_pmm_register(struct gk20a *g, u32 offset, u32 val, - u32 num_chiplets, u32 chiplet_stride, u32 num_perfmons); -void gr_gv100_get_num_hwpm_perfmon(struct gk20a *g, u32 *num_sys_perfmon, - u32 *num_fbp_perfmon, u32 *num_gpc_perfmon); #endif /* CONFIG_NVGPU_DEBUGGER */ #endif /* NVGPU_GR_GV100_H */ diff --git a/drivers/gpu/nvgpu/hal/init/hal_gm20b.c b/drivers/gpu/nvgpu/hal/init/hal_gm20b.c index a5cf3dc81..6c4d38f16 100644 --- a/drivers/gpu/nvgpu/hal/init/hal_gm20b.c +++ b/drivers/gpu/nvgpu/hal/init/hal_gm20b.c @@ -487,6 +487,7 @@ static const struct gops_gr gm20b_ops_gr = { .get_offset_in_gpccs_segment = gr_gk20a_get_offset_in_gpccs_segment, .process_context_buffer_priv_segment = gr_gk20a_process_context_buffer_priv_segment, .get_ctx_buffer_offsets = gr_gk20a_get_ctx_buffer_offsets, + .get_pm_ctx_buffer_offsets = gr_gk20a_get_pm_ctx_buffer_offsets, .find_priv_offset_in_buffer = gr_gk20a_find_priv_offset_in_buffer, .set_debug_mode = gm20b_gr_set_debug_mode, diff --git a/drivers/gpu/nvgpu/hal/init/hal_gp10b.c b/drivers/gpu/nvgpu/hal/init/hal_gp10b.c index c3465bf4d..0071995fb 100644 --- a/drivers/gpu/nvgpu/hal/init/hal_gp10b.c +++ b/drivers/gpu/nvgpu/hal/init/hal_gp10b.c @@ -564,6 +564,7 @@ static const struct gops_gr gp10b_ops_gr = { .get_offset_in_gpccs_segment = gr_gk20a_get_offset_in_gpccs_segment, .process_context_buffer_priv_segment = gr_gk20a_process_context_buffer_priv_segment, .get_ctx_buffer_offsets = gr_gk20a_get_ctx_buffer_offsets, + .get_pm_ctx_buffer_offsets = gr_gk20a_get_pm_ctx_buffer_offsets, .find_priv_offset_in_buffer = gr_gk20a_find_priv_offset_in_buffer, .set_debug_mode = gm20b_gr_set_debug_mode, diff --git a/drivers/gpu/nvgpu/hal/init/hal_gv11b.c b/drivers/gpu/nvgpu/hal/init/hal_gv11b.c index 59ffcc655..01fbc8936 100644 --- a/drivers/gpu/nvgpu/hal/init/hal_gv11b.c +++ b/drivers/gpu/nvgpu/hal/init/hal_gv11b.c @@ -650,11 +650,7 @@ static const struct gops_gr gv11b_ops_gr = { .set_sm_debug_mode = gv11b_gr_set_sm_debug_mode, .bpt_reg_info = gv11b_gr_bpt_reg_info, .update_smpc_ctxsw_mode = gr_gk20a_update_smpc_ctxsw_mode, - .get_num_hwpm_perfmon = gr_gv100_get_num_hwpm_perfmon, - .set_pmm_register = gr_gv100_set_pmm_register, .update_hwpm_ctxsw_mode = gr_gk20a_update_hwpm_ctxsw_mode, - .init_hwpm_pmm_register = gr_gv100_init_hwpm_pmm_register, - .reset_hwpm_pmm_registers = gr_gv100_reset_hwpm_pmm_registers, .clear_sm_error_state = gv11b_gr_clear_sm_error_state, .suspend_contexts = gr_gp10b_suspend_contexts, .resume_contexts = gr_gk20a_resume_contexts, @@ -689,6 +685,7 @@ static const struct gops_gr gv11b_ops_gr = { .get_offset_in_gpccs_segment = gr_gk20a_get_offset_in_gpccs_segment, .process_context_buffer_priv_segment = gr_gk20a_process_context_buffer_priv_segment, .get_ctx_buffer_offsets = gr_gk20a_get_ctx_buffer_offsets, + .get_pm_ctx_buffer_offsets = gr_gk20a_get_pm_ctx_buffer_offsets, .find_priv_offset_in_buffer = gr_gk20a_find_priv_offset_in_buffer, .set_debug_mode = gm20b_gr_set_debug_mode, @@ -1231,6 +1228,10 @@ static const struct gops_perf gv11b_ops_perf = { .get_hwpm_sys_perfmon_regs = gv11b_perf_get_hwpm_sys_perfmon_regs, .get_hwpm_gpc_perfmon_regs = gv11b_perf_get_hwpm_gpc_perfmon_regs, .get_hwpm_fbp_perfmon_regs = gv11b_perf_get_hwpm_fbp_perfmon_regs, + .set_pmm_register = gv11b_perf_set_pmm_register, + .get_num_hwpm_perfmon = gv11b_perf_get_num_hwpm_perfmon, + .init_hwpm_pmm_register = gv11b_perf_init_hwpm_pmm_register, + .reset_hwpm_pmm_registers = gv11b_perf_reset_hwpm_pmm_registers, }; #endif diff --git a/drivers/gpu/nvgpu/hal/init/hal_tu104.c b/drivers/gpu/nvgpu/hal/init/hal_tu104.c index 169a864f6..ef46284e9 100644 --- a/drivers/gpu/nvgpu/hal/init/hal_tu104.c +++ b/drivers/gpu/nvgpu/hal/init/hal_tu104.c @@ -693,12 +693,8 @@ static const struct gops_gr tu104_ops_gr = { .bpt_reg_info = gv11b_gr_bpt_reg_info, .update_smpc_ctxsw_mode = gr_gk20a_update_smpc_ctxsw_mode, .update_smpc_global_mode = tu104_gr_update_smpc_global_mode, - .get_num_hwpm_perfmon = gr_gv100_get_num_hwpm_perfmon, - .set_pmm_register = gr_gv100_set_pmm_register, .set_mmu_debug_mode = gm20b_gr_set_mmu_debug_mode, .update_hwpm_ctxsw_mode = gr_gk20a_update_hwpm_ctxsw_mode, - .init_hwpm_pmm_register = gr_gv100_init_hwpm_pmm_register, - .reset_hwpm_pmm_registers = gr_gv100_reset_hwpm_pmm_registers, .clear_sm_error_state = gv11b_gr_clear_sm_error_state, .suspend_contexts = gr_gp10b_suspend_contexts, .resume_contexts = gr_gk20a_resume_contexts, @@ -733,6 +729,7 @@ static const struct gops_gr tu104_ops_gr = { .get_offset_in_gpccs_segment = gr_tu104_get_offset_in_gpccs_segment, .process_context_buffer_priv_segment = gr_gk20a_process_context_buffer_priv_segment, .get_ctx_buffer_offsets = gr_gk20a_get_ctx_buffer_offsets, + .get_pm_ctx_buffer_offsets = gr_gk20a_get_pm_ctx_buffer_offsets, .find_priv_offset_in_buffer = gr_gk20a_find_priv_offset_in_buffer, .set_debug_mode = gm20b_gr_set_debug_mode, @@ -1300,6 +1297,10 @@ static const struct gops_perf tu104_ops_perf = { .get_hwpm_sys_perfmon_regs = tu104_perf_get_hwpm_sys_perfmon_regs, .get_hwpm_gpc_perfmon_regs = tu104_perf_get_hwpm_gpc_perfmon_regs, .get_hwpm_fbp_perfmon_regs = tu104_perf_get_hwpm_fbp_perfmon_regs, + .set_pmm_register = gv11b_perf_set_pmm_register, + .get_num_hwpm_perfmon = gv11b_perf_get_num_hwpm_perfmon, + .init_hwpm_pmm_register = gv11b_perf_init_hwpm_pmm_register, + .reset_hwpm_pmm_registers = gv11b_perf_reset_hwpm_pmm_registers, }; #endif diff --git a/drivers/gpu/nvgpu/hal/perf/perf_gv11b.c b/drivers/gpu/nvgpu/hal/perf/perf_gv11b.c index 985ea937c..6b36fd96e 100644 --- a/drivers/gpu/nvgpu/hal/perf/perf_gv11b.c +++ b/drivers/gpu/nvgpu/hal/perf/perf_gv11b.c @@ -22,6 +22,9 @@ #include #include +#include +#include +#include #include #include @@ -358,3 +361,135 @@ const u32 *gv11b_perf_get_hwpm_fbp_perfmon_regs(u32 *count) *count = sizeof(hwpm_fbp_perfmon_regs) / sizeof(hwpm_fbp_perfmon_regs[0]); return hwpm_fbp_perfmon_regs; } + +void gv11b_perf_set_pmm_register(struct gk20a *g, u32 offset, u32 val, + u32 num_chiplets, u32 chiplet_stride, u32 num_perfmons) +{ + u32 perfmon_index = 0; + u32 chiplet_index = 0; + u32 reg_offset = 0; + + for (chiplet_index = 0; chiplet_index < num_chiplets; chiplet_index++) { + for (perfmon_index = 0; perfmon_index < num_perfmons; + perfmon_index++) { + reg_offset = offset + perfmon_index * + perf_pmmsys_perdomain_offset_v() + + chiplet_index * chiplet_stride; + nvgpu_writel(g, reg_offset, val); + } + } +} + +void gv11b_perf_get_num_hwpm_perfmon(struct gk20a *g, u32 *num_sys_perfmon, + u32 *num_fbp_perfmon, u32 *num_gpc_perfmon) +{ + int err; + u32 buf_offset_lo, buf_offset_addr, num_offsets; + u32 perfmon_index = 0; + + for (perfmon_index = 0; perfmon_index < + perf_pmmsys_engine_sel__size_1_v(); + perfmon_index++) { + err = g->ops.gr.get_pm_ctx_buffer_offsets(g, + perf_pmmsys_engine_sel_r(perfmon_index), + 1, + &buf_offset_lo, + &buf_offset_addr, + &num_offsets); + if (err != 0) { + break; + } + } + *num_sys_perfmon = perfmon_index; + + for (perfmon_index = 0; perfmon_index < + perf_pmmfbp_engine_sel__size_1_v(); + perfmon_index++) { + err = g->ops.gr.get_pm_ctx_buffer_offsets(g, + perf_pmmfbp_engine_sel_r(perfmon_index), + 1, + &buf_offset_lo, + &buf_offset_addr, + &num_offsets); + if (err != 0) { + break; + } + } + *num_fbp_perfmon = perfmon_index; + + for (perfmon_index = 0; perfmon_index < + perf_pmmgpc_engine_sel__size_1_v(); + perfmon_index++) { + err = g->ops.gr.get_pm_ctx_buffer_offsets(g, + perf_pmmgpc_engine_sel_r(perfmon_index), + 1, + &buf_offset_lo, + &buf_offset_addr, + &num_offsets); + if (err != 0) { + break; + } + } + *num_gpc_perfmon = perfmon_index; +} + +void gv11b_perf_reset_hwpm_pmm_registers(struct gk20a *g) +{ + u32 count; + const u32 *perfmon_regs; + u32 i; + + if (g->num_sys_perfmon == 0U) { + g->ops.perf.get_num_hwpm_perfmon(g, &g->num_sys_perfmon, + &g->num_fbp_perfmon, &g->num_gpc_perfmon); + } + + perfmon_regs = g->ops.perf.get_hwpm_sys_perfmon_regs(&count); + + for (i = 0U; i < count; i++) { + g->ops.perf.set_pmm_register(g, perfmon_regs[i], 0U, 1U, + g->ops.perf.get_pmmsys_per_chiplet_offset(), + g->num_sys_perfmon); + } + + /* + * All the registers are broadcast ones so trigger + * g->ops.gr.set_pmm_register() only with 1 chiplet even for + * GPC and FBP chiplets. + */ + perfmon_regs = g->ops.perf.get_hwpm_fbp_perfmon_regs(&count); + + for (i = 0U; i < count; i++) { + g->ops.perf.set_pmm_register(g, perfmon_regs[i], 0U, 1U, + g->ops.perf.get_pmmfbp_per_chiplet_offset(), + g->num_fbp_perfmon); + } + + perfmon_regs = g->ops.perf.get_hwpm_gpc_perfmon_regs(&count); + + for (i = 0U; i < count; i++) { + g->ops.perf.set_pmm_register(g, perfmon_regs[i], 0U, 1U, + g->ops.perf.get_pmmgpc_per_chiplet_offset(), + g->num_gpc_perfmon); + } +} + +void gv11b_perf_init_hwpm_pmm_register(struct gk20a *g) +{ + if (g->num_sys_perfmon == 0U) { + g->ops.perf.get_num_hwpm_perfmon(g, &g->num_sys_perfmon, + &g->num_fbp_perfmon, &g->num_gpc_perfmon); + } + + g->ops.perf.set_pmm_register(g, perf_pmmsys_engine_sel_r(0), 0xFFFFFFFFU, + 1U, g->ops.perf.get_pmmsys_per_chiplet_offset(), + g->num_sys_perfmon); + g->ops.perf.set_pmm_register(g, perf_pmmfbp_engine_sel_r(0), 0xFFFFFFFFU, + nvgpu_fbp_get_num_fbps(g->fbp), + g->ops.perf.get_pmmfbp_per_chiplet_offset(), + g->num_fbp_perfmon); + g->ops.perf.set_pmm_register(g, perf_pmmgpc_engine_sel_r(0), 0xFFFFFFFFU, + nvgpu_gr_config_get_gpc_count(nvgpu_gr_get_config_ptr(g)), + g->ops.perf.get_pmmgpc_per_chiplet_offset(), + g->num_gpc_perfmon); +} diff --git a/drivers/gpu/nvgpu/hal/perf/perf_gv11b.h b/drivers/gpu/nvgpu/hal/perf/perf_gv11b.h index f8464dea4..ca5fb295d 100644 --- a/drivers/gpu/nvgpu/hal/perf/perf_gv11b.h +++ b/drivers/gpu/nvgpu/hal/perf/perf_gv11b.h @@ -56,5 +56,11 @@ const u32 *gv11b_perf_get_hwpm_sys_perfmon_regs(u32 *count); const u32 *gv11b_perf_get_hwpm_gpc_perfmon_regs(u32 *count); const u32 *gv11b_perf_get_hwpm_fbp_perfmon_regs(u32 *count); +void gv11b_perf_set_pmm_register(struct gk20a *g, u32 offset, u32 val, + u32 num_chiplets, u32 chiplet_stride, u32 num_perfmons); +void gv11b_perf_get_num_hwpm_perfmon(struct gk20a *g, u32 *num_sys_perfmon, + u32 *num_fbp_perfmon, u32 *num_gpc_perfmon); +void gv11b_perf_reset_hwpm_pmm_registers(struct gk20a *g); +void gv11b_perf_init_hwpm_pmm_register(struct gk20a *g); #endif /* CONFIG_NVGPU_DEBUGGER */ #endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/gops/debugger.h b/drivers/gpu/nvgpu/include/nvgpu/gops/debugger.h index eab61d67a..4d75cde86 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/gops/debugger.h +++ b/drivers/gpu/nvgpu/include/nvgpu/gops/debugger.h @@ -63,6 +63,13 @@ struct gops_perf { const u32 *(*get_hwpm_sys_perfmon_regs)(u32 *count); const u32 *(*get_hwpm_fbp_perfmon_regs)(u32 *count); const u32 *(*get_hwpm_gpc_perfmon_regs)(u32 *count); + void (*init_hwpm_pmm_register)(struct gk20a *g); + void (*get_num_hwpm_perfmon)(struct gk20a *g, u32 *num_sys_perfmon, + u32 *num_fbp_perfmon, + u32 *num_gpc_perfmon); + void (*set_pmm_register)(struct gk20a *g, u32 offset, u32 val, + u32 num_chiplets, u32 chiplet_stride, u32 num_perfmons); + void (*reset_hwpm_pmm_registers)(struct gk20a *g); }; struct gops_perfbuf { int (*perfbuf_enable)(struct gk20a *g, u64 offset, u32 size); diff --git a/drivers/gpu/nvgpu/include/nvgpu/gops/gr.h b/drivers/gpu/nvgpu/include/nvgpu/gops/gr.h index eb6394cc2..41e70ed82 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/gops/gr.h +++ b/drivers/gpu/nvgpu/include/nvgpu/gops/gr.h @@ -1083,13 +1083,6 @@ struct gops_gr { int (*ctx_patch_smpc)(struct gk20a *g, u32 addr, u32 data, struct nvgpu_gr_ctx *gr_ctx); - void (*init_hwpm_pmm_register)(struct gk20a *g); - void (*get_num_hwpm_perfmon)(struct gk20a *g, u32 *num_sys_perfmon, - u32 *num_fbp_perfmon, - u32 *num_gpc_perfmon); - void (*set_pmm_register)(struct gk20a *g, u32 offset, u32 val, - u32 num_chiplets, u32 chiplet_stride, u32 num_perfmons); - void (*reset_hwpm_pmm_registers)(struct gk20a *g); int (*dump_gr_regs)(struct gk20a *g, struct nvgpu_debug_context *o); int (*update_pc_sampling)(struct nvgpu_channel *ch, @@ -1169,6 +1162,11 @@ struct gops_gr { u32 max_offsets, u32 *offsets, u32 *offset_addrs, u32 *num_offsets); + int (*get_pm_ctx_buffer_offsets)(struct gk20a *g, + u32 addr, + u32 max_offsets, + u32 *offsets, u32 *offset_addrs, + u32 *num_offsets); int (*find_priv_offset_in_buffer)(struct gk20a *g, u32 addr, u32 *context_buffer, u32 context_buffer_size,