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gpu: nvgpu: add nvgpu-next infrastructure

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* As of now, working on multiple chip bringup in nvgpu-next repo has
   an issue because we end with losing control on source code (hard to
   find which part of the code belongs to which chip) and it's valuable
   history this affects chip migration on release.

 * To support multiple chip bringup simultaneously, we need new
   guidelines to avoid losing control on source code and make migration
   easier. This change adds links to nvgpu-next repo.

 * Updated return code to ENODEV for consistency
 * Updated ACR unittest to work with ENODEV return code

NOTE:
     These are the initial set of infrastructure changes, guidelines
     will evolve, and source code will get updated accordingly.

     Based on future chip features, Which part of the source code falls
     under nvgpu-next repo is decided.

JIRA NVGPU-6574

Change-Id: I81827e35d189c55554df00e255b527a4473e0338
Signed-off-by: Sagar Kadamati <skadamati@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2556793
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: svc_kernel_abi <svc_kernel_abi@nvidia.com>
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
This commit is contained in:
Sagar Kadamati
2021-07-09 20:57:49 +05:30
committed by mobile promotions
parent 9ffcb0fade
commit dd9b4364aa
11 changed files with 120 additions and 28 deletions
Download Patch File Download Diff File Expand all files Collapse all files

7
arch/nvgpu.yaml
View File

@@ -1,4 +1,4 @@
# Copyright (c) 2019-2020, NVIDIA CORPORATION. All Rights Reserved.
# Copyright (c) 2019-2021, NVIDIA CORPORATION. All Rights Reserved.
#
# Top level NVGPU architecure description in YAML.
#
@@ -67,3 +67,8 @@ nvgpu:
safe: no
children:
!include nvgpu-gpu_hw.yaml
nvgpu_next:
safe: no
children:
!include nvgpu-next.yaml

15
drivers/gpu/nvgpu/common/acr/acr.c
View File

@@ -42,6 +42,10 @@
#endif
#endif
#if defined(CONFIG_NVGPU_NON_FUSA) && defined(CONFIG_NVGPU_NEXT)
#include <nvgpu_next_acr.h>
#endif
/* ACR public API's */
bool nvgpu_acr_is_lsf_lazy_bootstrap(struct gk20a *g, struct nvgpu_acr *acr,
u32 falcon_id)
@@ -163,9 +167,14 @@ int nvgpu_acr_init(struct gk20a *g)
#endif /* CONFIG_NVGPU_NON_FUSA */
#endif
default:
nvgpu_kfree(g, g->acr);
err = -EINVAL;
nvgpu_err(g, "no support for GPUID %x", ver);
#if defined(CONFIG_NVGPU_NON_FUSA) && defined(CONFIG_NVGPU_NEXT)
if (nvgpu_next_acr_init(g))
#endif
{
nvgpu_kfree(g, g->acr);
err = -ENODEV;
nvgpu_err(g, "no support for GPUID %x", ver);
}
break;
}

12
drivers/gpu/nvgpu/common/acr/acr_blob_construct.c
View File

@@ -33,6 +33,10 @@
#include "acr_wpr.h"
#include "acr_priv.h"
#if defined(CONFIG_NVGPU_NON_FUSA) && defined(CONFIG_NVGPU_NEXT)
#include <nvgpu_next_firmware.h>
#endif
#define APP_IMEM_OFFSET (0)
#define APP_IMEM_ENTRY (0)
#define APP_DMEM_OFFSET (0)
@@ -210,7 +214,9 @@ int nvgpu_acr_lsf_fecs_ucode_details(struct gk20a *g, void *lsf_ucode_img)
#endif
default:
nvgpu_err(g, "no support for GPUID %x", ver);
#if defined(CONFIG_NVGPU_NON_FUSA) && defined(CONFIG_NVGPU_NEXT)
fecs_sig = nvgpu_next_request_fecs_firmware(g);
#endif
break;
}
@@ -361,7 +367,9 @@ int nvgpu_acr_lsf_gpccs_ucode_details(struct gk20a *g, void *lsf_ucode_img)
#endif
default:
nvgpu_err(g, "no support for GPUID %x", ver);
#if defined(CONFIG_NVGPU_NON_FUSA) && defined(CONFIG_NVGPU_NEXT)
gpccs_sig = nvgpu_next_request_gpccs_firmware(g);
#endif
break;
}

14
drivers/gpu/nvgpu/common/falcon/falcon.c
View File

@@ -34,6 +34,10 @@
#include "falcon_sw_ga10b.h"
#endif /* CONFIG_NVGPU_NON_FUSA */
#if defined(CONFIG_NVGPU_NON_FUSA) && defined(CONFIG_NVGPU_NEXT)
#include <nvgpu_next_falcon.h>
#endif
static bool is_falcon_valid(struct nvgpu_falcon *flcn)
{
if (flcn == NULL) {
@@ -476,8 +480,14 @@ static int falcon_sw_chip_init(struct gk20a *g, struct nvgpu_falcon *flcn)
gk20a_falcon_sw_init(flcn);
break;
default:
err = -EINVAL;
nvgpu_err(g, "no support for GPUID %x", ver);
#if defined(CONFIG_NVGPU_NON_FUSA) && defined(CONFIG_NVGPU_NEXT)
err = nvgpu_next_falcon_sw_init(g, flcn);
if (err != 0)
#endif
{
err = -ENODEV;
nvgpu_err(g, "no support for GPUID %x", ver);
}
break;
}

15
drivers/gpu/nvgpu/common/pmu/lsfm/lsfm.c
View File

@@ -34,6 +34,10 @@
#include "lsfm_sw_tu104.h"
#endif
#if defined(CONFIG_NVGPU_NON_FUSA) && defined(CONFIG_NVGPU_NEXT)
#include <nvgpu_next_lsfm.h>
#endif
static bool is_lsfm_supported(struct gk20a *g,
struct nvgpu_pmu *pmu, struct nvgpu_pmu_lsfm *lsfm)
{
@@ -170,9 +174,14 @@ int nvgpu_pmu_lsfm_init(struct gk20a *g, struct nvgpu_pmu_lsfm **lsfm)
break;
#endif
default:
nvgpu_kfree(g, *lsfm);
err = -EINVAL;
nvgpu_err(g, "no support for GPUID %x", ver);
#if defined(CONFIG_NVGPU_NON_FUSA) && defined(CONFIG_NVGPU_NEXT)
if (nvgpu_next_lsfm_sw_init(g, lsfm))
#endif
{
nvgpu_kfree(g, *lsfm);
err = -ENODEV;
nvgpu_err(g, "no support for GPUID %x", ver);
}
break;
}

24
drivers/gpu/nvgpu/common/pmu/perfmon/pmu_perfmon.c
View File

@@ -40,6 +40,10 @@
#include "pmu_perfmon_sw_ga10b.h"
#endif
#if defined(CONFIG_NVGPU_NON_FUSA) && defined(CONFIG_NVGPU_NEXT)
#include <nvgpu_next_perfmon.h>
#endif
static u8 get_perfmon_id(struct nvgpu_pmu *pmu)
{
struct gk20a *g = pmu->g;
@@ -60,10 +64,17 @@ static u8 get_perfmon_id(struct nvgpu_pmu *pmu)
unit_id = PMU_UNIT_PERFMON_T18X;
break;
default:
#if defined(CONFIG_NVGPU_NON_FUSA) && defined(CONFIG_NVGPU_NEXT)
unit_id = nvgpu_next_get_perfmon_id(pmu);
#else
unit_id = PMU_UNIT_INVALID;
#endif
break;
}
if (unit_id == PMU_UNIT_INVALID) {
nvgpu_err(g, "no support for %x", ver);
WARN_ON(true);
break;
}
return unit_id;
@@ -149,9 +160,14 @@ int nvgpu_pmu_initialize_perfmon(struct gk20a *g, struct nvgpu_pmu *pmu,
break;
#endif
default:
nvgpu_kfree(g, *perfmon_ptr);
err = -EINVAL;
nvgpu_err(g, "no support for GPUID %x", ver);
#if defined(CONFIG_NVGPU_NON_FUSA) && defined(CONFIG_NVGPU_NEXT)
if (nvgpu_next_pmu_initialize_perfmon(g, pmu, perfmon_ptr))
#endif
{
nvgpu_kfree(g, *perfmon_ptr);
err = -ENODEV;
nvgpu_err(g, "no support for GPUID %x", ver);
}
break;
}

15
drivers/gpu/nvgpu/common/pmu/pg/pmu_pg.c
View File

@@ -43,6 +43,10 @@
#endif /* CONFIG_NVGPU_NON_FUSA */
#include "pmu_pg.h"
#if defined(CONFIG_NVGPU_NON_FUSA) && defined(CONFIG_NVGPU_NEXT)
#include <nvgpu_next_pmu_pg.h>
#endif
static bool is_pg_supported(struct gk20a *g, struct nvgpu_pmu_pg *pg)
{
if (!g->support_ls_pmu || !g->can_elpg || pg == NULL) {
@@ -888,9 +892,14 @@ int nvgpu_pmu_pg_init(struct gk20a *g, struct nvgpu_pmu *pmu,
#endif /* CONFIG_NVGPU_NON_FUSA */
default:
nvgpu_kfree(g, *pg_p);
err = -EINVAL;
nvgpu_err(g, "no support for GPUID %x", ver);
#if defined(CONFIG_NVGPU_NON_FUSA) && defined(CONFIG_NVGPU_NEXT)
if (nvgpu_next_pg_sw_init(g, pg_p))
#endif
{
nvgpu_kfree(g, *pg_p);
err = -ENODEV;
nvgpu_err(g, "no support for GPUID %x", ver);
}
break;
}
exit:

27
drivers/gpu/nvgpu/hal/init/hal_init.c
View File

@@ -43,6 +43,10 @@
#endif
#endif
#if defined(CONFIG_NVGPU_NON_FUSA) && defined(CONFIG_NVGPU_NEXT)
#include <nvgpu_next_hal_init.h>
#endif
#include "hal/mc/mc_gm20b.h"
int nvgpu_init_hal(struct gk20a *g)
@@ -55,51 +59,56 @@ int nvgpu_init_hal(struct gk20a *g)
case GK20A_GPUID_GM20B:
nvgpu_log_info(g, "gm20b detected");
if (gm20b_init_hal(g) != 0) {
return -ENODEV;
err = -ENODEV;
}
break;
case GK20A_GPUID_GM20B_B:
nvgpu_log_info(g, "gm20b detected");
if (gm20b_init_hal(g) != 0) {
return -ENODEV;
err = -ENODEV;
}
break;
case NVGPU_GPUID_GP10B:
if (gp10b_init_hal(g) != 0) {
return -ENODEV;
err = -ENODEV;
}
break;
case NVGPU_GPUID_GA10B:
if (ga10b_init_hal(g) != 0) {
return -ENODEV;
err = -ENODEV;
}
break;
#endif
case NVGPU_GPUID_GV11B:
if (gv11b_init_hal(g) != 0) {
return -ENODEV;
err = -ENODEV;
}
break;
#if defined(CONFIG_NVGPU_DGPU) && defined(CONFIG_NVGPU_HAL_NON_FUSA)
case NVGPU_GPUID_TU104:
if (tu104_init_hal(g) != 0) {
return -ENODEV;
err = -ENODEV;
}
break;
#if defined(CONFIG_NVGPU_HAL_NON_FUSA) && defined(CONFIG_NVGPU_DGPU)
case NVGPU_GPUID_GA100:
if (ga100_init_hal(g) != 0) {
return -ENODEV;
err = -ENODEV;
}
break;
#endif
#endif
default:
nvgpu_err(g, "no support for %x", ver);
err = -ENODEV;
#if defined(CONFIG_NVGPU_HAL_NON_FUSA) && defined(CONFIG_NVGPU_NEXT)
if (nvgpu_next_init_hal(g) != 0)
#endif /* CONFIG_NVGPU_NEXT */
{
nvgpu_err(g, "no support for %x", ver);
err = -ENODEV;
}
break;
}

10
drivers/gpu/nvgpu/os/linux/module.c
View File

@@ -94,6 +94,10 @@
#include "cde.h"
#endif
#if defined(CONFIG_NVGPU_HAL_NON_FUSA) && defined(CONFIG_NVGPU_NEXT)
#include <nvgpu_next_chips.h>
#endif
#define GK20A_WAIT_FOR_IDLE_MS 2000
#define CREATE_TRACE_POINTS
@@ -691,6 +695,12 @@ static struct of_device_id tegra_gk20a_of_match[] = {
.data = &ga10b_vgpu_tegra_platform},
#endif
#endif
#endif
#ifdef CONFIG_NVGPU_NEXT
#if defined(CONFIG_NVGPU_HAL_NON_FUSA) && defined(CONFIG_NVGPU_NON_FUSA)
NVGPU_NEXT_COMPATIBLE_CHIPS
#endif
#endif
{ },
};

7
drivers/gpu/nvgpu/os/linux/platform_gk20a.h
View File

@@ -21,6 +21,10 @@
#include <nvgpu/lock.h>
#include <nvgpu/gk20a.h>
#if defined(CONFIG_NVGPU_NEXT)
#include <nvgpu_next_chips.h>
#endif
#define GK20A_CLKS_MAX 4
struct gk20a;
@@ -62,6 +66,9 @@ enum tegra_chip_id {
TEGRA_194,
TEGRA_194_VGPU,
TEGRA_234,
#ifdef CONFIG_NVGPU_NEXT
NVGPU_NEXT_TEGRA_CHIPS
#endif
};
struct gk20a_platform {

2
userspace/units/acr/nvgpu-acr.c
View File

@@ -944,7 +944,7 @@ int test_acr_init(struct unit_module *m,
g->params.gpu_impl = NV_PMC_BOOT_0_IMPLEMENTATION_INVALID;
err = nvgpu_acr_init(g);
if (err != -EINVAL) {
if (err != -ENODEV) {
unit_return_fail(m, "Version failure of chip for \
nvgpu_acr_init() didn't happen as expected\n");
}