gpu: nvgpu: Split clk.h into private and public

clk/clk*.h are used both by clk itself, and other units calling clk.
Move all public dependencies to include/nvgpu/pmu/clk.h

JIRA NVGPU-961

Change-Id: I54a8cefd8cb1d89782150ffcfc83992d39445f59
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1986070
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

drivers/gpu/nvgpu/clk/clk.c

@@ -29,6 +29,7 @@
 #include <nvgpu/pmuif/ctrlperf.h>
 #include <nvgpu/pmu/pstate.h>
 #include <nvgpu/pmu/volt.h>
+#include <nvgpu/pmu/clk.h>
 
 #include "clk.h"
 #include <nvgpu/timers.h>

drivers/gpu/nvgpu/clk/clk.h

@@ -21,8 +21,10 @@
  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  * DEALINGS IN THE SOFTWARE.
  */
-#ifndef NVGPU_CLK_H
+#ifndef NVGPU_CLK_CLK_H
-#define NVGPU_CLK_H
+#define NVGPU_CLK_CLK_H
+
+#include <nvgpu/types.h>
 
 #include "clk_vin.h"
 #include "clk_fll.h"
@@ -42,18 +44,6 @@ struct gk20a;
 
 int clk_set_boot_fll_clk(struct gk20a *g);
 
-/* clock related defines for GPUs supporting clock control from pmu*/
-struct clk_pmupstate {
-	struct avfsvinobjs avfs_vinobjs;
-	struct avfsfllobjs avfs_fllobjs;
-	struct clk_domains clk_domainobjs;
-	struct clk_progs clk_progobjs;
-	struct clk_vf_points clk_vf_pointobjs;
-	struct clk_mclk_state clk_mclk;
-	struct clk_freq_controllers clk_freq_controllers;
-	struct nvgpu_clk_freq_domain_grp freq_domain_grp_objs;
-};
-
 struct clockentry {
 		u8 vbios_clk_domain;
 		u8 clk_which;
@@ -67,25 +57,6 @@ struct change_fll_clk {
 		u32 voltuv;
 };
 
-struct set_fll_clk {
-		u32 voltuv;
-		u16 gpc2clkmhz;
-		u8 current_regime_id_gpc;
-		u8 target_regime_id_gpc;
-		u16 sys2clkmhz;
-		u8 current_regime_id_sys;
-		u8 target_regime_id_sys;
-		u16 xbar2clkmhz;
-		u8 current_regime_id_xbar;
-		u8 target_regime_id_xbar;
-		u16 nvdclkmhz;
-		u8 current_regime_id_nvd;
-		u8 target_regime_id_nvd;
-		u16 hostclkmhz;
-		u8 current_regime_id_host;
-		u8 target_regime_id_host;
-};
-
 #define NV_PERF_HEADER_4X_CLOCKS_DOMAINS_MAX_NUMCLKS         9U
 
 struct vbios_clock_domain {
@@ -125,10 +96,8 @@ struct vbios_clocks_table_1x_hal_clock_entry {
 #define PERF_CLK_PCIEGENCLK     12U
 #define PERF_CLK_NUM            13U
 
-int clk_init_pmupstate(struct gk20a *g);
+struct set_fll_clk;
-void clk_free_pmupstate(struct gk20a *g);
+
-int clk_pmu_vin_load(struct gk20a *g);
-int clk_pmu_clk_domains_load(struct gk20a *g);
 int clk_domain_print_vf_table(struct gk20a *g, u32 clkapidomain);
 int clk_domain_get_f_or_v(struct gk20a *g, u32 clkapidomain,
 	u16 *pclkmhz, u32 *pvoltuv, u8 railidx);
@@ -139,15 +108,6 @@ int clk_domain_volt_to_freq( struct gk20a *g, u8 clkdomain_idx,
 int clk_get_fll_clks(struct gk20a *g, struct set_fll_clk *setfllclk);
 int clk_set_fll_clks(struct gk20a *g, struct set_fll_clk *setfllclk);
 int clk_pmu_freq_controller_load(struct gk20a *g, bool bload, u8 bit_idx);
-u32 nvgpu_clk_vf_change_inject_data_fill_gv10x(struct gk20a *g,
-	struct nv_pmu_clk_rpc *rpccall,
-	struct set_fll_clk *setfllclk);
-u32 nvgpu_clk_vf_change_inject_data_fill_gp10x(struct gk20a *g,
-	struct nv_pmu_clk_rpc *rpccall,
-	struct set_fll_clk *setfllclk);
-int nvgpu_clk_set_boot_fll_clk_gv10x(struct gk20a *g);
-int nvgpu_clk_set_fll_clk_gv10x(struct gk20a *g);
 int clk_pmu_freq_effective_avg_load(struct gk20a *g, bool bload);
 int clk_freq_effective_avg(struct gk20a *g, u32 *freqkHz, u32  clkDomainMask);
-int nvgpu_clk_set_boot_fll_clk_tu10x(struct gk20a *g);
+#endif /* NVGPU_CLK_CLK_H */
-#endif /* NVGPU_CLK_H */

drivers/gpu/nvgpu/clk/clk_arb.c

@@ -36,8 +36,10 @@
 #include <nvgpu/pmu/pstate.h>
 #include <nvgpu/pmu/volt.h>
 #include <nvgpu/pmu/lpwr.h>
+#include <nvgpu/pmu/clk.h>
 
-#include "clk/clk.h"
+#include "clk.h"
+#include "clk_vf_point.h"
 
 int nvgpu_clk_notification_queue_alloc(struct gk20a *g,
 				struct nvgpu_clk_notification_queue *queue,

drivers/gpu/nvgpu/clk/clk_domain.h

@@ -28,6 +28,7 @@
 #include <nvgpu/pmuif/nvgpu_gpmu_cmdif.h>
 #include <nvgpu/boardobjgrp_e32.h>
 #include <nvgpu/boardobjgrpmask.h>
+#include <nvgpu/pmu/clk.h>
 
 #define CLK_DOMAIN_BOARDOBJGRP_VERSION 0x30
 #define CLK_DOMAIN_BOARDOBJGRP_VERSION_35 0x35
@@ -38,58 +39,10 @@
 struct clk_domains;
 struct clk_domain;
 
-/*data and function definition to talk to driver*/
-int clk_domain_sw_setup(struct gk20a *g);
-int clk_domain_pmu_setup(struct gk20a *g);
-
-typedef int clkproglink(struct gk20a *g, struct clk_pmupstate *pclk,
-			struct clk_domain *pdomain);
-
-typedef int clkvfsearch(struct gk20a *g, struct clk_pmupstate *pclk,
-			struct clk_domain *pdomain, u16 *clkmhz,
-			u32 *voltuv, u8 rail);
-
 typedef int clkgetslaveclk(struct gk20a *g, struct clk_pmupstate *pclk,
 			struct clk_domain *pdomain, u16 *clkmhz,
 			u16 masterclkmhz);
 
-typedef int clkgetfpoints(struct gk20a *g, struct clk_pmupstate *pclk,
-			struct clk_domain *pdomain, u32 *pfpointscount,
-			  u16 *pfreqpointsinmhz, u8 rail);
-
-struct clk_domains {
-	struct boardobjgrp_e32 super;
-	u8 n_num_entries;
-	u8 version;
-	bool b_enforce_vf_monotonicity;
-	bool b_enforce_vf_smoothening;
-	bool b_override_o_v_o_c;
-	bool b_debug_mode;
-	u32 vbios_domains;
-	u16 cntr_sampling_periodms;
-	struct boardobjgrpmask_e32 prog_domains_mask;
-	struct boardobjgrpmask_e32 master_domains_mask;
-	struct ctrl_clk_clk_delta  deltas;
-
-	struct clk_domain *ordered_noise_aware_list[CTRL_BOARDOBJ_MAX_BOARD_OBJECTS];
-
-	struct clk_domain *ordered_noise_unaware_list[CTRL_BOARDOBJ_MAX_BOARD_OBJECTS];
-};
-
-struct clk_domain {
-	struct boardobj super;
-	u32 api_domain;
-	u32 part_mask;
-	u32 domain;
-	u8 perf_domain_index;
-	u8 perf_domain_grp_idx;
-	u8 ratio_domain;
-	u8 usage;
-	clkproglink *clkdomainclkproglink;
-	clkvfsearch *clkdomainclkvfsearch;
-	clkgetfpoints *clkdomainclkgetfpoints;
-};
-
 struct clk_domain_3x {
 	struct clk_domain super;
 	bool b_noise_aware_capable;

drivers/gpu/nvgpu/clk/clk_fll.h

@@ -27,20 +27,8 @@
 #include <nvgpu/boardobjgrp_e32.h>
 #include <nvgpu/boardobjgrpmask.h>
 
-/*data and function definition to talk to driver*/
-int clk_fll_sw_setup(struct gk20a *g);
-int clk_fll_pmu_setup(struct gk20a *g);
-
-struct avfsfllobjs {
-	struct boardobjgrp_e32 super;
-	struct boardobjgrpmask_e32 lut_prog_master_mask;
-	u32 lut_step_size_uv;
-	u32 lut_min_voltage_uv;
-	u8 lut_num_entries;
-	u16 max_min_freq_mhz;
-};
-
 struct fll_device;
+struct avfsfllobjs;
 
 typedef u32 fll_lut_broadcast_slave_register(struct gk20a *g,
 	struct avfsfllobjs *pfllobjs,
@@ -67,9 +55,6 @@ struct fll_device {
 	fll_lut_broadcast_slave_register *lut_broadcast_slave_register;
 };
 
-u32 nvgpu_clk_get_vbios_clk_domain_gv10x( u32 vbios_domain);
-u32 nvgpu_clk_get_vbios_clk_domain_gp10x( u32 vbios_domain);
-
 #define CLK_FLL_LUT_VF_NUM_ENTRIES(pclk) \
 	((pclk)->avfs_fllobjs.lut_num_entries)
 

drivers/gpu/nvgpu/clk/clk_freq_controller.h

@@ -70,15 +70,4 @@ struct clk_freq_controller_pi {
 	bool bpoison;
 };
 
-struct clk_freq_controllers {
-	struct boardobjgrp_e32 super;
-	u32 sampling_period_ms;
-	struct boardobjgrpmask_e32 freq_ctrl_load_mask;
-	u8 volt_policy_idx;
-	void *pprereq_load;
-};
-
-int clk_freq_controller_sw_setup(struct gk20a *g);
-int clk_freq_controller_pmu_setup(struct gk20a *g);
-
 #endif /* NVGPU_CLK_FREQ_CONTROLLER_H */

drivers/gpu/nvgpu/clk/clk_freq_domain.h

@@ -33,12 +33,4 @@ struct nvgpu_clk_freq_domain {
 	u32 clk_domain;
 };
 
-struct nvgpu_clk_freq_domain_grp {
-	struct boardobjgrp_e32 super;
-	u32 init_flags;
-};
-
-int nvgpu_clk_freq_domain_sw_setup(struct gk20a *g);
-int nvgpu_clk_freq_domain_pmu_setup(struct gk20a *g);
-
 #endif /* NVGPU_CLK_FREQ_DOMAIN_H */

drivers/gpu/nvgpu/clk/clk_mclk.h

@@ -36,25 +36,4 @@ enum gk20a_mclk_speed {
 	gk20a_mclk_high_speed,
 };
 
-struct clk_mclk_state {
-	u32 speed;
-	struct nvgpu_mutex mclk_lock;
-	struct nvgpu_mutex data_lock;
-
-	u16 p5_min;
-	u16 p0_min;
-
-	void *vreg_buf;
-	bool init;
-
-#ifdef CONFIG_DEBUG_FS
-	s64 switch_max;
-	s64 switch_min;
-	u64 switch_num;
-	s64 switch_avg;
-	s64 switch_std;
-	bool debugfs_set;
-#endif
-};
-
 #endif /* NVGPU_CLK_MCLK_H */

drivers/gpu/nvgpu/clk/clk_prog.h

@@ -30,8 +30,6 @@
 #include <nvgpu/boardobjgrp_e255.h>
 #include <nvgpu/boardobjgrpmask.h>
 
-int clk_prog_sw_setup(struct gk20a *g);
-int clk_prog_pmu_setup(struct gk20a *g);
 struct clk_prog_1x_master;
 
 typedef int vf_flatten(struct gk20a *g, struct clk_pmupstate *pclk,
@@ -54,13 +52,6 @@ typedef int get_fpoints(struct gk20a *g, struct clk_pmupstate *pclk,
 			u16 **ppfreqpointsinmhz, u8 rail);
 
 
-struct clk_progs {
-	struct boardobjgrp_e255 super;
-	u8 slave_entry_count;
-	u8 vf_entry_count;
-	u8 vf_sec_entry_count;
-};
-
 struct clk_prog {
 	struct boardobj super;
 };

drivers/gpu/nvgpu/clk/clk_vf_point.h

@@ -26,12 +26,11 @@
 #include <nvgpu/pmuif/ctrlboardobj.h>
 #include <nvgpu/pmuif/nvgpu_gpmu_cmdif.h>
 #include <nvgpu/boardobjgrp_e32.h>
+#include <nvgpu/boardobjgrp_e255.h>
 #include <nvgpu/boardobjgrpmask.h>
 
 #define VMIN_PAD_UV 50000U
 
-int clk_vf_point_sw_setup(struct gk20a *g);
-int clk_vf_point_pmu_setup(struct gk20a *g);
 int clk_vf_point_cache(struct gk20a *g);
 struct nvgpu_clk_arb;
 struct nvgpu_clk_slave_freq{
@@ -45,10 +44,6 @@ struct nvgpu_clk_slave_freq{
 int nvgpu_clk_set_req_fll_clk_ps35(struct gk20a *g, struct nvgpu_clk_slave_freq *vf_point);
 int nvgpu_clk_arb_find_slave_points(struct nvgpu_clk_arb *arb,struct nvgpu_clk_slave_freq *vf_point);
 
-struct clk_vf_points {
-	struct boardobjgrp_e255 super;
-};
-
 struct clk_vf_point {
 	struct boardobj super;
 	u8  vfe_equ_idx;

drivers/gpu/nvgpu/clk/clk_vin.h

@@ -30,12 +30,6 @@
 struct vin_device;
 struct clk_pmupstate;
 
-struct avfsvinobjs {
-	struct boardobjgrp_e32 super;
-	u8 calibration_rev_vbios;
-	u8 calibration_rev_fused;
-	bool vin_is_disable_allowed;
-};
 typedef u32 vin_device_state_load(struct gk20a *g,
 			struct clk_pmupstate *clk, struct vin_device *pdev);
 
@@ -69,13 +63,6 @@ int construct_vindevice(struct gk20a *g, struct boardobj **ppboardobj,
 int vindeviceinit_pmudata_super(struct gk20a *g, struct boardobj *pboardobj,
 			struct nv_pmu_boardobj *pmudata);
 
-int clk_vin_sw_setup(struct gk20a *g);
+struct avfsvinobjs;
-int clk_vin_pmu_setup(struct gk20a *g);
-int clk_avfs_get_vin_cal_fuse_v10(struct gk20a *g,
-					struct avfsvinobjs *pvinobjs,
-					struct vin_device_v20 *pvindev);
-int clk_avfs_get_vin_cal_fuse_v20(struct gk20a *g,
-					struct avfsvinobjs *pvinobjs,
-					struct vin_device_v20 *pvindev);
 
 #endif /* NVGPU_CLK_VIN_H */

drivers/gpu/nvgpu/common/pmu/pmu_fw.c

@@ -32,10 +32,7 @@
 #include <nvgpu/boardobjgrp.h>
 #include <nvgpu/pmu/pstate.h>
 #include <nvgpu/pmu/volt.h>
-
+#include <nvgpu/pmu/clk.h>
-#include "clk/clk.h"
-#include "clk/clk_vin.h"
-#include "clk/clk_fll.h"
 
 /* PMU NS UCODE IMG */
 #define NVGPU_PMU_NS_UCODE_IMAGE	"gpmu_ucode.bin"

drivers/gpu/nvgpu/common/pmu/pmu_gp106.c

@@ -34,8 +34,6 @@
 #include "pmu_gp106.h"
 #include "acr_gp106.h"
 
-#include "clk/clk_mclk.h"
-
 #include <nvgpu/hw/gp106/hw_psec_gp106.h>
 #include <nvgpu/hw/gp106/hw_pwr_gp106.h>
 

drivers/gpu/nvgpu/gv100/clk_arb_gv100.c

@@ -22,7 +22,10 @@
 
 #include <nvgpu/gk20a.h>
 #include <nvgpu/clk_arb.h>
+#include <nvgpu/pmu/clk.h>
+
 #include "clk_arb_gv100.h"
+#include "clk/clk.h"
 
 u32 gv100_get_arbiter_clk_domains(struct gk20a *g)
 {

drivers/gpu/nvgpu/gv100/clk_gv100.c

@@ -34,6 +34,7 @@
 #include <nvgpu/timers.h>
 #include <nvgpu/gk20a.h>
 #include <nvgpu/clk.h>
+#include <nvgpu/pmu/clk.h>
 
 #include "clk_gv100.h"
 

drivers/gpu/nvgpu/include/nvgpu/boardobjgrpmask.h

@@ -24,6 +24,7 @@
 #define NVGPU_BOARDOBJGRPMASK_H
 
 #include <nvgpu/types.h>
+#include <nvgpu/pmuif/ctrlboardobj.h>
 
 struct ctrl_boardobjgrp_mask;
 

drivers/gpu/nvgpu/include/nvgpu/clk_arb.h

@@ -39,8 +39,6 @@ struct gk20a;
 #include <nvgpu/pmu/volt.h>
 #include <nvgpu/pmu/lpwr.h>
 
-#include "clk/clk.h"
-
 #define MAX_F_POINTS 256
 #define DEFAULT_EVENT_NUMBER 32
 

drivers/gpu/nvgpu/include/nvgpu/pmu/clk.h

@@ -0,0 +1,215 @@
+/*
+ * general clock structures & definitions
+ *
+ * Copyright (c) 2016-2019, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+#ifndef NVGPU_PMU_CLK_H
+#define NVGPU_PMU_CLK_H
+
+#include <nvgpu/boardobjgrp_e32.h>
+#include <nvgpu/boardobjgrp_e255.h>
+#include <nvgpu/boardobjgrpmask.h>
+#include <nvgpu/types.h>
+#include <nvgpu/pmuif/ctrlclk.h>
+
+struct clk_domain;
+struct gk20a;
+
+/* clock related defines for GPUs supporting clock control from pmu*/
+struct avfsvinobjs {
+	struct boardobjgrp_e32 super;
+	u8 calibration_rev_vbios;
+	u8 calibration_rev_fused;
+	bool vin_is_disable_allowed;
+};
+
+struct avfsfllobjs {
+	struct boardobjgrp_e32 super;
+	struct boardobjgrpmask_e32 lut_prog_master_mask;
+	u32 lut_step_size_uv;
+	u32 lut_min_voltage_uv;
+	u8 lut_num_entries;
+	u16 max_min_freq_mhz;
+};
+
+typedef int clkproglink(struct gk20a *g, struct clk_pmupstate *pclk,
+			struct clk_domain *pdomain);
+
+typedef int clkvfsearch(struct gk20a *g, struct clk_pmupstate *pclk,
+			struct clk_domain *pdomain, u16 *clkmhz,
+			u32 *voltuv, u8 rail);
+
+typedef int clkgetfpoints(struct gk20a *g, struct clk_pmupstate *pclk,
+			struct clk_domain *pdomain, u32 *pfpointscount,
+			  u16 *pfreqpointsinmhz, u8 rail);
+
+struct clk_domain {
+	struct boardobj super;
+	u32 api_domain;
+	u32 part_mask;
+	u32 domain;
+	u8 perf_domain_index;
+	u8 perf_domain_grp_idx;
+	u8 ratio_domain;
+	u8 usage;
+	clkproglink *clkdomainclkproglink;
+	clkvfsearch *clkdomainclkvfsearch;
+	clkgetfpoints *clkdomainclkgetfpoints;
+};
+
+struct clk_domains {
+	struct boardobjgrp_e32 super;
+	u8 n_num_entries;
+	u8 version;
+	bool b_enforce_vf_monotonicity;
+	bool b_enforce_vf_smoothening;
+	bool b_override_o_v_o_c;
+	bool b_debug_mode;
+	u32 vbios_domains;
+	u16 cntr_sampling_periodms;
+	struct boardobjgrpmask_e32 prog_domains_mask;
+	struct boardobjgrpmask_e32 master_domains_mask;
+	struct ctrl_clk_clk_delta  deltas;
+
+	struct clk_domain *ordered_noise_aware_list[CTRL_BOARDOBJ_MAX_BOARD_OBJECTS];
+
+	struct clk_domain *ordered_noise_unaware_list[CTRL_BOARDOBJ_MAX_BOARD_OBJECTS];
+};
+
+struct clk_progs {
+	struct boardobjgrp_e255 super;
+	u8 slave_entry_count;
+	u8 vf_entry_count;
+	u8 vf_sec_entry_count;
+};
+
+struct clk_vf_points {
+	struct boardobjgrp_e255 super;
+};
+
+struct clk_mclk_state {
+	u32 speed;
+	struct nvgpu_mutex mclk_lock;
+	struct nvgpu_mutex data_lock;
+
+	u16 p5_min;
+	u16 p0_min;
+
+	void *vreg_buf;
+	bool init;
+
+	s64 switch_max;
+	s64 switch_min;
+	u64 switch_num;
+	s64 switch_avg;
+	s64 switch_std;
+	bool debugfs_set;
+};
+
+struct clk_freq_controllers {
+	struct boardobjgrp_e32 super;
+	u32 sampling_period_ms;
+	struct boardobjgrpmask_e32 freq_ctrl_load_mask;
+	u8 volt_policy_idx;
+	void *pprereq_load;
+};
+
+struct nvgpu_clk_freq_domain_grp {
+	struct boardobjgrp_e32 super;
+	u32 init_flags;
+};
+
+struct clk_pmupstate {
+	struct avfsvinobjs avfs_vinobjs;
+	struct avfsfllobjs avfs_fllobjs;
+	struct clk_domains clk_domainobjs;
+	struct clk_progs clk_progobjs;
+	struct clk_vf_points clk_vf_pointobjs;
+	struct clk_mclk_state clk_mclk;
+	struct clk_freq_controllers clk_freq_controllers;
+	struct nvgpu_clk_freq_domain_grp freq_domain_grp_objs;
+};
+
+struct set_fll_clk {
+		u32 voltuv;
+		u16 gpc2clkmhz;
+		u8 current_regime_id_gpc;
+		u8 target_regime_id_gpc;
+		u16 sys2clkmhz;
+		u8 current_regime_id_sys;
+		u8 target_regime_id_sys;
+		u16 xbar2clkmhz;
+		u8 current_regime_id_xbar;
+		u8 target_regime_id_xbar;
+		u16 nvdclkmhz;
+		u8 current_regime_id_nvd;
+		u8 target_regime_id_nvd;
+		u16 hostclkmhz;
+		u8 current_regime_id_host;
+		u8 target_regime_id_host;
+};
+
+int clk_init_pmupstate(struct gk20a *g);
+void clk_free_pmupstate(struct gk20a *g);
+int nvgpu_clk_set_fll_clk_gv10x(struct gk20a *g);
+int clk_pmu_vin_load(struct gk20a *g);
+int clk_pmu_clk_domains_load(struct gk20a *g);
+u32 nvgpu_clk_vf_change_inject_data_fill_gv10x(struct gk20a *g,
+	struct nv_pmu_clk_rpc *rpccall,
+	struct set_fll_clk *setfllclk);
+u32 nvgpu_clk_vf_change_inject_data_fill_gp10x(struct gk20a *g,
+	struct nv_pmu_clk_rpc *rpccall,
+	struct set_fll_clk *setfllclk);
+int nvgpu_clk_set_boot_fll_clk_gv10x(struct gk20a *g);
+int nvgpu_clk_set_boot_fll_clk_tu10x(struct gk20a *g);
+
+int clk_vin_sw_setup(struct gk20a *g);
+int clk_vin_pmu_setup(struct gk20a *g);
+int clk_avfs_get_vin_cal_fuse_v10(struct gk20a *g,
+					struct avfsvinobjs *pvinobjs,
+					struct vin_device_v20 *pvindev);
+int clk_avfs_get_vin_cal_fuse_v20(struct gk20a *g,
+					struct avfsvinobjs *pvinobjs,
+					struct vin_device_v20 *pvindev);
+
+/*data and function definition to talk to driver*/
+int clk_fll_sw_setup(struct gk20a *g);
+int clk_fll_pmu_setup(struct gk20a *g);
+u32 nvgpu_clk_get_vbios_clk_domain_gv10x( u32 vbios_domain);
+u32 nvgpu_clk_get_vbios_clk_domain_gp10x( u32 vbios_domain);
+
+/*data and function definition to talk to driver*/
+int clk_domain_sw_setup(struct gk20a *g);
+int clk_domain_pmu_setup(struct gk20a *g);
+
+int clk_vf_point_sw_setup(struct gk20a *g);
+int clk_vf_point_pmu_setup(struct gk20a *g);
+
+int clk_prog_sw_setup(struct gk20a *g);
+int clk_prog_pmu_setup(struct gk20a *g);
+
+int nvgpu_clk_freq_domain_sw_setup(struct gk20a *g);
+int nvgpu_clk_freq_domain_pmu_setup(struct gk20a *g);
+
+int clk_freq_controller_sw_setup(struct gk20a *g);
+int clk_freq_controller_pmu_setup(struct gk20a *g);
+
+#endif /* NVGPU_PMU_CLK_H */

drivers/gpu/nvgpu/os/linux/debug_clk_gp106.c

@@ -17,6 +17,7 @@
 #include <linux/debugfs.h>
 
 #include <nvgpu/clk.h>
+#include <nvgpu/boardobjgrpmask.h>
 
 #include "os_linux.h"
 #include "clk/clk.h"

drivers/gpu/nvgpu/os/linux/ioctl_clk_arb.c

@@ -41,8 +41,6 @@
 #include <nvgpu/pmu/volt.h>
 #include <nvgpu/pmu/lpwr.h>
 
-#include "clk/clk.h"
-
 #ifdef CONFIG_DEBUG_FS
 #include "os_linux.h"
 #endif

drivers/gpu/nvgpu/os/linux/pci.c

@@ -31,8 +31,6 @@
 #include <nvgpu/string.h>
 
 #include "nvlink.h"
-#include "clk/clk.h"
-#include "clk/clk_mclk.h"
 #include "module.h"
 #include "intr.h"
 #include "sysfs.h"

drivers/gpu/nvgpu/pmu_perf/change_seq.c

@@ -27,9 +27,8 @@
 #include <nvgpu/timers.h>
 #include <nvgpu/pmuif/ctrlclk.h>
 #include <nvgpu/pmu/pstate.h>
+#include <nvgpu/pmu/clk.h>
 
-#include "clk/clk.h"
-#include "clk/clk_domain.h"
 #include "pmu_perf.h"
 
 #include "change_seq.h"

drivers/gpu/nvgpu/pmu_perf/perf_gv100.c

@@ -25,10 +25,10 @@
 #include <nvgpu/pmu.h>
 #include <nvgpu/bug.h>
 #include <nvgpu/gk20a.h>
+#include <nvgpu/pmu/clk.h>
 
-#include "clk/clk.h"
 #include "perf_gv100.h"
-#include "pmu_perf/pmu_perf.h"
+#include "pmu_perf.h"
 
 static int pmu_set_boot_clk_runcb_fn(void *arg)
 {

drivers/gpu/nvgpu/pstate/pstate.c

@@ -25,9 +25,8 @@
 #include <nvgpu/bios.h>
 #include <nvgpu/gk20a.h>
 #include <nvgpu/pmu.h>
+#include <nvgpu/pmu/clk.h>
 
-#include "clk/clk.h"
-#include "clk/clk_freq_domain.h"
 #include "pmu_perf/pmu_perf.h"
 #include "pmu_perf/change_seq.h"
 #include "pmgr/pmgr.h"