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gpu: nvgpu: gk20a: cde: Add base_post_divide param

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This patch adds a parameter to communicate the compression bit
backing store address we write to the hardware.

Change-Id: Ibc0e3d8304e893ddf15b4e03b405c7d85a73e95b
Signed-off-by: Arto Merilainen <amerilainen@nvidia.com>
Reviewed-on: http://git-master/r/454510
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
This commit is contained in:
Arto Merilainen
2014-08-08 16:18:30 +03:00
committed by Dan Willemsen
parent 8827b64518
commit dde83cb0d2
4 changed files with 10 additions and 0 deletions
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3
drivers/gpu/nvgpu/gk20a/cde_gk20a.c
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@@ -321,6 +321,9 @@ static int gk20a_cde_patch_params(struct gk20a_cde_ctx *cde_ctx)
if (new_data == 0) if (new_data == 0)
err = -EINVAL; err = -EINVAL;
break; break;
case TYPE_PARAM_BACKINGSTORE_BASE_HW:
new_data = g->gr.compbit_store.base_hw;
break;
default: default:
user_id = param->id - NUM_RESERVED_PARAMS; user_id = param->id - NUM_RESERVED_PARAMS;
if (user_id < 0 || user_id >= MAX_CDE_USER_PARAMS) if (user_id < 0 || user_id >= MAX_CDE_USER_PARAMS)

1
drivers/gpu/nvgpu/gk20a/cde_gk20a.h
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@@ -119,6 +119,7 @@ enum {
TYPE_PARAM_DESTINATION_SIZE, TYPE_PARAM_DESTINATION_SIZE,
TYPE_PARAM_BACKINGSTORE_SIZE, TYPE_PARAM_BACKINGSTORE_SIZE,
TYPE_PARAM_SOURCE_SMMU_ADDR, TYPE_PARAM_SOURCE_SMMU_ADDR,
TYPE_PARAM_BACKINGSTORE_BASE_HW,
NUM_RESERVED_PARAMS = 1024, NUM_RESERVED_PARAMS = 1024,
}; };

2
drivers/gpu/nvgpu/gk20a/ltc_common.c
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@@ -261,6 +261,8 @@ static void gk20a_ltc_init_cbc(struct gk20a *g, struct gr_gk20a *gr)
(u32)(compbit_store_base_iova & 0xffffffff), (u32)(compbit_store_base_iova & 0xffffffff),
compbit_base_post_divide); compbit_base_post_divide);
gr->compbit_store.base_hw = compbit_base_post_divide;
g->ops.ltc.cbc_ctrl(g, gk20a_cbc_op_invalidate, g->ops.ltc.cbc_ctrl(g, gk20a_cbc_op_invalidate,
0, max_comptag_lines - 1); 0, max_comptag_lines - 1);

4
drivers/gpu/nvgpu/gk20a/mm_gk20a.h
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@@ -172,6 +172,10 @@ struct compbit_store_desc {
struct sg_table *sgt; struct sg_table *sgt;
size_t size; size_t size;
u64 base_iova; u64 base_iova;
/* The value that is written to the hardware. This depends on
* on the number of ltcs and is not an address. */
u64 base_hw;
}; };
struct gk20a_buffer_state { struct gk20a_buffer_state {