gpu: nvgpu: gk20a: cde: Add base_post_divide param

This patch adds a parameter to communicate the compression bit
backing store address we write to the hardware.

Change-Id: Ibc0e3d8304e893ddf15b4e03b405c7d85a73e95b
Signed-off-by: Arto Merilainen <amerilainen@nvidia.com>
Reviewed-on: http://git-master/r/454510
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>

drivers/gpu/nvgpu/gk20a/cde_gk20a.c

@@ -321,6 +321,9 @@ static int gk20a_cde_patch_params(struct gk20a_cde_ctx *cde_ctx)
 			if (new_data == 0)
 				err = -EINVAL;
 			break;
+		case TYPE_PARAM_BACKINGSTORE_BASE_HW:
+			new_data = g->gr.compbit_store.base_hw;
+			break;
 		default:
 			user_id = param->id - NUM_RESERVED_PARAMS;
 			if (user_id < 0 || user_id >= MAX_CDE_USER_PARAMS)

drivers/gpu/nvgpu/gk20a/cde_gk20a.h

@@ -119,6 +119,7 @@ enum {
 	TYPE_PARAM_DESTINATION_SIZE,
 	TYPE_PARAM_BACKINGSTORE_SIZE,
 	TYPE_PARAM_SOURCE_SMMU_ADDR,
+	TYPE_PARAM_BACKINGSTORE_BASE_HW,
 	NUM_RESERVED_PARAMS = 1024,
 };
 

drivers/gpu/nvgpu/gk20a/ltc_common.c

@@ -261,6 +261,8 @@ static void gk20a_ltc_init_cbc(struct gk20a *g, struct gr_gk20a *gr)
 		   (u32)(compbit_store_base_iova & 0xffffffff),
 		   compbit_base_post_divide);
 
+	gr->compbit_store.base_hw = compbit_base_post_divide;
+
 	g->ops.ltc.cbc_ctrl(g, gk20a_cbc_op_invalidate,
 			    0, max_comptag_lines - 1);
 

drivers/gpu/nvgpu/gk20a/mm_gk20a.h

@@ -172,6 +172,10 @@ struct compbit_store_desc {
 	struct sg_table *sgt;
 	size_t size;
 	u64 base_iova;
+
+	/* The value that is written to the hardware. This depends on
+	 * on the number of ltcs and is not an address. */
+	u64 base_hw;
 };
 
 struct gk20a_buffer_state {