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gpu: nvgpu: init: fix MISRA 21.2 violations

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MISRA Rule 21.2 prohibits naming identifiers beginning with a double
underscore. This updates the function names __nvgpu_check_gpu_state()
and __gk20a_warn_on_no_regs() to comply.

JIRA NVGPU-3318

Change-Id: Ied2d168272a0f45fb8a08dda0e6fc798ebe3d22d
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2114656
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Philip Elcan
2019-05-08 10:03:51 -04:00
committed by mobile promotions
parent d9f1ee6d84
commit de2d39a422
3 changed files with 12 additions and 12 deletions
Download Patch File Download Diff File Expand all files Collapse all files

4
drivers/gpu/nvgpu/common/init/nvgpu_init.c
View File

@@ -61,7 +61,7 @@ bool is_nvgpu_gpu_state_valid(struct gk20a *g)
return true;
}
void __nvgpu_check_gpu_state(struct gk20a *g)
void nvgpu_check_gpu_state(struct gk20a *g)
{
if (!is_nvgpu_gpu_state_valid(g)) {
nvgpu_err(g, "Rebooting system!!");
@@ -69,7 +69,7 @@ void __nvgpu_check_gpu_state(struct gk20a *g)
}
}
void __gk20a_warn_on_no_regs(void)
void gk20a_warn_on_no_regs(void)
{
WARN_ONCE(true, "Attempted access to GPU regs after unmapping!");
}

4
drivers/gpu/nvgpu/include/nvgpu/gk20a.h
View File

@@ -2213,8 +2213,8 @@ static inline u32 nvgpu_get_poll_timeout(struct gk20a *g)
#define GK20A_NONSTALL_OPS_POST_EVENTS BIT32(1)
/* register accessors */
void __nvgpu_check_gpu_state(struct gk20a *g);
void __gk20a_warn_on_no_regs(void);
void nvgpu_check_gpu_state(struct gk20a *g);
void gk20a_warn_on_no_regs(void);
bool is_nvgpu_gpu_state_valid(struct gk20a *g);

16
drivers/gpu/nvgpu/os/linux/linux-io.c
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2017-2019, NVIDIA CORPORATION. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
@@ -22,7 +22,7 @@ void nvgpu_writel(struct gk20a *g, u32 r, u32 v)
struct nvgpu_os_linux *l = nvgpu_os_linux_from_gk20a(g);
if (unlikely(!l->regs)) {
__gk20a_warn_on_no_regs();
gk20a_warn_on_no_regs();
nvgpu_log(g, gpu_dbg_reg, "r=0x%x v=0x%x (failed)", r, v);
} else {
writel_relaxed(v, l->regs + r);
@@ -36,7 +36,7 @@ void nvgpu_writel_relaxed(struct gk20a *g, u32 r, u32 v)
struct nvgpu_os_linux *l = nvgpu_os_linux_from_gk20a(g);
if (unlikely(!l->regs)) {
__gk20a_warn_on_no_regs();
gk20a_warn_on_no_regs();
nvgpu_log(g, gpu_dbg_reg, "r=0x%x v=0x%x (failed)", r, v);
} else {
writel_relaxed(v, l->regs + r);
@@ -48,7 +48,7 @@ u32 nvgpu_readl(struct gk20a *g, u32 r)
u32 v = __nvgpu_readl(g, r);
if (v == 0xffffffff)
__nvgpu_check_gpu_state(g);
nvgpu_check_gpu_state(g);
return v;
}
@@ -59,7 +59,7 @@ u32 __nvgpu_readl(struct gk20a *g, u32 r)
u32 v = 0xffffffff;
if (unlikely(!l->regs)) {
__gk20a_warn_on_no_regs();
gk20a_warn_on_no_regs();
nvgpu_log(g, gpu_dbg_reg, "r=0x%x v=0x%x (failed)", r, v);
} else {
v = readl(l->regs + r);
@@ -74,7 +74,7 @@ void nvgpu_writel_loop(struct gk20a *g, u32 r, u32 v)
struct nvgpu_os_linux *l = nvgpu_os_linux_from_gk20a(g);
if (unlikely(!l->regs)) {
__gk20a_warn_on_no_regs();
gk20a_warn_on_no_regs();
nvgpu_log(g, gpu_dbg_reg, "r=0x%x v=0x%x (failed)", r, v);
} else {
nvgpu_wmb();
@@ -90,7 +90,7 @@ void nvgpu_bar1_writel(struct gk20a *g, u32 b, u32 v)
struct nvgpu_os_linux *l = nvgpu_os_linux_from_gk20a(g);
if (unlikely(!l->bar1)) {
__gk20a_warn_on_no_regs();
gk20a_warn_on_no_regs();
nvgpu_log(g, gpu_dbg_reg, "b=0x%x v=0x%x (failed)", b, v);
} else {
nvgpu_wmb();
@@ -105,7 +105,7 @@ u32 nvgpu_bar1_readl(struct gk20a *g, u32 b)
u32 v = 0xffffffff;
if (unlikely(!l->bar1)) {
__gk20a_warn_on_no_regs();
gk20a_warn_on_no_regs();
nvgpu_log(g, gpu_dbg_reg, "b=0x%x v=0x%x (failed)", b, v);
} else {
v = readl(l->bar1 + b);