From defc27ac9b9f605bbcc84efa6e7eea586b86a689 Mon Sep 17 00:00:00 2001 From: Seema Khowala Date: Thu, 9 May 2019 14:03:52 -0700 Subject: [PATCH] gpu: nvgpu: cg fix MISRA violations Fix Rule 10.1 Rename gk20a_readl and gk20a_writel Moved ELCG_* and BLCG_* defines from gk20a.h to cg.h Cleaned up checkpatch errors JIRA NVGPU-3424 Change-Id: I8d7de11dd7beb22c0fe44ff770af3b2609434385 Signed-off-by: Seema Khowala Reviewed-on: https://git-master.nvidia.com/r/2115908 Reviewed-by: mobile promotions Tested-by: mobile promotions --- .../gpu/nvgpu/common/power_features/cg/cg.c | 6 +- drivers/gpu/nvgpu/hal/therm/therm_gm20b.c | 61 ++++++++++--------- drivers/gpu/nvgpu/hal/therm/therm_gp106.c | 14 ++--- drivers/gpu/nvgpu/hal/therm/therm_gv11b.c | 3 + drivers/gpu/nvgpu/include/nvgpu/gk20a.h | 12 ---- .../nvgpu/include/nvgpu/power_features/cg.h | 19 ++++++ 6 files changed, 63 insertions(+), 52 deletions(-) diff --git a/drivers/gpu/nvgpu/common/power_features/cg/cg.c b/drivers/gpu/nvgpu/common/power_features/cg/cg.c index f77c65d4d..d0eeef528 100644 --- a/drivers/gpu/nvgpu/common/power_features/cg/cg.c +++ b/drivers/gpu/nvgpu/common/power_features/cg/cg.c @@ -25,11 +25,7 @@ #include #include -#define ELCG_MODE (1 << 0) -#define BLCG_MODE (1 << 1) -#define INVALID_MODE (1 << 2) - -static void nvgpu_cg_set_mode(struct gk20a *g, int cgmode, int mode_config) +static void nvgpu_cg_set_mode(struct gk20a *g, u32 cgmode, u32 mode_config) { u32 engine_idx; u32 active_engine_id = 0; diff --git a/drivers/gpu/nvgpu/hal/therm/therm_gm20b.c b/drivers/gpu/nvgpu/hal/therm/therm_gm20b.c index 988d3226f..6a24dbeed 100644 --- a/drivers/gpu/nvgpu/hal/therm/therm_gm20b.c +++ b/drivers/gpu/nvgpu/hal/therm/therm_gm20b.c @@ -23,6 +23,10 @@ */ #include +#include +#include +#include +#include #include #include "therm_gm20b.h" @@ -36,44 +40,44 @@ int gm20b_init_therm_setup_hw(struct gk20a *g) nvgpu_log_fn(g, " "); /* program NV_THERM registers */ - gk20a_writel(g, therm_use_a_r(), therm_use_a_ext_therm_0_enable_f() | + nvgpu_writel(g, therm_use_a_r(), therm_use_a_ext_therm_0_enable_f() | therm_use_a_ext_therm_1_enable_f() | therm_use_a_ext_therm_2_enable_f()); - gk20a_writel(g, therm_evt_ext_therm_0_r(), + nvgpu_writel(g, therm_evt_ext_therm_0_r(), therm_evt_ext_therm_0_slow_factor_f(0x2)); - gk20a_writel(g, therm_evt_ext_therm_1_r(), + nvgpu_writel(g, therm_evt_ext_therm_1_r(), therm_evt_ext_therm_1_slow_factor_f(0x6)); - gk20a_writel(g, therm_evt_ext_therm_2_r(), + nvgpu_writel(g, therm_evt_ext_therm_2_r(), therm_evt_ext_therm_2_slow_factor_f(0xe)); - gk20a_writel(g, therm_grad_stepping_table_r(0), + nvgpu_writel(g, therm_grad_stepping_table_r(0), therm_grad_stepping_table_slowdown_factor0_f(therm_grad_stepping_table_slowdown_factor0_fpdiv_by1p5_f()) | therm_grad_stepping_table_slowdown_factor1_f(therm_grad_stepping_table_slowdown_factor0_fpdiv_by2_f()) | therm_grad_stepping_table_slowdown_factor2_f(therm_grad_stepping_table_slowdown_factor0_fpdiv_by4_f()) | therm_grad_stepping_table_slowdown_factor3_f(therm_grad_stepping_table_slowdown_factor0_fpdiv_by8_f()) | therm_grad_stepping_table_slowdown_factor4_f(therm_grad_stepping_table_slowdown_factor0_fpdiv_by8_f())); - gk20a_writel(g, therm_grad_stepping_table_r(1), + nvgpu_writel(g, therm_grad_stepping_table_r(1), therm_grad_stepping_table_slowdown_factor0_f(therm_grad_stepping_table_slowdown_factor0_fpdiv_by8_f()) | therm_grad_stepping_table_slowdown_factor1_f(therm_grad_stepping_table_slowdown_factor0_fpdiv_by8_f()) | therm_grad_stepping_table_slowdown_factor2_f(therm_grad_stepping_table_slowdown_factor0_fpdiv_by8_f()) | therm_grad_stepping_table_slowdown_factor3_f(therm_grad_stepping_table_slowdown_factor0_fpdiv_by8_f()) | therm_grad_stepping_table_slowdown_factor4_f(therm_grad_stepping_table_slowdown_factor0_fpdiv_by8_f())); - v = gk20a_readl(g, therm_clk_timing_r(0)); + v = nvgpu_readl(g, therm_clk_timing_r(0)); v |= therm_clk_timing_grad_slowdown_enabled_f(); - gk20a_writel(g, therm_clk_timing_r(0), v); + nvgpu_writel(g, therm_clk_timing_r(0), v); - v = gk20a_readl(g, therm_config2_r()); + v = nvgpu_readl(g, therm_config2_r()); v |= therm_config2_grad_enable_f(1); v |= therm_config2_slowdown_factor_extended_f(1); - gk20a_writel(g, therm_config2_r(), v); + nvgpu_writel(g, therm_config2_r(), v); - gk20a_writel(g, therm_grad_stepping1_r(), + nvgpu_writel(g, therm_grad_stepping1_r(), therm_grad_stepping1_pdiv_duration_f(32)); - v = gk20a_readl(g, therm_grad_stepping0_r()); + v = nvgpu_readl(g, therm_grad_stepping0_r()); v |= therm_grad_stepping0_feature_enable_f(); - gk20a_writel(g, therm_grad_stepping0_r(), v); + nvgpu_writel(g, therm_grad_stepping0_r(), v); return 0; } @@ -89,7 +93,7 @@ int gm20b_elcg_init_idle_filters(struct gk20a *g) for (engine_id = 0; engine_id < f->num_engines; engine_id++) { active_engine_id = f->active_engines_list[engine_id]; - gate_ctrl = gk20a_readl(g, therm_gate_ctrl_r(active_engine_id)); + gate_ctrl = nvgpu_readl(g, therm_gate_ctrl_r(active_engine_id)); if (nvgpu_is_enabled(g, NVGPU_IS_FMODEL)) { gate_ctrl = set_field(gate_ctrl, @@ -104,17 +108,17 @@ int gm20b_elcg_init_idle_filters(struct gk20a *g) gate_ctrl = set_field(gate_ctrl, therm_gate_ctrl_eng_idle_filt_mant_m(), therm_gate_ctrl_eng_idle_filt_mant_f(2)); - gk20a_writel(g, therm_gate_ctrl_r(active_engine_id), gate_ctrl); + nvgpu_writel(g, therm_gate_ctrl_r(active_engine_id), gate_ctrl); } /* default fecs_idle_filter to 0 */ - idle_filter = gk20a_readl(g, therm_fecs_idle_filter_r()); + idle_filter = nvgpu_readl(g, therm_fecs_idle_filter_r()); idle_filter &= ~therm_fecs_idle_filter_value_m(); - gk20a_writel(g, therm_fecs_idle_filter_r(), idle_filter); + nvgpu_writel(g, therm_fecs_idle_filter_r(), idle_filter); /* default hubmmu_idle_filter to 0 */ - idle_filter = gk20a_readl(g, therm_hubmmu_idle_filter_r()); + idle_filter = nvgpu_readl(g, therm_hubmmu_idle_filter_r()); idle_filter &= ~therm_hubmmu_idle_filter_value_m(); - gk20a_writel(g, therm_hubmmu_idle_filter_r(), idle_filter); + nvgpu_writel(g, therm_hubmmu_idle_filter_r(), idle_filter); nvgpu_log_fn(g, "done"); return 0; @@ -129,7 +133,7 @@ void gm20b_therm_init_blcg_mode(struct gk20a *g, u32 mode, u32 engine) return; } - gate_ctrl = gk20a_readl(g, therm_gate_ctrl_r(engine)); + gate_ctrl = nvgpu_readl(g, therm_gate_ctrl_r(engine)); switch (mode) { case BLCG_RUN: @@ -153,14 +157,14 @@ void gm20b_therm_init_blcg_mode(struct gk20a *g, u32 mode, u32 engine) return; } - gk20a_writel(g, therm_gate_ctrl_r(engine), gate_ctrl); + nvgpu_writel(g, therm_gate_ctrl_r(engine), gate_ctrl); } void gm20b_therm_init_elcg_mode(struct gk20a *g, u32 mode, u32 engine) { u32 gate_ctrl; - gate_ctrl = gk20a_readl(g, therm_gate_ctrl_r(engine)); + gate_ctrl = nvgpu_readl(g, therm_gate_ctrl_r(engine)); if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_ELCG)) { return; @@ -192,29 +196,30 @@ void gm20b_therm_init_elcg_mode(struct gk20a *g, u32 mode, u32 engine) break; } - gk20a_writel(g, therm_gate_ctrl_r(engine), gate_ctrl); + nvgpu_writel(g, therm_gate_ctrl_r(engine), gate_ctrl); } void gm20b_therm_throttle_enable(struct gk20a *g, u32 val) { - gk20a_writel(g, therm_use_a_r(), val); + nvgpu_writel(g, therm_use_a_r(), val); } u32 gm20b_therm_throttle_disable(struct gk20a *g) { - u32 val = gk20a_readl(g, therm_use_a_r()); - gk20a_writel(g, therm_use_a_r(), 0); + u32 val = nvgpu_readl(g, therm_use_a_r()); + + nvgpu_writel(g, therm_use_a_r(), 0); return val; } void gm20b_therm_idle_slowdown_enable(struct gk20a *g, u32 val) { - gk20a_writel(g, therm_clk_slowdown_r(0), val); + nvgpu_writel(g, therm_clk_slowdown_r(0), val); } u32 gm20b_therm_idle_slowdown_disable(struct gk20a *g) { - u32 saved_val = gk20a_readl(g, therm_clk_slowdown_r(0)); + u32 saved_val = nvgpu_readl(g, therm_clk_slowdown_r(0)); u32 val = set_field(saved_val, therm_clk_slowdown_idle_factor_m(), therm_clk_slowdown_idle_factor_disabled_f()); nvgpu_writel_check(g, therm_clk_slowdown_r(0), val); diff --git a/drivers/gpu/nvgpu/hal/therm/therm_gp106.c b/drivers/gpu/nvgpu/hal/therm/therm_gp106.c index c8e92b18e..87e58900f 100644 --- a/drivers/gpu/nvgpu/hal/therm/therm_gp106.c +++ b/drivers/gpu/nvgpu/hal/therm/therm_gp106.c @@ -41,7 +41,7 @@ int gp106_get_internal_sensor_curr_temp(struct gk20a *g, u32 *temp_f24_8) int err = 0; u32 readval; - readval = gk20a_readl(g, therm_temp_sensor_tsense_r()); + readval = nvgpu_readl(g, therm_temp_sensor_tsense_r()); if ((therm_temp_sensor_tsense_state_v(readval) & therm_temp_sensor_tsense_state_valid_v()) == 0U) { @@ -74,7 +74,7 @@ int gp106_elcg_init_idle_filters(struct gk20a *g) for (engine_id = 0; engine_id < f->num_engines; engine_id++) { active_engine_id = f->active_engines_list[engine_id]; - gate_ctrl = gk20a_readl(g, therm_gate_ctrl_r(active_engine_id)); + gate_ctrl = nvgpu_readl(g, therm_gate_ctrl_r(active_engine_id)); gate_ctrl = set_field(gate_ctrl, therm_gate_ctrl_eng_idle_filt_exp_m(), @@ -85,17 +85,17 @@ int gp106_elcg_init_idle_filters(struct gk20a *g) gate_ctrl = set_field(gate_ctrl, therm_gate_ctrl_eng_delay_before_m(), therm_gate_ctrl_eng_delay_before_f(0)); - gk20a_writel(g, therm_gate_ctrl_r(active_engine_id), gate_ctrl); + nvgpu_writel(g, therm_gate_ctrl_r(active_engine_id), gate_ctrl); } /* default fecs_idle_filter to 0 */ - idle_filter = gk20a_readl(g, therm_fecs_idle_filter_r()); + idle_filter = nvgpu_readl(g, therm_fecs_idle_filter_r()); idle_filter &= ~therm_fecs_idle_filter_value_m(); - gk20a_writel(g, therm_fecs_idle_filter_r(), idle_filter); + nvgpu_writel(g, therm_fecs_idle_filter_r(), idle_filter); /* default hubmmu_idle_filter to 0 */ - idle_filter = gk20a_readl(g, therm_hubmmu_idle_filter_r()); + idle_filter = nvgpu_readl(g, therm_hubmmu_idle_filter_r()); idle_filter &= ~therm_hubmmu_idle_filter_value_m(); - gk20a_writel(g, therm_hubmmu_idle_filter_r(), idle_filter); + nvgpu_writel(g, therm_hubmmu_idle_filter_r(), idle_filter); nvgpu_log_fn(g, "done"); return 0; diff --git a/drivers/gpu/nvgpu/hal/therm/therm_gv11b.c b/drivers/gpu/nvgpu/hal/therm/therm_gv11b.c index c1a35227c..9949b3433 100644 --- a/drivers/gpu/nvgpu/hal/therm/therm_gv11b.c +++ b/drivers/gpu/nvgpu/hal/therm/therm_gv11b.c @@ -24,6 +24,9 @@ #include #include #include +#include +#include +#include #include #include "therm_gv11b.h" diff --git a/drivers/gpu/nvgpu/include/nvgpu/gk20a.h b/drivers/gpu/nvgpu/include/nvgpu/gk20a.h index 9c8f49a6c..6d449e2b3 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/gk20a.h +++ b/drivers/gpu/nvgpu/include/nvgpu/gk20a.h @@ -207,18 +207,6 @@ enum nvgpu_event_id_type { * in nvgpu/enabled.h */ -/* Parameters for init_elcg_mode/init_blcg_mode */ -enum { - ELCG_RUN, /* clk always run, i.e. disable elcg */ - ELCG_STOP, /* clk is stopped */ - ELCG_AUTO /* clk will run when non-idle, standard elcg mode */ -}; - -enum { - BLCG_RUN, /* clk always run, i.e. disable blcg */ - BLCG_AUTO /* clk will run when non-idle, standard blcg mode */ -}; - struct gpu_ops { struct { int (*determine_L2_size_bytes)(struct gk20a *gk20a); diff --git a/drivers/gpu/nvgpu/include/nvgpu/power_features/cg.h b/drivers/gpu/nvgpu/include/nvgpu/power_features/cg.h index eb6c28a54..c0000de89 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/power_features/cg.h +++ b/drivers/gpu/nvgpu/include/nvgpu/power_features/cg.h @@ -25,6 +25,25 @@ #define NVGPU_POWER_FEATURES_CG_H #include +#include + +/* Parameters for init_elcg_mode/init_blcg_mode */ + +/* clk always run, i.e. disable elcg */ +#define ELCG_RUN BIT32(0U) +/* clk is stopped */ +#define ELCG_STOP BIT32(1U) +/* clk will run when non-idle, standard elcg mode */ +#define ELCG_AUTO BIT32(2U) + +/* clk always run, i.e. disable blcg */ +#define BLCG_RUN BIT32(0U) +/* clk will run when non-idle, standard blcg mode */ +#define BLCG_AUTO BIT32(1U) + +#define ELCG_MODE BIT32(0U) +#define BLCG_MODE BIT32(1U) +#define INVALID_MODE BIT32(2U) struct gk20a; struct nvgpu_fifo;