gpu: nvgpu: vgpu: get constants of gpc_tpc_count/mask arrays

It'll cover multi-gpcs.

JIRA VFND-2103

Change-Id: Ie82bdaad360294696c5a679d694f6f0e2364ca2e
Signed-off-by: Richard Zhao <rizhao@nvidia.com>
Reviewed-on: http://git-master/r/1194631
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vladislav Buzov <vbuzov@nvidia.com>

drivers/gpu/nvgpu/vgpu/gr_vgpu.c

@@ -617,18 +617,6 @@ static int vgpu_gr_free_obj_ctx(struct channel_gk20a  *c,
 	return 0;
 }
 
-static u32 vgpu_gr_get_gpc_tpc_count(struct gk20a *g, u32 gpc_index)
-{
-	u32 data;
-
-	WARN_ON(gpc_index > 0);
-
-	if (vgpu_get_attribute(vgpu_get_handle(g),
-			TEGRA_VGPU_ATTRIB_GPC0_TPC_COUNT, &data))
-		gk20a_err(dev_from_gk20a(g), "failed to retrieve gpc0_tpc_count");
-	return data;
-}
-
 static int vgpu_gr_init_gr_config(struct gk20a *g, struct gr_gk20a *gr)
 {
 	struct vgpu_priv_data *priv = vgpu_get_priv_data(g);
@@ -640,11 +628,6 @@ static int vgpu_gr_init_gr_config(struct gk20a *g, struct gr_gk20a *gr)
 	gr->gpc_count = priv->constants.gpc_count;
 	gr->max_tpc_per_gpc_count = priv->constants.max_tpc_per_gpc_count;
 
-	if (vgpu_get_attribute(vgpu_get_handle(g),
-			TEGRA_VGPU_ATTRIB_TPC_COUNT,
-			&gr->tpc_count))
-		return -ENOMEM;
-
 	gr->max_tpc_count = gr->max_gpc_count * gr->max_tpc_per_gpc_count;
 
 	gr->gpc_tpc_count = kzalloc(gr->gpc_count * sizeof(u32), GFP_KERNEL);
@@ -660,9 +643,12 @@ static int vgpu_gr_init_gr_config(struct gk20a *g, struct gr_gk20a *gr)
 	if (!gr->sm_to_cluster)
 		goto cleanup;
 
+	gr->tpc_count = 0;
 	for (gpc_index = 0; gpc_index < gr->gpc_count; gpc_index++) {
 		gr->gpc_tpc_count[gpc_index] =
-			vgpu_gr_get_gpc_tpc_count(g, gpc_index);
+			priv->constants.gpc_tpc_count[gpc_index];
+
+		gr->tpc_count += gr->gpc_tpc_count[gpc_index];
 
 		if (g->ops.gr.get_gpc_tpc_mask)
 			gr->gpc_tpc_mask[gpc_index] =
@@ -739,15 +725,9 @@ static int vgpu_gr_get_zcull_info(struct gk20a *g, struct gr_gk20a *gr,
 
 static u32 vgpu_gr_get_gpc_tpc_mask(struct gk20a *g, u32 gpc_index)
 {
-	u32 data;
+	struct vgpu_priv_data *priv = vgpu_get_priv_data(g);
 
-	WARN_ON(gpc_index > 0);
+	return priv->constants.gpc_tpc_mask[gpc_index];
-
-	if (vgpu_get_attribute(vgpu_get_handle(g),
-			TEGRA_VGPU_ATTRIB_GPC0_TPC_MASK, &data))
-		gk20a_err(dev_from_gk20a(g), "failed to retrieve gpc0_tpc_mask");
-
-	return data;
 }
 
 static u32 vgpu_gr_get_max_fbps_count(struct gk20a *g)

drivers/gpu/nvgpu/vgpu/vgpu.c

@@ -504,6 +504,13 @@ static int vgpu_get_constants(struct gk20a *g)
 		return err;
 	}
 
+	if (unlikely(p->gpc_count > TEGRA_VGPU_MAX_GPC_COUNT ||
+		p->max_tpc_per_gpc_count > TEGRA_VGPU_MAX_TPC_COUNT_PER_GPC)) {
+		gk20a_err(g->dev, "gpc_count %d max_tpc_per_gpc %d overflow",
+			(int)p->gpc_count, (int)p->max_tpc_per_gpc_count);
+		return -EINVAL;
+	}
+
 	priv->constants = *p;
 	return 0;
 }

include/linux/tegra_vgpu.h

@@ -117,7 +117,7 @@ enum {
 	TEGRA_VGPU_ATTRIB_COMPTAG_LINES = 3, /* deprecated */
 	TEGRA_VGPU_ATTRIB_GPC_COUNT = 4, /* deprecated */
 	TEGRA_VGPU_ATTRIB_MAX_TPC_PER_GPC_COUNT = 5, /* deprecated */
-	TEGRA_VGPU_ATTRIB_MAX_TPC_COUNT = 6,
+	TEGRA_VGPU_ATTRIB_MAX_TPC_COUNT = 6, /* deprecated */
 	TEGRA_VGPU_ATTRIB_PMC_BOOT_0 = 7, /* deprecated */
 	TEGRA_VGPU_ATTRIB_L2_SIZE = 8, /* deprecated */
 	TEGRA_VGPU_ATTRIB_GPC0_TPC0_SM_ARCH = 9, /* deprecated */
@@ -125,13 +125,13 @@ enum {
 	TEGRA_VGPU_ATTRIB_FBP_EN_MASK = 11, /* deprecated */
 	TEGRA_VGPU_ATTRIB_MAX_LTC_PER_FBP = 12, /* deprecated */
 	TEGRA_VGPU_ATTRIB_MAX_LTS_PER_LTC = 13, /* deprecated */
-	TEGRA_VGPU_ATTRIB_GPC0_TPC_MASK = 14,
+	TEGRA_VGPU_ATTRIB_GPC0_TPC_MASK = 14, /* deprecated */
 	TEGRA_VGPU_ATTRIB_CACHELINE_SIZE = 15, /* deprecated */
 	TEGRA_VGPU_ATTRIB_COMPTAGS_PER_CACHELINE = 16, /* deprecated */
 	TEGRA_VGPU_ATTRIB_SLICES_PER_LTC = 17, /* deprecated */
 	TEGRA_VGPU_ATTRIB_LTC_COUNT = 18, /* deprecated */
 	TEGRA_VGPU_ATTRIB_TPC_COUNT = 19, /* deprecated */
-	TEGRA_VGPU_ATTRIB_GPC0_TPC_COUNT = 20,
+	TEGRA_VGPU_ATTRIB_GPC0_TPC_COUNT = 20, /* deprecated */
 	TEGRA_VGPU_ATTRIB_MAX_FREQ = 21, /* deprecated */
 };
 
@@ -403,6 +403,9 @@ struct tegra_vgpu_gpu_clk_rate_params {
 	u32 rate; /* in kHz */
 };
 
+#define TEGRA_VGPU_MAX_GPC_COUNT 16
+#define TEGRA_VGPU_MAX_TPC_COUNT_PER_GPC 16
+
 struct tegra_vgpu_constants_params {
 	u32 arch;
 	u32 impl;
@@ -427,6 +430,11 @@ struct tegra_vgpu_constants_params {
 	u32 fbp_en_mask;
 	u32 ltc_per_fbp;
 	u32 max_lts_per_ltc;
+	u8 gpc_tpc_count[TEGRA_VGPU_MAX_GPC_COUNT];
+	/* mask bits should be equal or larger than
+	 * TEGRA_VGPU_MAX_TPC_COUNT_PER_GPC
+	 */
+	u16 gpc_tpc_mask[TEGRA_VGPU_MAX_GPC_COUNT];
 };
 
 struct tegra_vgpu_cmd_msg {