gpu: nvgpu: unit: add tests for common.gr.setup

Add tests to cover common.gr.setup subunit. This includes
g->ops.gr.setup.alloc_obj_ctx
g->ops.gr.setup.set_preemption_mode
g->ops.gr.setup.free_gr_ctx and
g->ops.gr.setup.free_subctx.

Update register space to include the registers used by
context creation.
Update SWUT files for doxygen.

Jira NVGPU-3968

Change-Id: I3ab539d18584231142a1945d621d015b7ca772de
Signed-off-by: vinodg <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2244825
GVS: Gerrit_Virtual_Submit
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

Makefile.umbrella.tmk

@@ -85,6 +85,7 @@ NV_REPOSITORY_COMPONENTS += userspace/units/gr
 NV_REPOSITORY_COMPONENTS += userspace/units/gr/falcon
 NV_REPOSITORY_COMPONENTS += userspace/units/gr/config
 NV_REPOSITORY_COMPONENTS += userspace/units/gr/init
+NV_REPOSITORY_COMPONENTS += userspace/units/gr/setup
 NV_REPOSITORY_COMPONENTS += userspace/units/gr/intr
 NV_REPOSITORY_COMPONENTS += userspace/units/acr
 NV_REPOSITORY_COMPONENTS += userspace/units/cg

userspace/Makefile.sources

@@ -98,5 +98,6 @@ UNITS :=				\
 	$(UNIT_SRC)/gr/config		\
 	$(UNIT_SRC)/gr/init		\
 	$(UNIT_SRC)/gr/intr		\
+	$(UNIT_SRC)/gr/setup		\
 	$(UNIT_SRC)/acr			\
 	$(UNIT_SRC)/cg

userspace/SWUTS.h

@@ -72,6 +72,7 @@
  *   - @ref SWUTS-channel_os
  *   - @ref SWUTS-top
  *   - @ref SWUTS-gr
+ *   - @ref SWUTS-gr-setup
  *   - @ref SWUTS-gr-intr
  *   - @ref SWUTS-gr-config
  *

userspace/SWUTS.sources

@@ -42,5 +42,6 @@ INPUT += ../../../userspace/units/ptimer/nvgpu-ptimer.h
 INPUT += ../../../userspace/units/acr/nvgpu-acr.h
 INPUT += ../../../userspace/units/top/nvgpu-top.h
 INPUT += ../../../userspace/units/gr/nvgpu-gr.h
+INPUT += ../../../userspace/units/gr/setup/nvgpu-gr-setup.h
 INPUT += ../../../userspace/units/gr/intr/nvgpu-gr-intr.h
 INPUT += ../../../userspace/units/gr/config/nvgpu-gr-config.h

userspace/required_tests.json

@@ -1773,6 +1773,31 @@
         "test_level": 0,
         "unit": "nvgpu_gr_intr"
     },
+    {
+        "test": "gr_setup_setup",
+        "test_level": 0,
+        "unit": "nvgpu_gr_setup"
+    },
+    {
+        "test": "gr_setup_alloc_obj_ctx",
+        "test_level": 0,
+        "unit": "nvgpu_gr_setup"
+    },
+    {
+        "test": "gr_setup_set_preemption_mode",
+        "test_level": 0,
+        "unit": "nvgpu_gr_setup"
+    },
+    {
+        "test": "gr_setup_free_obj_ctx",
+        "test_level": 0,
+        "unit": "nvgpu_gr_setup"
+    },
+    {
+        "test": "gr_setup_cleanup",
+        "test_level": 0,
+        "unit": "nvgpu_gr_setup"
+    },
     {
        "test": "ltc_init_support",
        "test_level": 0,

userspace/units/gr/intr/nvgpu-gr-intr.h

@@ -42,7 +42,7 @@ struct unit_module;
  *
  * Test Type: Feature based, Error guessing.
  *
- * Input: test_gr_intr_setup must have been executed successfully.
+ * Input: #test_gr_init_setup_ready must have been executed successfully.
  *
  * Steps:
  * -  Set exception for FE, MEMFMT, PD, SCC, DS, SSYNC, MME, SKED
@@ -69,7 +69,7 @@ int test_gr_intr_without_channel(struct unit_module *m,
  *
  * Test Type: Feature based, Error guessing
  *
- * Input: test_gr_intr_setup must have been executed successfully.
+ * Input: #test_gr_init_setup_ready must have been executed successfully.
  *
  * Steps:
  * -  Setup channel and tsg and bing tsg & channel.
@@ -99,7 +99,7 @@ int test_gr_intr_setup_channel(struct unit_module *m,
  *
  * Test Type: Feature based, Error guessing.
  *
- * Input: test_gr_intr_setup must have been executed successfully.
+ * Input: #test_gr_init_setup_ready must have been executed successfully.
  *
  * Steps:
  * -  Setup illegal method pending interrupt bit.
@@ -124,7 +124,7 @@ int test_gr_intr_sw_exceptions(struct unit_module *m,
  *
  * Test Type: Feature based, Error guessing.
  *
- * Input: test_gr_intr_setup must have been executed successfully.
+ * Input: #test_gr_init_setup_ready must have been executed successfully.
  *
  * Steps:
  * -  Set fecs exception interrupt bits.
@@ -144,7 +144,7 @@ int test_gr_intr_fecs_exceptions(struct unit_module *m,
  *
  * Test Type: Feature based, Error guessing.
  *
- * Input: test_gr_intr_setup must have been executed successfully.
+ * Input: #test_gr_init_setup_ready must have been executed successfully.
  *
  * Steps:
  * -  Negative tests.

userspace/units/gr/nvgpu-gr-gv11b.c

@@ -111,6 +111,18 @@ struct gr_test_reg_info gr_reg_info[] = {
 		.base = 0x2a30,
 		.size = 0x4,
 	      },
+	[16] = { /* NV_PRI_GPCS_SWDX_DSS_DEBUG REGSPACE */
+		.base = 0x418000,
+		.size = 0xc,
+	      },
+	[17] = { /* NV_PRI_EGPCS_ETPCS_SM_DSM REGSPACE */
+		.base = 0x481a00,
+		.size = 0x5FF,
+	      },
+	[18] = { /* NV_PCCSR_CHANNEL REGSPACE */
+		.base = 0x800004,
+		.size = 0x1F,
+	      },
 };
 
 /*

userspace/units/gr/nvgpu-gr.c

@@ -172,6 +172,8 @@ int test_gr_init_setup_ready(struct unit_module *m,
 		unit_return_fail(m, "gr init support failed\n");
 	}
 
+	nvgpu_ref_init(&g->refcount);
+
 	return UNIT_SUCCESS;
 }
 

userspace/units/gr/setup/Makefile

@@ -0,0 +1,33 @@
+# Copyright (c) 2019, NVIDIA CORPORATION.  All rights reserved.
+#
+# Permission is hereby granted, free of charge, to any person obtaining a
+# copy of this software and associated documentation files (the "Software"),
+# to deal in the Software without restriction, including without limitation
+# the rights to use, copy, modify, merge, publish, distribute, sublicense,
+# and/or sell copies of the Software, and to permit persons to whom the
+# Software is furnished to do so, subject to the following conditions:
+#
+# The above copyright notice and this permission notice shall be included in
+# all copies or substantial portions of the Software.
+#
+# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+# THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+# FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+# DEALINGS IN THE SOFTWARE.
+
+.SUFFIXES:
+
+OBJS   = nvgpu-gr-setup.o
+MODULE = nvgpu-gr-setup
+
+LIB_PATHS += -lnvgpu-gr
+include ../../Makefile.units
+
+lib$(MODULE).so: nvgpu-gr
+
+nvgpu-gr:
+	$(MAKE) -C ..
+

userspace/units/gr/setup/Makefile.interface.tmk

@@ -0,0 +1,35 @@
+################################### tell Emacs this is a -*- makefile-gmake -*-
+#
+# Copyright (c) 2019, NVIDIA CORPORATION.  All rights reserved.
+#
+# Permission is hereby granted, free of charge, to any person obtaining a
+# copy of this software and associated documentation files (the "Software"),
+# to deal in the Software without restriction, including without limitation
+# the rights to use, copy, modify, merge, publish, distribute, sublicense,
+# and/or sell copies of the Software, and to permit persons to whom the
+# Software is furnished to do so, subject to the following conditions:
+#
+# The above copyright notice and this permission notice shall be included in
+# all copies or substantial portions of the Software.
+#
+# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+# THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+# FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+# DEALINGS IN THE SOFTWARE.
+#
+# tmake for SW Mobile component makefile
+#
+###############################################################################
+
+NVGPU_UNIT_NAME=nvgpu-gr-setup
+
+include $(NV_COMPONENT_DIR)/../../Makefile.units.common.interface.tmk
+
+# Local Variables:
+# indent-tabs-mode: t
+# tab-width: 8
+# End:
+# vi: set tabstop=8 noexpandtab:

userspace/units/gr/setup/Makefile.tmk

@@ -0,0 +1,40 @@
+################################### tell Emacs this is a -*- makefile-gmake -*-
+#
+# Copyright (c) 2019, NVIDIA CORPORATION.  All rights reserved.
+#
+# Permission is hereby granted, free of charge, to any person obtaining a
+# copy of this software and associated documentation files (the "Software"),
+# to deal in the Software without restriction, including without limitation
+# the rights to use, copy, modify, merge, publish, distribute, sublicense,
+# and/or sell copies of the Software, and to permit persons to whom the
+# Software is furnished to do so, subject to the following conditions:
+#
+# The above copyright notice and this permission notice shall be included in
+# all copies or substantial portions of the Software.
+#
+# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+# THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+# FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+# DEALINGS IN THE SOFTWARE.
+#
+# tmake for SW Mobile component makefile
+#
+###############################################################################
+
+NVGPU_UNIT_NAME = nvgpu-gr-setup
+NVGPU_UNIT_SRCS = nvgpu-gr-setup.c
+
+NVGPU_UNIT_INTERFACE_DIRS := \
+	$(NV_COMPONENT_DIR)/.. \
+	$(NV_SOURCE)/kernel/nvgpu/drivers/gpu/nvgpu
+
+include $(NV_COMPONENT_DIR)/../../Makefile.units.common.tmk
+
+# Local Variables:
+# indent-tabs-mode: t
+# tab-width: 8
+# End:
+# vi: set tabstop=8 noexpandtab:

userspace/units/gr/setup/nvgpu-gr-setup.c

@@ -0,0 +1,261 @@
+/*
+ * Copyright (c) 2019, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+
+#include <stdlib.h>
+#include <unistd.h>
+
+#include <unit/unit.h>
+#include <unit/io.h>
+
+#include <nvgpu/posix/io.h>
+#include <nvgpu/types.h>
+#include <nvgpu/gk20a.h>
+
+#include <nvgpu/channel.h>
+#include <nvgpu/runlist.h>
+#include <nvgpu/tsg.h>
+#include <nvgpu/class.h>
+#include <nvgpu/falcon.h>
+
+#include <nvgpu/gr/gr.h>
+#include <nvgpu/gr/ctx.h>
+
+#include <nvgpu/hw/gv11b/hw_gr_gv11b.h>
+
+#include "common/gr/gr_priv.h"
+#include "common/gr/obj_ctx_priv.h"
+
+#include "../nvgpu-gr.h"
+#include "nvgpu-gr-setup.h"
+
+static struct nvgpu_channel *gr_setup_ch;
+static struct nvgpu_tsg *gr_setup_tsg;
+
+static u32 stub_channel_count(struct gk20a *g)
+{
+	return 4;
+}
+
+static int stub_runlist_update_for_channel(struct gk20a *g, u32 runlist_id,
+					   struct nvgpu_channel *ch,
+					   bool add, bool wait_for_finish)
+{
+	return 0;
+}
+
+static int stub_mm_l2_flush(struct gk20a *g, bool invalidate)
+{
+	return 0;
+}
+
+static int stub_gr_init_fe_pwr_mode(struct gk20a *g, bool force_on)
+{
+	return 0;
+}
+
+static int stub_gr_init_wait_idle(struct gk20a *g)
+{
+	return 0;
+}
+
+static int stub_gr_falcon_ctrl_ctxsw(struct gk20a *g, u32 fecs_method,
+				     u32 data, u32 *ret_val)
+{
+	return 0;
+}
+
+static int gr_test_setup_unbind_tsg(struct unit_module *m, struct gk20a *g)
+{
+	int err = 0;
+
+	if ((gr_setup_ch == NULL) || (gr_setup_tsg == NULL)) {
+		goto unbind_tsg;
+	}
+
+	err = nvgpu_tsg_unbind_channel(gr_setup_tsg, gr_setup_ch);
+	if (err != 0) {
+		unit_err(m, "failed tsg channel unbind\n");
+	}
+
+unbind_tsg:
+	return (err == 0) ? UNIT_SUCCESS: UNIT_FAIL;
+}
+
+static void gr_test_setup_cleanup_ch_tsg(struct unit_module *m,
+					 struct gk20a *g)
+{
+	if (gr_setup_ch != NULL) {
+		nvgpu_channel_close(gr_setup_ch);
+	}
+
+	if (gr_setup_tsg != NULL) {
+		nvgpu_ref_put(&gr_setup_tsg->refcount, nvgpu_tsg_release);
+	}
+
+	gr_setup_tsg = NULL;
+	gr_setup_ch = NULL;
+}
+
+static int gr_test_setup_allocate_ch_tsg(struct unit_module *m,
+					 struct gk20a *g)
+{
+	u32 tsgid = getpid();
+	struct nvgpu_channel *ch = NULL;
+	struct nvgpu_tsg *tsg = NULL;
+        struct gk20a_as_share *as_share = NULL;
+	int err;
+
+	err = nvgpu_channel_setup_sw(g);
+	if (err != 0) {
+		unit_return_fail(m, "failed channel setup\n");
+	}
+
+	err = nvgpu_tsg_setup_sw(g);
+	if (err != 0) {
+		unit_return_fail(m, "failed tsg setup\n");
+	}
+
+	tsg = nvgpu_tsg_open(g, tsgid);
+	if (tsg == NULL) {
+		unit_return_fail(m, "failed tsg open\n");
+	}
+
+	ch = nvgpu_channel_open_new(g, NVGPU_INVALID_RUNLIST_ID,
+				false, tsgid, tsgid);
+	if (ch == NULL) {
+		unit_err(m, "failed channel open\n");
+		goto ch_cleanup;
+	}
+
+	err = nvgpu_tsg_bind_channel(tsg, ch);
+	if (err != 0) {
+		unit_err(m, "failed tsg channel bind\n");
+		goto ch_cleanup;
+	}
+
+	err = gk20a_as_alloc_share(g, 0, 0, &as_share);
+	if (err != 0) {
+		unit_err(m, "failed vm memory alloc\n");
+		goto tsg_unbind;
+	}
+
+	err = g->ops.mm.vm_bind_channel(as_share->vm, ch);
+	if (err != 0) {
+		unit_err(m, "failed vm binding to ch\n");
+		goto tsg_unbind;
+	}
+
+	gr_setup_ch = ch;
+	gr_setup_tsg = tsg;
+
+	goto ch_alloc_end;
+
+tsg_unbind:
+	gr_test_setup_unbind_tsg(m, g);
+
+ch_cleanup:
+	gr_test_setup_cleanup_ch_tsg(m, g);
+
+ch_alloc_end:
+	return (err == 0) ? UNIT_SUCCESS: UNIT_FAIL;
+}
+
+int test_gr_setup_set_preemption_mode(struct unit_module *m,
+				      struct gk20a *g, void *args)
+{
+	int err;
+
+	if (gr_setup_ch == NULL) {
+		unit_return_fail(m, "failed setup with valid channel\n");
+	}
+
+	err = g->ops.gr.setup.set_preemption_mode(gr_setup_ch, 0,
+		NVGPU_PREEMPTION_MODE_COMPUTE_CTA);
+	if (err != 0) {
+		unit_return_fail(m, "setup preemption_mode failed\n");
+	}
+
+	return UNIT_SUCCESS;
+}
+
+int test_gr_setup_free_obj_ctx(struct unit_module *m,
+			       struct gk20a *g, void *args)
+{
+	int err = 0;
+
+	err = gr_test_setup_unbind_tsg(m, g);
+
+	gr_test_setup_cleanup_ch_tsg(m, g);
+
+	return (err == 0) ? UNIT_SUCCESS: UNIT_FAIL;
+}
+
+int test_gr_setup_alloc_obj_ctx(struct unit_module *m,
+				struct gk20a *g, void *args)
+{
+	u32 tsgid = getpid();
+	int err;
+	struct nvgpu_fifo *f = &g->fifo;
+
+	nvgpu_posix_io_writel_reg_space(g, gr_fecs_current_ctx_r(),
+							tsgid);
+
+	g->ops.channel.count = stub_channel_count;
+	g->ops.runlist.update_for_channel = stub_runlist_update_for_channel;
+
+	/* Disable those function which need register update in timeout loop */
+	g->ops.mm.cache.l2_flush = stub_mm_l2_flush;
+	g->ops.gr.init.fe_pwr_mode_force_on = stub_gr_init_fe_pwr_mode;
+	g->ops.gr.init.wait_idle = stub_gr_init_wait_idle;
+	g->ops.gr.falcon.ctrl_ctxsw = stub_gr_falcon_ctrl_ctxsw;
+
+	if (f != NULL) {
+		f->g = g;
+	}
+
+	/* Set a default size for golden image */
+	g->gr->golden_image->size = 0x800;
+
+	/* Test with channel and tsg */
+	err = gr_test_setup_allocate_ch_tsg(m, g);
+	if (err != 0) {
+		unit_return_fail(m, "setup channel allocation failed\n");
+	}
+
+	err = g->ops.gr.setup.alloc_obj_ctx(gr_setup_ch, VOLTA_COMPUTE_A, 0);
+	if (err != 0) {
+		unit_return_fail(m, "setup alloc ob as current_ctx\n");
+	}
+
+	return UNIT_SUCCESS;
+}
+
+struct unit_module_test nvgpu_gr_setup_tests[] = {
+	UNIT_TEST(gr_setup_setup, test_gr_init_setup_ready, NULL, 0),
+	UNIT_TEST(gr_setup_alloc_obj_ctx, test_gr_setup_alloc_obj_ctx, NULL, 0),
+	UNIT_TEST(gr_setup_set_preemption_mode, test_gr_setup_set_preemption_mode, NULL, 0),
+	UNIT_TEST(gr_setup_free_obj_ctx, test_gr_setup_free_obj_ctx, NULL, 0),
+	UNIT_TEST(gr_setup_cleanup, test_gr_init_setup_cleanup, NULL, 0),
+};
+
+UNIT_MODULE(nvgpu_gr_setup, nvgpu_gr_setup_tests, UNIT_PRIO_NVGPU_TEST);

userspace/units/gr/setup/nvgpu-gr-setup.h

@@ -0,0 +1,110 @@
+/*
+ * Copyright (c) 2019, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+#ifndef UNIT_NVGPU_GR_SETUP_H
+#define UNIT_NVGPU_GR_SETUP_H
+
+#include <nvgpu/types.h>
+
+struct gk20a;
+struct unit_module;
+
+/** @addtogroup SWUTS-common-gr-setup
+ *  @{
+ *
+ * Software Unit Test Specification for common.gr.setup
+ */
+
+/**
+ * Test specification for: test_gr_setup_alloc_obj_ctx.
+ *
+ * Description: This test helps to verify common.gr object context creation.
+ *
+ * Test Type: Feature based.
+ *
+ * Input: #test_gr_init_setup_ready must have been executed successfully.
+ *
+ * Steps:
+ * -  Use stub functions for hals that use timeout and requires register update
+ *    within timeout loop.
+ *    - g->ops.mm.cache.l2_flush.
+ *    - g->ops.gr.init.fe_pwr_mode_force_on.
+ *    - g->ops.gr.init.wait_idle.
+ *    - g->ops.gr.falcon.ctrl_ctxsw.
+ * -  Set default golden image size.
+ * -  Allocate and bind channel and tsg.
+ * -  Call g->ops.gr.setup.alloc_obj_ctx.
+ *
+ * Output: Returns PASS if the steps above were executed successfully. FAIL
+ * otherwise.
+ */
+
+int test_gr_setup_alloc_obj_ctx(struct unit_module *m,
+				 struct gk20a *g, void *args);
+
+/**
+ * Test specification for: test_gr_setup_set_preemption_mode.
+ *
+ * Description: This test helps to verify set_preemption_mode.
+ *
+ * Test Type: Feature based.
+ *
+ * Input: #test_gr_init_setup_ready and #test_gr_setup_alloc_obj_ctx
+ *        must have been executed successfully.
+ *
+ * Steps:
+ * -  Call g->ops.gr.setup.set_preemption_mode
+ *
+ * Output: Returns PASS if the steps above were executed successfully. FAIL
+ * otherwise.
+ */
+
+int test_gr_setup_set_preemption_mode(struct unit_module *m,
+			       struct gk20a *g, void *args);
+
+/**
+ * Test specification for: test_gr_setup_free_obj_ctx.
+ *
+ * Description: Helps to verify common.gr object context cleanup.
+ *
+ * Test Type: Feature based.
+ *
+ * Input: #test_gr_init_setup_ready and #test_gr_setup_alloc_obj_ctx
+ *        must have been executed successfully.
+ *
+ * Steps:
+ * -  Call nvgpu_tsg_unbind_channel.
+ * -  Call nvgpu_channel_close.
+ * -  Call nvgpu_tsg_release.
+ *
+ * Output: Returns PASS if the steps above were executed successfully. FAIL
+ * otherwise.
+ */
+
+int test_gr_setup_free_obj_ctx(struct unit_module *m,
+			       struct gk20a *g, void *args);
+
+#endif /* UNIT_NVGPU_GR_SETUP_H */
+
+/**
+ * @}
+ */
+