From df831c200bf4bbbbf4b0c8448fdf0ec5ab66ba7c Mon Sep 17 00:00:00 2001 From: Seema Khowala Date: Fri, 19 Apr 2019 10:58:50 -0700 Subject: [PATCH] gpu: nvgpu: rename enable/disable sched Rename gk20a_tsg_enable_sched -> nvgpu_tsg_enable_sched gk20a_tsg_disable_sched -> nvgpu_tsg_disable_sched JIRA NVGPU-3144 Change-Id: I569025ea96e64b2bf3f8216a6080a8496570acf3 Signed-off-by: Seema Khowala Reviewed-on: https://git-master.nvidia.com/r/2101277 Reviewed-by: Thomas Fleury Reviewed-by: svc-mobile-coverity Reviewed-by: svc-mobile-misra GVS: Gerrit_Virtual_Submit Reviewed-by: Alex Waterman Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/common/fifo/tsg.c | 4 ++-- drivers/gpu/nvgpu/hal/fifo/preempt_gv11b.c | 4 ++-- drivers/gpu/nvgpu/hal/fifo/tsg_gk20a.c | 4 ++-- drivers/gpu/nvgpu/include/nvgpu/tsg.h | 4 ++-- 4 files changed, 8 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/nvgpu/common/fifo/tsg.c b/drivers/gpu/nvgpu/common/fifo/tsg.c index 3cf87ad44..eab6a7b8e 100644 --- a/drivers/gpu/nvgpu/common/fifo/tsg.c +++ b/drivers/gpu/nvgpu/common/fifo/tsg.c @@ -557,14 +557,14 @@ u32 gk20a_tsg_get_timeslice(struct tsg_gk20a *tsg) return tsg->timeslice_us; } -void gk20a_tsg_enable_sched(struct gk20a *g, struct tsg_gk20a *tsg) +void nvgpu_tsg_enable_sched(struct gk20a *g, struct tsg_gk20a *tsg) { gk20a_fifo_set_runlist_state(g, BIT32(tsg->runlist_id), RUNLIST_ENABLED); } -void gk20a_tsg_disable_sched(struct gk20a *g, struct tsg_gk20a *tsg) +void nvgpu_tsg_disable_sched(struct gk20a *g, struct tsg_gk20a *tsg) { gk20a_fifo_set_runlist_state(g, BIT32(tsg->runlist_id), RUNLIST_DISABLED); diff --git a/drivers/gpu/nvgpu/hal/fifo/preempt_gv11b.c b/drivers/gpu/nvgpu/hal/fifo/preempt_gv11b.c index 6af4ab77e..efcc226e9 100644 --- a/drivers/gpu/nvgpu/hal/fifo/preempt_gv11b.c +++ b/drivers/gpu/nvgpu/hal/fifo/preempt_gv11b.c @@ -433,7 +433,7 @@ int gv11b_fifo_preempt_tsg(struct gk20a *g, struct tsg_gk20a *tsg) nvgpu_mutex_acquire(&f->runlist_info[runlist_id]->runlist_lock); /* WAR for Bug 2065990 */ - gk20a_tsg_disable_sched(g, tsg); + nvgpu_tsg_disable_sched(g, tsg); mutex_ret = nvgpu_pmu_lock_acquire(g, &g->pmu, PMU_MUTEX_ID_FIFO, &token); @@ -450,7 +450,7 @@ int gv11b_fifo_preempt_tsg(struct gk20a *g, struct tsg_gk20a *tsg) } /* WAR for Bug 2065990 */ - gk20a_tsg_enable_sched(g, tsg); + nvgpu_tsg_enable_sched(g, tsg); nvgpu_mutex_release(&f->runlist_info[runlist_id]->runlist_lock); diff --git a/drivers/gpu/nvgpu/hal/fifo/tsg_gk20a.c b/drivers/gpu/nvgpu/hal/fifo/tsg_gk20a.c index b39cc0ec4..809b060b9 100644 --- a/drivers/gpu/nvgpu/hal/fifo/tsg_gk20a.c +++ b/drivers/gpu/nvgpu/hal/fifo/tsg_gk20a.c @@ -32,7 +32,7 @@ void gk20a_tsg_enable(struct tsg_gk20a *tsg) struct gk20a *g = tsg->g; struct channel_gk20a *ch; - gk20a_tsg_disable_sched(g, tsg); + nvgpu_tsg_disable_sched(g, tsg); /* * Due to h/w bug that exists in Maxwell and Pascal, @@ -63,5 +63,5 @@ void gk20a_tsg_enable(struct tsg_gk20a *tsg) } nvgpu_rwsem_up_read(&tsg->ch_list_lock); - gk20a_tsg_enable_sched(g, tsg); + nvgpu_tsg_enable_sched(g, tsg); } diff --git a/drivers/gpu/nvgpu/include/nvgpu/tsg.h b/drivers/gpu/nvgpu/include/nvgpu/tsg.h index eef10d5f6..de2e5f1db 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/tsg.h +++ b/drivers/gpu/nvgpu/include/nvgpu/tsg.h @@ -117,8 +117,8 @@ bool nvgpu_tsg_check_ctxsw_timeout(struct tsg_gk20a *tsg, int gk20a_tsg_set_runlist_interleave(struct tsg_gk20a *tsg, u32 level); int gk20a_tsg_set_timeslice(struct tsg_gk20a *tsg, u32 timeslice); u32 gk20a_tsg_get_timeslice(struct tsg_gk20a *tsg); -void gk20a_tsg_enable_sched(struct gk20a *g, struct tsg_gk20a *tsg); -void gk20a_tsg_disable_sched(struct gk20a *g, struct tsg_gk20a *tsg); +void nvgpu_tsg_enable_sched(struct gk20a *g, struct tsg_gk20a *tsg); +void nvgpu_tsg_disable_sched(struct gk20a *g, struct tsg_gk20a *tsg); int gk20a_tsg_set_priority(struct gk20a *g, struct tsg_gk20a *tsg, u32 priority); int gk20a_tsg_alloc_sm_error_states_mem(struct gk20a *g,