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gpu: nvgpu: add init_pbdma_intr_desc fifo ops

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Init device_fatal, channel_fatal and restartable fifo intr pbdma s/w
variables for pbdma_intr_0 interrupt masks for each GPU version separately

pbdma_intr_0 field differences for each GPU version:-
-gk20a  : bit 28 does not exists in hw
-gm20b  : bit 8(lbreq), 20(xbarconnect) and 28 do not exist in hw
-gp10b  : bit 8(lbreq), 20(xbarconnect) do not exist in hw. bit 28,
          (syncpoint_illegal) added in hw but is not being handled.
-gk20a/gm20b/gp10b
bit 24 eng_reset and bit 25 semaphore always existed in hw but never
handled

JIRA GPUT19X-47

Change-Id: I209191f57c5ea5b15081b7dc2411801d3537017c
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: http://git-master/r/1325402
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Seema Khowala
2017-03-21 11:17:48 -07:00
committed by mobile promotions
parent 4492c62ffe
commit df94d474a8
4 changed files with 107 additions and 8 deletions
Download Patch File Download Diff File Expand all files Collapse all files

46
drivers/gpu/nvgpu/gp10b/fifo_gp10b.c
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@@ -230,6 +230,51 @@ static void gp10b_device_info_data_parse(struct gk20a *g, u32 table_entry,
top_device_info_data_type_v(table_entry));
}
static void gp10b_fifo_init_pbdma_intr_descs(struct fifo_gk20a *f)
{
/*
* These are all errors which indicate something really wrong
* going on in the device
*/
f->intr.pbdma.device_fatal_0 =
pbdma_intr_0_memreq_pending_f() |
pbdma_intr_0_memack_timeout_pending_f() |
pbdma_intr_0_memack_extra_pending_f() |
pbdma_intr_0_memdat_timeout_pending_f() |
pbdma_intr_0_memdat_extra_pending_f() |
pbdma_intr_0_memflush_pending_f() |
pbdma_intr_0_memop_pending_f() |
pbdma_intr_0_lbconnect_pending_f() |
pbdma_intr_0_lback_timeout_pending_f() |
pbdma_intr_0_lback_extra_pending_f() |
pbdma_intr_0_lbdat_timeout_pending_f() |
pbdma_intr_0_lbdat_extra_pending_f() |
pbdma_intr_0_pri_pending_f();
/*
* These are data parsing, framing errors or others which can be
* recovered from with intervention... or just resetting the
* channel
*/
f->intr.pbdma.channel_fatal_0 =
pbdma_intr_0_gpfifo_pending_f() |
pbdma_intr_0_gpptr_pending_f() |
pbdma_intr_0_gpentry_pending_f() |
pbdma_intr_0_gpcrc_pending_f() |
pbdma_intr_0_pbptr_pending_f() |
pbdma_intr_0_pbentry_pending_f() |
pbdma_intr_0_pbcrc_pending_f() |
pbdma_intr_0_method_pending_f() |
pbdma_intr_0_methodcrc_pending_f() |
pbdma_intr_0_pbseg_pending_f() |
pbdma_intr_0_syncpoint_illegal_pending_f() |
pbdma_intr_0_signature_pending_f();
/* Can be used for sw-methods, or represents a recoverable timeout. */
f->intr.pbdma.restartable_0 =
pbdma_intr_0_device_pending_f();
}
void gp10b_init_fifo(struct gpu_ops *gops)
{
gm20b_init_fifo(gops);
@@ -240,4 +285,5 @@ void gp10b_init_fifo(struct gpu_ops *gops)
gops->fifo.device_info_data_parse = gp10b_device_info_data_parse;
gops->fifo.eng_runlist_base_size = fifo_eng_runlist_base__size_1_v;
gops->fifo.device_info_fault_id = top_device_info_data_fault_id_enum_v;
gops->fifo.init_pbdma_intr_descs = gp10b_fifo_init_pbdma_intr_descs;
}