gpu: nvgpu: disable fecs trace support for safety builds

Compile all files with fecs trace support only if flag
NVGPU_FECS_TRACE_SUPPORT is set

remove CONFIG_GK20A_CTXSW_TRACE checks from within the files

add POSIX file for fecs trace support for compilation with
make command

Jira NVGPU-3414

Change-Id: I205e3494ce94138ab6c6fccf7fbcefc41f953c77
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2120276
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: Thomas Fleury <tfleury@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Deepak Nibade
2019-05-16 15:35:47 +05:30
committed by mobile promotions
parent f39a5c4ead
commit dfdd05a3d6
9 changed files with 98 additions and 31 deletions

View File

@@ -32,6 +32,7 @@ all:
os/posix/posix-sim.c, os/posix/posix-sim.c,
os/posix/posix-vgpu.c, os/posix/posix-vgpu.c,
os/posix/posix-vidmem.c, os/posix/posix-vidmem.c,
os/posix/fecs_trace_posix.c,
os/posix/stubs.c ] os/posix/stubs.c ]
headers: headers:

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@@ -60,7 +60,6 @@ nvgpu-y += \
common/gr/subctx.o \ common/gr/subctx.o \
common/gr/zcull.o \ common/gr/zcull.o \
common/gr/gr_config.o \ common/gr/gr_config.o \
common/gr/fecs_trace.o \
common/gr/zbc.o \ common/gr/zbc.o \
common/gr/gr_setup.o \ common/gr/gr_setup.o \
common/gr/hwpm_map.o \ common/gr/hwpm_map.o \
@@ -185,8 +184,6 @@ nvgpu-y += \
hal/gr/ecc/ecc_gp10b.o \ hal/gr/ecc/ecc_gp10b.o \
hal/gr/ecc/ecc_gv11b.o \ hal/gr/ecc/ecc_gv11b.o \
hal/gr/ecc/ecc_tu104.o \ hal/gr/ecc/ecc_tu104.o \
hal/gr/fecs_trace/fecs_trace_gm20b.o \
hal/gr/fecs_trace/fecs_trace_gv11b.o \
hal/gr/zcull/zcull_gm20b.o \ hal/gr/zcull/zcull_gm20b.o \
hal/gr/zcull/zcull_gv11b.o \ hal/gr/zcull/zcull_gv11b.o \
hal/gr/ctxsw_prog/ctxsw_prog_gm20b.o \ hal/gr/ctxsw_prog/ctxsw_prog_gm20b.o \
@@ -429,6 +426,9 @@ nvgpu-$(CONFIG_DEBUG_FS) += \
endif endif
nvgpu-$(CONFIG_GK20A_CTXSW_TRACE) += \ nvgpu-$(CONFIG_GK20A_CTXSW_TRACE) += \
common/gr/fecs_trace.o \
hal/gr/fecs_trace/fecs_trace_gm20b.o \
hal/gr/fecs_trace/fecs_trace_gv11b.o \
os/linux/fecs_trace_linux.o os/linux/fecs_trace_linux.o
ifeq ($(CONFIG_GK20A_CTXSW_TRACE),y) ifeq ($(CONFIG_GK20A_CTXSW_TRACE),y)
@@ -472,9 +472,13 @@ nvgpu-$(CONFIG_TEGRA_GR_VIRTUALIZATION) += \
os/linux/vgpu/vgpu_ivc.o \ os/linux/vgpu/vgpu_ivc.o \
os/linux/vgpu/vgpu_ivm.o \ os/linux/vgpu/vgpu_ivm.o \
os/linux/vgpu/vgpu_linux.o \ os/linux/vgpu/vgpu_linux.o \
os/linux/vgpu/fecs_trace_vgpu_linux.o \
os/linux/vgpu/gv11b/platform_gv11b_vgpu_tegra.o os/linux/vgpu/gv11b/platform_gv11b_vgpu_tegra.o
ifeq ($(CONFIG_GK20A_CTXSW_TRACE),y)
nvgpu-$(CONFIG_TEGRA_GR_VIRTUALIZATION) += \
os/linux/vgpu/fecs_trace_vgpu_linux.o
endif
nvgpu-$(CONFIG_COMMON_CLK) += \ nvgpu-$(CONFIG_COMMON_CLK) += \
os/linux/clk.o os/linux/clk.o

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@@ -50,4 +50,6 @@ NVGPU_DGPU_SUPPORT := 1
NVGPU_COMMON_CFLAGS += -DNVGPU_DGPU_SUPPORT NVGPU_COMMON_CFLAGS += -DNVGPU_DGPU_SUPPORT
ifeq ($(NV_BUILD_CONFIGURATION_IS_SAFETY),0) ifeq ($(NV_BUILD_CONFIGURATION_IS_SAFETY),0)
NVGPU_FECS_TRACE_SUPPORT := 1
NVGPU_COMMON_CFLAGS += -DCONFIG_GK20A_CTXSW_TRACE
endif endif

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@@ -43,7 +43,8 @@ srcs += os/posix/nvgpu.c \
os/posix/posix-nvhost.c \ os/posix/posix-nvhost.c \
os/posix/posix-vgpu.c \ os/posix/posix-vgpu.c \
os/posix/posix-dt.c \ os/posix/posix-dt.c \
os/posix/posix-vidmem.c os/posix/posix-vidmem.c \
os/posix/fecs_trace_posix.c
endif endif
# POSIX sources shared between the POSIX and QNX builds. # POSIX sources shared between the POSIX and QNX builds.
@@ -116,7 +117,6 @@ srcs += common/sim/sim.c \
common/gr/gr_falcon.c \ common/gr/gr_falcon.c \
common/gr/zcull.c \ common/gr/zcull.c \
common/gr/gr_config.c \ common/gr/gr_config.c \
common/gr/fecs_trace.c \
common/gr/zbc.c \ common/gr/zbc.c \
common/gr/gr_setup.c \ common/gr/gr_setup.c \
common/gr/hwpm_map.c \ common/gr/hwpm_map.c \
@@ -278,8 +278,6 @@ srcs += common/sim/sim.c \
hal/gr/ecc/ecc_gp10b.c \ hal/gr/ecc/ecc_gp10b.c \
hal/gr/ecc/ecc_gv11b.c \ hal/gr/ecc/ecc_gv11b.c \
hal/gr/ecc/ecc_tu104.c \ hal/gr/ecc/ecc_tu104.c \
hal/gr/fecs_trace/fecs_trace_gm20b.c \
hal/gr/fecs_trace/fecs_trace_gv11b.c \
hal/gr/zcull/zcull_gm20b.c \ hal/gr/zcull/zcull_gm20b.c \
hal/gr/zcull/zcull_gv11b.c \ hal/gr/zcull/zcull_gv11b.c \
hal/gr/ctxsw_prog/ctxsw_prog_gm20b.c \ hal/gr/ctxsw_prog/ctxsw_prog_gm20b.c \
@@ -456,6 +454,18 @@ ifeq ($(NVGPU_DEBUGGER),1)
srcs += common/debugger.c srcs += common/debugger.c
endif endif
ifeq ($(NVGPU_FECS_TRACE_SUPPORT),1)
srcs += common/gr/fecs_trace.c \
hal/gr/fecs_trace/fecs_trace_gm20b.c \
hal/gr/fecs_trace/fecs_trace_gv11b.c
endif
ifeq ($(NVGPU_FECS_TRACE_SUPPORT),1)
ifeq ($(IGPU_VIRT_SUPPORT), 1)
srcs += common/vgpu/gr/fecs_trace_vgpu.c
endif
endif
# POSIX file used for unit testing for both qnx and linux # POSIX file used for unit testing for both qnx and linux
ifdef NVGPU_FAULT_INJECTION_ENABLEMENT ifdef NVGPU_FAULT_INJECTION_ENABLEMENT
srcs += os/posix/posix-fault-injection.c srcs += os/posix/posix-fault-injection.c
@@ -484,7 +494,6 @@ srcs += common/vgpu/init/init_vgpu.c \
common/vgpu/tsg_vgpu.c \ common/vgpu/tsg_vgpu.c \
common/vgpu/perf/cyclestats_snapshot_vgpu.c \ common/vgpu/perf/cyclestats_snapshot_vgpu.c \
common/vgpu/perf/perf_vgpu.c \ common/vgpu/perf/perf_vgpu.c \
common/vgpu/gr/fecs_trace_vgpu.c \
common/vgpu/mm/mm_vgpu.c \ common/vgpu/mm/mm_vgpu.c \
common/vgpu/mm/vm_vgpu.c \ common/vgpu/mm/vm_vgpu.c \
common/vgpu/gr/gr_vgpu.c \ common/vgpu/gr/gr_vgpu.c \

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@@ -34,8 +34,6 @@
#include <nvgpu/gr/fecs_trace.h> #include <nvgpu/gr/fecs_trace.h>
#include <nvgpu/gr/gr_utils.h> #include <nvgpu/gr/gr_utils.h>
#ifdef CONFIG_GK20A_CTXSW_TRACE
static int nvgpu_gr_fecs_trace_periodic_polling(void *arg); static int nvgpu_gr_fecs_trace_periodic_polling(void *arg);
int nvgpu_gr_fecs_trace_add_context(struct gk20a *g, u32 context_ptr, int nvgpu_gr_fecs_trace_add_context(struct gk20a *g, u32 context_ptr,
@@ -707,5 +705,3 @@ int nvgpu_gr_fecs_trace_unbind_channel(struct gk20a *g,
return 0; return 0;
} }
#endif /* CONFIG_GK20A_CTXSW_TRACE */

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@@ -30,8 +30,6 @@
#include <nvgpu/hw/gm20b/hw_gr_gm20b.h> #include <nvgpu/hw/gm20b/hw_gr_gm20b.h>
#ifdef CONFIG_GK20A_CTXSW_TRACE
int gm20b_fecs_trace_flush(struct gk20a *g) int gm20b_fecs_trace_flush(struct gk20a *g)
{ {
int err; int err;
@@ -70,5 +68,3 @@ u32 gm20b_fecs_trace_get_buffer_full_mailbox_val(void)
{ {
return 0x26; return 0x26;
} }
#endif /* CONFIG_GK20A_CTXSW_TRACE */

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@@ -22,11 +22,7 @@
#include "fecs_trace_gv11b.h" #include "fecs_trace_gv11b.h"
#ifdef CONFIG_GK20A_CTXSW_TRACE
u32 gv11b_fecs_trace_get_buffer_full_mailbox_val(void) u32 gv11b_fecs_trace_get_buffer_full_mailbox_val(void)
{ {
return 0x32; return 0x32;
} }
#endif /* CONFIG_GK20A_CTXSW_TRACE */

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@@ -547,7 +547,6 @@ int gk20a_ctxsw_dev_mmap(struct file *filp, struct vm_area_struct *vma)
return ret; return ret;
} }
#ifdef CONFIG_GK20A_CTXSW_TRACE
static int gk20a_ctxsw_init_devs(struct gk20a *g) static int gk20a_ctxsw_init_devs(struct gk20a *g)
{ {
struct gk20a_ctxsw_trace *trace = g->ctxsw_trace; struct gk20a_ctxsw_trace *trace = g->ctxsw_trace;
@@ -568,11 +567,9 @@ static int gk20a_ctxsw_init_devs(struct gk20a *g)
} }
return 0; return 0;
} }
#endif
int gk20a_ctxsw_trace_init(struct gk20a *g) int gk20a_ctxsw_trace_init(struct gk20a *g)
{ {
#ifdef CONFIG_GK20A_CTXSW_TRACE
struct gk20a_ctxsw_trace *trace = g->ctxsw_trace; struct gk20a_ctxsw_trace *trace = g->ctxsw_trace;
int err; int err;
@@ -605,14 +602,10 @@ fail:
nvgpu_kfree(g, trace); nvgpu_kfree(g, trace);
g->ctxsw_trace = NULL; g->ctxsw_trace = NULL;
return err; return err;
#else
return 0;
#endif
} }
void gk20a_ctxsw_trace_cleanup(struct gk20a *g) void gk20a_ctxsw_trace_cleanup(struct gk20a *g)
{ {
#ifdef CONFIG_GK20A_CTXSW_TRACE
struct gk20a_ctxsw_trace *trace; struct gk20a_ctxsw_trace *trace;
struct gk20a_ctxsw_dev *dev; struct gk20a_ctxsw_dev *dev;
int i; int i;
@@ -632,7 +625,6 @@ void gk20a_ctxsw_trace_cleanup(struct gk20a *g)
g->ctxsw_trace = NULL; g->ctxsw_trace = NULL;
g->ops.gr.fecs_trace.deinit(g); g->ops.gr.fecs_trace.deinit(g);
#endif
} }
int nvgpu_gr_fecs_trace_write_entry(struct gk20a *g, int nvgpu_gr_fecs_trace_write_entry(struct gk20a *g,
@@ -744,7 +736,6 @@ void nvgpu_gr_fecs_trace_wake_up(struct gk20a *g, int vmid)
void nvgpu_gr_fecs_trace_add_tsg_reset(struct gk20a *g, struct nvgpu_tsg *tsg) void nvgpu_gr_fecs_trace_add_tsg_reset(struct gk20a *g, struct nvgpu_tsg *tsg)
{ {
#ifdef CONFIG_GK20A_CTXSW_TRACE
struct nvgpu_gpu_ctxsw_trace_entry entry = { struct nvgpu_gpu_ctxsw_trace_entry entry = {
.vmid = 0, .vmid = 0,
.tag = NVGPU_CTXSW_TAG_ENGINE_RESET, .tag = NVGPU_CTXSW_TAG_ENGINE_RESET,
@@ -758,7 +749,7 @@ void nvgpu_gr_fecs_trace_add_tsg_reset(struct gk20a *g, struct nvgpu_tsg *tsg)
g->ops.ptimer.read_ptimer(g, &entry.timestamp); g->ops.ptimer.read_ptimer(g, &entry.timestamp);
nvgpu_gr_fecs_trace_write_entry(g, &entry); nvgpu_gr_fecs_trace_write_entry(g, &entry);
nvgpu_gr_fecs_trace_wake_up(g, 0); nvgpu_gr_fecs_trace_wake_up(g, 0);
#endif
trace_gk20a_channel_reset(~0, tsg->tsgid); trace_gk20a_channel_reset(~0, tsg->tsgid);
} }

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@@ -0,0 +1,72 @@
/*
* Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
#include <nvgpu/types.h>
#include <nvgpu/gr/fecs_trace.h>
int vgpu_alloc_user_buffer(struct gk20a *g, void **buf, size_t *size);
void vgpu_fecs_trace_data_update(struct gk20a *g);
void vgpu_get_mmap_user_buffer_info(struct gk20a *g,
void **mmapaddr, size_t *mmapsize);
int nvgpu_gr_fecs_trace_ring_alloc(struct gk20a *g,
void **buf, size_t *size)
{
return -EINVAL;
}
int nvgpu_gr_fecs_trace_ring_free(struct gk20a *g)
{
return -EINVAL;
}
void nvgpu_gr_fecs_trace_get_mmap_buffer_info(struct gk20a *g,
void **mmapaddr, size_t *mmapsize)
{
}
int nvgpu_gr_fecs_trace_write_entry(struct gk20a *g,
struct nvgpu_gpu_ctxsw_trace_entry *entry)
{
return -EINVAL;
}
void nvgpu_gr_fecs_trace_wake_up(struct gk20a *g, int vmid)
{
}
void nvgpu_gr_fecs_trace_add_tsg_reset(struct gk20a *g, struct nvgpu_tsg *tsg)
{
}
u8 nvgpu_gpu_ctxsw_tags_to_common_tags(u8 tags)
{
return 0;
}
int vgpu_alloc_user_buffer(struct gk20a *g, void **buf, size_t *size)
{
return -EINVAL;
}
void vgpu_fecs_trace_data_update(struct gk20a *g)
{
}
void vgpu_get_mmap_user_buffer_info(struct gk20a *g,
void **mmapaddr, size_t *mmapsize)
{
}