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gpu: nvgpu: remove gk20a_is_channel_marked_as_tsg

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Use tsg_gk20a_from_ch to get tsg pointer for tsgid of a channel. For
invalid tsgid, tsg pointer will be NULL

Bug 2092051
Bug 2429295
Bug 2484211

Change-Id: I82cd6a2dc5fab4acb147202af667ca97a2842a73
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2006722
Signed-off-by: Debarshi Dutta <ddutta@nvidia.com>
(cherry picked from commit 13f37f9c70
in dev-kernel)
Reviewed-on: https://git-master.nvidia.com/r/2025507
GVS: Gerrit_Virtual_Submit
Reviewed-by: Bibek Basu <bbasu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Seema Khowala
2018-12-27 19:23:06 -08:00
committed by mobile promotions
parent 0c47ce7d72
commit e00804594b
8 changed files with 49 additions and 38 deletions
Download Patch File Download Diff File Expand all files Collapse all files

16
drivers/gpu/nvgpu/common/fb/fb_gv11b.c
View File

@@ -839,6 +839,7 @@ static void gv11b_fb_handle_mmu_fault_common(struct gk20a *g,
int err = 0;
u32 id = FIFO_INVAL_TSG_ID;
unsigned int rc_type = RC_TYPE_NO_RC;
struct tsg_gk20a *tsg = NULL;
if (!mmfault->valid) {
return;
@@ -912,14 +913,17 @@ static void gv11b_fb_handle_mmu_fault_common(struct gk20a *g,
mmfault->refch->mmu_nack_handled = true;
}
rc_type = RC_TYPE_MMU_FAULT;
if (gk20a_is_channel_marked_as_tsg(mmfault->refch)) {
tsg = tsg_gk20a_from_ch(mmfault->refch);
if (tsg != NULL) {
id = mmfault->refch->tsgid;
if (id != FIFO_INVAL_TSG_ID) {
id_type = ID_TYPE_TSG;
}
id_type = ID_TYPE_TSG;
rc_type = RC_TYPE_MMU_FAULT;
} else {
nvgpu_err(g, "bare channels not supported");
nvgpu_err(g, "chid: %d is referenceable but "
"not bound to tsg",
mmfault->refch->chid);
id_type = ID_TYPE_CHANNEL;
rc_type = RC_TYPE_NO_RC;
}
}

16
drivers/gpu/nvgpu/common/fifo/channel.c
View File

@@ -326,7 +326,12 @@ static void gk20a_free_channel(struct channel_gk20a *ch, bool force)
*/
if (!nvgpu_is_enabled(g, NVGPU_DRIVER_IS_DYING)) {
/* abort channel and remove from runlist */
if (gk20a_is_channel_marked_as_tsg(ch)) {
if (tsg_gk20a_from_ch(ch) != NULL) {
/* Between tsg is not null and unbind_channel call,
* ioctl cannot be called anymore because user doesn't
* have an open channel fd anymore to use for the unbind
* ioctl.
*/
err = gk20a_tsg_unbind_channel(ch);
if (err) {
nvgpu_err(g,
@@ -2264,7 +2269,7 @@ int gk20a_init_channel_support(struct gk20a *g, u32 chid)
if (err) {
goto fail_6;
}
nvgpu_init_list_node(&c->ch_entry);
nvgpu_list_add(&c->free_chs, &g->fifo.free_chs);
return 0;
@@ -2403,10 +2408,9 @@ void gk20a_channel_semaphore_wakeup(struct gk20a *g, bool post_events)
nvgpu_cond_broadcast_interruptible(
&c->semaphore_wq);
if (post_events) {
if (gk20a_is_channel_marked_as_tsg(c)) {
struct tsg_gk20a *tsg =
&g->fifo.tsg[c->tsgid];
struct tsg_gk20a *tsg =
tsg_gk20a_from_ch(c);
if (tsg != NULL) {
g->ops.fifo.post_event_id(tsg,
NVGPU_EVENT_ID_BLOCKING_SYNC);
}

26
drivers/gpu/nvgpu/common/fifo/tsg.c
View File

@@ -28,11 +28,6 @@
#include <nvgpu/tsg.h>
#include <nvgpu/gk20a.h>
bool gk20a_is_channel_marked_as_tsg(struct channel_gk20a *ch)
{
return !(ch->tsgid == NVGPU_INVALID_TSG_ID);
}
int gk20a_enable_tsg(struct tsg_gk20a *tsg)
{
struct gk20a *g = tsg->g;
@@ -116,7 +111,7 @@ int gk20a_tsg_bind_channel(struct tsg_gk20a *tsg,
nvgpu_log_fn(g, " ");
/* check if channel is already bound to some TSG */
if (gk20a_is_channel_marked_as_tsg(ch)) {
if (tsg_gk20a_from_ch(ch) != NULL) {
return -EINVAL;
}
@@ -125,7 +120,6 @@ int gk20a_tsg_bind_channel(struct tsg_gk20a *tsg,
return -EINVAL;
}
ch->tsgid = tsg->tsgid;
/* all the channel part of TSG should need to be same runlist_id */
if (tsg->runlist_id == FIFO_INVAL_TSG_ID) {
@@ -139,6 +133,7 @@ int gk20a_tsg_bind_channel(struct tsg_gk20a *tsg,
nvgpu_rwsem_down_write(&tsg->ch_list_lock);
nvgpu_list_add_tail(&ch->ch_entry, &tsg->ch_list);
ch->tsgid = tsg->tsgid;
nvgpu_rwsem_up_write(&tsg->ch_list_lock);
nvgpu_ref_get(&tsg->refcount);
@@ -172,14 +167,13 @@ int gk20a_tsg_unbind_channel(struct channel_gk20a *ch)
nvgpu_rwsem_down_write(&tsg->ch_list_lock);
nvgpu_list_del(&ch->ch_entry);
ch->tsgid = NVGPU_INVALID_TSG_ID;
nvgpu_rwsem_up_write(&tsg->ch_list_lock);
}
nvgpu_log(g, gpu_dbg_fn, "UNBIND tsg:%d channel:%d",
tsg->tsgid, ch->chid);
nvgpu_ref_put(&tsg->refcount, gk20a_tsg_release);
ch->tsgid = NVGPU_INVALID_TSG_ID;
nvgpu_log(g, gpu_dbg_fn, "UNBIND tsg:%d channel:%d\n",
tsg->tsgid, ch->chid);
return 0;
}
@@ -395,13 +389,17 @@ void gk20a_tsg_release(struct nvgpu_ref *ref)
struct tsg_gk20a *tsg_gk20a_from_ch(struct channel_gk20a *ch)
{
struct tsg_gk20a *tsg = NULL;
u32 tsgid = ch->tsgid;
if (gk20a_is_channel_marked_as_tsg(ch)) {
if (tsgid != NVGPU_INVALID_TSG_ID) {
struct gk20a *g = ch->g;
struct fifo_gk20a *f = &g->fifo;
tsg = &f->tsg[ch->tsgid];
}
tsg = &f->tsg[tsgid];
} else {
nvgpu_log(ch->g, gpu_dbg_fn, "tsgid is invalid for chid: %d",
ch->chid);
}
return tsg;
}