From e0089374013468206db28a0c4db3e96686ddf88c Mon Sep 17 00:00:00 2001 From: Seshendra Gadagottu Date: Mon, 1 Apr 2019 18:43:11 -0700 Subject: [PATCH] gpu: nvgpu: gm20b: register usage optimizations With hw minimal headers, lot of unwanted hw registers are stripped. SW needed few updates to use minimal headers: 1. Use stride value to get non zero instance offset: gr_pri_gpc0_tpc1_tpccs_tpc_activity_0_r() = gr_pri_gpc0_tpc0_tpccs_tpc_activity_0_r() + nvgpu_get_litter_value(g, GPU_LIT_TPC_IN_GPC_STRIDE); gr_pri_be1_becs_be_activity0_r() = gr_pri_be0_becs_be_activity0_r() + nvgpu_get_litter_value(g, GPU_LIT_ROP_STRIDE); 2. Broadcast registers should not be used for reading status and they should be used only for broadcast register writes. Removed following register reads from gm20b register dump: NV_PGRAPH_PRI_GPCS_TPC0_TPCCS_TPC_ACTIVITY0 NV_PGRAPH_PRI_GPCS_TPC1_TPCCS_TPC_ACTIVITY0 JIRA NVGPU-2917 Change-Id: Ie1359699136c16b67121038024c2318ddd06190c Signed-off-by: Seshendra Gadagottu Reviewed-on: https://git-master.nvidia.com/r/2087231 Reviewed-by: svc-mobile-coverity Reviewed-by: svc-mobile-misra GVS: Gerrit_Virtual_Submit Reviewed-by: Alex Waterman Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/gm20b/gr_gm20b.c | 14 ++++--------- .../include/nvgpu/hw/gm20b/hw_gr_gm20b.h | 20 ------------------- 2 files changed, 4 insertions(+), 30 deletions(-) diff --git a/drivers/gpu/nvgpu/gm20b/gr_gm20b.c b/drivers/gpu/nvgpu/gm20b/gr_gm20b.c index bd0026e3c..6ae93f83f 100644 --- a/drivers/gpu/nvgpu/gm20b/gr_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/gr_gm20b.c @@ -468,10 +468,9 @@ int gr_gm20b_dump_gr_status_regs(struct gk20a *g, gk20a_readl(g, gr_pri_gpc0_tpc0_tpccs_tpc_activity_0_r())); if ((gr->config->gpc_tpc_count != NULL) && (gr->config->gpc_tpc_count[0] == 2U)) { gk20a_debug_output(o, "NV_PGRAPH_PRI_GPC0_TPC1_TPCCS_TPC_ACTIVITY0: 0x%x\n", - gk20a_readl(g, gr_pri_gpc0_tpc1_tpccs_tpc_activity_0_r())); + gk20a_readl(g, (gr_pri_gpc0_tpc0_tpccs_tpc_activity_0_r() + + nvgpu_get_litter_value(g, GPU_LIT_TPC_IN_GPC_STRIDE)))); } - gk20a_debug_output(o, "NV_PGRAPH_PRI_GPC0_TPCS_TPCCS_TPC_ACTIVITY0: 0x%x\n", - gk20a_readl(g, gr_pri_gpc0_tpcs_tpccs_tpc_activity_0_r())); gk20a_debug_output(o, "NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY0: 0x%x\n", gk20a_readl(g, gr_pri_gpcs_gpccs_gpc_activity_0_r())); gk20a_debug_output(o, "NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY1: 0x%x\n", @@ -480,18 +479,13 @@ int gr_gm20b_dump_gr_status_regs(struct gk20a *g, gk20a_readl(g, gr_pri_gpcs_gpccs_gpc_activity_2_r())); gk20a_debug_output(o, "NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY3: 0x%x\n", gk20a_readl(g, gr_pri_gpcs_gpccs_gpc_activity_3_r())); - gk20a_debug_output(o, "NV_PGRAPH_PRI_GPCS_TPC0_TPCCS_TPC_ACTIVITY0: 0x%x\n", - gk20a_readl(g, gr_pri_gpcs_tpc0_tpccs_tpc_activity_0_r())); - if ((gr->config->gpc_tpc_count != NULL) && (gr->config->gpc_tpc_count[0] == 2U)) { - gk20a_debug_output(o, "NV_PGRAPH_PRI_GPCS_TPC1_TPCCS_TPC_ACTIVITY0: 0x%x\n", - gk20a_readl(g, gr_pri_gpcs_tpc1_tpccs_tpc_activity_0_r())); - } gk20a_debug_output(o, "NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_TPC_ACTIVITY0: 0x%x\n", gk20a_readl(g, gr_pri_gpcs_tpcs_tpccs_tpc_activity_0_r())); gk20a_debug_output(o, "NV_PGRAPH_PRI_BE0_BECS_BE_ACTIVITY0: 0x%x\n", gk20a_readl(g, gr_pri_be0_becs_be_activity0_r())); gk20a_debug_output(o, "NV_PGRAPH_PRI_BE1_BECS_BE_ACTIVITY0: 0x%x\n", - gk20a_readl(g, gr_pri_be1_becs_be_activity0_r())); + gk20a_readl(g, (gr_pri_be0_becs_be_activity0_r() + + nvgpu_get_litter_value(g, GPU_LIT_ROP_STRIDE)))); gk20a_debug_output(o, "NV_PGRAPH_PRI_BES_BECS_BE_ACTIVITY0: 0x%x\n", gk20a_readl(g, gr_pri_bes_becs_be_activity0_r())); gk20a_debug_output(o, "NV_PGRAPH_PRI_DS_MPIPE_STATUS: 0x%x\n", diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_gr_gm20b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_gr_gm20b.h index 8ce0c4442..7db81f12d 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_gr_gm20b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_gr_gm20b.h @@ -434,14 +434,6 @@ static inline u32 gr_pri_gpc0_tpc0_tpccs_tpc_activity_0_r(void) { return 0x00504500U; } -static inline u32 gr_pri_gpc0_tpc1_tpccs_tpc_activity_0_r(void) -{ - return 0x00504d00U; -} -static inline u32 gr_pri_gpc0_tpcs_tpccs_tpc_activity_0_r(void) -{ - return 0x00501d00U; -} static inline u32 gr_pri_gpcs_gpccs_gpc_activity_0_r(void) { return 0x0041ac80U; @@ -458,14 +450,6 @@ static inline u32 gr_pri_gpcs_gpccs_gpc_activity_3_r(void) { return 0x0041ac8cU; } -static inline u32 gr_pri_gpcs_tpc0_tpccs_tpc_activity_0_r(void) -{ - return 0x0041c500U; -} -static inline u32 gr_pri_gpcs_tpc1_tpccs_tpc_activity_0_r(void) -{ - return 0x0041cd00U; -} static inline u32 gr_pri_gpcs_tpcs_tpccs_tpc_activity_0_r(void) { return 0x00419d00U; @@ -474,10 +458,6 @@ static inline u32 gr_pri_be0_becs_be_activity0_r(void) { return 0x00410200U; } -static inline u32 gr_pri_be1_becs_be_activity0_r(void) -{ - return 0x00410600U; -} static inline u32 gr_pri_bes_becs_be_activity0_r(void) { return 0x00408a00U;