From e00eabcbd32320e97df73ad3b6f8670bd6ecaf15 Mon Sep 17 00:00:00 2001 From: Sagar Kamble Date: Tue, 31 Aug 2021 18:38:35 +0530 Subject: [PATCH] gpu: nvgpu: reset ltc_ltc0_lts0_intr3 register LTC INTR3 register is not reset after handling. Reset it. JIRA NVGPU-6982 Change-Id: I6ab9e6de515e3dd2b45240d1a6953ffef171e1c0 Signed-off-by: Sagar Kamble Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2586573 (cherry picked from commit bc754e5b0494d3ea2da71f186126f19ef5686c08) Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2623622 Tested-by: mobile promotions Reviewed-by: svc-mobile-coverity Reviewed-by: svc-mobile-misra Reviewed-by: svc-mobile-cert Reviewed-by: svcacv Reviewed-by: Vaibhav Kachore Reviewed-by: mobile promotions GVS: Gerrit_Virtual_Submit --- drivers/gpu/nvgpu/hal/ltc/intr/ltc_intr_gv11b_fusa.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/nvgpu/hal/ltc/intr/ltc_intr_gv11b_fusa.c b/drivers/gpu/nvgpu/hal/ltc/intr/ltc_intr_gv11b_fusa.c index 6b90dbdd1..f277b8164 100644 --- a/drivers/gpu/nvgpu/hal/ltc/intr/ltc_intr_gv11b_fusa.c +++ b/drivers/gpu/nvgpu/hal/ltc/intr/ltc_intr_gv11b_fusa.c @@ -1,7 +1,7 @@ /* * GV11B LTC INTR * - * Copyright (c) 2016-2020, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2016-2021, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -294,6 +294,10 @@ static void gv11b_ltc_intr_handle_lts_interrupts(struct gk20a *g, } nvgpu_log(g, gpu_dbg_intr, "ecc error address: 0x%x", ecc_addr); + + nvgpu_writel(g, + nvgpu_safe_add_u32(ltc_ltc0_lts0_intr3_r(), offset), + ltc_intr3); } gp10b_ltc_intr_handle_lts_interrupts(g, ltc, slice);