From e02ea5456b9979e54264d8fe74d8c277b9dea8b7 Mon Sep 17 00:00:00 2001 From: Antony Clince Alex Date: Wed, 5 Aug 2020 19:08:32 +0530 Subject: [PATCH] gpu: nvgpu: tu104: update offset calculation of gpccs ctxsw'ed priregs The ctxsw'ed registers have been moved to a separate list starting from nvgpu_next chip onwards. Hence, update gr_tu104_get_offset_in_gpccs_segment function to account for ctxsw'ed registers in nvgpu_next. Introduce functions: nvgpu_netlist_get_gpc_ctxsw_regs_count to compute the number of ctxsw'ed gpc registers. Bug 2916121 Change-Id: I69fcd8df883af62999d0fa8d1f9a398f8f5d7454 Signed-off-by: Antony Clince Alex Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2394684 Tested-by: mobile promotions Reviewed-by: svc-mobile-coverity Reviewed-by: svc-mobile-cert Reviewed-by: automaticguardword Reviewed-by: Alex Waterman Reviewed-by: Seema Khowala Reviewed-by: Deepak Nibade Reviewed-by: svc-mobile-misra Reviewed-by: Vaibhav Kachore Reviewed-by: mobile promotions GVS: Gerrit_Virtual_Submit --- drivers/gpu/nvgpu/common/netlist/netlist.c | 12 ++++++++++++ drivers/gpu/nvgpu/hal/gr/gr/gr_tu104.c | 6 +++--- drivers/gpu/nvgpu/include/nvgpu/netlist.h | 1 + 3 files changed, 16 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/nvgpu/common/netlist/netlist.c b/drivers/gpu/nvgpu/common/netlist/netlist.c index 602012e14..a097e20b4 100644 --- a/drivers/gpu/nvgpu/common/netlist/netlist.c +++ b/drivers/gpu/nvgpu/common/netlist/netlist.c @@ -901,6 +901,18 @@ u32 nvgpu_netlist_get_ppc_ctxsw_regs_count(struct gk20a *g) return count; } +u32 nvgpu_netlist_get_gpc_ctxsw_regs_count(struct gk20a *g) +{ + u32 count = nvgpu_netlist_get_gpc_ctxsw_regs(g)->count; + +#if defined(CONFIG_NVGPU_NON_FUSA) && defined(CONFIG_NVGPU_NEXT) + if (count == 0U) { + count = nvgpu_next_netlist_get_gpc_ctxsw_regs_count(g); + } +#endif + return count; +} + u32 nvgpu_netlist_get_tpc_ctxsw_regs_count(struct gk20a *g) { u32 count = nvgpu_netlist_get_tpc_ctxsw_regs(g)->count; diff --git a/drivers/gpu/nvgpu/hal/gr/gr/gr_tu104.c b/drivers/gpu/nvgpu/hal/gr/gr/gr_tu104.c index 731d8aa7e..3aa2d82fb 100644 --- a/drivers/gpu/nvgpu/hal/gr/gr/gr_tu104.c +++ b/drivers/gpu/nvgpu/hal/gr/gr/gr_tu104.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018-2019, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2018-2020, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -41,8 +41,8 @@ int gr_tu104_get_offset_in_gpccs_segment(struct gk20a *g, u32 offset_in_segment = 0; u32 num_pes_per_gpc = nvgpu_get_litter_value(g, GPU_LIT_NUM_PES_PER_GPC); - u32 tpc_count = nvgpu_netlist_get_tpc_ctxsw_regs(g)->count; - u32 gpc_count = nvgpu_netlist_get_gpc_ctxsw_regs(g)->count; + u32 tpc_count = nvgpu_netlist_get_tpc_ctxsw_regs_count(g); + u32 gpc_count = nvgpu_netlist_get_gpc_ctxsw_regs_count(g); if (addr_type == CTXSW_ADDR_TYPE_TPC) { /* diff --git a/drivers/gpu/nvgpu/include/nvgpu/netlist.h b/drivers/gpu/nvgpu/include/nvgpu/netlist.h index c63add0bd..f95cdc0ab 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/netlist.h +++ b/drivers/gpu/nvgpu/include/nvgpu/netlist.h @@ -389,6 +389,7 @@ struct netlist_aiv_list *nvgpu_netlist_get_perf_gpc_control_ctxsw_regs( struct netlist_aiv_list *nvgpu_netlist_get_perf_pma_control_ctxsw_regs( struct gk20a *g); u32 nvgpu_netlist_get_ppc_ctxsw_regs_count(struct gk20a *g); +u32 nvgpu_netlist_get_gpc_ctxsw_regs_count(struct gk20a *g); u32 nvgpu_netlist_get_tpc_ctxsw_regs_count(struct gk20a *g); u32 nvgpu_netlist_get_etpc_ctxsw_regs_count(struct gk20a *g); #endif /* CONFIG_NVGPU_DEBUGGER */