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gpu: nvgpu: add runlist unit to common
Extract non-chip-specific code that manages the runlists (init, update, reschedule etc.) to a new file in the common directory. Move the declarations to a new matching runlist.h header. Jira NVGPU-1309 Change-Id: I3c7e0032899516487037f47ddc9a7e7aa4b0b33a Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1978058 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Konsta Holtta
committed by
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5504d368ec
commit
e05c0d13a0
@@ -44,6 +44,7 @@
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#include <nvgpu/io.h>
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#include <nvgpu/utils.h>
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#include <nvgpu/fifo.h>
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#include <nvgpu/runlist.h>
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#include <nvgpu/gk20a.h>
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#include <nvgpu/channel.h>
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#include <nvgpu/unit.h>
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@@ -393,42 +394,6 @@ u32 gk20a_fifo_engine_interrupt_mask(struct gk20a *g)
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return eng_intr_mask;
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}
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void gk20a_fifo_delete_runlist(struct fifo_gk20a *f)
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{
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u32 i;
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u32 runlist_id;
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struct fifo_runlist_info_gk20a *runlist;
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struct gk20a *g = NULL;
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if ((f == NULL) || (f->runlist_info == NULL)) {
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return;
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}
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g = f->g;
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for (runlist_id = 0; runlist_id < f->max_runlists; runlist_id++) {
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runlist = &f->runlist_info[runlist_id];
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for (i = 0; i < MAX_RUNLIST_BUFFERS; i++) {
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nvgpu_dma_free(g, &runlist->mem[i]);
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}
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nvgpu_kfree(g, runlist->active_channels);
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runlist->active_channels = NULL;
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nvgpu_kfree(g, runlist->active_tsgs);
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runlist->active_tsgs = NULL;
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nvgpu_mutex_destroy(&runlist->runlist_lock);
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}
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(void) memset(f->runlist_info, 0,
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(sizeof(struct fifo_runlist_info_gk20a) * f->max_runlists));
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nvgpu_kfree(g, f->runlist_info);
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f->runlist_info = NULL;
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f->max_runlists = 0;
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}
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static void gk20a_remove_fifo_support(struct fifo_gk20a *f)
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{
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struct gk20a *g = f->g;
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@@ -482,104 +447,6 @@ static void gk20a_remove_fifo_support(struct fifo_gk20a *f)
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f->active_engines_list = NULL;
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}
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static int init_runlist(struct gk20a *g, struct fifo_gk20a *f)
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{
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struct fifo_runlist_info_gk20a *runlist;
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struct fifo_engine_info_gk20a *engine_info;
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unsigned int runlist_id;
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u32 i;
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size_t runlist_size;
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u32 active_engine_id, pbdma_id, engine_id;
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int err = 0;
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nvgpu_log_fn(g, " ");
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f->max_runlists = g->ops.fifo.eng_runlist_base_size();
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f->runlist_info = nvgpu_kzalloc(g,
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sizeof(struct fifo_runlist_info_gk20a) *
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f->max_runlists);
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if (f->runlist_info == NULL) {
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goto clean_up_runlist;
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}
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(void) memset(f->runlist_info, 0,
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(sizeof(struct fifo_runlist_info_gk20a) * f->max_runlists));
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for (runlist_id = 0; runlist_id < f->max_runlists; runlist_id++) {
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runlist = &f->runlist_info[runlist_id];
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runlist->active_channels =
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nvgpu_kzalloc(g, DIV_ROUND_UP(f->num_channels,
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BITS_PER_BYTE));
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if (runlist->active_channels == NULL) {
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goto clean_up_runlist;
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}
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runlist->active_tsgs =
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nvgpu_kzalloc(g, DIV_ROUND_UP(f->num_channels,
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BITS_PER_BYTE));
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if (runlist->active_tsgs == NULL) {
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goto clean_up_runlist;
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}
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runlist_size = (size_t)f->runlist_entry_size *
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(size_t)f->num_runlist_entries;
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nvgpu_log(g, gpu_dbg_info,
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"runlist_entries %d runlist size %zu",
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f->num_runlist_entries, runlist_size);
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for (i = 0; i < MAX_RUNLIST_BUFFERS; i++) {
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err = nvgpu_dma_alloc_flags_sys(g,
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NVGPU_DMA_PHYSICALLY_ADDRESSED,
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runlist_size,
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&runlist->mem[i]);
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if (err != 0) {
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nvgpu_err(g, "memory allocation failed");
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goto clean_up_runlist;
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}
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}
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err = nvgpu_mutex_init(&runlist->runlist_lock);
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if (err != 0) {
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nvgpu_err(g,
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"Error in runlist_lock mutex initialization");
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goto clean_up_runlist;
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}
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/* None of buffers is pinned if this value doesn't change.
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Otherwise, one of them (cur_buffer) must have been pinned. */
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runlist->cur_buffer = MAX_RUNLIST_BUFFERS;
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for (pbdma_id = 0; pbdma_id < f->num_pbdma; pbdma_id++) {
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if ((f->pbdma_map[pbdma_id] & BIT32(runlist_id)) != 0U) {
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runlist->pbdma_bitmask |= BIT32(pbdma_id);
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}
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}
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nvgpu_log(g, gpu_dbg_info, "runlist %d : pbdma bitmask 0x%x",
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runlist_id, runlist->pbdma_bitmask);
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for (engine_id = 0; engine_id < f->num_engines; ++engine_id) {
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active_engine_id = f->active_engines_list[engine_id];
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engine_info = &f->engine_info[active_engine_id];
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if ((engine_info != NULL) &&
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(engine_info->runlist_id == runlist_id)) {
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runlist->eng_bitmask |= BIT(active_engine_id);
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}
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}
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nvgpu_log(g, gpu_dbg_info, "runlist %d : act eng bitmask 0x%x",
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runlist_id, runlist->eng_bitmask);
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}
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nvgpu_log_fn(g, "done");
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return 0;
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clean_up_runlist:
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gk20a_fifo_delete_runlist(f);
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nvgpu_log_fn(g, "fail");
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return err;
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}
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u32 gk20a_fifo_intr_0_error_mask(struct gk20a *g)
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{
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u32 intr_0_error_mask =
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@@ -752,7 +619,7 @@ int gk20a_init_fifo_setup_sw_common(struct gk20a *g)
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g->ops.fifo.init_engine_info(f);
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err = init_runlist(g, f);
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err = nvgpu_init_runlist(g, f);
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if (err != 0) {
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nvgpu_err(g, "failed to init runlist");
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goto clean_up;
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@@ -2851,16 +2718,6 @@ u32 gk20a_fifo_runlist_busy_engines(struct gk20a *g, u32 runlist_id)
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return engines;
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}
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static void gk20a_fifo_runlist_reset_engines(struct gk20a *g, u32 runlist_id)
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{
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u32 engines = g->ops.fifo.runlist_busy_engines(g, runlist_id);
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if (engines != 0U) {
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gk20a_fifo_recover(g, engines, ~(u32)0, false, false, true,
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RC_TYPE_RUNLIST_UPDATE_TIMEOUT);
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}
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}
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int gk20a_fifo_runlist_wait_pending(struct gk20a *g, u32 runlist_id)
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{
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struct nvgpu_timeout timeout;
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@@ -2938,254 +2795,6 @@ void gk20a_get_ch_runlist_entry(struct channel_gk20a *ch, u32 *runlist)
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runlist[1] = 0;
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}
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static u32 nvgpu_runlist_append_tsg(struct gk20a *g,
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struct fifo_runlist_info_gk20a *runlist,
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u32 **runlist_entry,
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u32 *entries_left,
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struct tsg_gk20a *tsg)
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{
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struct fifo_gk20a *f = &g->fifo;
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u32 runlist_entry_words = f->runlist_entry_size / (u32)sizeof(u32);
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struct channel_gk20a *ch;
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u32 count = 0;
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nvgpu_log_fn(f->g, " ");
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if (*entries_left == 0U) {
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return RUNLIST_APPEND_FAILURE;
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}
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/* add TSG entry */
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nvgpu_log_info(g, "add TSG %d to runlist", tsg->tsgid);
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g->ops.fifo.get_tsg_runlist_entry(tsg, *runlist_entry);
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nvgpu_log_info(g, "tsg rl entries left %d runlist [0] %x [1] %x",
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*entries_left,
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(*runlist_entry)[0], (*runlist_entry)[1]);
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*runlist_entry += runlist_entry_words;
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count++;
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(*entries_left)--;
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nvgpu_rwsem_down_read(&tsg->ch_list_lock);
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/* add runnable channels bound to this TSG */
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nvgpu_list_for_each_entry(ch, &tsg->ch_list,
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channel_gk20a, ch_entry) {
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if (!test_bit((int)ch->chid,
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runlist->active_channels)) {
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continue;
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}
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if (*entries_left == 0U) {
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nvgpu_rwsem_up_read(&tsg->ch_list_lock);
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return RUNLIST_APPEND_FAILURE;
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}
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nvgpu_log_info(g, "add channel %d to runlist",
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ch->chid);
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g->ops.fifo.get_ch_runlist_entry(ch, *runlist_entry);
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nvgpu_log_info(g, "rl entries left %d runlist [0] %x [1] %x",
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*entries_left,
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(*runlist_entry)[0], (*runlist_entry)[1]);
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count++;
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*runlist_entry += runlist_entry_words;
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(*entries_left)--;
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}
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nvgpu_rwsem_up_read(&tsg->ch_list_lock);
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return count;
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}
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static u32 nvgpu_runlist_append_prio(struct fifo_gk20a *f,
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struct fifo_runlist_info_gk20a *runlist,
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u32 **runlist_entry,
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u32 *entries_left,
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u32 interleave_level)
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{
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u32 count = 0;
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unsigned long tsgid;
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nvgpu_log_fn(f->g, " ");
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for_each_set_bit(tsgid, runlist->active_tsgs, f->num_channels) {
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struct tsg_gk20a *tsg = &f->tsg[tsgid];
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u32 entries;
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if (tsg->interleave_level == interleave_level) {
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entries = nvgpu_runlist_append_tsg(f->g, runlist,
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runlist_entry, entries_left, tsg);
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if (entries == RUNLIST_APPEND_FAILURE) {
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return RUNLIST_APPEND_FAILURE;
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}
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count += entries;
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}
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}
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return count;
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}
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static u32 nvgpu_runlist_append_hi(struct fifo_gk20a *f,
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struct fifo_runlist_info_gk20a *runlist,
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u32 **runlist_entry,
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u32 *entries_left)
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{
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nvgpu_log_fn(f->g, " ");
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/*
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* No higher levels - this is where the "recursion" ends; just add all
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* active TSGs at this level.
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*/
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return nvgpu_runlist_append_prio(f, runlist, runlist_entry,
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entries_left,
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NVGPU_FIFO_RUNLIST_INTERLEAVE_LEVEL_HIGH);
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}
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static u32 nvgpu_runlist_append_med(struct fifo_gk20a *f,
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struct fifo_runlist_info_gk20a *runlist,
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u32 **runlist_entry,
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u32 *entries_left)
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{
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u32 count = 0;
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unsigned long tsgid;
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nvgpu_log_fn(f->g, " ");
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for_each_set_bit(tsgid, runlist->active_tsgs, f->num_channels) {
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struct tsg_gk20a *tsg = &f->tsg[tsgid];
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u32 entries;
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if (tsg->interleave_level !=
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NVGPU_FIFO_RUNLIST_INTERLEAVE_LEVEL_MEDIUM) {
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continue;
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}
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/* LEVEL_MEDIUM list starts with a LEVEL_HIGH, if any */
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entries = nvgpu_runlist_append_hi(f, runlist,
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runlist_entry, entries_left);
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if (entries == RUNLIST_APPEND_FAILURE) {
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return RUNLIST_APPEND_FAILURE;
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}
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count += entries;
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entries = nvgpu_runlist_append_tsg(f->g, runlist,
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runlist_entry, entries_left, tsg);
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if (entries == RUNLIST_APPEND_FAILURE) {
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return RUNLIST_APPEND_FAILURE;
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}
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count += entries;
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}
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return count;
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}
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static u32 nvgpu_runlist_append_low(struct fifo_gk20a *f,
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struct fifo_runlist_info_gk20a *runlist,
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u32 **runlist_entry,
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u32 *entries_left)
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{
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u32 count = 0;
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unsigned long tsgid;
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nvgpu_log_fn(f->g, " ");
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for_each_set_bit(tsgid, runlist->active_tsgs, f->num_channels) {
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struct tsg_gk20a *tsg = &f->tsg[tsgid];
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u32 entries;
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if (tsg->interleave_level !=
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NVGPU_FIFO_RUNLIST_INTERLEAVE_LEVEL_LOW) {
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continue;
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}
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/* The medium level starts with the highs, if any. */
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entries = nvgpu_runlist_append_med(f, runlist,
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runlist_entry, entries_left);
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if (entries == RUNLIST_APPEND_FAILURE) {
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return RUNLIST_APPEND_FAILURE;
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}
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count += entries;
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entries = nvgpu_runlist_append_hi(f, runlist,
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runlist_entry, entries_left);
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if (entries == RUNLIST_APPEND_FAILURE) {
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return RUNLIST_APPEND_FAILURE;
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}
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count += entries;
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entries = nvgpu_runlist_append_tsg(f->g, runlist,
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runlist_entry, entries_left, tsg);
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if (entries == RUNLIST_APPEND_FAILURE) {
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return RUNLIST_APPEND_FAILURE;
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}
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count += entries;
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}
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if (count == 0U) {
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/*
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* No transitions to fill with higher levels, so add
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* the next level once. If that's empty too, we have only
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* LEVEL_HIGH jobs.
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*/
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count = nvgpu_runlist_append_med(f, runlist,
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runlist_entry, entries_left);
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if (count == 0U) {
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count = nvgpu_runlist_append_hi(f, runlist,
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runlist_entry, entries_left);
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}
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}
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return count;
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}
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static u32 nvgpu_runlist_append_flat(struct fifo_gk20a *f,
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struct fifo_runlist_info_gk20a *runlist,
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u32 **runlist_entry,
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u32 *entries_left)
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{
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u32 count = 0, entries, i;
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nvgpu_log_fn(f->g, " ");
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/* Group by priority but don't interleave. High comes first. */
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for (i = 0; i < NVGPU_FIFO_RUNLIST_INTERLEAVE_NUM_LEVELS; i++) {
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u32 level = NVGPU_FIFO_RUNLIST_INTERLEAVE_LEVEL_HIGH - i;
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entries = nvgpu_runlist_append_prio(f, runlist, runlist_entry,
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entries_left, level);
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if (entries == RUNLIST_APPEND_FAILURE) {
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return RUNLIST_APPEND_FAILURE;
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}
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count += entries;
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}
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return count;
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}
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u32 nvgpu_runlist_construct_locked(struct fifo_gk20a *f,
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struct fifo_runlist_info_gk20a *runlist,
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u32 buf_id,
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u32 max_entries)
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{
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u32 *runlist_entry_base = runlist->mem[buf_id].cpu_va;
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nvgpu_log_fn(f->g, " ");
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/*
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* The entry pointer and capacity counter that live on the stack here
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* keep track of the current position and the remaining space when tsg
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* and channel entries are ultimately appended.
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*/
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if (f->g->runlist_interleave) {
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return nvgpu_runlist_append_low(f, runlist,
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&runlist_entry_base, &max_entries);
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} else {
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return nvgpu_runlist_append_flat(f, runlist,
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&runlist_entry_base, &max_entries);
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}
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}
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int gk20a_fifo_set_runlist_interleave(struct gk20a *g,
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u32 id,
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u32 runlist_id,
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@@ -3242,131 +2851,6 @@ void gk20a_fifo_runlist_hw_submit(struct gk20a *g, u32 runlist_id,
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nvgpu_spinlock_release(&g->fifo.runlist_submit_lock);
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}
|
||||
|
||||
int gk20a_fifo_update_runlist_locked(struct gk20a *g, u32 runlist_id,
|
||||
u32 chid, bool add,
|
||||
bool wait_for_finish)
|
||||
{
|
||||
int ret = 0;
|
||||
struct fifo_gk20a *f = &g->fifo;
|
||||
struct fifo_runlist_info_gk20a *runlist = NULL;
|
||||
u64 runlist_iova;
|
||||
u32 new_buf;
|
||||
struct channel_gk20a *ch = NULL;
|
||||
struct tsg_gk20a *tsg = NULL;
|
||||
|
||||
runlist = &f->runlist_info[runlist_id];
|
||||
|
||||
/* valid channel, add/remove it from active list.
|
||||
Otherwise, keep active list untouched for suspend/resume. */
|
||||
if (chid != FIFO_INVAL_CHANNEL_ID) {
|
||||
ch = &f->channel[chid];
|
||||
if (gk20a_is_channel_marked_as_tsg(ch)) {
|
||||
tsg = &f->tsg[ch->tsgid];
|
||||
}
|
||||
|
||||
if (add) {
|
||||
if (test_and_set_bit(chid,
|
||||
runlist->active_channels)) {
|
||||
return 0;
|
||||
}
|
||||
if ((tsg != NULL) && (++tsg->num_active_channels != 0U)) {
|
||||
set_bit((int)f->channel[chid].tsgid,
|
||||
runlist->active_tsgs);
|
||||
}
|
||||
} else {
|
||||
if (!test_and_clear_bit(chid,
|
||||
runlist->active_channels)) {
|
||||
return 0;
|
||||
}
|
||||
if ((tsg != NULL) &&
|
||||
(--tsg->num_active_channels == 0U)) {
|
||||
clear_bit((int)f->channel[chid].tsgid,
|
||||
runlist->active_tsgs);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/* There just 2 buffers */
|
||||
new_buf = runlist->cur_buffer == 0U ? 1U : 0U;
|
||||
|
||||
runlist_iova = nvgpu_mem_get_addr(g, &runlist->mem[new_buf]);
|
||||
|
||||
nvgpu_log_info(g, "runlist_id : %d, switch to new buffer 0x%16llx",
|
||||
runlist_id, (u64)runlist_iova);
|
||||
|
||||
if (runlist_iova == 0ULL) {
|
||||
ret = -EINVAL;
|
||||
goto clean_up;
|
||||
}
|
||||
|
||||
if (chid != FIFO_INVAL_CHANNEL_ID || /* add/remove a valid channel */
|
||||
add /* resume to add all channels back */) {
|
||||
u32 num_entries;
|
||||
|
||||
num_entries = nvgpu_runlist_construct_locked(f,
|
||||
runlist,
|
||||
new_buf,
|
||||
f->num_runlist_entries);
|
||||
if (num_entries == RUNLIST_APPEND_FAILURE) {
|
||||
ret = -E2BIG;
|
||||
goto clean_up;
|
||||
}
|
||||
runlist->count = num_entries;
|
||||
WARN_ON(runlist->count > f->num_runlist_entries);
|
||||
} else {
|
||||
/* suspend to remove all channels */
|
||||
runlist->count = 0;
|
||||
}
|
||||
|
||||
g->ops.fifo.runlist_hw_submit(g, runlist_id, runlist->count, new_buf);
|
||||
|
||||
if (wait_for_finish) {
|
||||
ret = g->ops.fifo.runlist_wait_pending(g, runlist_id);
|
||||
|
||||
if (ret == -ETIMEDOUT) {
|
||||
nvgpu_err(g, "runlist %d update timeout", runlist_id);
|
||||
/* trigger runlist update timeout recovery */
|
||||
return ret;
|
||||
|
||||
} else if (ret == -EINTR) {
|
||||
nvgpu_err(g, "runlist update interrupted");
|
||||
}
|
||||
}
|
||||
|
||||
runlist->cur_buffer = new_buf;
|
||||
|
||||
clean_up:
|
||||
return ret;
|
||||
}
|
||||
|
||||
int gk20a_fifo_update_runlist_ids(struct gk20a *g, u32 runlist_ids, u32 chid,
|
||||
bool add, bool wait_for_finish)
|
||||
{
|
||||
int ret = -EINVAL;
|
||||
unsigned long runlist_id = 0;
|
||||
int errcode;
|
||||
unsigned long ulong_runlist_ids = (unsigned long)runlist_ids;
|
||||
|
||||
if (g == NULL) {
|
||||
goto end;
|
||||
}
|
||||
|
||||
ret = 0;
|
||||
for_each_set_bit(runlist_id, &ulong_runlist_ids, 32U) {
|
||||
/* Capture the last failure error code */
|
||||
errcode = g->ops.fifo.update_runlist(g, (u32)runlist_id, chid,
|
||||
add, wait_for_finish);
|
||||
if (errcode != 0) {
|
||||
nvgpu_err(g,
|
||||
"failed to update_runlist %lu %d",
|
||||
runlist_id, errcode);
|
||||
ret = errcode;
|
||||
}
|
||||
}
|
||||
end:
|
||||
return ret;
|
||||
}
|
||||
|
||||
/* trigger host preempt of GR pending load ctx if that ctx is not for ch */
|
||||
int gk20a_fifo_reschedule_preempt_next(struct channel_gk20a *ch,
|
||||
bool wait_preempt)
|
||||
@@ -3433,79 +2917,6 @@ int gk20a_fifo_reschedule_runlist(struct channel_gk20a *ch, bool preempt_next)
|
||||
return nvgpu_fifo_reschedule_runlist(ch, preempt_next, true);
|
||||
}
|
||||
|
||||
/* trigger host to expire current timeslice and reschedule runlist from front */
|
||||
int nvgpu_fifo_reschedule_runlist(struct channel_gk20a *ch, bool preempt_next,
|
||||
bool wait_preempt)
|
||||
{
|
||||
struct gk20a *g = ch->g;
|
||||
struct fifo_runlist_info_gk20a *runlist;
|
||||
u32 token = PMU_INVALID_MUTEX_OWNER_ID;
|
||||
int mutex_ret;
|
||||
int ret = 0;
|
||||
|
||||
runlist = &g->fifo.runlist_info[ch->runlist_id];
|
||||
if (nvgpu_mutex_tryacquire(&runlist->runlist_lock) == 0) {
|
||||
return -EBUSY;
|
||||
}
|
||||
|
||||
mutex_ret = nvgpu_pmu_mutex_acquire(
|
||||
&g->pmu, PMU_MUTEX_ID_FIFO, &token);
|
||||
|
||||
g->ops.fifo.runlist_hw_submit(
|
||||
g, ch->runlist_id, runlist->count, runlist->cur_buffer);
|
||||
|
||||
if (preempt_next) {
|
||||
g->ops.fifo.reschedule_preempt_next_locked(ch, wait_preempt);
|
||||
}
|
||||
|
||||
gk20a_fifo_runlist_wait_pending(g, ch->runlist_id);
|
||||
|
||||
if (mutex_ret == 0) {
|
||||
nvgpu_pmu_mutex_release(
|
||||
&g->pmu, PMU_MUTEX_ID_FIFO, &token);
|
||||
}
|
||||
nvgpu_mutex_release(&runlist->runlist_lock);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
/* add/remove a channel from runlist
|
||||
special cases below: runlist->active_channels will NOT be changed.
|
||||
(chid == ~0 && !add) means remove all active channels from runlist.
|
||||
(chid == ~0 && add) means restore all active channels on runlist. */
|
||||
int gk20a_fifo_update_runlist(struct gk20a *g, u32 runlist_id, u32 chid,
|
||||
bool add, bool wait_for_finish)
|
||||
{
|
||||
struct fifo_runlist_info_gk20a *runlist = NULL;
|
||||
struct fifo_gk20a *f = &g->fifo;
|
||||
u32 token = PMU_INVALID_MUTEX_OWNER_ID;
|
||||
int mutex_ret;
|
||||
int ret = 0;
|
||||
|
||||
nvgpu_log_fn(g, " ");
|
||||
|
||||
runlist = &f->runlist_info[runlist_id];
|
||||
|
||||
nvgpu_mutex_acquire(&runlist->runlist_lock);
|
||||
|
||||
mutex_ret = nvgpu_pmu_mutex_acquire(&g->pmu, PMU_MUTEX_ID_FIFO, &token);
|
||||
|
||||
ret = gk20a_fifo_update_runlist_locked(g, runlist_id, chid, add,
|
||||
wait_for_finish);
|
||||
|
||||
if (mutex_ret == 0) {
|
||||
nvgpu_pmu_mutex_release(&g->pmu, PMU_MUTEX_ID_FIFO, &token);
|
||||
}
|
||||
|
||||
nvgpu_mutex_release(&runlist->runlist_lock);
|
||||
|
||||
if (ret == -ETIMEDOUT) {
|
||||
gk20a_fifo_runlist_reset_engines(g, runlist_id);
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
int gk20a_fifo_suspend(struct gk20a *g)
|
||||
{
|
||||
nvgpu_log_fn(g, " ");
|
||||
@@ -4201,31 +3612,6 @@ u32 gk20a_fifo_pbdma_acquire_val(u64 timeout)
|
||||
return val;
|
||||
}
|
||||
|
||||
const char *gk20a_fifo_interleave_level_name(u32 interleave_level)
|
||||
{
|
||||
const char *ret_string = NULL;
|
||||
|
||||
switch (interleave_level) {
|
||||
case NVGPU_FIFO_RUNLIST_INTERLEAVE_LEVEL_LOW:
|
||||
ret_string = "LOW";
|
||||
break;
|
||||
|
||||
case NVGPU_FIFO_RUNLIST_INTERLEAVE_LEVEL_MEDIUM:
|
||||
ret_string = "MEDIUM";
|
||||
break;
|
||||
|
||||
case NVGPU_FIFO_RUNLIST_INTERLEAVE_LEVEL_HIGH:
|
||||
ret_string = "HIGH";
|
||||
break;
|
||||
|
||||
default:
|
||||
ret_string = "?";
|
||||
break;
|
||||
}
|
||||
|
||||
return ret_string;
|
||||
}
|
||||
|
||||
u32 gk20a_fifo_get_sema_wait_cmd_size(void)
|
||||
{
|
||||
return 8;
|
||||
|
||||
Reference in New Issue
Block a user