gpu: nvgpu: FALCON/FALCON2 core selection based on fuse

-Read the PMU and GSP fuse to select the FALCON/FALCON2 core
-FUSE read based on FALCON id is done in FUSE unit
-Core selection and info dump based on fuse is done in FALCON unit

JIRA NVGPU-6369

Change-Id: I0747f7383c60f546bbce94eb89c0a8bd41fa7471
Signed-off-by: mkumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2465808
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: svc_kernel_abi <svc_kernel_abi@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

drivers/gpu/nvgpu/common/falcon/falcon.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2017-2020, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2017-2021, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -401,6 +401,19 @@ u32 nvgpu_falcon_get_id(struct nvgpu_falcon *flcn)
 	return flcn->flcn_id;
 }
 
+#if defined(CONFIG_NVGPU_NEXT)
+bool nvgpu_falcon_is_falcon2_enabled(struct nvgpu_falcon *flcn)
+{
+	return flcn->is_falcon2_enabled ? true : false;
+}
+
+bool nvgpu_falcon_is_feature_supported(struct nvgpu_falcon *flcn,
+		u32 feature)
+{
+	return nvgpu_test_bit(feature, (void *)&flcn->fuse_settings);
+}
+#endif
+
 struct nvgpu_falcon *nvgpu_falcon_get_instance(struct gk20a *g, u32 flcn_id)
 {
 	struct nvgpu_falcon *flcn = NULL;

drivers/gpu/nvgpu/common/pmu/pmu.c

@@ -182,6 +182,12 @@ int nvgpu_pmu_early_init(struct gk20a *g)
 	pmu->g = g;
 	pmu->flcn = &g->pmu_flcn;
 
+#if defined(CONFIG_NVGPU_NEXT)
+	if (nvgpu_falcon_is_falcon2_enabled(&g->pmu_flcn)) {
+		nvgpu_set_enabled(g, NVGPU_PMU_NEXT_CORE_ENABLED, true);
+	}
+#endif
+
 	if ((g->ops.pmu.ecc_init != NULL) && !g->ecc.initialized) {
 		err = g->ops.pmu.ecc_init(g);
 		if (err != 0) {

drivers/gpu/nvgpu/include/nvgpu/falcon.h

@@ -175,6 +175,25 @@
 #define APP_0_CODE_OFFSET 0x5U
 #define APP_0_CODE_SIZE   0x6U
 
+/**
+ * Falcon/Falcon2 fuse settings bit
+ */
+#if defined(CONFIG_NVGPU_NEXT)
+#define FALCON_DISABLE                         (0U)
+#define FALCON_FORCE_ENCRYPTION_EN             (1U)
+#define NVRISCV_BR_ERROR_INFO_EN               (2U)
+#define NVRISCV_DEV_DIS                        (3U)
+#define NVRISCV_PL3_DISABLE                    (4U)
+#define DEFAULT_CORE_SELECT                    (5U)
+#define NVRISCV_DCLS_EN                        (6U)
+#define NVRISCV_DCLS_SECURITY_ACTION_ASSERT    (7U)
+#define NVRISCV_DCLS_SECURITY_ACTION_HALT      (8U)
+#define NVRISCV_DCLS_SECURITY_ACTION_INTERRUPT (9U)
+#define SECURE_DEBUG_DISABLE                   (10U)
+#define AES_ALGO_DISABLE                       (11U)
+#define PKC_ALGO_DISABLE                       (12U)
+#endif
+
 struct gk20a;
 struct nvgpu_falcon;
 
@@ -224,6 +243,10 @@ struct nvgpu_falcon {
 	bool is_falcon2_enabled;
 	/** Indicates if the falcon interrupts are enabled. */
 	bool is_interrupt_enabled;
+#if defined(CONFIG_NVGPU_NEXT)
+	/** Fuse settings */
+	unsigned long fuse_settings;
+#endif
 	/** Lock to access the falcon's IMEM. */
 	struct nvgpu_mutex imem_lock;
 	/** Lock to access the falcon's DMEM. */
@@ -633,6 +656,10 @@ void nvgpu_falcon_sw_free(struct gk20a *g, u32 flcn_id);
 void nvgpu_falcon_set_irq(struct nvgpu_falcon *flcn, bool enable,
 	u32 intr_mask, u32 intr_dest);
 
+bool nvgpu_falcon_is_falcon2_enabled(struct nvgpu_falcon *flcn);
+bool nvgpu_falcon_is_feature_supported(struct nvgpu_falcon *flcn,
+		u32 feature);
+
 #ifdef CONFIG_NVGPU_DGPU
 int nvgpu_falcon_copy_from_emem(struct nvgpu_falcon *flcn,
 	u32 src, u8 *dst, u32 size, u8 port);

drivers/gpu/nvgpu/include/nvgpu/gops/fuse.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2019-2020, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2019-2021, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -218,6 +218,11 @@ struct gops_fuse {
 	int (*read_ucode_version)(struct gk20a *g, u32 falcon_id,
 			u32 *ucode_version);
 
+#if defined(CONFIG_NVGPU_NEXT)
+	int (*fetch_falcon_fuse_settings)(struct gk20a *g, u32 falcon_id,
+			unsigned long *fuse_settings);
+#endif
+
 #if defined(CONFIG_NVGPU_HAL_NON_FUSA) && defined(CONFIG_NVGPU_NEXT)
 #include "include/nvgpu/nvgpu_next_gops_fuse.h"
 #endif