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gpu: nvgpu: update hw headers to fix MISRA errors

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This patch updates hw headers corresponding to changes in gen_registers
scripts.

Jira NVGPU-3839

Change-Id: Ief4f1545fdc5186d50a00289150d71fdae158641
Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2155611
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Vedashree Vidwans
2019-07-18 11:08:26 -07:00
committed by mobile promotions
parent 4c509a6df7
commit e08e705087
150 changed files with 4712 additions and 4349 deletions
Download Patch File Download Diff File Expand all files Collapse all files

6
drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_bus_gk20a.h
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@@ -60,19 +60,19 @@
#include <nvgpu/safe_ops.h> #include <nvgpu/safe_ops.h>
#define bus_bar0_window_r() (0x00001700U) #define bus_bar0_window_r() (0x00001700U)
#define bus_bar0_window_base_f(v) (((v)&0xffffffU) << 0U) #define bus_bar0_window_base_f(v) ((U32(v) & 0xffffffU) << 0U)
#define bus_bar0_window_target_vid_mem_f() (0x0U) #define bus_bar0_window_target_vid_mem_f() (0x0U)
#define bus_bar0_window_target_sys_mem_coherent_f() (0x2000000U) #define bus_bar0_window_target_sys_mem_coherent_f() (0x2000000U)
#define bus_bar0_window_target_sys_mem_noncoherent_f() (0x3000000U) #define bus_bar0_window_target_sys_mem_noncoherent_f() (0x3000000U)
#define bus_bar0_window_target_bar0_window_base_shift_v() (0x00000010U) #define bus_bar0_window_target_bar0_window_base_shift_v() (0x00000010U)
#define bus_bar1_block_r() (0x00001704U) #define bus_bar1_block_r() (0x00001704U)
#define bus_bar1_block_ptr_f(v) (((v)&0xfffffffU) << 0U) #define bus_bar1_block_ptr_f(v) ((U32(v) & 0xfffffffU) << 0U)
#define bus_bar1_block_target_vid_mem_f() (0x0U) #define bus_bar1_block_target_vid_mem_f() (0x0U)
#define bus_bar1_block_target_sys_mem_coh_f() (0x20000000U) #define bus_bar1_block_target_sys_mem_coh_f() (0x20000000U)
#define bus_bar1_block_target_sys_mem_ncoh_f() (0x30000000U) #define bus_bar1_block_target_sys_mem_ncoh_f() (0x30000000U)
#define bus_bar1_block_mode_virtual_f() (0x80000000U) #define bus_bar1_block_mode_virtual_f() (0x80000000U)
#define bus_bar2_block_r() (0x00001714U) #define bus_bar2_block_r() (0x00001714U)
#define bus_bar2_block_ptr_f(v) (((v)&0xfffffffU) << 0U) #define bus_bar2_block_ptr_f(v) ((U32(v) & 0xfffffffU) << 0U)
#define bus_bar2_block_target_vid_mem_f() (0x0U) #define bus_bar2_block_target_vid_mem_f() (0x0U)
#define bus_bar2_block_target_sys_mem_coh_f() (0x20000000U) #define bus_bar2_block_target_sys_mem_coh_f() (0x20000000U)
#define bus_bar2_block_target_sys_mem_ncoh_f() (0x30000000U) #define bus_bar2_block_target_sys_mem_ncoh_f() (0x30000000U)

6
drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_ccsr_gk20a.h
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@@ -62,7 +62,7 @@
#define ccsr_channel_inst_r(i)\ #define ccsr_channel_inst_r(i)\
(nvgpu_safe_add_u32(0x00800000U, nvgpu_safe_mult_u32((i), 8U))) (nvgpu_safe_add_u32(0x00800000U, nvgpu_safe_mult_u32((i), 8U)))
#define ccsr_channel_inst__size_1_v() (0x00000080U) #define ccsr_channel_inst__size_1_v() (0x00000080U)
#define ccsr_channel_inst_ptr_f(v) (((v)&0xfffffffU) << 0U) #define ccsr_channel_inst_ptr_f(v) ((U32(v) & 0xfffffffU) << 0U)
#define ccsr_channel_inst_target_vid_mem_f() (0x0U) #define ccsr_channel_inst_target_vid_mem_f() (0x0U)
#define ccsr_channel_inst_target_sys_mem_coh_f() (0x20000000U) #define ccsr_channel_inst_target_sys_mem_coh_f() (0x20000000U)
#define ccsr_channel_inst_target_sys_mem_ncoh_f() (0x30000000U) #define ccsr_channel_inst_target_sys_mem_ncoh_f() (0x30000000U)
@@ -73,10 +73,10 @@
#define ccsr_channel__size_1_v() (0x00000080U) #define ccsr_channel__size_1_v() (0x00000080U)
#define ccsr_channel_enable_v(r) (((r) >> 0U) & 0x1U) #define ccsr_channel_enable_v(r) (((r) >> 0U) & 0x1U)
#define ccsr_channel_enable_in_use_v() (0x00000001U) #define ccsr_channel_enable_in_use_v() (0x00000001U)
#define ccsr_channel_enable_set_f(v) (((v)&0x1U) << 10U) #define ccsr_channel_enable_set_f(v) ((U32(v) & 0x1U) << 10U)
#define ccsr_channel_enable_set_true_f() (0x400U) #define ccsr_channel_enable_set_true_f() (0x400U)
#define ccsr_channel_enable_clr_true_f() (0x800U) #define ccsr_channel_enable_clr_true_f() (0x800U)
#define ccsr_channel_runlist_f(v) (((v)&0xfU) << 16U) #define ccsr_channel_runlist_f(v) ((U32(v) & 0xfU) << 16U)
#define ccsr_channel_status_v(r) (((r) >> 24U) & 0xfU) #define ccsr_channel_status_v(r) (((r) >> 24U) & 0xfU)
#define ccsr_channel_status_idle_v() (0x00000000U) #define ccsr_channel_status_idle_v() (0x00000000U)
#define ccsr_channel_status_pending_v() (0x00000001U) #define ccsr_channel_status_pending_v() (0x00000001U)

12
drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_ctxsw_prog_gk20a.h
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@@ -103,7 +103,7 @@
#define ctxsw_prog_main_image_priv_access_map_config_o() (0x000000a0U) #define ctxsw_prog_main_image_priv_access_map_config_o() (0x000000a0U)
#define ctxsw_prog_main_image_priv_access_map_config_mode_s() (2U) #define ctxsw_prog_main_image_priv_access_map_config_mode_s() (2U)
#define ctxsw_prog_main_image_priv_access_map_config_mode_f(v)\ #define ctxsw_prog_main_image_priv_access_map_config_mode_f(v)\
(((v)&0x3U) << 0U) ((U32(v) & 0x3U) << 0U)
#define ctxsw_prog_main_image_priv_access_map_config_mode_m() (U32(0x3U) << 0U) #define ctxsw_prog_main_image_priv_access_map_config_mode_m() (U32(0x3U) << 0U)
#define ctxsw_prog_main_image_priv_access_map_config_mode_v(r)\ #define ctxsw_prog_main_image_priv_access_map_config_mode_v(r)\
(((r) >> 0U) & 0x3U) (((r) >> 0U) & 0x3U)
@@ -116,7 +116,7 @@
#define ctxsw_prog_main_image_misc_options_verif_features_disabled_f() (0x0U) #define ctxsw_prog_main_image_misc_options_verif_features_disabled_f() (0x0U)
#define ctxsw_prog_main_image_context_timestamp_buffer_control_o() (0x000000acU) #define ctxsw_prog_main_image_context_timestamp_buffer_control_o() (0x000000acU)
#define ctxsw_prog_main_image_context_timestamp_buffer_control_num_records_f(v)\ #define ctxsw_prog_main_image_context_timestamp_buffer_control_num_records_f(v)\
(((v)&0xffffU) << 0U) ((U32(v) & 0xffffU) << 0U)
#define ctxsw_prog_main_image_context_timestamp_buffer_ptr_hi_o() (0x000000b0U) #define ctxsw_prog_main_image_context_timestamp_buffer_ptr_hi_o() (0x000000b0U)
#define ctxsw_prog_main_image_context_timestamp_buffer_ptr_hi_v_m()\ #define ctxsw_prog_main_image_context_timestamp_buffer_ptr_hi_v_m()\
(U32(0xfffffffU) << 0U) (U32(0xfffffffU) << 0U)
@@ -130,7 +130,7 @@
(0x30000000U) (0x30000000U)
#define ctxsw_prog_main_image_context_timestamp_buffer_ptr_o() (0x000000b4U) #define ctxsw_prog_main_image_context_timestamp_buffer_ptr_o() (0x000000b4U)
#define ctxsw_prog_main_image_context_timestamp_buffer_ptr_v_f(v)\ #define ctxsw_prog_main_image_context_timestamp_buffer_ptr_v_f(v)\
(((v)&0xffffffffU) << 0U) ((U32(v) & 0xffffffffU) << 0U)
#define ctxsw_prog_record_timestamp_record_size_in_bytes_v() (0x00000080U) #define ctxsw_prog_record_timestamp_record_size_in_bytes_v() (0x00000080U)
#define ctxsw_prog_record_timestamp_record_size_in_words_v() (0x00000020U) #define ctxsw_prog_record_timestamp_record_size_in_words_v() (0x00000020U)
#define ctxsw_prog_record_timestamp_magic_value_lo_o() (0x00000000U) #define ctxsw_prog_record_timestamp_magic_value_lo_o() (0x00000000U)
@@ -143,10 +143,12 @@
#define ctxsw_prog_record_timestamp_new_context_ptr_o() (0x00000014U) #define ctxsw_prog_record_timestamp_new_context_ptr_o() (0x00000014U)
#define ctxsw_prog_record_timestamp_timestamp_lo_o() (0x00000018U) #define ctxsw_prog_record_timestamp_timestamp_lo_o() (0x00000018U)
#define ctxsw_prog_record_timestamp_timestamp_hi_o() (0x0000001cU) #define ctxsw_prog_record_timestamp_timestamp_hi_o() (0x0000001cU)
#define ctxsw_prog_record_timestamp_timestamp_hi_v_f(v) (((v)&0xffffffU) << 0U) #define ctxsw_prog_record_timestamp_timestamp_hi_v_f(v)\
((U32(v) & 0xffffffU) << 0U)
#define ctxsw_prog_record_timestamp_timestamp_hi_v_v(r)\ #define ctxsw_prog_record_timestamp_timestamp_hi_v_v(r)\
(((r) >> 0U) & 0xffffffU) (((r) >> 0U) & 0xffffffU)
#define ctxsw_prog_record_timestamp_timestamp_hi_tag_f(v) (((v)&0xffU) << 24U) #define ctxsw_prog_record_timestamp_timestamp_hi_tag_f(v)\
((U32(v) & 0xffU) << 24U)
#define ctxsw_prog_record_timestamp_timestamp_hi_tag_m() (U32(0xffU) << 24U) #define ctxsw_prog_record_timestamp_timestamp_hi_tag_m() (U32(0xffU) << 24U)
#define ctxsw_prog_record_timestamp_timestamp_hi_tag_v(r) (((r) >> 24U) & 0xffU) #define ctxsw_prog_record_timestamp_timestamp_hi_tag_v(r) (((r) >> 24U) & 0xffU)
#define ctxsw_prog_record_timestamp_timestamp_hi_tag_ctxsw_req_by_host_v()\ #define ctxsw_prog_record_timestamp_timestamp_hi_tag_ctxsw_req_by_host_v()\

112
drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_falcon_gk20a.h
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@@ -68,44 +68,44 @@
#define falcon_falcon_irqstat_swgen0_true_f() (0x40U) #define falcon_falcon_irqstat_swgen0_true_f() (0x40U)
#define falcon_falcon_irqmode_r() (0x0000000cU) #define falcon_falcon_irqmode_r() (0x0000000cU)
#define falcon_falcon_irqmset_r() (0x00000010U) #define falcon_falcon_irqmset_r() (0x00000010U)
#define falcon_falcon_irqmset_gptmr_f(v) (((v)&0x1U) << 0U) #define falcon_falcon_irqmset_gptmr_f(v) ((U32(v) & 0x1U) << 0U)
#define falcon_falcon_irqmset_wdtmr_f(v) (((v)&0x1U) << 1U) #define falcon_falcon_irqmset_wdtmr_f(v) ((U32(v) & 0x1U) << 1U)
#define falcon_falcon_irqmset_mthd_f(v) (((v)&0x1U) << 2U) #define falcon_falcon_irqmset_mthd_f(v) ((U32(v) & 0x1U) << 2U)
#define falcon_falcon_irqmset_ctxsw_f(v) (((v)&0x1U) << 3U) #define falcon_falcon_irqmset_ctxsw_f(v) ((U32(v) & 0x1U) << 3U)
#define falcon_falcon_irqmset_halt_f(v) (((v)&0x1U) << 4U) #define falcon_falcon_irqmset_halt_f(v) ((U32(v) & 0x1U) << 4U)
#define falcon_falcon_irqmset_exterr_f(v) (((v)&0x1U) << 5U) #define falcon_falcon_irqmset_exterr_f(v) ((U32(v) & 0x1U) << 5U)
#define falcon_falcon_irqmset_swgen0_f(v) (((v)&0x1U) << 6U) #define falcon_falcon_irqmset_swgen0_f(v) ((U32(v) & 0x1U) << 6U)
#define falcon_falcon_irqmset_swgen1_f(v) (((v)&0x1U) << 7U) #define falcon_falcon_irqmset_swgen1_f(v) ((U32(v) & 0x1U) << 7U)
#define falcon_falcon_irqmclr_r() (0x00000014U) #define falcon_falcon_irqmclr_r() (0x00000014U)
#define falcon_falcon_irqmclr_gptmr_f(v) (((v)&0x1U) << 0U) #define falcon_falcon_irqmclr_gptmr_f(v) ((U32(v) & 0x1U) << 0U)
#define falcon_falcon_irqmclr_wdtmr_f(v) (((v)&0x1U) << 1U) #define falcon_falcon_irqmclr_wdtmr_f(v) ((U32(v) & 0x1U) << 1U)
#define falcon_falcon_irqmclr_mthd_f(v) (((v)&0x1U) << 2U) #define falcon_falcon_irqmclr_mthd_f(v) ((U32(v) & 0x1U) << 2U)
#define falcon_falcon_irqmclr_ctxsw_f(v) (((v)&0x1U) << 3U) #define falcon_falcon_irqmclr_ctxsw_f(v) ((U32(v) & 0x1U) << 3U)
#define falcon_falcon_irqmclr_halt_f(v) (((v)&0x1U) << 4U) #define falcon_falcon_irqmclr_halt_f(v) ((U32(v) & 0x1U) << 4U)
#define falcon_falcon_irqmclr_exterr_f(v) (((v)&0x1U) << 5U) #define falcon_falcon_irqmclr_exterr_f(v) ((U32(v) & 0x1U) << 5U)
#define falcon_falcon_irqmclr_swgen0_f(v) (((v)&0x1U) << 6U) #define falcon_falcon_irqmclr_swgen0_f(v) ((U32(v) & 0x1U) << 6U)
#define falcon_falcon_irqmclr_swgen1_f(v) (((v)&0x1U) << 7U) #define falcon_falcon_irqmclr_swgen1_f(v) ((U32(v) & 0x1U) << 7U)
#define falcon_falcon_irqmclr_ext_f(v) (((v)&0xffU) << 8U) #define falcon_falcon_irqmclr_ext_f(v) ((U32(v) & 0xffU) << 8U)
#define falcon_falcon_irqmask_r() (0x00000018U) #define falcon_falcon_irqmask_r() (0x00000018U)
#define falcon_falcon_irqdest_r() (0x0000001cU) #define falcon_falcon_irqdest_r() (0x0000001cU)
#define falcon_falcon_irqdest_host_gptmr_f(v) (((v)&0x1U) << 0U) #define falcon_falcon_irqdest_host_gptmr_f(v) ((U32(v) & 0x1U) << 0U)
#define falcon_falcon_irqdest_host_wdtmr_f(v) (((v)&0x1U) << 1U) #define falcon_falcon_irqdest_host_wdtmr_f(v) ((U32(v) & 0x1U) << 1U)
#define falcon_falcon_irqdest_host_mthd_f(v) (((v)&0x1U) << 2U) #define falcon_falcon_irqdest_host_mthd_f(v) ((U32(v) & 0x1U) << 2U)
#define falcon_falcon_irqdest_host_ctxsw_f(v) (((v)&0x1U) << 3U) #define falcon_falcon_irqdest_host_ctxsw_f(v) ((U32(v) & 0x1U) << 3U)
#define falcon_falcon_irqdest_host_halt_f(v) (((v)&0x1U) << 4U) #define falcon_falcon_irqdest_host_halt_f(v) ((U32(v) & 0x1U) << 4U)
#define falcon_falcon_irqdest_host_exterr_f(v) (((v)&0x1U) << 5U) #define falcon_falcon_irqdest_host_exterr_f(v) ((U32(v) & 0x1U) << 5U)
#define falcon_falcon_irqdest_host_swgen0_f(v) (((v)&0x1U) << 6U) #define falcon_falcon_irqdest_host_swgen0_f(v) ((U32(v) & 0x1U) << 6U)
#define falcon_falcon_irqdest_host_swgen1_f(v) (((v)&0x1U) << 7U) #define falcon_falcon_irqdest_host_swgen1_f(v) ((U32(v) & 0x1U) << 7U)
#define falcon_falcon_irqdest_host_ext_f(v) (((v)&0xffU) << 8U) #define falcon_falcon_irqdest_host_ext_f(v) ((U32(v) & 0xffU) << 8U)
#define falcon_falcon_irqdest_target_gptmr_f(v) (((v)&0x1U) << 16U) #define falcon_falcon_irqdest_target_gptmr_f(v) ((U32(v) & 0x1U) << 16U)
#define falcon_falcon_irqdest_target_wdtmr_f(v) (((v)&0x1U) << 17U) #define falcon_falcon_irqdest_target_wdtmr_f(v) ((U32(v) & 0x1U) << 17U)
#define falcon_falcon_irqdest_target_mthd_f(v) (((v)&0x1U) << 18U) #define falcon_falcon_irqdest_target_mthd_f(v) ((U32(v) & 0x1U) << 18U)
#define falcon_falcon_irqdest_target_ctxsw_f(v) (((v)&0x1U) << 19U) #define falcon_falcon_irqdest_target_ctxsw_f(v) ((U32(v) & 0x1U) << 19U)
#define falcon_falcon_irqdest_target_halt_f(v) (((v)&0x1U) << 20U) #define falcon_falcon_irqdest_target_halt_f(v) ((U32(v) & 0x1U) << 20U)
#define falcon_falcon_irqdest_target_exterr_f(v) (((v)&0x1U) << 21U) #define falcon_falcon_irqdest_target_exterr_f(v) ((U32(v) & 0x1U) << 21U)
#define falcon_falcon_irqdest_target_swgen0_f(v) (((v)&0x1U) << 22U) #define falcon_falcon_irqdest_target_swgen0_f(v) ((U32(v) & 0x1U) << 22U)
#define falcon_falcon_irqdest_target_swgen1_f(v) (((v)&0x1U) << 23U) #define falcon_falcon_irqdest_target_swgen1_f(v) ((U32(v) & 0x1U) << 23U)
#define falcon_falcon_irqdest_target_ext_f(v) (((v)&0xffU) << 24U) #define falcon_falcon_irqdest_target_ext_f(v) ((U32(v) & 0xffU) << 24U)
#define falcon_falcon_curctx_r() (0x00000050U) #define falcon_falcon_curctx_r() (0x00000050U)
#define falcon_falcon_nxtctx_r() (0x00000054U) #define falcon_falcon_nxtctx_r() (0x00000054U)
#define falcon_falcon_mailbox0_r() (0x00000040U) #define falcon_falcon_mailbox0_r() (0x00000040U)
@@ -118,39 +118,39 @@
#define falcon_falcon_os_r() (0x00000080U) #define falcon_falcon_os_r() (0x00000080U)
#define falcon_falcon_engctl_r() (0x000000a4U) #define falcon_falcon_engctl_r() (0x000000a4U)
#define falcon_falcon_cpuctl_r() (0x00000100U) #define falcon_falcon_cpuctl_r() (0x00000100U)
#define falcon_falcon_cpuctl_startcpu_f(v) (((v)&0x1U) << 1U) #define falcon_falcon_cpuctl_startcpu_f(v) ((U32(v) & 0x1U) << 1U)
#define falcon_falcon_cpuctl_sreset_f(v) (((v)&0x1U) << 2U) #define falcon_falcon_cpuctl_sreset_f(v) ((U32(v) & 0x1U) << 2U)
#define falcon_falcon_cpuctl_hreset_f(v) (((v)&0x1U) << 3U) #define falcon_falcon_cpuctl_hreset_f(v) ((U32(v) & 0x1U) << 3U)
#define falcon_falcon_cpuctl_halt_intr_f(v) (((v)&0x1U) << 4U) #define falcon_falcon_cpuctl_halt_intr_f(v) ((U32(v) & 0x1U) << 4U)
#define falcon_falcon_cpuctl_halt_intr_m() (U32(0x1U) << 4U) #define falcon_falcon_cpuctl_halt_intr_m() (U32(0x1U) << 4U)
#define falcon_falcon_cpuctl_halt_intr_v(r) (((r) >> 4U) & 0x1U) #define falcon_falcon_cpuctl_halt_intr_v(r) (((r) >> 4U) & 0x1U)
#define falcon_falcon_cpuctl_stopped_m() (U32(0x1U) << 5U) #define falcon_falcon_cpuctl_stopped_m() (U32(0x1U) << 5U)
#define falcon_falcon_imemc_r(i)\ #define falcon_falcon_imemc_r(i)\
(nvgpu_safe_add_u32(0x00000180U, nvgpu_safe_mult_u32((i), 16U))) (nvgpu_safe_add_u32(0x00000180U, nvgpu_safe_mult_u32((i), 16U)))
#define falcon_falcon_imemc_offs_f(v) (((v)&0x3fU) << 2U) #define falcon_falcon_imemc_offs_f(v) ((U32(v) & 0x3fU) << 2U)
#define falcon_falcon_imemc_blk_f(v) (((v)&0xffU) << 8U) #define falcon_falcon_imemc_blk_f(v) ((U32(v) & 0xffU) << 8U)
#define falcon_falcon_imemc_aincw_f(v) (((v)&0x1U) << 24U) #define falcon_falcon_imemc_aincw_f(v) ((U32(v) & 0x1U) << 24U)
#define falcon_falcon_imemc_secure_f(v) (((v)&0x1U) << 28U) #define falcon_falcon_imemc_secure_f(v) ((U32(v) & 0x1U) << 28U)
#define falcon_falcon_imemd_r(i)\ #define falcon_falcon_imemd_r(i)\
(nvgpu_safe_add_u32(0x00000184U, nvgpu_safe_mult_u32((i), 16U))) (nvgpu_safe_add_u32(0x00000184U, nvgpu_safe_mult_u32((i), 16U)))
#define falcon_falcon_imemt_r(i)\ #define falcon_falcon_imemt_r(i)\
(nvgpu_safe_add_u32(0x00000188U, nvgpu_safe_mult_u32((i), 16U))) (nvgpu_safe_add_u32(0x00000188U, nvgpu_safe_mult_u32((i), 16U)))
#define falcon_falcon_bootvec_r() (0x00000104U) #define falcon_falcon_bootvec_r() (0x00000104U)
#define falcon_falcon_bootvec_vec_f(v) (((v)&0xffffffffU) << 0U) #define falcon_falcon_bootvec_vec_f(v) ((U32(v) & 0xffffffffU) << 0U)
#define falcon_falcon_dmactl_r() (0x0000010cU) #define falcon_falcon_dmactl_r() (0x0000010cU)
#define falcon_falcon_dmactl_dmem_scrubbing_m() (U32(0x1U) << 1U) #define falcon_falcon_dmactl_dmem_scrubbing_m() (U32(0x1U) << 1U)
#define falcon_falcon_dmactl_imem_scrubbing_m() (U32(0x1U) << 2U) #define falcon_falcon_dmactl_imem_scrubbing_m() (U32(0x1U) << 2U)
#define falcon_falcon_dmactl_require_ctx_f(v) (((v)&0x1U) << 0U) #define falcon_falcon_dmactl_require_ctx_f(v) ((U32(v) & 0x1U) << 0U)
#define falcon_falcon_hwcfg_r() (0x00000108U) #define falcon_falcon_hwcfg_r() (0x00000108U)
#define falcon_falcon_hwcfg_imem_size_v(r) (((r) >> 0U) & 0x1ffU) #define falcon_falcon_hwcfg_imem_size_v(r) (((r) >> 0U) & 0x1ffU)
#define falcon_falcon_hwcfg_dmem_size_v(r) (((r) >> 9U) & 0x1ffU) #define falcon_falcon_hwcfg_dmem_size_v(r) (((r) >> 9U) & 0x1ffU)
#define falcon_falcon_dmatrfbase_r() (0x00000110U) #define falcon_falcon_dmatrfbase_r() (0x00000110U)
#define falcon_falcon_dmatrfmoffs_r() (0x00000114U) #define falcon_falcon_dmatrfmoffs_r() (0x00000114U)
#define falcon_falcon_dmatrfcmd_r() (0x00000118U) #define falcon_falcon_dmatrfcmd_r() (0x00000118U)
#define falcon_falcon_dmatrfcmd_imem_f(v) (((v)&0x1U) << 4U) #define falcon_falcon_dmatrfcmd_imem_f(v) ((U32(v) & 0x1U) << 4U)
#define falcon_falcon_dmatrfcmd_write_f(v) (((v)&0x1U) << 5U) #define falcon_falcon_dmatrfcmd_write_f(v) ((U32(v) & 0x1U) << 5U)
#define falcon_falcon_dmatrfcmd_size_f(v) (((v)&0x7U) << 8U) #define falcon_falcon_dmatrfcmd_size_f(v) ((U32(v) & 0x7U) << 8U)
#define falcon_falcon_dmatrfcmd_ctxdma_f(v) (((v)&0x7U) << 12U) #define falcon_falcon_dmatrfcmd_ctxdma_f(v) ((U32(v) & 0x7U) << 12U)
#define falcon_falcon_dmatrffboffs_r() (0x0000011cU) #define falcon_falcon_dmatrffboffs_r() (0x0000011cU)
#define falcon_falcon_imstat_r() (0x00000144U) #define falcon_falcon_imstat_r() (0x00000144U)
#define falcon_falcon_traceidx_r() (0x00000148U) #define falcon_falcon_traceidx_r() (0x00000148U)
@@ -165,26 +165,26 @@
#define falcon_falcon_exterrstat_valid_true_v() (0x00000001U) #define falcon_falcon_exterrstat_valid_true_v() (0x00000001U)
#define falcon_falcon_icd_cmd_r() (0x00000200U) #define falcon_falcon_icd_cmd_r() (0x00000200U)
#define falcon_falcon_icd_cmd_opc_s() (4U) #define falcon_falcon_icd_cmd_opc_s() (4U)
#define falcon_falcon_icd_cmd_opc_f(v) (((v)&0xfU) << 0U) #define falcon_falcon_icd_cmd_opc_f(v) ((U32(v) & 0xfU) << 0U)
#define falcon_falcon_icd_cmd_opc_m() (U32(0xfU) << 0U) #define falcon_falcon_icd_cmd_opc_m() (U32(0xfU) << 0U)
#define falcon_falcon_icd_cmd_opc_v(r) (((r) >> 0U) & 0xfU) #define falcon_falcon_icd_cmd_opc_v(r) (((r) >> 0U) & 0xfU)
#define falcon_falcon_icd_cmd_opc_rreg_f() (0x8U) #define falcon_falcon_icd_cmd_opc_rreg_f() (0x8U)
#define falcon_falcon_icd_cmd_opc_rstat_f() (0xeU) #define falcon_falcon_icd_cmd_opc_rstat_f() (0xeU)
#define falcon_falcon_icd_cmd_idx_f(v) (((v)&0x1fU) << 8U) #define falcon_falcon_icd_cmd_idx_f(v) ((U32(v) & 0x1fU) << 8U)
#define falcon_falcon_icd_rdata_r() (0x0000020cU) #define falcon_falcon_icd_rdata_r() (0x0000020cU)
#define falcon_falcon_dmemc_r(i)\ #define falcon_falcon_dmemc_r(i)\
(nvgpu_safe_add_u32(0x000001c0U, nvgpu_safe_mult_u32((i), 8U))) (nvgpu_safe_add_u32(0x000001c0U, nvgpu_safe_mult_u32((i), 8U)))
#define falcon_falcon_dmemc_offs_f(v) (((v)&0x3fU) << 2U) #define falcon_falcon_dmemc_offs_f(v) ((U32(v) & 0x3fU) << 2U)
#define falcon_falcon_dmemc_offs_m() (U32(0x3fU) << 2U) #define falcon_falcon_dmemc_offs_m() (U32(0x3fU) << 2U)
#define falcon_falcon_dmemc_blk_f(v) (((v)&0xffU) << 8U) #define falcon_falcon_dmemc_blk_f(v) ((U32(v) & 0xffU) << 8U)
#define falcon_falcon_dmemc_blk_m() (U32(0xffU) << 8U) #define falcon_falcon_dmemc_blk_m() (U32(0xffU) << 8U)
#define falcon_falcon_dmemc_aincw_f(v) (((v)&0x1U) << 24U) #define falcon_falcon_dmemc_aincw_f(v) ((U32(v) & 0x1U) << 24U)
#define falcon_falcon_dmemc_aincr_f(v) (((v)&0x1U) << 25U) #define falcon_falcon_dmemc_aincr_f(v) ((U32(v) & 0x1U) << 25U)
#define falcon_falcon_dmemd_r(i)\ #define falcon_falcon_dmemd_r(i)\
(nvgpu_safe_add_u32(0x000001c4U, nvgpu_safe_mult_u32((i), 8U))) (nvgpu_safe_add_u32(0x000001c4U, nvgpu_safe_mult_u32((i), 8U)))
#define falcon_falcon_debug1_r() (0x00000090U) #define falcon_falcon_debug1_r() (0x00000090U)
#define falcon_falcon_debug1_ctxsw_mode_s() (1U) #define falcon_falcon_debug1_ctxsw_mode_s() (1U)
#define falcon_falcon_debug1_ctxsw_mode_f(v) (((v)&0x1U) << 16U) #define falcon_falcon_debug1_ctxsw_mode_f(v) ((U32(v) & 0x1U) << 16U)
#define falcon_falcon_debug1_ctxsw_mode_m() (U32(0x1U) << 16U) #define falcon_falcon_debug1_ctxsw_mode_m() (U32(0x1U) << 16U)
#define falcon_falcon_debug1_ctxsw_mode_v(r) (((r) >> 16U) & 0x1U) #define falcon_falcon_debug1_ctxsw_mode_v(r) (((r) >> 16U) & 0x1U)
#define falcon_falcon_debug1_ctxsw_mode_init_f() (0x0U) #define falcon_falcon_debug1_ctxsw_mode_init_f() (0x0U)

12
drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_fb_gk20a.h
View File

@@ -60,7 +60,7 @@
#include <nvgpu/safe_ops.h> #include <nvgpu/safe_ops.h>
#define fb_mmu_ctrl_r() (0x00100c80U) #define fb_mmu_ctrl_r() (0x00100c80U)
#define fb_mmu_ctrl_vm_pg_size_f(v) (((v)&0x1U) << 0U) #define fb_mmu_ctrl_vm_pg_size_f(v) ((U32(v) & 0x1U) << 0U)
#define fb_mmu_ctrl_vm_pg_size_128kb_f() (0x0U) #define fb_mmu_ctrl_vm_pg_size_128kb_f() (0x0U)
#define fb_mmu_ctrl_vm_pg_size_64kb_f() (0x1U) #define fb_mmu_ctrl_vm_pg_size_64kb_f() (0x1U)
#define fb_mmu_ctrl_pri_fifo_empty_v(r) (((r) >> 15U) & 0x1U) #define fb_mmu_ctrl_pri_fifo_empty_v(r) (((r) >> 15U) & 0x1U)
@@ -69,18 +69,18 @@
#define fb_mmu_invalidate_pdb_r() (0x00100cb8U) #define fb_mmu_invalidate_pdb_r() (0x00100cb8U)
#define fb_mmu_invalidate_pdb_aperture_vid_mem_f() (0x0U) #define fb_mmu_invalidate_pdb_aperture_vid_mem_f() (0x0U)
#define fb_mmu_invalidate_pdb_aperture_sys_mem_f() (0x2U) #define fb_mmu_invalidate_pdb_aperture_sys_mem_f() (0x2U)
#define fb_mmu_invalidate_pdb_addr_f(v) (((v)&0xfffffffU) << 4U) #define fb_mmu_invalidate_pdb_addr_f(v) ((U32(v) & 0xfffffffU) << 4U)
#define fb_mmu_invalidate_r() (0x00100cbcU) #define fb_mmu_invalidate_r() (0x00100cbcU)
#define fb_mmu_invalidate_all_va_true_f() (0x1U) #define fb_mmu_invalidate_all_va_true_f() (0x1U)
#define fb_mmu_invalidate_all_pdb_true_f() (0x2U) #define fb_mmu_invalidate_all_pdb_true_f() (0x2U)
#define fb_mmu_invalidate_trigger_s() (1U) #define fb_mmu_invalidate_trigger_s() (1U)
#define fb_mmu_invalidate_trigger_f(v) (((v)&0x1U) << 31U) #define fb_mmu_invalidate_trigger_f(v) ((U32(v) & 0x1U) << 31U)
#define fb_mmu_invalidate_trigger_m() (U32(0x1U) << 31U) #define fb_mmu_invalidate_trigger_m() (U32(0x1U) << 31U)
#define fb_mmu_invalidate_trigger_v(r) (((r) >> 31U) & 0x1U) #define fb_mmu_invalidate_trigger_v(r) (((r) >> 31U) & 0x1U)
#define fb_mmu_invalidate_trigger_true_f() (0x80000000U) #define fb_mmu_invalidate_trigger_true_f() (0x80000000U)
#define fb_mmu_debug_wr_r() (0x00100cc8U) #define fb_mmu_debug_wr_r() (0x00100cc8U)
#define fb_mmu_debug_wr_aperture_s() (2U) #define fb_mmu_debug_wr_aperture_s() (2U)
#define fb_mmu_debug_wr_aperture_f(v) (((v)&0x3U) << 0U) #define fb_mmu_debug_wr_aperture_f(v) ((U32(v) & 0x3U) << 0U)
#define fb_mmu_debug_wr_aperture_m() (U32(0x3U) << 0U) #define fb_mmu_debug_wr_aperture_m() (U32(0x3U) << 0U)
#define fb_mmu_debug_wr_aperture_v(r) (((r) >> 0U) & 0x3U) #define fb_mmu_debug_wr_aperture_v(r) (((r) >> 0U) & 0x3U)
#define fb_mmu_debug_wr_aperture_vid_mem_f() (0x0U) #define fb_mmu_debug_wr_aperture_vid_mem_f() (0x0U)
@@ -89,14 +89,14 @@
#define fb_mmu_debug_wr_vol_false_f() (0x0U) #define fb_mmu_debug_wr_vol_false_f() (0x0U)
#define fb_mmu_debug_wr_vol_true_v() (0x00000001U) #define fb_mmu_debug_wr_vol_true_v() (0x00000001U)
#define fb_mmu_debug_wr_vol_true_f() (0x4U) #define fb_mmu_debug_wr_vol_true_f() (0x4U)
#define fb_mmu_debug_wr_addr_f(v) (((v)&0xfffffffU) << 4U) #define fb_mmu_debug_wr_addr_f(v) ((U32(v) & 0xfffffffU) << 4U)
#define fb_mmu_debug_wr_addr_alignment_v() (0x0000000cU) #define fb_mmu_debug_wr_addr_alignment_v() (0x0000000cU)
#define fb_mmu_debug_rd_r() (0x00100cccU) #define fb_mmu_debug_rd_r() (0x00100cccU)
#define fb_mmu_debug_rd_aperture_vid_mem_f() (0x0U) #define fb_mmu_debug_rd_aperture_vid_mem_f() (0x0U)
#define fb_mmu_debug_rd_aperture_sys_mem_coh_f() (0x2U) #define fb_mmu_debug_rd_aperture_sys_mem_coh_f() (0x2U)
#define fb_mmu_debug_rd_aperture_sys_mem_ncoh_f() (0x3U) #define fb_mmu_debug_rd_aperture_sys_mem_ncoh_f() (0x3U)
#define fb_mmu_debug_rd_vol_false_f() (0x0U) #define fb_mmu_debug_rd_vol_false_f() (0x0U)
#define fb_mmu_debug_rd_addr_f(v) (((v)&0xfffffffU) << 4U) #define fb_mmu_debug_rd_addr_f(v) ((U32(v) & 0xfffffffU) << 4U)
#define fb_mmu_debug_rd_addr_alignment_v() (0x0000000cU) #define fb_mmu_debug_rd_addr_alignment_v() (0x0000000cU)
#define fb_mmu_debug_ctrl_r() (0x00100cc4U) #define fb_mmu_debug_ctrl_r() (0x00100cc4U)
#define fb_mmu_debug_ctrl_debug_v(r) (((r) >> 16U) & 0x1U) #define fb_mmu_debug_ctrl_debug_v(r) (((r) >> 16U) & 0x1U)

26
drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_fifo_gk20a.h
View File

@@ -60,24 +60,24 @@
#include <nvgpu/safe_ops.h> #include <nvgpu/safe_ops.h>
#define fifo_bar1_base_r() (0x00002254U) #define fifo_bar1_base_r() (0x00002254U)
#define fifo_bar1_base_ptr_f(v) (((v)&0xfffffffU) << 0U) #define fifo_bar1_base_ptr_f(v) ((U32(v) & 0xfffffffU) << 0U)
#define fifo_bar1_base_ptr_align_shift_v() (0x0000000cU) #define fifo_bar1_base_ptr_align_shift_v() (0x0000000cU)
#define fifo_bar1_base_valid_false_f() (0x0U) #define fifo_bar1_base_valid_false_f() (0x0U)
#define fifo_bar1_base_valid_true_f() (0x10000000U) #define fifo_bar1_base_valid_true_f() (0x10000000U)
#define fifo_runlist_base_r() (0x00002270U) #define fifo_runlist_base_r() (0x00002270U)
#define fifo_runlist_base_ptr_f(v) (((v)&0xfffffffU) << 0U) #define fifo_runlist_base_ptr_f(v) ((U32(v) & 0xfffffffU) << 0U)
#define fifo_runlist_base_target_vid_mem_f() (0x0U) #define fifo_runlist_base_target_vid_mem_f() (0x0U)
#define fifo_runlist_base_target_sys_mem_coh_f() (0x20000000U) #define fifo_runlist_base_target_sys_mem_coh_f() (0x20000000U)
#define fifo_runlist_base_target_sys_mem_ncoh_f() (0x30000000U) #define fifo_runlist_base_target_sys_mem_ncoh_f() (0x30000000U)
#define fifo_runlist_r() (0x00002274U) #define fifo_runlist_r() (0x00002274U)
#define fifo_runlist_engine_f(v) (((v)&0xfU) << 20U) #define fifo_runlist_engine_f(v) ((U32(v) & 0xfU) << 20U)
#define fifo_eng_runlist_base_r(i)\ #define fifo_eng_runlist_base_r(i)\
(nvgpu_safe_add_u32(0x00002280U, nvgpu_safe_mult_u32((i), 8U))) (nvgpu_safe_add_u32(0x00002280U, nvgpu_safe_mult_u32((i), 8U)))
#define fifo_eng_runlist_base__size_1_v() (0x00000001U) #define fifo_eng_runlist_base__size_1_v() (0x00000001U)
#define fifo_eng_runlist_r(i)\ #define fifo_eng_runlist_r(i)\
(nvgpu_safe_add_u32(0x00002284U, nvgpu_safe_mult_u32((i), 8U))) (nvgpu_safe_add_u32(0x00002284U, nvgpu_safe_mult_u32((i), 8U)))
#define fifo_eng_runlist__size_1_v() (0x00000001U) #define fifo_eng_runlist__size_1_v() (0x00000001U)
#define fifo_eng_runlist_length_f(v) (((v)&0xffffU) << 0U) #define fifo_eng_runlist_length_f(v) ((U32(v) & 0xffffU) << 0U)
#define fifo_eng_runlist_length_max_v() (0x0000ffffU) #define fifo_eng_runlist_length_max_v() (0x0000ffffU)
#define fifo_eng_runlist_pending_true_f() (0x100000U) #define fifo_eng_runlist_pending_true_f() (0x100000U)
#define fifo_runlist_timeslice_r(i)\ #define fifo_runlist_timeslice_r(i)\
@@ -116,14 +116,14 @@
#define fifo_intr_0_runlist_event_pending_f() (0x40000000U) #define fifo_intr_0_runlist_event_pending_f() (0x40000000U)
#define fifo_intr_0_channel_intr_pending_f() (0x80000000U) #define fifo_intr_0_channel_intr_pending_f() (0x80000000U)
#define fifo_intr_en_0_r() (0x00002140U) #define fifo_intr_en_0_r() (0x00002140U)
#define fifo_intr_en_0_sched_error_f(v) (((v)&0x1U) << 8U) #define fifo_intr_en_0_sched_error_f(v) ((U32(v) & 0x1U) << 8U)
#define fifo_intr_en_0_sched_error_m() (U32(0x1U) << 8U) #define fifo_intr_en_0_sched_error_m() (U32(0x1U) << 8U)
#define fifo_intr_en_0_mmu_fault_f(v) (((v)&0x1U) << 28U) #define fifo_intr_en_0_mmu_fault_f(v) ((U32(v) & 0x1U) << 28U)
#define fifo_intr_en_0_mmu_fault_m() (U32(0x1U) << 28U) #define fifo_intr_en_0_mmu_fault_m() (U32(0x1U) << 28U)
#define fifo_intr_en_1_r() (0x00002528U) #define fifo_intr_en_1_r() (0x00002528U)
#define fifo_intr_bind_error_r() (0x0000252cU) #define fifo_intr_bind_error_r() (0x0000252cU)
#define fifo_intr_sched_error_r() (0x0000254cU) #define fifo_intr_sched_error_r() (0x0000254cU)
#define fifo_intr_sched_error_code_f(v) (((v)&0xffU) << 0U) #define fifo_intr_sched_error_code_f(v) ((U32(v) & 0xffU) << 0U)
#define fifo_intr_sched_error_code_ctxsw_timeout_v() (0x0000000aU) #define fifo_intr_sched_error_code_ctxsw_timeout_v() (0x0000000aU)
#define fifo_intr_chsw_error_r() (0x0000256cU) #define fifo_intr_chsw_error_r() (0x0000256cU)
#define fifo_intr_mmu_fault_id_r() (0x0000259cU) #define fifo_intr_mmu_fault_id_r() (0x0000259cU)
@@ -147,7 +147,7 @@
#define fifo_intr_mmu_fault_info_client_v(r) (((r) >> 8U) & 0x1fU) #define fifo_intr_mmu_fault_info_client_v(r) (((r) >> 8U) & 0x1fU)
#define fifo_intr_pbdma_id_r() (0x000025a0U) #define fifo_intr_pbdma_id_r() (0x000025a0U)
#define fifo_intr_pbdma_id_status_f(v, i)\ #define fifo_intr_pbdma_id_status_f(v, i)\
(((v) & 0x1) << (0U + i*1U)) ((U32(v) & 0x1U) << (0U + (i)*1U))
#define fifo_intr_pbdma_id_status_v(r, i)\ #define fifo_intr_pbdma_id_status_v(r, i)\
(((r) >> (0U + i*1U)) & 0x1U) (((r) >> (0U + i*1U)) & 0x1U)
#define fifo_intr_pbdma_id_status__size_1_v() (0x00000001U) #define fifo_intr_pbdma_id_status__size_1_v() (0x00000001U)
@@ -160,7 +160,7 @@
#define fifo_error_sched_disable_r() (0x0000262cU) #define fifo_error_sched_disable_r() (0x0000262cU)
#define fifo_sched_disable_r() (0x00002630U) #define fifo_sched_disable_r() (0x00002630U)
#define fifo_sched_disable_runlist_f(v, i)\ #define fifo_sched_disable_runlist_f(v, i)\
(((v) & 0x1) << (0U + i*1U)) ((U32(v) & 0x1U) << (0U + (i)*1U))
#define fifo_sched_disable_runlist_m(i)\ #define fifo_sched_disable_runlist_m(i)\
(U32(0x1U) << (0U + (i)*1U)) (U32(0x1U) << (0U + (i)*1U))
#define fifo_sched_disable_true_v() (0x00000001U) #define fifo_sched_disable_true_v() (0x00000001U)
@@ -168,12 +168,12 @@
#define fifo_preempt_pending_true_f() (0x100000U) #define fifo_preempt_pending_true_f() (0x100000U)
#define fifo_preempt_type_channel_f() (0x0U) #define fifo_preempt_type_channel_f() (0x0U)
#define fifo_preempt_type_tsg_f() (0x1000000U) #define fifo_preempt_type_tsg_f() (0x1000000U)
#define fifo_preempt_chid_f(v) (((v)&0xfffU) << 0U) #define fifo_preempt_chid_f(v) ((U32(v) & 0xfffU) << 0U)
#define fifo_preempt_id_f(v) (((v)&0xfffU) << 0U) #define fifo_preempt_id_f(v) ((U32(v) & 0xfffU) << 0U)
#define fifo_trigger_mmu_fault_r(i)\ #define fifo_trigger_mmu_fault_r(i)\
(nvgpu_safe_add_u32(0x00002a30U, nvgpu_safe_mult_u32((i), 4U))) (nvgpu_safe_add_u32(0x00002a30U, nvgpu_safe_mult_u32((i), 4U)))
#define fifo_trigger_mmu_fault_id_f(v) (((v)&0x1fU) << 0U) #define fifo_trigger_mmu_fault_id_f(v) ((U32(v) & 0x1fU) << 0U)
#define fifo_trigger_mmu_fault_enable_f(v) (((v)&0x1U) << 8U) #define fifo_trigger_mmu_fault_enable_f(v) ((U32(v) & 0x1U) << 8U)
#define fifo_engine_status_r(i)\ #define fifo_engine_status_r(i)\
(nvgpu_safe_add_u32(0x00002640U, nvgpu_safe_mult_u32((i), 8U))) (nvgpu_safe_add_u32(0x00002640U, nvgpu_safe_mult_u32((i), 8U)))
#define fifo_engine_status__size_1_v() (0x00000002U) #define fifo_engine_status__size_1_v() (0x00000002U)

12
drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_gmmu_gk20a.h
View File

@@ -66,7 +66,7 @@
#define gmmu_pde_aperture_big_sys_mem_ncoh_f() (0x3U) #define gmmu_pde_aperture_big_sys_mem_ncoh_f() (0x3U)
#define gmmu_pde_size_w() (0U) #define gmmu_pde_size_w() (0U)
#define gmmu_pde_size_full_f() (0x0U) #define gmmu_pde_size_full_f() (0x0U)
#define gmmu_pde_address_big_sys_f(v) (((v)&0xfffffffU) << 4U) #define gmmu_pde_address_big_sys_f(v) ((U32(v) & 0xfffffffU) << 4U)
#define gmmu_pde_address_big_sys_w() (0U) #define gmmu_pde_address_big_sys_w() (0U)
#define gmmu_pde_aperture_small_w() (1U) #define gmmu_pde_aperture_small_w() (1U)
#define gmmu_pde_aperture_small_invalid_f() (0x0U) #define gmmu_pde_aperture_small_invalid_f() (0x0U)
@@ -79,7 +79,7 @@
#define gmmu_pde_vol_big_w() (1U) #define gmmu_pde_vol_big_w() (1U)
#define gmmu_pde_vol_big_true_f() (0x8U) #define gmmu_pde_vol_big_true_f() (0x8U)
#define gmmu_pde_vol_big_false_f() (0x0U) #define gmmu_pde_vol_big_false_f() (0x0U)
#define gmmu_pde_address_small_sys_f(v) (((v)&0xfffffffU) << 4U) #define gmmu_pde_address_small_sys_f(v) ((U32(v) & 0xfffffffU) << 4U)
#define gmmu_pde_address_small_sys_w() (1U) #define gmmu_pde_address_small_sys_w() (1U)
#define gmmu_pde_address_shift_v() (0x0000000cU) #define gmmu_pde_address_shift_v() (0x0000000cU)
#define gmmu_pde__size_v() (0x00000008U) #define gmmu_pde__size_v() (0x00000008U)
@@ -90,9 +90,9 @@
#define gmmu_pte_privilege_w() (0U) #define gmmu_pte_privilege_w() (0U)
#define gmmu_pte_privilege_true_f() (0x2U) #define gmmu_pte_privilege_true_f() (0x2U)
#define gmmu_pte_privilege_false_f() (0x0U) #define gmmu_pte_privilege_false_f() (0x0U)
#define gmmu_pte_address_sys_f(v) (((v)&0xfffffffU) << 4U) #define gmmu_pte_address_sys_f(v) ((U32(v) & 0xfffffffU) << 4U)
#define gmmu_pte_address_sys_w() (0U) #define gmmu_pte_address_sys_w() (0U)
#define gmmu_pte_address_vid_f(v) (((v)&0x1ffffffU) << 4U) #define gmmu_pte_address_vid_f(v) ((U32(v) & 0x1ffffffU) << 4U)
#define gmmu_pte_address_vid_w() (0U) #define gmmu_pte_address_vid_w() (0U)
#define gmmu_pte_vol_w() (1U) #define gmmu_pte_vol_w() (1U)
#define gmmu_pte_vol_true_f() (0x1U) #define gmmu_pte_vol_true_f() (0x1U)
@@ -108,10 +108,10 @@
#define gmmu_pte_read_disable_w() (1U) #define gmmu_pte_read_disable_w() (1U)
#define gmmu_pte_read_disable_true_f() (0x40000000U) #define gmmu_pte_read_disable_true_f() (0x40000000U)
#define gmmu_pte_comptagline_s() (17U) #define gmmu_pte_comptagline_s() (17U)
#define gmmu_pte_comptagline_f(v) (((v)&0x1ffffU) << 12U) #define gmmu_pte_comptagline_f(v) ((U32(v) & 0x1ffffU) << 12U)
#define gmmu_pte_comptagline_w() (1U) #define gmmu_pte_comptagline_w() (1U)
#define gmmu_pte_address_shift_v() (0x0000000cU) #define gmmu_pte_address_shift_v() (0x0000000cU)
#define gmmu_pte_kind_f(v) (((v)&0xffU) << 4U) #define gmmu_pte_kind_f(v) ((U32(v) & 0xffU) << 4U)
#define gmmu_pte_kind_w() (1U) #define gmmu_pte_kind_w() (1U)
#define gmmu_pte_kind_invalid_v() (0x000000ffU) #define gmmu_pte_kind_invalid_v() (0x000000ffU)
#define gmmu_pte_kind_pitch_v() (0x00000000U) #define gmmu_pte_kind_pitch_v() (0x00000000U)

465
drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_gr_gk20a.h
View File

@@ -71,7 +71,7 @@
#define gr_intr_illegal_method_reset_f() (0x10U) #define gr_intr_illegal_method_reset_f() (0x10U)
#define gr_intr_illegal_notify_pending_f() (0x40U) #define gr_intr_illegal_notify_pending_f() (0x40U)
#define gr_intr_illegal_notify_reset_f() (0x40U) #define gr_intr_illegal_notify_reset_f() (0x40U)
#define gr_intr_firmware_method_f(v) (((v)&0x1U) << 8U) #define gr_intr_firmware_method_f(v) ((U32(v) & 0x1U) << 8U)
#define gr_intr_firmware_method_pending_f() (0x100U) #define gr_intr_firmware_method_pending_f() (0x100U)
#define gr_intr_firmware_method_reset_f() (0x100U) #define gr_intr_firmware_method_reset_f() (0x100U)
#define gr_intr_illegal_class_pending_f() (0x20U) #define gr_intr_illegal_class_pending_f() (0x20U)
@@ -106,10 +106,10 @@
#define gr_exception1_en_r() (0x00400130U) #define gr_exception1_en_r() (0x00400130U)
#define gr_exception2_en_r() (0x00400134U) #define gr_exception2_en_r() (0x00400134U)
#define gr_gpfifo_ctl_r() (0x00400500U) #define gr_gpfifo_ctl_r() (0x00400500U)
#define gr_gpfifo_ctl_access_f(v) (((v)&0x1U) << 0U) #define gr_gpfifo_ctl_access_f(v) ((U32(v) & 0x1U) << 0U)
#define gr_gpfifo_ctl_access_disabled_f() (0x0U) #define gr_gpfifo_ctl_access_disabled_f() (0x0U)
#define gr_gpfifo_ctl_access_enabled_f() (0x1U) #define gr_gpfifo_ctl_access_enabled_f() (0x1U)
#define gr_gpfifo_ctl_semaphore_access_f(v) (((v)&0x1U) << 16U) #define gr_gpfifo_ctl_semaphore_access_f(v) ((U32(v) & 0x1U) << 16U)
#define gr_gpfifo_ctl_semaphore_access_enabled_v() (0x00000001U) #define gr_gpfifo_ctl_semaphore_access_enabled_v() (0x00000001U)
#define gr_gpfifo_ctl_semaphore_access_enabled_f() (0x10000U) #define gr_gpfifo_ctl_semaphore_access_enabled_f() (0x10000U)
#define gr_gpfifo_status_r() (0x00400504U) #define gr_gpfifo_status_r() (0x00400504U)
@@ -187,7 +187,7 @@
#define gr_fe_hww_esr_en_enable_f() (0x80000000U) #define gr_fe_hww_esr_en_enable_f() (0x80000000U)
#define gr_fe_hww_esr_info_r() (0x004041b0U) #define gr_fe_hww_esr_info_r() (0x004041b0U)
#define gr_fe_go_idle_timeout_r() (0x00404154U) #define gr_fe_go_idle_timeout_r() (0x00404154U)
#define gr_fe_go_idle_timeout_count_f(v) (((v)&0xffffffffU) << 0U) #define gr_fe_go_idle_timeout_count_f(v) ((U32(v) & 0xffffffffU) << 0U)
#define gr_fe_go_idle_timeout_count_disabled_f() (0x0U) #define gr_fe_go_idle_timeout_count_disabled_f() (0x0U)
#define gr_fe_go_idle_timeout_count_prod_f() (0x800U) #define gr_fe_go_idle_timeout_count_prod_f() (0x800U)
#define gr_fe_object_table_r(i)\ #define gr_fe_object_table_r(i)\
@@ -204,9 +204,9 @@
#define gr_memfmt_hww_esr_reset_active_f() (0x40000000U) #define gr_memfmt_hww_esr_reset_active_f() (0x40000000U)
#define gr_memfmt_hww_esr_en_enable_f() (0x80000000U) #define gr_memfmt_hww_esr_en_enable_f() (0x80000000U)
#define gr_fecs_cpuctl_r() (0x00409100U) #define gr_fecs_cpuctl_r() (0x00409100U)
#define gr_fecs_cpuctl_startcpu_f(v) (((v)&0x1U) << 1U) #define gr_fecs_cpuctl_startcpu_f(v) ((U32(v) & 0x1U) << 1U)
#define gr_fecs_dmactl_r() (0x0040910cU) #define gr_fecs_dmactl_r() (0x0040910cU)
#define gr_fecs_dmactl_require_ctx_f(v) (((v)&0x1U) << 0U) #define gr_fecs_dmactl_require_ctx_f(v) ((U32(v) & 0x1U) << 0U)
#define gr_fecs_dmactl_dmem_scrubbing_m() (U32(0x1U) << 1U) #define gr_fecs_dmactl_dmem_scrubbing_m() (U32(0x1U) << 1U)
#define gr_fecs_dmactl_imem_scrubbing_m() (U32(0x1U) << 2U) #define gr_fecs_dmactl_imem_scrubbing_m() (U32(0x1U) << 2U)
#define gr_fecs_os_r() (0x00409080U) #define gr_fecs_os_r() (0x00409080U)
@@ -224,43 +224,43 @@
#define gr_fecs_debuginfo_r() (0x00409094U) #define gr_fecs_debuginfo_r() (0x00409094U)
#define gr_fecs_icd_cmd_r() (0x00409200U) #define gr_fecs_icd_cmd_r() (0x00409200U)
#define gr_fecs_icd_cmd_opc_s() (4U) #define gr_fecs_icd_cmd_opc_s() (4U)
#define gr_fecs_icd_cmd_opc_f(v) (((v)&0xfU) << 0U) #define gr_fecs_icd_cmd_opc_f(v) ((U32(v) & 0xfU) << 0U)
#define gr_fecs_icd_cmd_opc_m() (U32(0xfU) << 0U) #define gr_fecs_icd_cmd_opc_m() (U32(0xfU) << 0U)
#define gr_fecs_icd_cmd_opc_v(r) (((r) >> 0U) & 0xfU) #define gr_fecs_icd_cmd_opc_v(r) (((r) >> 0U) & 0xfU)
#define gr_fecs_icd_cmd_opc_rreg_f() (0x8U) #define gr_fecs_icd_cmd_opc_rreg_f() (0x8U)
#define gr_fecs_icd_cmd_opc_rstat_f() (0xeU) #define gr_fecs_icd_cmd_opc_rstat_f() (0xeU)
#define gr_fecs_icd_cmd_idx_f(v) (((v)&0x1fU) << 8U) #define gr_fecs_icd_cmd_idx_f(v) ((U32(v) & 0x1fU) << 8U)
#define gr_fecs_icd_rdata_r() (0x0040920cU) #define gr_fecs_icd_rdata_r() (0x0040920cU)
#define gr_fecs_imemc_r(i)\ #define gr_fecs_imemc_r(i)\
(nvgpu_safe_add_u32(0x00409180U, nvgpu_safe_mult_u32((i), 16U))) (nvgpu_safe_add_u32(0x00409180U, nvgpu_safe_mult_u32((i), 16U)))
#define gr_fecs_imemc_offs_f(v) (((v)&0x3fU) << 2U) #define gr_fecs_imemc_offs_f(v) ((U32(v) & 0x3fU) << 2U)
#define gr_fecs_imemc_blk_f(v) (((v)&0xffU) << 8U) #define gr_fecs_imemc_blk_f(v) ((U32(v) & 0xffU) << 8U)
#define gr_fecs_imemc_aincw_f(v) (((v)&0x1U) << 24U) #define gr_fecs_imemc_aincw_f(v) ((U32(v) & 0x1U) << 24U)
#define gr_fecs_imemd_r(i)\ #define gr_fecs_imemd_r(i)\
(nvgpu_safe_add_u32(0x00409184U, nvgpu_safe_mult_u32((i), 16U))) (nvgpu_safe_add_u32(0x00409184U, nvgpu_safe_mult_u32((i), 16U)))
#define gr_fecs_imemt_r(i)\ #define gr_fecs_imemt_r(i)\
(nvgpu_safe_add_u32(0x00409188U, nvgpu_safe_mult_u32((i), 16U))) (nvgpu_safe_add_u32(0x00409188U, nvgpu_safe_mult_u32((i), 16U)))
#define gr_fecs_imemt_tag_f(v) (((v)&0xffffU) << 0U) #define gr_fecs_imemt_tag_f(v) ((U32(v) & 0xffffU) << 0U)
#define gr_fecs_dmemc_r(i)\ #define gr_fecs_dmemc_r(i)\
(nvgpu_safe_add_u32(0x004091c0U, nvgpu_safe_mult_u32((i), 8U))) (nvgpu_safe_add_u32(0x004091c0U, nvgpu_safe_mult_u32((i), 8U)))
#define gr_fecs_dmemc_offs_s() (6U) #define gr_fecs_dmemc_offs_s() (6U)
#define gr_fecs_dmemc_offs_f(v) (((v)&0x3fU) << 2U) #define gr_fecs_dmemc_offs_f(v) ((U32(v) & 0x3fU) << 2U)
#define gr_fecs_dmemc_offs_m() (U32(0x3fU) << 2U) #define gr_fecs_dmemc_offs_m() (U32(0x3fU) << 2U)
#define gr_fecs_dmemc_offs_v(r) (((r) >> 2U) & 0x3fU) #define gr_fecs_dmemc_offs_v(r) (((r) >> 2U) & 0x3fU)
#define gr_fecs_dmemc_blk_f(v) (((v)&0xffU) << 8U) #define gr_fecs_dmemc_blk_f(v) ((U32(v) & 0xffU) << 8U)
#define gr_fecs_dmemc_aincw_f(v) (((v)&0x1U) << 24U) #define gr_fecs_dmemc_aincw_f(v) ((U32(v) & 0x1U) << 24U)
#define gr_fecs_dmemd_r(i)\ #define gr_fecs_dmemd_r(i)\
(nvgpu_safe_add_u32(0x004091c4U, nvgpu_safe_mult_u32((i), 8U))) (nvgpu_safe_add_u32(0x004091c4U, nvgpu_safe_mult_u32((i), 8U)))
#define gr_fecs_dmatrfbase_r() (0x00409110U) #define gr_fecs_dmatrfbase_r() (0x00409110U)
#define gr_fecs_dmatrfmoffs_r() (0x00409114U) #define gr_fecs_dmatrfmoffs_r() (0x00409114U)
#define gr_fecs_dmatrffboffs_r() (0x0040911cU) #define gr_fecs_dmatrffboffs_r() (0x0040911cU)
#define gr_fecs_dmatrfcmd_r() (0x00409118U) #define gr_fecs_dmatrfcmd_r() (0x00409118U)
#define gr_fecs_dmatrfcmd_imem_f(v) (((v)&0x1U) << 4U) #define gr_fecs_dmatrfcmd_imem_f(v) ((U32(v) & 0x1U) << 4U)
#define gr_fecs_dmatrfcmd_write_f(v) (((v)&0x1U) << 5U) #define gr_fecs_dmatrfcmd_write_f(v) ((U32(v) & 0x1U) << 5U)
#define gr_fecs_dmatrfcmd_size_f(v) (((v)&0x7U) << 8U) #define gr_fecs_dmatrfcmd_size_f(v) ((U32(v) & 0x7U) << 8U)
#define gr_fecs_dmatrfcmd_ctxdma_f(v) (((v)&0x7U) << 12U) #define gr_fecs_dmatrfcmd_ctxdma_f(v) ((U32(v) & 0x7U) << 12U)
#define gr_fecs_bootvec_r() (0x00409104U) #define gr_fecs_bootvec_r() (0x00409104U)
#define gr_fecs_bootvec_vec_f(v) (((v)&0xffffffffU) << 0U) #define gr_fecs_bootvec_vec_f(v) ((U32(v) & 0xffffffffU) << 0U)
#define gr_fecs_irqsset_r() (0x00409000U) #define gr_fecs_irqsset_r() (0x00409000U)
#define gr_fecs_irqsclear_r() (0x00409004U) #define gr_fecs_irqsclear_r() (0x00409004U)
#define gr_fecs_falcon_hwcfg_r() (0x00409108U) #define gr_fecs_falcon_hwcfg_r() (0x00409108U)
@@ -269,23 +269,23 @@
#define gr_gpcs_gpccs_falcon_hwcfg_r() (0x0041a108U) #define gr_gpcs_gpccs_falcon_hwcfg_r() (0x0041a108U)
#define gr_fecs_falcon_rm_r() (0x00409084U) #define gr_fecs_falcon_rm_r() (0x00409084U)
#define gr_fecs_current_ctx_r() (0x00409b00U) #define gr_fecs_current_ctx_r() (0x00409b00U)
#define gr_fecs_current_ctx_ptr_f(v) (((v)&0xfffffffU) << 0U) #define gr_fecs_current_ctx_ptr_f(v) ((U32(v) & 0xfffffffU) << 0U)
#define gr_fecs_current_ctx_ptr_v(r) (((r) >> 0U) & 0xfffffffU) #define gr_fecs_current_ctx_ptr_v(r) (((r) >> 0U) & 0xfffffffU)
#define gr_fecs_current_ctx_target_s() (2U) #define gr_fecs_current_ctx_target_s() (2U)
#define gr_fecs_current_ctx_target_f(v) (((v)&0x3U) << 28U) #define gr_fecs_current_ctx_target_f(v) ((U32(v) & 0x3U) << 28U)
#define gr_fecs_current_ctx_target_m() (U32(0x3U) << 28U) #define gr_fecs_current_ctx_target_m() (U32(0x3U) << 28U)
#define gr_fecs_current_ctx_target_v(r) (((r) >> 28U) & 0x3U) #define gr_fecs_current_ctx_target_v(r) (((r) >> 28U) & 0x3U)
#define gr_fecs_current_ctx_target_vid_mem_f() (0x0U) #define gr_fecs_current_ctx_target_vid_mem_f() (0x0U)
#define gr_fecs_current_ctx_target_sys_mem_coh_f() (0x20000000U) #define gr_fecs_current_ctx_target_sys_mem_coh_f() (0x20000000U)
#define gr_fecs_current_ctx_target_sys_mem_ncoh_f() (0x30000000U) #define gr_fecs_current_ctx_target_sys_mem_ncoh_f() (0x30000000U)
#define gr_fecs_current_ctx_valid_s() (1U) #define gr_fecs_current_ctx_valid_s() (1U)
#define gr_fecs_current_ctx_valid_f(v) (((v)&0x1U) << 31U) #define gr_fecs_current_ctx_valid_f(v) ((U32(v) & 0x1U) << 31U)
#define gr_fecs_current_ctx_valid_m() (U32(0x1U) << 31U) #define gr_fecs_current_ctx_valid_m() (U32(0x1U) << 31U)
#define gr_fecs_current_ctx_valid_v(r) (((r) >> 31U) & 0x1U) #define gr_fecs_current_ctx_valid_v(r) (((r) >> 31U) & 0x1U)
#define gr_fecs_current_ctx_valid_false_f() (0x0U) #define gr_fecs_current_ctx_valid_false_f() (0x0U)
#define gr_fecs_method_data_r() (0x00409500U) #define gr_fecs_method_data_r() (0x00409500U)
#define gr_fecs_method_push_r() (0x00409504U) #define gr_fecs_method_push_r() (0x00409504U)
#define gr_fecs_method_push_adr_f(v) (((v)&0xfffU) << 0U) #define gr_fecs_method_push_adr_f(v) ((U32(v) & 0xfffU) << 0U)
#define gr_fecs_method_push_adr_bind_pointer_v() (0x00000003U) #define gr_fecs_method_push_adr_bind_pointer_v() (0x00000003U)
#define gr_fecs_method_push_adr_bind_pointer_f() (0x3U) #define gr_fecs_method_push_adr_bind_pointer_f() (0x3U)
#define gr_fecs_method_push_adr_discover_image_size_v() (0x00000010U) #define gr_fecs_method_push_adr_discover_image_size_v() (0x00000010U)
@@ -301,13 +301,15 @@
#define gr_fecs_method_push_adr_set_watchdog_timeout_f() (0x21U) #define gr_fecs_method_push_adr_set_watchdog_timeout_f() (0x21U)
#define gr_fecs_method_push_adr_halt_pipeline_v() (0x00000004U) #define gr_fecs_method_push_adr_halt_pipeline_v() (0x00000004U)
#define gr_fecs_host_int_status_r() (0x00409c18U) #define gr_fecs_host_int_status_r() (0x00409c18U)
#define gr_fecs_host_int_status_fault_during_ctxsw_f(v) (((v)&0x1U) << 16U) #define gr_fecs_host_int_status_fault_during_ctxsw_f(v) ((U32(v) & 0x1U) << 16U)
#define gr_fecs_host_int_status_umimp_firmware_method_f(v) (((v)&0x1U) << 17U) #define gr_fecs_host_int_status_umimp_firmware_method_f(v)\
#define gr_fecs_host_int_status_umimp_illegal_method_f(v) (((v)&0x1U) << 18U) ((U32(v) & 0x1U) << 17U)
#define gr_fecs_host_int_status_umimp_illegal_method_f(v)\
((U32(v) & 0x1U) << 18U)
#define gr_fecs_host_int_status_watchdog_active_f() (0x80000U) #define gr_fecs_host_int_status_watchdog_active_f() (0x80000U)
#define gr_fecs_host_int_status_ctxsw_intr_f(v) (((v)&0xffffU) << 0U) #define gr_fecs_host_int_status_ctxsw_intr_f(v) ((U32(v) & 0xffffU) << 0U)
#define gr_fecs_host_int_clear_r() (0x00409c20U) #define gr_fecs_host_int_clear_r() (0x00409c20U)
#define gr_fecs_host_int_clear_ctxsw_intr1_f(v) (((v)&0x1U) << 1U) #define gr_fecs_host_int_clear_ctxsw_intr1_f(v) ((U32(v) & 0x1U) << 1U)
#define gr_fecs_host_int_clear_ctxsw_intr1_clear_f() (0x2U) #define gr_fecs_host_int_clear_ctxsw_intr1_clear_f() (0x2U)
#define gr_fecs_host_int_enable_r() (0x00409c24U) #define gr_fecs_host_int_enable_r() (0x00409c24U)
#define gr_fecs_host_int_enable_ctxsw_intr1_enable_f() (0x2U) #define gr_fecs_host_int_enable_ctxsw_intr1_enable_f() (0x2U)
@@ -327,7 +329,7 @@
#define gr_fecs_ctxsw_reset_ctl_gpc_context_reset_enabled_f() (0x0U) #define gr_fecs_ctxsw_reset_ctl_gpc_context_reset_enabled_f() (0x0U)
#define gr_fecs_ctxsw_reset_ctl_gpc_context_reset_disabled_f() (0x200U) #define gr_fecs_ctxsw_reset_ctl_gpc_context_reset_disabled_f() (0x200U)
#define gr_fecs_ctxsw_reset_ctl_be_context_reset_s() (1U) #define gr_fecs_ctxsw_reset_ctl_be_context_reset_s() (1U)
#define gr_fecs_ctxsw_reset_ctl_be_context_reset_f(v) (((v)&0x1U) << 10U) #define gr_fecs_ctxsw_reset_ctl_be_context_reset_f(v) ((U32(v) & 0x1U) << 10U)
#define gr_fecs_ctxsw_reset_ctl_be_context_reset_m() (U32(0x1U) << 10U) #define gr_fecs_ctxsw_reset_ctl_be_context_reset_m() (U32(0x1U) << 10U)
#define gr_fecs_ctxsw_reset_ctl_be_context_reset_v(r) (((r) >> 10U) & 0x1U) #define gr_fecs_ctxsw_reset_ctl_be_context_reset_v(r) (((r) >> 10U) & 0x1U)
#define gr_fecs_ctxsw_reset_ctl_be_context_reset_enabled_f() (0x0U) #define gr_fecs_ctxsw_reset_ctl_be_context_reset_enabled_f() (0x0U)
@@ -336,60 +338,60 @@
#define gr_fecs_ctxsw_mailbox_r(i)\ #define gr_fecs_ctxsw_mailbox_r(i)\
(nvgpu_safe_add_u32(0x00409800U, nvgpu_safe_mult_u32((i), 4U))) (nvgpu_safe_add_u32(0x00409800U, nvgpu_safe_mult_u32((i), 4U)))
#define gr_fecs_ctxsw_mailbox__size_1_v() (0x00000008U) #define gr_fecs_ctxsw_mailbox__size_1_v() (0x00000008U)
#define gr_fecs_ctxsw_mailbox_value_f(v) (((v)&0xffffffffU) << 0U) #define gr_fecs_ctxsw_mailbox_value_f(v) ((U32(v) & 0xffffffffU) << 0U)
#define gr_fecs_ctxsw_mailbox_value_pass_v() (0x00000001U) #define gr_fecs_ctxsw_mailbox_value_pass_v() (0x00000001U)
#define gr_fecs_ctxsw_mailbox_value_fail_v() (0x00000002U) #define gr_fecs_ctxsw_mailbox_value_fail_v() (0x00000002U)
#define gr_fecs_ctxsw_mailbox_set_r(i)\ #define gr_fecs_ctxsw_mailbox_set_r(i)\
(nvgpu_safe_add_u32(0x00409820U, nvgpu_safe_mult_u32((i), 4U))) (nvgpu_safe_add_u32(0x00409820U, nvgpu_safe_mult_u32((i), 4U)))
#define gr_fecs_ctxsw_mailbox_set_value_f(v) (((v)&0xffffffffU) << 0U) #define gr_fecs_ctxsw_mailbox_set_value_f(v) ((U32(v) & 0xffffffffU) << 0U)
#define gr_fecs_ctxsw_mailbox_clear_r(i)\ #define gr_fecs_ctxsw_mailbox_clear_r(i)\
(nvgpu_safe_add_u32(0x00409840U, nvgpu_safe_mult_u32((i), 4U))) (nvgpu_safe_add_u32(0x00409840U, nvgpu_safe_mult_u32((i), 4U)))
#define gr_fecs_ctxsw_mailbox_clear_value_f(v) (((v)&0xffffffffU) << 0U) #define gr_fecs_ctxsw_mailbox_clear_value_f(v) ((U32(v) & 0xffffffffU) << 0U)
#define gr_fecs_fs_r() (0x00409604U) #define gr_fecs_fs_r() (0x00409604U)
#define gr_fecs_fs_num_available_gpcs_s() (5U) #define gr_fecs_fs_num_available_gpcs_s() (5U)
#define gr_fecs_fs_num_available_gpcs_f(v) (((v)&0x1fU) << 0U) #define gr_fecs_fs_num_available_gpcs_f(v) ((U32(v) & 0x1fU) << 0U)
#define gr_fecs_fs_num_available_gpcs_m() (U32(0x1fU) << 0U) #define gr_fecs_fs_num_available_gpcs_m() (U32(0x1fU) << 0U)
#define gr_fecs_fs_num_available_gpcs_v(r) (((r) >> 0U) & 0x1fU) #define gr_fecs_fs_num_available_gpcs_v(r) (((r) >> 0U) & 0x1fU)
#define gr_fecs_fs_num_available_fbps_s() (5U) #define gr_fecs_fs_num_available_fbps_s() (5U)
#define gr_fecs_fs_num_available_fbps_f(v) (((v)&0x1fU) << 16U) #define gr_fecs_fs_num_available_fbps_f(v) ((U32(v) & 0x1fU) << 16U)
#define gr_fecs_fs_num_available_fbps_m() (U32(0x1fU) << 16U) #define gr_fecs_fs_num_available_fbps_m() (U32(0x1fU) << 16U)
#define gr_fecs_fs_num_available_fbps_v(r) (((r) >> 16U) & 0x1fU) #define gr_fecs_fs_num_available_fbps_v(r) (((r) >> 16U) & 0x1fU)
#define gr_fecs_cfg_r() (0x00409620U) #define gr_fecs_cfg_r() (0x00409620U)
#define gr_fecs_cfg_imem_sz_v(r) (((r) >> 0U) & 0xffU) #define gr_fecs_cfg_imem_sz_v(r) (((r) >> 0U) & 0xffU)
#define gr_fecs_rc_lanes_r() (0x00409880U) #define gr_fecs_rc_lanes_r() (0x00409880U)
#define gr_fecs_rc_lanes_num_chains_s() (6U) #define gr_fecs_rc_lanes_num_chains_s() (6U)
#define gr_fecs_rc_lanes_num_chains_f(v) (((v)&0x3fU) << 0U) #define gr_fecs_rc_lanes_num_chains_f(v) ((U32(v) & 0x3fU) << 0U)
#define gr_fecs_rc_lanes_num_chains_m() (U32(0x3fU) << 0U) #define gr_fecs_rc_lanes_num_chains_m() (U32(0x3fU) << 0U)
#define gr_fecs_rc_lanes_num_chains_v(r) (((r) >> 0U) & 0x3fU) #define gr_fecs_rc_lanes_num_chains_v(r) (((r) >> 0U) & 0x3fU)
#define gr_fecs_ctxsw_status_1_r() (0x00409400U) #define gr_fecs_ctxsw_status_1_r() (0x00409400U)
#define gr_fecs_ctxsw_status_1_arb_busy_s() (1U) #define gr_fecs_ctxsw_status_1_arb_busy_s() (1U)
#define gr_fecs_ctxsw_status_1_arb_busy_f(v) (((v)&0x1U) << 12U) #define gr_fecs_ctxsw_status_1_arb_busy_f(v) ((U32(v) & 0x1U) << 12U)
#define gr_fecs_ctxsw_status_1_arb_busy_m() (U32(0x1U) << 12U) #define gr_fecs_ctxsw_status_1_arb_busy_m() (U32(0x1U) << 12U)
#define gr_fecs_ctxsw_status_1_arb_busy_v(r) (((r) >> 12U) & 0x1U) #define gr_fecs_ctxsw_status_1_arb_busy_v(r) (((r) >> 12U) & 0x1U)
#define gr_fecs_arb_ctx_adr_r() (0x00409a24U) #define gr_fecs_arb_ctx_adr_r() (0x00409a24U)
#define gr_fecs_new_ctx_r() (0x00409b04U) #define gr_fecs_new_ctx_r() (0x00409b04U)
#define gr_fecs_new_ctx_ptr_s() (28U) #define gr_fecs_new_ctx_ptr_s() (28U)
#define gr_fecs_new_ctx_ptr_f(v) (((v)&0xfffffffU) << 0U) #define gr_fecs_new_ctx_ptr_f(v) ((U32(v) & 0xfffffffU) << 0U)
#define gr_fecs_new_ctx_ptr_m() (U32(0xfffffffU) << 0U) #define gr_fecs_new_ctx_ptr_m() (U32(0xfffffffU) << 0U)
#define gr_fecs_new_ctx_ptr_v(r) (((r) >> 0U) & 0xfffffffU) #define gr_fecs_new_ctx_ptr_v(r) (((r) >> 0U) & 0xfffffffU)
#define gr_fecs_new_ctx_target_s() (2U) #define gr_fecs_new_ctx_target_s() (2U)
#define gr_fecs_new_ctx_target_f(v) (((v)&0x3U) << 28U) #define gr_fecs_new_ctx_target_f(v) ((U32(v) & 0x3U) << 28U)
#define gr_fecs_new_ctx_target_m() (U32(0x3U) << 28U) #define gr_fecs_new_ctx_target_m() (U32(0x3U) << 28U)
#define gr_fecs_new_ctx_target_v(r) (((r) >> 28U) & 0x3U) #define gr_fecs_new_ctx_target_v(r) (((r) >> 28U) & 0x3U)
#define gr_fecs_new_ctx_target_vid_mem_f() (0x0U) #define gr_fecs_new_ctx_target_vid_mem_f() (0x0U)
#define gr_fecs_new_ctx_target_sys_mem_ncoh_f() (0x30000000U) #define gr_fecs_new_ctx_target_sys_mem_ncoh_f() (0x30000000U)
#define gr_fecs_new_ctx_target_sys_mem_coh_f() (0x20000000U) #define gr_fecs_new_ctx_target_sys_mem_coh_f() (0x20000000U)
#define gr_fecs_new_ctx_valid_s() (1U) #define gr_fecs_new_ctx_valid_s() (1U)
#define gr_fecs_new_ctx_valid_f(v) (((v)&0x1U) << 31U) #define gr_fecs_new_ctx_valid_f(v) ((U32(v) & 0x1U) << 31U)
#define gr_fecs_new_ctx_valid_m() (U32(0x1U) << 31U) #define gr_fecs_new_ctx_valid_m() (U32(0x1U) << 31U)
#define gr_fecs_new_ctx_valid_v(r) (((r) >> 31U) & 0x1U) #define gr_fecs_new_ctx_valid_v(r) (((r) >> 31U) & 0x1U)
#define gr_fecs_arb_ctx_ptr_r() (0x00409a0cU) #define gr_fecs_arb_ctx_ptr_r() (0x00409a0cU)
#define gr_fecs_arb_ctx_ptr_ptr_s() (28U) #define gr_fecs_arb_ctx_ptr_ptr_s() (28U)
#define gr_fecs_arb_ctx_ptr_ptr_f(v) (((v)&0xfffffffU) << 0U) #define gr_fecs_arb_ctx_ptr_ptr_f(v) ((U32(v) & 0xfffffffU) << 0U)
#define gr_fecs_arb_ctx_ptr_ptr_m() (U32(0xfffffffU) << 0U) #define gr_fecs_arb_ctx_ptr_ptr_m() (U32(0xfffffffU) << 0U)
#define gr_fecs_arb_ctx_ptr_ptr_v(r) (((r) >> 0U) & 0xfffffffU) #define gr_fecs_arb_ctx_ptr_ptr_v(r) (((r) >> 0U) & 0xfffffffU)
#define gr_fecs_arb_ctx_ptr_target_s() (2U) #define gr_fecs_arb_ctx_ptr_target_s() (2U)
#define gr_fecs_arb_ctx_ptr_target_f(v) (((v)&0x3U) << 28U) #define gr_fecs_arb_ctx_ptr_target_f(v) ((U32(v) & 0x3U) << 28U)
#define gr_fecs_arb_ctx_ptr_target_m() (U32(0x3U) << 28U) #define gr_fecs_arb_ctx_ptr_target_m() (U32(0x3U) << 28U)
#define gr_fecs_arb_ctx_ptr_target_v(r) (((r) >> 28U) & 0x3U) #define gr_fecs_arb_ctx_ptr_target_v(r) (((r) >> 28U) & 0x3U)
#define gr_fecs_arb_ctx_ptr_target_vid_mem_f() (0x0U) #define gr_fecs_arb_ctx_ptr_target_vid_mem_f() (0x0U)
@@ -397,7 +399,7 @@
#define gr_fecs_arb_ctx_ptr_target_sys_mem_coh_f() (0x20000000U) #define gr_fecs_arb_ctx_ptr_target_sys_mem_coh_f() (0x20000000U)
#define gr_fecs_arb_ctx_cmd_r() (0x00409a10U) #define gr_fecs_arb_ctx_cmd_r() (0x00409a10U)
#define gr_fecs_arb_ctx_cmd_cmd_s() (5U) #define gr_fecs_arb_ctx_cmd_cmd_s() (5U)
#define gr_fecs_arb_ctx_cmd_cmd_f(v) (((v)&0x1fU) << 0U) #define gr_fecs_arb_ctx_cmd_cmd_f(v) ((U32(v) & 0x1fU) << 0U)
#define gr_fecs_arb_ctx_cmd_cmd_m() (U32(0x1fU) << 0U) #define gr_fecs_arb_ctx_cmd_cmd_m() (U32(0x1fU) << 0U)
#define gr_fecs_arb_ctx_cmd_cmd_v(r) (((r) >> 0U) & 0x1fU) #define gr_fecs_arb_ctx_cmd_cmd_v(r) (((r) >> 0U) & 0x1fU)
#define gr_fecs_ctxsw_status_fe_0_r() (0x00409c00U) #define gr_fecs_ctxsw_status_fe_0_r() (0x00409c00U)
@@ -412,72 +414,72 @@
#define gr_rstr2d_gpc_map4_r() (0x0040781cU) #define gr_rstr2d_gpc_map4_r() (0x0040781cU)
#define gr_rstr2d_gpc_map5_r() (0x00407820U) #define gr_rstr2d_gpc_map5_r() (0x00407820U)
#define gr_rstr2d_map_table_cfg_r() (0x004078bcU) #define gr_rstr2d_map_table_cfg_r() (0x004078bcU)
#define gr_rstr2d_map_table_cfg_row_offset_f(v) (((v)&0xffU) << 0U) #define gr_rstr2d_map_table_cfg_row_offset_f(v) ((U32(v) & 0xffU) << 0U)
#define gr_rstr2d_map_table_cfg_num_entries_f(v) (((v)&0xffU) << 8U) #define gr_rstr2d_map_table_cfg_num_entries_f(v) ((U32(v) & 0xffU) << 8U)
#define gr_pd_hww_esr_r() (0x00406018U) #define gr_pd_hww_esr_r() (0x00406018U)
#define gr_pd_hww_esr_reset_active_f() (0x40000000U) #define gr_pd_hww_esr_reset_active_f() (0x40000000U)
#define gr_pd_hww_esr_en_enable_f() (0x80000000U) #define gr_pd_hww_esr_en_enable_f() (0x80000000U)
#define gr_pd_num_tpc_per_gpc_r(i)\ #define gr_pd_num_tpc_per_gpc_r(i)\
(nvgpu_safe_add_u32(0x00406028U, nvgpu_safe_mult_u32((i), 4U))) (nvgpu_safe_add_u32(0x00406028U, nvgpu_safe_mult_u32((i), 4U)))
#define gr_pd_num_tpc_per_gpc__size_1_v() (0x00000004U) #define gr_pd_num_tpc_per_gpc__size_1_v() (0x00000004U)
#define gr_pd_num_tpc_per_gpc_count0_f(v) (((v)&0xfU) << 0U) #define gr_pd_num_tpc_per_gpc_count0_f(v) ((U32(v) & 0xfU) << 0U)
#define gr_pd_num_tpc_per_gpc_count1_f(v) (((v)&0xfU) << 4U) #define gr_pd_num_tpc_per_gpc_count1_f(v) ((U32(v) & 0xfU) << 4U)
#define gr_pd_num_tpc_per_gpc_count2_f(v) (((v)&0xfU) << 8U) #define gr_pd_num_tpc_per_gpc_count2_f(v) ((U32(v) & 0xfU) << 8U)
#define gr_pd_num_tpc_per_gpc_count3_f(v) (((v)&0xfU) << 12U) #define gr_pd_num_tpc_per_gpc_count3_f(v) ((U32(v) & 0xfU) << 12U)
#define gr_pd_num_tpc_per_gpc_count4_f(v) (((v)&0xfU) << 16U) #define gr_pd_num_tpc_per_gpc_count4_f(v) ((U32(v) & 0xfU) << 16U)
#define gr_pd_num_tpc_per_gpc_count5_f(v) (((v)&0xfU) << 20U) #define gr_pd_num_tpc_per_gpc_count5_f(v) ((U32(v) & 0xfU) << 20U)
#define gr_pd_num_tpc_per_gpc_count6_f(v) (((v)&0xfU) << 24U) #define gr_pd_num_tpc_per_gpc_count6_f(v) ((U32(v) & 0xfU) << 24U)
#define gr_pd_num_tpc_per_gpc_count7_f(v) (((v)&0xfU) << 28U) #define gr_pd_num_tpc_per_gpc_count7_f(v) ((U32(v) & 0xfU) << 28U)
#define gr_pd_ab_dist_cfg0_r() (0x004064c0U) #define gr_pd_ab_dist_cfg0_r() (0x004064c0U)
#define gr_pd_ab_dist_cfg0_timeslice_enable_en_f() (0x80000000U) #define gr_pd_ab_dist_cfg0_timeslice_enable_en_f() (0x80000000U)
#define gr_pd_ab_dist_cfg0_timeslice_enable_dis_f() (0x0U) #define gr_pd_ab_dist_cfg0_timeslice_enable_dis_f() (0x0U)
#define gr_pd_ab_dist_cfg1_r() (0x004064c4U) #define gr_pd_ab_dist_cfg1_r() (0x004064c4U)
#define gr_pd_ab_dist_cfg1_max_batches_init_f() (0xffffU) #define gr_pd_ab_dist_cfg1_max_batches_init_f() (0xffffU)
#define gr_pd_ab_dist_cfg1_max_output_f(v) (((v)&0x7ffU) << 16U) #define gr_pd_ab_dist_cfg1_max_output_f(v) ((U32(v) & 0x7ffU) << 16U)
#define gr_pd_ab_dist_cfg1_max_output_granularity_v() (0x00000080U) #define gr_pd_ab_dist_cfg1_max_output_granularity_v() (0x00000080U)
#define gr_pd_ab_dist_cfg2_r() (0x004064c8U) #define gr_pd_ab_dist_cfg2_r() (0x004064c8U)
#define gr_pd_ab_dist_cfg2_token_limit_f(v) (((v)&0xfffU) << 0U) #define gr_pd_ab_dist_cfg2_token_limit_f(v) ((U32(v) & 0xfffU) << 0U)
#define gr_pd_ab_dist_cfg2_token_limit_init_v() (0x00000100U) #define gr_pd_ab_dist_cfg2_token_limit_init_v() (0x00000100U)
#define gr_pd_ab_dist_cfg2_state_limit_f(v) (((v)&0xfffU) << 16U) #define gr_pd_ab_dist_cfg2_state_limit_f(v) ((U32(v) & 0xfffU) << 16U)
#define gr_pd_ab_dist_cfg2_state_limit_scc_bundle_granularity_v() (0x00000020U) #define gr_pd_ab_dist_cfg2_state_limit_scc_bundle_granularity_v() (0x00000020U)
#define gr_pd_ab_dist_cfg2_state_limit_min_gpm_fifo_depths_v() (0x00000062U) #define gr_pd_ab_dist_cfg2_state_limit_min_gpm_fifo_depths_v() (0x00000062U)
#define gr_pd_pagepool_r() (0x004064ccU) #define gr_pd_pagepool_r() (0x004064ccU)
#define gr_pd_pagepool_total_pages_f(v) (((v)&0xffU) << 0U) #define gr_pd_pagepool_total_pages_f(v) ((U32(v) & 0xffU) << 0U)
#define gr_pd_pagepool_valid_true_f() (0x80000000U) #define gr_pd_pagepool_valid_true_f() (0x80000000U)
#define gr_pd_dist_skip_table_r(i)\ #define gr_pd_dist_skip_table_r(i)\
(nvgpu_safe_add_u32(0x004064d0U, nvgpu_safe_mult_u32((i), 4U))) (nvgpu_safe_add_u32(0x004064d0U, nvgpu_safe_mult_u32((i), 4U)))
#define gr_pd_dist_skip_table__size_1_v() (0x00000008U) #define gr_pd_dist_skip_table__size_1_v() (0x00000008U)
#define gr_pd_dist_skip_table_gpc_4n0_mask_f(v) (((v)&0xffU) << 0U) #define gr_pd_dist_skip_table_gpc_4n0_mask_f(v) ((U32(v) & 0xffU) << 0U)
#define gr_pd_dist_skip_table_gpc_4n1_mask_f(v) (((v)&0xffU) << 8U) #define gr_pd_dist_skip_table_gpc_4n1_mask_f(v) ((U32(v) & 0xffU) << 8U)
#define gr_pd_dist_skip_table_gpc_4n2_mask_f(v) (((v)&0xffU) << 16U) #define gr_pd_dist_skip_table_gpc_4n2_mask_f(v) ((U32(v) & 0xffU) << 16U)
#define gr_pd_dist_skip_table_gpc_4n3_mask_f(v) (((v)&0xffU) << 24U) #define gr_pd_dist_skip_table_gpc_4n3_mask_f(v) ((U32(v) & 0xffU) << 24U)
#define gr_pd_alpha_ratio_table_r(i)\ #define gr_pd_alpha_ratio_table_r(i)\
(nvgpu_safe_add_u32(0x00406800U, nvgpu_safe_mult_u32((i), 4U))) (nvgpu_safe_add_u32(0x00406800U, nvgpu_safe_mult_u32((i), 4U)))
#define gr_pd_alpha_ratio_table__size_1_v() (0x00000100U) #define gr_pd_alpha_ratio_table__size_1_v() (0x00000100U)
#define gr_pd_alpha_ratio_table_gpc_4n0_mask_f(v) (((v)&0xffU) << 0U) #define gr_pd_alpha_ratio_table_gpc_4n0_mask_f(v) ((U32(v) & 0xffU) << 0U)
#define gr_pd_alpha_ratio_table_gpc_4n1_mask_f(v) (((v)&0xffU) << 8U) #define gr_pd_alpha_ratio_table_gpc_4n1_mask_f(v) ((U32(v) & 0xffU) << 8U)
#define gr_pd_alpha_ratio_table_gpc_4n2_mask_f(v) (((v)&0xffU) << 16U) #define gr_pd_alpha_ratio_table_gpc_4n2_mask_f(v) ((U32(v) & 0xffU) << 16U)
#define gr_pd_alpha_ratio_table_gpc_4n3_mask_f(v) (((v)&0xffU) << 24U) #define gr_pd_alpha_ratio_table_gpc_4n3_mask_f(v) ((U32(v) & 0xffU) << 24U)
#define gr_pd_beta_ratio_table_r(i)\ #define gr_pd_beta_ratio_table_r(i)\
(nvgpu_safe_add_u32(0x00406c00U, nvgpu_safe_mult_u32((i), 4U))) (nvgpu_safe_add_u32(0x00406c00U, nvgpu_safe_mult_u32((i), 4U)))
#define gr_pd_beta_ratio_table__size_1_v() (0x00000100U) #define gr_pd_beta_ratio_table__size_1_v() (0x00000100U)
#define gr_pd_beta_ratio_table_gpc_4n0_mask_f(v) (((v)&0xffU) << 0U) #define gr_pd_beta_ratio_table_gpc_4n0_mask_f(v) ((U32(v) & 0xffU) << 0U)
#define gr_pd_beta_ratio_table_gpc_4n1_mask_f(v) (((v)&0xffU) << 8U) #define gr_pd_beta_ratio_table_gpc_4n1_mask_f(v) ((U32(v) & 0xffU) << 8U)
#define gr_pd_beta_ratio_table_gpc_4n2_mask_f(v) (((v)&0xffU) << 16U) #define gr_pd_beta_ratio_table_gpc_4n2_mask_f(v) ((U32(v) & 0xffU) << 16U)
#define gr_pd_beta_ratio_table_gpc_4n3_mask_f(v) (((v)&0xffU) << 24U) #define gr_pd_beta_ratio_table_gpc_4n3_mask_f(v) ((U32(v) & 0xffU) << 24U)
#define gr_ds_debug_r() (0x00405800U) #define gr_ds_debug_r() (0x00405800U)
#define gr_ds_debug_timeslice_mode_disable_f() (0x0U) #define gr_ds_debug_timeslice_mode_disable_f() (0x0U)
#define gr_ds_debug_timeslice_mode_enable_f() (0x8000000U) #define gr_ds_debug_timeslice_mode_enable_f() (0x8000000U)
#define gr_ds_zbc_color_r_r() (0x00405804U) #define gr_ds_zbc_color_r_r() (0x00405804U)
#define gr_ds_zbc_color_r_val_f(v) (((v)&0xffffffffU) << 0U) #define gr_ds_zbc_color_r_val_f(v) ((U32(v) & 0xffffffffU) << 0U)
#define gr_ds_zbc_color_g_r() (0x00405808U) #define gr_ds_zbc_color_g_r() (0x00405808U)
#define gr_ds_zbc_color_g_val_f(v) (((v)&0xffffffffU) << 0U) #define gr_ds_zbc_color_g_val_f(v) ((U32(v) & 0xffffffffU) << 0U)
#define gr_ds_zbc_color_b_r() (0x0040580cU) #define gr_ds_zbc_color_b_r() (0x0040580cU)
#define gr_ds_zbc_color_b_val_f(v) (((v)&0xffffffffU) << 0U) #define gr_ds_zbc_color_b_val_f(v) ((U32(v) & 0xffffffffU) << 0U)
#define gr_ds_zbc_color_a_r() (0x00405810U) #define gr_ds_zbc_color_a_r() (0x00405810U)
#define gr_ds_zbc_color_a_val_f(v) (((v)&0xffffffffU) << 0U) #define gr_ds_zbc_color_a_val_f(v) ((U32(v) & 0xffffffffU) << 0U)
#define gr_ds_zbc_color_fmt_r() (0x00405814U) #define gr_ds_zbc_color_fmt_r() (0x00405814U)
#define gr_ds_zbc_color_fmt_val_f(v) (((v)&0x7fU) << 0U) #define gr_ds_zbc_color_fmt_val_f(v) ((U32(v) & 0x7fU) << 0U)
#define gr_ds_zbc_color_fmt_val_invalid_f() (0x0U) #define gr_ds_zbc_color_fmt_val_invalid_f() (0x0U)
#define gr_ds_zbc_color_fmt_val_zero_v() (0x00000001U) #define gr_ds_zbc_color_fmt_val_zero_v() (0x00000001U)
#define gr_ds_zbc_color_fmt_val_unorm_one_v() (0x00000002U) #define gr_ds_zbc_color_fmt_val_unorm_one_v() (0x00000002U)
@@ -485,28 +487,28 @@
#define gr_ds_zbc_color_fmt_val_a8_b8_g8_r8_v() (0x00000028U) #define gr_ds_zbc_color_fmt_val_a8_b8_g8_r8_v() (0x00000028U)
#define gr_ds_zbc_z_r() (0x00405818U) #define gr_ds_zbc_z_r() (0x00405818U)
#define gr_ds_zbc_z_val_s() (32U) #define gr_ds_zbc_z_val_s() (32U)
#define gr_ds_zbc_z_val_f(v) (((v)&0xffffffffU) << 0U) #define gr_ds_zbc_z_val_f(v) ((U32(v) & 0xffffffffU) << 0U)
#define gr_ds_zbc_z_val_m() (U32(0xffffffffU) << 0U) #define gr_ds_zbc_z_val_m() (U32(0xffffffffU) << 0U)
#define gr_ds_zbc_z_val_v(r) (((r) >> 0U) & 0xffffffffU) #define gr_ds_zbc_z_val_v(r) (((r) >> 0U) & 0xffffffffU)
#define gr_ds_zbc_z_val__init_v() (0x00000000U) #define gr_ds_zbc_z_val__init_v() (0x00000000U)
#define gr_ds_zbc_z_val__init_f() (0x0U) #define gr_ds_zbc_z_val__init_f() (0x0U)
#define gr_ds_zbc_z_fmt_r() (0x0040581cU) #define gr_ds_zbc_z_fmt_r() (0x0040581cU)
#define gr_ds_zbc_z_fmt_val_f(v) (((v)&0x1U) << 0U) #define gr_ds_zbc_z_fmt_val_f(v) ((U32(v) & 0x1U) << 0U)
#define gr_ds_zbc_z_fmt_val_invalid_f() (0x0U) #define gr_ds_zbc_z_fmt_val_invalid_f() (0x0U)
#define gr_ds_zbc_z_fmt_val_fp32_v() (0x00000001U) #define gr_ds_zbc_z_fmt_val_fp32_v() (0x00000001U)
#define gr_ds_zbc_tbl_index_r() (0x00405820U) #define gr_ds_zbc_tbl_index_r() (0x00405820U)
#define gr_ds_zbc_tbl_index_val_f(v) (((v)&0xfU) << 0U) #define gr_ds_zbc_tbl_index_val_f(v) ((U32(v) & 0xfU) << 0U)
#define gr_ds_zbc_tbl_ld_r() (0x00405824U) #define gr_ds_zbc_tbl_ld_r() (0x00405824U)
#define gr_ds_zbc_tbl_ld_select_c_f() (0x0U) #define gr_ds_zbc_tbl_ld_select_c_f() (0x0U)
#define gr_ds_zbc_tbl_ld_select_z_f() (0x1U) #define gr_ds_zbc_tbl_ld_select_z_f() (0x1U)
#define gr_ds_zbc_tbl_ld_action_write_f() (0x0U) #define gr_ds_zbc_tbl_ld_action_write_f() (0x0U)
#define gr_ds_zbc_tbl_ld_trigger_active_f() (0x4U) #define gr_ds_zbc_tbl_ld_trigger_active_f() (0x4U)
#define gr_ds_tga_constraintlogic_r() (0x00405830U) #define gr_ds_tga_constraintlogic_r() (0x00405830U)
#define gr_ds_tga_constraintlogic_beta_cbsize_f(v) (((v)&0xfffU) << 16U) #define gr_ds_tga_constraintlogic_beta_cbsize_f(v) ((U32(v) & 0xfffU) << 16U)
#define gr_ds_tga_constraintlogic_alpha_cbsize_f(v) (((v)&0xfffU) << 0U) #define gr_ds_tga_constraintlogic_alpha_cbsize_f(v) ((U32(v) & 0xfffU) << 0U)
#define gr_ds_hww_esr_r() (0x00405840U) #define gr_ds_hww_esr_r() (0x00405840U)
#define gr_ds_hww_esr_reset_s() (1U) #define gr_ds_hww_esr_reset_s() (1U)
#define gr_ds_hww_esr_reset_f(v) (((v)&0x1U) << 30U) #define gr_ds_hww_esr_reset_f(v) ((U32(v) & 0x1U) << 30U)
#define gr_ds_hww_esr_reset_m() (U32(0x1U) << 30U) #define gr_ds_hww_esr_reset_m() (U32(0x1U) << 30U)
#define gr_ds_hww_esr_reset_v(r) (((r) >> 30U) & 0x1U) #define gr_ds_hww_esr_reset_v(r) (((r) >> 30U) & 0x1U)
#define gr_ds_hww_esr_reset_task_v() (0x00000001U) #define gr_ds_hww_esr_reset_task_v() (0x00000001U)
@@ -540,25 +542,25 @@
#define gr_ds_num_tpc_per_gpc_r(i)\ #define gr_ds_num_tpc_per_gpc_r(i)\
(nvgpu_safe_add_u32(0x00405870U, nvgpu_safe_mult_u32((i), 4U))) (nvgpu_safe_add_u32(0x00405870U, nvgpu_safe_mult_u32((i), 4U)))
#define gr_scc_bundle_cb_base_r() (0x00408004U) #define gr_scc_bundle_cb_base_r() (0x00408004U)
#define gr_scc_bundle_cb_base_addr_39_8_f(v) (((v)&0xffffffffU) << 0U) #define gr_scc_bundle_cb_base_addr_39_8_f(v) ((U32(v) & 0xffffffffU) << 0U)
#define gr_scc_bundle_cb_base_addr_39_8_align_bits_v() (0x00000008U) #define gr_scc_bundle_cb_base_addr_39_8_align_bits_v() (0x00000008U)
#define gr_scc_bundle_cb_size_r() (0x00408008U) #define gr_scc_bundle_cb_size_r() (0x00408008U)
#define gr_scc_bundle_cb_size_div_256b_f(v) (((v)&0x7ffU) << 0U) #define gr_scc_bundle_cb_size_div_256b_f(v) ((U32(v) & 0x7ffU) << 0U)
#define gr_scc_bundle_cb_size_div_256b__prod_v() (0x00000018U) #define gr_scc_bundle_cb_size_div_256b__prod_v() (0x00000018U)
#define gr_scc_bundle_cb_size_div_256b_byte_granularity_v() (0x00000100U) #define gr_scc_bundle_cb_size_div_256b_byte_granularity_v() (0x00000100U)
#define gr_scc_bundle_cb_size_valid_false_v() (0x00000000U) #define gr_scc_bundle_cb_size_valid_false_v() (0x00000000U)
#define gr_scc_bundle_cb_size_valid_false_f() (0x0U) #define gr_scc_bundle_cb_size_valid_false_f() (0x0U)
#define gr_scc_bundle_cb_size_valid_true_f() (0x80000000U) #define gr_scc_bundle_cb_size_valid_true_f() (0x80000000U)
#define gr_scc_pagepool_base_r() (0x0040800cU) #define gr_scc_pagepool_base_r() (0x0040800cU)
#define gr_scc_pagepool_base_addr_39_8_f(v) (((v)&0xffffffffU) << 0U) #define gr_scc_pagepool_base_addr_39_8_f(v) ((U32(v) & 0xffffffffU) << 0U)
#define gr_scc_pagepool_base_addr_39_8_align_bits_v() (0x00000008U) #define gr_scc_pagepool_base_addr_39_8_align_bits_v() (0x00000008U)
#define gr_scc_pagepool_r() (0x00408010U) #define gr_scc_pagepool_r() (0x00408010U)
#define gr_scc_pagepool_total_pages_f(v) (((v)&0xffU) << 0U) #define gr_scc_pagepool_total_pages_f(v) ((U32(v) & 0xffU) << 0U)
#define gr_scc_pagepool_total_pages_hwmax_v() (0x00000000U) #define gr_scc_pagepool_total_pages_hwmax_v() (0x00000000U)
#define gr_scc_pagepool_total_pages_hwmax_value_v() (0x00000080U) #define gr_scc_pagepool_total_pages_hwmax_value_v() (0x00000080U)
#define gr_scc_pagepool_total_pages_byte_granularity_v() (0x00000100U) #define gr_scc_pagepool_total_pages_byte_granularity_v() (0x00000100U)
#define gr_scc_pagepool_max_valid_pages_s() (8U) #define gr_scc_pagepool_max_valid_pages_s() (8U)
#define gr_scc_pagepool_max_valid_pages_f(v) (((v)&0xffU) << 8U) #define gr_scc_pagepool_max_valid_pages_f(v) ((U32(v) & 0xffU) << 8U)
#define gr_scc_pagepool_max_valid_pages_m() (U32(0xffU) << 8U) #define gr_scc_pagepool_max_valid_pages_m() (U32(0xffU) << 8U)
#define gr_scc_pagepool_max_valid_pages_v(r) (((r) >> 8U) & 0xffU) #define gr_scc_pagepool_max_valid_pages_v(r) (((r) >> 8U) & 0xffU)
#define gr_scc_pagepool_valid_true_f() (0x80000000U) #define gr_scc_pagepool_valid_true_f() (0x80000000U)
@@ -568,8 +570,8 @@
#define gr_sked_hww_esr_r() (0x00407020U) #define gr_sked_hww_esr_r() (0x00407020U)
#define gr_sked_hww_esr_reset_active_f() (0x40000000U) #define gr_sked_hww_esr_reset_active_f() (0x40000000U)
#define gr_cwd_fs_r() (0x00405b00U) #define gr_cwd_fs_r() (0x00405b00U)
#define gr_cwd_fs_num_gpcs_f(v) (((v)&0xffU) << 0U) #define gr_cwd_fs_num_gpcs_f(v) ((U32(v) & 0xffU) << 0U)
#define gr_cwd_fs_num_tpcs_f(v) (((v)&0xffU) << 8U) #define gr_cwd_fs_num_tpcs_f(v) ((U32(v) & 0xffU) << 8U)
#define gr_gpc0_fs_gpc_r() (0x00502608U) #define gr_gpc0_fs_gpc_r() (0x00502608U)
#define gr_gpc0_fs_gpc_num_available_tpcs_v(r) (((r) >> 0U) & 0x1fU) #define gr_gpc0_fs_gpc_num_available_tpcs_v(r) (((r) >> 0U) & 0x1fU)
#define gr_gpc0_fs_gpc_num_available_zculls_v(r) (((r) >> 16U) & 0x1fU) #define gr_gpc0_fs_gpc_num_available_zculls_v(r) (((r) >> 16U) & 0x1fU)
@@ -577,50 +579,51 @@
#define gr_gpc0_cfg_imem_sz_v(r) (((r) >> 0U) & 0xffU) #define gr_gpc0_cfg_imem_sz_v(r) (((r) >> 0U) & 0xffU)
#define gr_gpccs_rc_lanes_r() (0x00502880U) #define gr_gpccs_rc_lanes_r() (0x00502880U)
#define gr_gpccs_rc_lanes_num_chains_s() (6U) #define gr_gpccs_rc_lanes_num_chains_s() (6U)
#define gr_gpccs_rc_lanes_num_chains_f(v) (((v)&0x3fU) << 0U) #define gr_gpccs_rc_lanes_num_chains_f(v) ((U32(v) & 0x3fU) << 0U)
#define gr_gpccs_rc_lanes_num_chains_m() (U32(0x3fU) << 0U) #define gr_gpccs_rc_lanes_num_chains_m() (U32(0x3fU) << 0U)
#define gr_gpccs_rc_lanes_num_chains_v(r) (((r) >> 0U) & 0x3fU) #define gr_gpccs_rc_lanes_num_chains_v(r) (((r) >> 0U) & 0x3fU)
#define gr_gpccs_rc_lane_size_r(i)\ #define gr_gpccs_rc_lane_size_r(i)\
(nvgpu_safe_add_u32(0x00502910U, nvgpu_safe_mult_u32((i), 0U))) (nvgpu_safe_add_u32(0x00502910U, nvgpu_safe_mult_u32((i), 0U)))
#define gr_gpccs_rc_lane_size__size_1_v() (0x00000010U) #define gr_gpccs_rc_lane_size__size_1_v() (0x00000010U)
#define gr_gpccs_rc_lane_size_v_s() (24U) #define gr_gpccs_rc_lane_size_v_s() (24U)
#define gr_gpccs_rc_lane_size_v_f(v) (((v)&0xffffffU) << 0U) #define gr_gpccs_rc_lane_size_v_f(v) ((U32(v) & 0xffffffU) << 0U)
#define gr_gpccs_rc_lane_size_v_m() (U32(0xffffffU) << 0U) #define gr_gpccs_rc_lane_size_v_m() (U32(0xffffffU) << 0U)
#define gr_gpccs_rc_lane_size_v_v(r) (((r) >> 0U) & 0xffffffU) #define gr_gpccs_rc_lane_size_v_v(r) (((r) >> 0U) & 0xffffffU)
#define gr_gpccs_rc_lane_size_v_0_v() (0x00000000U) #define gr_gpccs_rc_lane_size_v_0_v() (0x00000000U)
#define gr_gpccs_rc_lane_size_v_0_f() (0x0U) #define gr_gpccs_rc_lane_size_v_0_f() (0x0U)
#define gr_gpc0_zcull_fs_r() (0x00500910U) #define gr_gpc0_zcull_fs_r() (0x00500910U)
#define gr_gpc0_zcull_fs_num_sms_f(v) (((v)&0x1ffU) << 0U) #define gr_gpc0_zcull_fs_num_sms_f(v) ((U32(v) & 0x1ffU) << 0U)
#define gr_gpc0_zcull_fs_num_active_banks_f(v) (((v)&0xfU) << 16U) #define gr_gpc0_zcull_fs_num_active_banks_f(v) ((U32(v) & 0xfU) << 16U)
#define gr_gpc0_zcull_ram_addr_r() (0x00500914U) #define gr_gpc0_zcull_ram_addr_r() (0x00500914U)
#define gr_gpc0_zcull_ram_addr_tiles_per_hypertile_row_per_gpc_f(v)\ #define gr_gpc0_zcull_ram_addr_tiles_per_hypertile_row_per_gpc_f(v)\
(((v)&0xfU) << 0U) ((U32(v) & 0xfU) << 0U)
#define gr_gpc0_zcull_ram_addr_row_offset_f(v) (((v)&0xfU) << 8U) #define gr_gpc0_zcull_ram_addr_row_offset_f(v) ((U32(v) & 0xfU) << 8U)
#define gr_gpc0_zcull_sm_num_rcp_r() (0x00500918U) #define gr_gpc0_zcull_sm_num_rcp_r() (0x00500918U)
#define gr_gpc0_zcull_sm_num_rcp_conservative_f(v) (((v)&0xffffffU) << 0U) #define gr_gpc0_zcull_sm_num_rcp_conservative_f(v) ((U32(v) & 0xffffffU) << 0U)
#define gr_gpc0_zcull_sm_num_rcp_conservative__max_v() (0x00800000U) #define gr_gpc0_zcull_sm_num_rcp_conservative__max_v() (0x00800000U)
#define gr_gpc0_zcull_total_ram_size_r() (0x00500920U) #define gr_gpc0_zcull_total_ram_size_r() (0x00500920U)
#define gr_gpc0_zcull_total_ram_size_num_aliquots_f(v) (((v)&0xffffU) << 0U) #define gr_gpc0_zcull_total_ram_size_num_aliquots_f(v)\
((U32(v) & 0xffffU) << 0U)
#define gr_gpc0_zcull_zcsize_r(i)\ #define gr_gpc0_zcull_zcsize_r(i)\
(nvgpu_safe_add_u32(0x00500a04U, nvgpu_safe_mult_u32((i), 32U))) (nvgpu_safe_add_u32(0x00500a04U, nvgpu_safe_mult_u32((i), 32U)))
#define gr_gpc0_zcull_zcsize_height_subregion__multiple_v() (0x00000040U) #define gr_gpc0_zcull_zcsize_height_subregion__multiple_v() (0x00000040U)
#define gr_gpc0_zcull_zcsize_width_subregion__multiple_v() (0x00000010U) #define gr_gpc0_zcull_zcsize_width_subregion__multiple_v() (0x00000010U)
#define gr_gpc0_gpm_pd_active_tpcs_r() (0x00500c08U) #define gr_gpc0_gpm_pd_active_tpcs_r() (0x00500c08U)
#define gr_gpc0_gpm_pd_active_tpcs_num_f(v) (((v)&0x7U) << 0U) #define gr_gpc0_gpm_pd_active_tpcs_num_f(v) ((U32(v) & 0x7U) << 0U)
#define gr_gpc0_gpm_pd_sm_id_r(i)\ #define gr_gpc0_gpm_pd_sm_id_r(i)\
(nvgpu_safe_add_u32(0x00500c10U, nvgpu_safe_mult_u32((i), 4U))) (nvgpu_safe_add_u32(0x00500c10U, nvgpu_safe_mult_u32((i), 4U)))
#define gr_gpc0_gpm_pd_sm_id_id_f(v) (((v)&0xffU) << 0U) #define gr_gpc0_gpm_pd_sm_id_id_f(v) ((U32(v) & 0xffU) << 0U)
#define gr_gpc0_gpm_pd_pes_tpc_id_mask_r(i)\ #define gr_gpc0_gpm_pd_pes_tpc_id_mask_r(i)\
(nvgpu_safe_add_u32(0x00500c30U, nvgpu_safe_mult_u32((i), 4U))) (nvgpu_safe_add_u32(0x00500c30U, nvgpu_safe_mult_u32((i), 4U)))
#define gr_gpc0_gpm_pd_pes_tpc_id_mask_mask_v(r) (((r) >> 0U) & 0xffU) #define gr_gpc0_gpm_pd_pes_tpc_id_mask_mask_v(r) (((r) >> 0U) & 0xffU)
#define gr_gpc0_gpm_sd_active_tpcs_r() (0x00500c8cU) #define gr_gpc0_gpm_sd_active_tpcs_r() (0x00500c8cU)
#define gr_gpc0_gpm_sd_active_tpcs_num_f(v) (((v)&0x7U) << 0U) #define gr_gpc0_gpm_sd_active_tpcs_num_f(v) ((U32(v) & 0x7U) << 0U)
#define gr_gpc0_tpc0_pe_cfg_smid_r() (0x00504088U) #define gr_gpc0_tpc0_pe_cfg_smid_r() (0x00504088U)
#define gr_gpc0_tpc0_pe_cfg_smid_value_f(v) (((v)&0xffffU) << 0U) #define gr_gpc0_tpc0_pe_cfg_smid_value_f(v) ((U32(v) & 0xffffU) << 0U)
#define gr_gpc0_tpc0_l1c_cfg_smid_r() (0x005044e8U) #define gr_gpc0_tpc0_l1c_cfg_smid_r() (0x005044e8U)
#define gr_gpc0_tpc0_l1c_cfg_smid_value_f(v) (((v)&0xffffU) << 0U) #define gr_gpc0_tpc0_l1c_cfg_smid_value_f(v) ((U32(v) & 0xffffU) << 0U)
#define gr_gpc0_tpc0_sm_cfg_r() (0x00504698U) #define gr_gpc0_tpc0_sm_cfg_r() (0x00504698U)
#define gr_gpc0_tpc0_sm_cfg_sm_id_f(v) (((v)&0xffffU) << 0U) #define gr_gpc0_tpc0_sm_cfg_sm_id_f(v) ((U32(v) & 0xffffU) << 0U)
#define gr_gpc0_tpc0_sm_cfg_sm_id_v(r) (((r) >> 0U) & 0xffffU) #define gr_gpc0_tpc0_sm_cfg_sm_id_v(r) (((r) >> 0U) & 0xffffU)
#define gr_gpc0_tpc0_sm_arch_r() (0x0050469cU) #define gr_gpc0_tpc0_sm_arch_r() (0x0050469cU)
#define gr_gpc0_tpc0_sm_arch_warp_count_v(r) (((r) >> 0U) & 0xffU) #define gr_gpc0_tpc0_sm_arch_warp_count_v(r) (((r) >> 0U) & 0xffU)
@@ -630,76 +633,77 @@
#define gr_gpc0_ppc0_pes_vsc_strem_master_pe_m() (U32(0x1U) << 0U) #define gr_gpc0_ppc0_pes_vsc_strem_master_pe_m() (U32(0x1U) << 0U)
#define gr_gpc0_ppc0_pes_vsc_strem_master_pe_true_f() (0x1U) #define gr_gpc0_ppc0_pes_vsc_strem_master_pe_true_f() (0x1U)
#define gr_gpc0_ppc0_cbm_cfg_r() (0x005030c0U) #define gr_gpc0_ppc0_cbm_cfg_r() (0x005030c0U)
#define gr_gpc0_ppc0_cbm_cfg_start_offset_f(v) (((v)&0xffffU) << 0U) #define gr_gpc0_ppc0_cbm_cfg_start_offset_f(v) ((U32(v) & 0xffffU) << 0U)
#define gr_gpc0_ppc0_cbm_cfg_start_offset_m() (U32(0xffffU) << 0U) #define gr_gpc0_ppc0_cbm_cfg_start_offset_m() (U32(0xffffU) << 0U)
#define gr_gpc0_ppc0_cbm_cfg_start_offset_v(r) (((r) >> 0U) & 0xffffU) #define gr_gpc0_ppc0_cbm_cfg_start_offset_v(r) (((r) >> 0U) & 0xffffU)
#define gr_gpc0_ppc0_cbm_cfg_size_f(v) (((v)&0xfffU) << 16U) #define gr_gpc0_ppc0_cbm_cfg_size_f(v) ((U32(v) & 0xfffU) << 16U)
#define gr_gpc0_ppc0_cbm_cfg_size_m() (U32(0xfffU) << 16U) #define gr_gpc0_ppc0_cbm_cfg_size_m() (U32(0xfffU) << 16U)
#define gr_gpc0_ppc0_cbm_cfg_size_v(r) (((r) >> 16U) & 0xfffU) #define gr_gpc0_ppc0_cbm_cfg_size_v(r) (((r) >> 16U) & 0xfffU)
#define gr_gpc0_ppc0_cbm_cfg_size_default_v() (0x00000240U) #define gr_gpc0_ppc0_cbm_cfg_size_default_v() (0x00000240U)
#define gr_gpc0_ppc0_cbm_cfg_size_granularity_v() (0x00000020U) #define gr_gpc0_ppc0_cbm_cfg_size_granularity_v() (0x00000020U)
#define gr_gpc0_ppc0_cbm_cfg_timeslice_mode_f(v) (((v)&0x1U) << 28U) #define gr_gpc0_ppc0_cbm_cfg_timeslice_mode_f(v) ((U32(v) & 0x1U) << 28U)
#define gr_gpc0_ppc0_cbm_cfg2_r() (0x005030e4U) #define gr_gpc0_ppc0_cbm_cfg2_r() (0x005030e4U)
#define gr_gpc0_ppc0_cbm_cfg2_start_offset_f(v) (((v)&0xffffU) << 0U) #define gr_gpc0_ppc0_cbm_cfg2_start_offset_f(v) ((U32(v) & 0xffffU) << 0U)
#define gr_gpc0_ppc0_cbm_cfg2_size_f(v) (((v)&0xfffU) << 16U) #define gr_gpc0_ppc0_cbm_cfg2_size_f(v) ((U32(v) & 0xfffU) << 16U)
#define gr_gpc0_ppc0_cbm_cfg2_size_m() (U32(0xfffU) << 16U) #define gr_gpc0_ppc0_cbm_cfg2_size_m() (U32(0xfffU) << 16U)
#define gr_gpc0_ppc0_cbm_cfg2_size_v(r) (((r) >> 16U) & 0xfffU) #define gr_gpc0_ppc0_cbm_cfg2_size_v(r) (((r) >> 16U) & 0xfffU)
#define gr_gpc0_ppc0_cbm_cfg2_size_default_v() (0x00000648U) #define gr_gpc0_ppc0_cbm_cfg2_size_default_v() (0x00000648U)
#define gr_gpc0_ppc0_cbm_cfg2_size_granularity_v() (0x00000020U) #define gr_gpc0_ppc0_cbm_cfg2_size_granularity_v() (0x00000020U)
#define gr_gpccs_falcon_addr_r() (0x0041a0acU) #define gr_gpccs_falcon_addr_r() (0x0041a0acU)
#define gr_gpccs_falcon_addr_lsb_s() (6U) #define gr_gpccs_falcon_addr_lsb_s() (6U)
#define gr_gpccs_falcon_addr_lsb_f(v) (((v)&0x3fU) << 0U) #define gr_gpccs_falcon_addr_lsb_f(v) ((U32(v) & 0x3fU) << 0U)
#define gr_gpccs_falcon_addr_lsb_m() (U32(0x3fU) << 0U) #define gr_gpccs_falcon_addr_lsb_m() (U32(0x3fU) << 0U)
#define gr_gpccs_falcon_addr_lsb_v(r) (((r) >> 0U) & 0x3fU) #define gr_gpccs_falcon_addr_lsb_v(r) (((r) >> 0U) & 0x3fU)
#define gr_gpccs_falcon_addr_lsb_init_v() (0x00000000U) #define gr_gpccs_falcon_addr_lsb_init_v() (0x00000000U)
#define gr_gpccs_falcon_addr_lsb_init_f() (0x0U) #define gr_gpccs_falcon_addr_lsb_init_f() (0x0U)
#define gr_gpccs_falcon_addr_msb_s() (6U) #define gr_gpccs_falcon_addr_msb_s() (6U)
#define gr_gpccs_falcon_addr_msb_f(v) (((v)&0x3fU) << 6U) #define gr_gpccs_falcon_addr_msb_f(v) ((U32(v) & 0x3fU) << 6U)
#define gr_gpccs_falcon_addr_msb_m() (U32(0x3fU) << 6U) #define gr_gpccs_falcon_addr_msb_m() (U32(0x3fU) << 6U)
#define gr_gpccs_falcon_addr_msb_v(r) (((r) >> 6U) & 0x3fU) #define gr_gpccs_falcon_addr_msb_v(r) (((r) >> 6U) & 0x3fU)
#define gr_gpccs_falcon_addr_msb_init_v() (0x00000000U) #define gr_gpccs_falcon_addr_msb_init_v() (0x00000000U)
#define gr_gpccs_falcon_addr_msb_init_f() (0x0U) #define gr_gpccs_falcon_addr_msb_init_f() (0x0U)
#define gr_gpccs_falcon_addr_ext_s() (12U) #define gr_gpccs_falcon_addr_ext_s() (12U)
#define gr_gpccs_falcon_addr_ext_f(v) (((v)&0xfffU) << 0U) #define gr_gpccs_falcon_addr_ext_f(v) ((U32(v) & 0xfffU) << 0U)
#define gr_gpccs_falcon_addr_ext_m() (U32(0xfffU) << 0U) #define gr_gpccs_falcon_addr_ext_m() (U32(0xfffU) << 0U)
#define gr_gpccs_falcon_addr_ext_v(r) (((r) >> 0U) & 0xfffU) #define gr_gpccs_falcon_addr_ext_v(r) (((r) >> 0U) & 0xfffU)
#define gr_gpccs_cpuctl_r() (0x0041a100U) #define gr_gpccs_cpuctl_r() (0x0041a100U)
#define gr_gpccs_cpuctl_startcpu_f(v) (((v)&0x1U) << 1U) #define gr_gpccs_cpuctl_startcpu_f(v) ((U32(v) & 0x1U) << 1U)
#define gr_gpccs_dmactl_r() (0x0041a10cU) #define gr_gpccs_dmactl_r() (0x0041a10cU)
#define gr_gpccs_dmactl_require_ctx_f(v) (((v)&0x1U) << 0U) #define gr_gpccs_dmactl_require_ctx_f(v) ((U32(v) & 0x1U) << 0U)
#define gr_gpccs_dmactl_dmem_scrubbing_m() (U32(0x1U) << 1U) #define gr_gpccs_dmactl_dmem_scrubbing_m() (U32(0x1U) << 1U)
#define gr_gpccs_dmactl_imem_scrubbing_m() (U32(0x1U) << 2U) #define gr_gpccs_dmactl_imem_scrubbing_m() (U32(0x1U) << 2U)
#define gr_gpccs_imemc_r(i)\ #define gr_gpccs_imemc_r(i)\
(nvgpu_safe_add_u32(0x0041a180U, nvgpu_safe_mult_u32((i), 16U))) (nvgpu_safe_add_u32(0x0041a180U, nvgpu_safe_mult_u32((i), 16U)))
#define gr_gpccs_imemc_offs_f(v) (((v)&0x3fU) << 2U) #define gr_gpccs_imemc_offs_f(v) ((U32(v) & 0x3fU) << 2U)
#define gr_gpccs_imemc_blk_f(v) (((v)&0xffU) << 8U) #define gr_gpccs_imemc_blk_f(v) ((U32(v) & 0xffU) << 8U)
#define gr_gpccs_imemc_aincw_f(v) (((v)&0x1U) << 24U) #define gr_gpccs_imemc_aincw_f(v) ((U32(v) & 0x1U) << 24U)
#define gr_gpccs_imemd_r(i)\ #define gr_gpccs_imemd_r(i)\
(nvgpu_safe_add_u32(0x0041a184U, nvgpu_safe_mult_u32((i), 16U))) (nvgpu_safe_add_u32(0x0041a184U, nvgpu_safe_mult_u32((i), 16U)))
#define gr_gpccs_imemt_r(i)\ #define gr_gpccs_imemt_r(i)\
(nvgpu_safe_add_u32(0x0041a188U, nvgpu_safe_mult_u32((i), 16U))) (nvgpu_safe_add_u32(0x0041a188U, nvgpu_safe_mult_u32((i), 16U)))
#define gr_gpccs_imemt__size_1_v() (0x00000004U) #define gr_gpccs_imemt__size_1_v() (0x00000004U)
#define gr_gpccs_imemt_tag_f(v) (((v)&0xffffU) << 0U) #define gr_gpccs_imemt_tag_f(v) ((U32(v) & 0xffffU) << 0U)
#define gr_gpccs_dmemc_r(i)\ #define gr_gpccs_dmemc_r(i)\
(nvgpu_safe_add_u32(0x0041a1c0U, nvgpu_safe_mult_u32((i), 8U))) (nvgpu_safe_add_u32(0x0041a1c0U, nvgpu_safe_mult_u32((i), 8U)))
#define gr_gpccs_dmemc_offs_f(v) (((v)&0x3fU) << 2U) #define gr_gpccs_dmemc_offs_f(v) ((U32(v) & 0x3fU) << 2U)
#define gr_gpccs_dmemc_blk_f(v) (((v)&0xffU) << 8U) #define gr_gpccs_dmemc_blk_f(v) ((U32(v) & 0xffU) << 8U)
#define gr_gpccs_dmemc_aincw_f(v) (((v)&0x1U) << 24U) #define gr_gpccs_dmemc_aincw_f(v) ((U32(v) & 0x1U) << 24U)
#define gr_gpccs_dmemd_r(i)\ #define gr_gpccs_dmemd_r(i)\
(nvgpu_safe_add_u32(0x0041a1c4U, nvgpu_safe_mult_u32((i), 8U))) (nvgpu_safe_add_u32(0x0041a1c4U, nvgpu_safe_mult_u32((i), 8U)))
#define gr_gpccs_ctxsw_mailbox_r(i)\ #define gr_gpccs_ctxsw_mailbox_r(i)\
(nvgpu_safe_add_u32(0x0041a800U, nvgpu_safe_mult_u32((i), 4U))) (nvgpu_safe_add_u32(0x0041a800U, nvgpu_safe_mult_u32((i), 4U)))
#define gr_gpccs_ctxsw_mailbox_value_f(v) (((v)&0xffffffffU) << 0U) #define gr_gpccs_ctxsw_mailbox_value_f(v) ((U32(v) & 0xffffffffU) << 0U)
#define gr_gpcs_setup_bundle_cb_base_r() (0x00418808U) #define gr_gpcs_setup_bundle_cb_base_r() (0x00418808U)
#define gr_gpcs_setup_bundle_cb_base_addr_39_8_s() (32U) #define gr_gpcs_setup_bundle_cb_base_addr_39_8_s() (32U)
#define gr_gpcs_setup_bundle_cb_base_addr_39_8_f(v) (((v)&0xffffffffU) << 0U) #define gr_gpcs_setup_bundle_cb_base_addr_39_8_f(v)\
((U32(v) & 0xffffffffU) << 0U)
#define gr_gpcs_setup_bundle_cb_base_addr_39_8_m() (U32(0xffffffffU) << 0U) #define gr_gpcs_setup_bundle_cb_base_addr_39_8_m() (U32(0xffffffffU) << 0U)
#define gr_gpcs_setup_bundle_cb_base_addr_39_8_v(r) (((r) >> 0U) & 0xffffffffU) #define gr_gpcs_setup_bundle_cb_base_addr_39_8_v(r) (((r) >> 0U) & 0xffffffffU)
#define gr_gpcs_setup_bundle_cb_base_addr_39_8_init_v() (0x00000000U) #define gr_gpcs_setup_bundle_cb_base_addr_39_8_init_v() (0x00000000U)
#define gr_gpcs_setup_bundle_cb_base_addr_39_8_init_f() (0x0U) #define gr_gpcs_setup_bundle_cb_base_addr_39_8_init_f() (0x0U)
#define gr_gpcs_setup_bundle_cb_size_r() (0x0041880cU) #define gr_gpcs_setup_bundle_cb_size_r() (0x0041880cU)
#define gr_gpcs_setup_bundle_cb_size_div_256b_s() (11U) #define gr_gpcs_setup_bundle_cb_size_div_256b_s() (11U)
#define gr_gpcs_setup_bundle_cb_size_div_256b_f(v) (((v)&0x7ffU) << 0U) #define gr_gpcs_setup_bundle_cb_size_div_256b_f(v) ((U32(v) & 0x7ffU) << 0U)
#define gr_gpcs_setup_bundle_cb_size_div_256b_m() (U32(0x7ffU) << 0U) #define gr_gpcs_setup_bundle_cb_size_div_256b_m() (U32(0x7ffU) << 0U)
#define gr_gpcs_setup_bundle_cb_size_div_256b_v(r) (((r) >> 0U) & 0x7ffU) #define gr_gpcs_setup_bundle_cb_size_div_256b_v(r) (((r) >> 0U) & 0x7ffU)
#define gr_gpcs_setup_bundle_cb_size_div_256b_init_v() (0x00000000U) #define gr_gpcs_setup_bundle_cb_size_div_256b_init_v() (0x00000000U)
@@ -707,7 +711,7 @@
#define gr_gpcs_setup_bundle_cb_size_div_256b__prod_v() (0x00000018U) #define gr_gpcs_setup_bundle_cb_size_div_256b__prod_v() (0x00000018U)
#define gr_gpcs_setup_bundle_cb_size_div_256b__prod_f() (0x18U) #define gr_gpcs_setup_bundle_cb_size_div_256b__prod_f() (0x18U)
#define gr_gpcs_setup_bundle_cb_size_valid_s() (1U) #define gr_gpcs_setup_bundle_cb_size_valid_s() (1U)
#define gr_gpcs_setup_bundle_cb_size_valid_f(v) (((v)&0x1U) << 31U) #define gr_gpcs_setup_bundle_cb_size_valid_f(v) ((U32(v) & 0x1U) << 31U)
#define gr_gpcs_setup_bundle_cb_size_valid_m() (U32(0x1U) << 31U) #define gr_gpcs_setup_bundle_cb_size_valid_m() (U32(0x1U) << 31U)
#define gr_gpcs_setup_bundle_cb_size_valid_v(r) (((r) >> 31U) & 0x1U) #define gr_gpcs_setup_bundle_cb_size_valid_v(r) (((r) >> 31U) & 0x1U)
#define gr_gpcs_setup_bundle_cb_size_valid_false_v() (0x00000000U) #define gr_gpcs_setup_bundle_cb_size_valid_false_v() (0x00000000U)
@@ -715,105 +719,123 @@
#define gr_gpcs_setup_bundle_cb_size_valid_true_v() (0x00000001U) #define gr_gpcs_setup_bundle_cb_size_valid_true_v() (0x00000001U)
#define gr_gpcs_setup_bundle_cb_size_valid_true_f() (0x80000000U) #define gr_gpcs_setup_bundle_cb_size_valid_true_f() (0x80000000U)
#define gr_gpcs_setup_attrib_cb_base_r() (0x00418810U) #define gr_gpcs_setup_attrib_cb_base_r() (0x00418810U)
#define gr_gpcs_setup_attrib_cb_base_addr_39_12_f(v) (((v)&0xfffffffU) << 0U) #define gr_gpcs_setup_attrib_cb_base_addr_39_12_f(v)\
((U32(v) & 0xfffffffU) << 0U)
#define gr_gpcs_setup_attrib_cb_base_addr_39_12_align_bits_v() (0x0000000cU) #define gr_gpcs_setup_attrib_cb_base_addr_39_12_align_bits_v() (0x0000000cU)
#define gr_gpcs_setup_attrib_cb_base_valid_true_f() (0x80000000U) #define gr_gpcs_setup_attrib_cb_base_valid_true_f() (0x80000000U)
#define gr_crstr_gpc_map0_r() (0x00418b08U) #define gr_crstr_gpc_map0_r() (0x00418b08U)
#define gr_crstr_gpc_map0_tile0_f(v) (((v)&0x7U) << 0U) #define gr_crstr_gpc_map0_tile0_f(v) ((U32(v) & 0x7U) << 0U)
#define gr_crstr_gpc_map0_tile1_f(v) (((v)&0x7U) << 5U) #define gr_crstr_gpc_map0_tile1_f(v) ((U32(v) & 0x7U) << 5U)
#define gr_crstr_gpc_map0_tile2_f(v) (((v)&0x7U) << 10U) #define gr_crstr_gpc_map0_tile2_f(v) ((U32(v) & 0x7U) << 10U)
#define gr_crstr_gpc_map0_tile3_f(v) (((v)&0x7U) << 15U) #define gr_crstr_gpc_map0_tile3_f(v) ((U32(v) & 0x7U) << 15U)
#define gr_crstr_gpc_map0_tile4_f(v) (((v)&0x7U) << 20U) #define gr_crstr_gpc_map0_tile4_f(v) ((U32(v) & 0x7U) << 20U)
#define gr_crstr_gpc_map0_tile5_f(v) (((v)&0x7U) << 25U) #define gr_crstr_gpc_map0_tile5_f(v) ((U32(v) & 0x7U) << 25U)
#define gr_crstr_gpc_map1_r() (0x00418b0cU) #define gr_crstr_gpc_map1_r() (0x00418b0cU)
#define gr_crstr_gpc_map1_tile6_f(v) (((v)&0x7U) << 0U) #define gr_crstr_gpc_map1_tile6_f(v) ((U32(v) & 0x7U) << 0U)
#define gr_crstr_gpc_map1_tile7_f(v) (((v)&0x7U) << 5U) #define gr_crstr_gpc_map1_tile7_f(v) ((U32(v) & 0x7U) << 5U)
#define gr_crstr_gpc_map1_tile8_f(v) (((v)&0x7U) << 10U) #define gr_crstr_gpc_map1_tile8_f(v) ((U32(v) & 0x7U) << 10U)
#define gr_crstr_gpc_map1_tile9_f(v) (((v)&0x7U) << 15U) #define gr_crstr_gpc_map1_tile9_f(v) ((U32(v) & 0x7U) << 15U)
#define gr_crstr_gpc_map1_tile10_f(v) (((v)&0x7U) << 20U) #define gr_crstr_gpc_map1_tile10_f(v) ((U32(v) & 0x7U) << 20U)
#define gr_crstr_gpc_map1_tile11_f(v) (((v)&0x7U) << 25U) #define gr_crstr_gpc_map1_tile11_f(v) ((U32(v) & 0x7U) << 25U)
#define gr_crstr_gpc_map2_r() (0x00418b10U) #define gr_crstr_gpc_map2_r() (0x00418b10U)
#define gr_crstr_gpc_map2_tile12_f(v) (((v)&0x7U) << 0U) #define gr_crstr_gpc_map2_tile12_f(v) ((U32(v) & 0x7U) << 0U)
#define gr_crstr_gpc_map2_tile13_f(v) (((v)&0x7U) << 5U) #define gr_crstr_gpc_map2_tile13_f(v) ((U32(v) & 0x7U) << 5U)
#define gr_crstr_gpc_map2_tile14_f(v) (((v)&0x7U) << 10U) #define gr_crstr_gpc_map2_tile14_f(v) ((U32(v) & 0x7U) << 10U)
#define gr_crstr_gpc_map2_tile15_f(v) (((v)&0x7U) << 15U) #define gr_crstr_gpc_map2_tile15_f(v) ((U32(v) & 0x7U) << 15U)
#define gr_crstr_gpc_map2_tile16_f(v) (((v)&0x7U) << 20U) #define gr_crstr_gpc_map2_tile16_f(v) ((U32(v) & 0x7U) << 20U)
#define gr_crstr_gpc_map2_tile17_f(v) (((v)&0x7U) << 25U) #define gr_crstr_gpc_map2_tile17_f(v) ((U32(v) & 0x7U) << 25U)
#define gr_crstr_gpc_map3_r() (0x00418b14U) #define gr_crstr_gpc_map3_r() (0x00418b14U)
#define gr_crstr_gpc_map3_tile18_f(v) (((v)&0x7U) << 0U) #define gr_crstr_gpc_map3_tile18_f(v) ((U32(v) & 0x7U) << 0U)
#define gr_crstr_gpc_map3_tile19_f(v) (((v)&0x7U) << 5U) #define gr_crstr_gpc_map3_tile19_f(v) ((U32(v) & 0x7U) << 5U)
#define gr_crstr_gpc_map3_tile20_f(v) (((v)&0x7U) << 10U) #define gr_crstr_gpc_map3_tile20_f(v) ((U32(v) & 0x7U) << 10U)
#define gr_crstr_gpc_map3_tile21_f(v) (((v)&0x7U) << 15U) #define gr_crstr_gpc_map3_tile21_f(v) ((U32(v) & 0x7U) << 15U)
#define gr_crstr_gpc_map3_tile22_f(v) (((v)&0x7U) << 20U) #define gr_crstr_gpc_map3_tile22_f(v) ((U32(v) & 0x7U) << 20U)
#define gr_crstr_gpc_map3_tile23_f(v) (((v)&0x7U) << 25U) #define gr_crstr_gpc_map3_tile23_f(v) ((U32(v) & 0x7U) << 25U)
#define gr_crstr_gpc_map4_r() (0x00418b18U) #define gr_crstr_gpc_map4_r() (0x00418b18U)
#define gr_crstr_gpc_map4_tile24_f(v) (((v)&0x7U) << 0U) #define gr_crstr_gpc_map4_tile24_f(v) ((U32(v) & 0x7U) << 0U)
#define gr_crstr_gpc_map4_tile25_f(v) (((v)&0x7U) << 5U) #define gr_crstr_gpc_map4_tile25_f(v) ((U32(v) & 0x7U) << 5U)
#define gr_crstr_gpc_map4_tile26_f(v) (((v)&0x7U) << 10U) #define gr_crstr_gpc_map4_tile26_f(v) ((U32(v) & 0x7U) << 10U)
#define gr_crstr_gpc_map4_tile27_f(v) (((v)&0x7U) << 15U) #define gr_crstr_gpc_map4_tile27_f(v) ((U32(v) & 0x7U) << 15U)
#define gr_crstr_gpc_map4_tile28_f(v) (((v)&0x7U) << 20U) #define gr_crstr_gpc_map4_tile28_f(v) ((U32(v) & 0x7U) << 20U)
#define gr_crstr_gpc_map4_tile29_f(v) (((v)&0x7U) << 25U) #define gr_crstr_gpc_map4_tile29_f(v) ((U32(v) & 0x7U) << 25U)
#define gr_crstr_gpc_map5_r() (0x00418b1cU) #define gr_crstr_gpc_map5_r() (0x00418b1cU)
#define gr_crstr_gpc_map5_tile30_f(v) (((v)&0x7U) << 0U) #define gr_crstr_gpc_map5_tile30_f(v) ((U32(v) & 0x7U) << 0U)
#define gr_crstr_gpc_map5_tile31_f(v) (((v)&0x7U) << 5U) #define gr_crstr_gpc_map5_tile31_f(v) ((U32(v) & 0x7U) << 5U)
#define gr_crstr_gpc_map5_tile32_f(v) (((v)&0x7U) << 10U) #define gr_crstr_gpc_map5_tile32_f(v) ((U32(v) & 0x7U) << 10U)
#define gr_crstr_gpc_map5_tile33_f(v) (((v)&0x7U) << 15U) #define gr_crstr_gpc_map5_tile33_f(v) ((U32(v) & 0x7U) << 15U)
#define gr_crstr_gpc_map5_tile34_f(v) (((v)&0x7U) << 20U) #define gr_crstr_gpc_map5_tile34_f(v) ((U32(v) & 0x7U) << 20U)
#define gr_crstr_gpc_map5_tile35_f(v) (((v)&0x7U) << 25U) #define gr_crstr_gpc_map5_tile35_f(v) ((U32(v) & 0x7U) << 25U)
#define gr_crstr_map_table_cfg_r() (0x00418bb8U) #define gr_crstr_map_table_cfg_r() (0x00418bb8U)
#define gr_crstr_map_table_cfg_row_offset_f(v) (((v)&0xffU) << 0U) #define gr_crstr_map_table_cfg_row_offset_f(v) ((U32(v) & 0xffU) << 0U)
#define gr_crstr_map_table_cfg_num_entries_f(v) (((v)&0xffU) << 8U) #define gr_crstr_map_table_cfg_num_entries_f(v) ((U32(v) & 0xffU) << 8U)
#define gr_gpcs_zcull_sm_in_gpc_number_map0_r() (0x00418980U) #define gr_gpcs_zcull_sm_in_gpc_number_map0_r() (0x00418980U)
#define gr_gpcs_zcull_sm_in_gpc_number_map0_tile_0_f(v) (((v)&0x7U) << 0U) #define gr_gpcs_zcull_sm_in_gpc_number_map0_tile_0_f(v) ((U32(v) & 0x7U) << 0U)
#define gr_gpcs_zcull_sm_in_gpc_number_map0_tile_1_f(v) (((v)&0x7U) << 4U) #define gr_gpcs_zcull_sm_in_gpc_number_map0_tile_1_f(v) ((U32(v) & 0x7U) << 4U)
#define gr_gpcs_zcull_sm_in_gpc_number_map0_tile_2_f(v) (((v)&0x7U) << 8U) #define gr_gpcs_zcull_sm_in_gpc_number_map0_tile_2_f(v) ((U32(v) & 0x7U) << 8U)
#define gr_gpcs_zcull_sm_in_gpc_number_map0_tile_3_f(v) (((v)&0x7U) << 12U) #define gr_gpcs_zcull_sm_in_gpc_number_map0_tile_3_f(v) ((U32(v) & 0x7U) << 12U)
#define gr_gpcs_zcull_sm_in_gpc_number_map0_tile_4_f(v) (((v)&0x7U) << 16U) #define gr_gpcs_zcull_sm_in_gpc_number_map0_tile_4_f(v) ((U32(v) & 0x7U) << 16U)
#define gr_gpcs_zcull_sm_in_gpc_number_map0_tile_5_f(v) (((v)&0x7U) << 20U) #define gr_gpcs_zcull_sm_in_gpc_number_map0_tile_5_f(v) ((U32(v) & 0x7U) << 20U)
#define gr_gpcs_zcull_sm_in_gpc_number_map0_tile_6_f(v) (((v)&0x7U) << 24U) #define gr_gpcs_zcull_sm_in_gpc_number_map0_tile_6_f(v) ((U32(v) & 0x7U) << 24U)
#define gr_gpcs_zcull_sm_in_gpc_number_map0_tile_7_f(v) (((v)&0x7U) << 28U) #define gr_gpcs_zcull_sm_in_gpc_number_map0_tile_7_f(v) ((U32(v) & 0x7U) << 28U)
#define gr_gpcs_zcull_sm_in_gpc_number_map1_r() (0x00418984U) #define gr_gpcs_zcull_sm_in_gpc_number_map1_r() (0x00418984U)
#define gr_gpcs_zcull_sm_in_gpc_number_map1_tile_8_f(v) (((v)&0x7U) << 0U) #define gr_gpcs_zcull_sm_in_gpc_number_map1_tile_8_f(v) ((U32(v) & 0x7U) << 0U)
#define gr_gpcs_zcull_sm_in_gpc_number_map1_tile_9_f(v) (((v)&0x7U) << 4U) #define gr_gpcs_zcull_sm_in_gpc_number_map1_tile_9_f(v) ((U32(v) & 0x7U) << 4U)
#define gr_gpcs_zcull_sm_in_gpc_number_map1_tile_10_f(v) (((v)&0x7U) << 8U) #define gr_gpcs_zcull_sm_in_gpc_number_map1_tile_10_f(v) ((U32(v) & 0x7U) << 8U)
#define gr_gpcs_zcull_sm_in_gpc_number_map1_tile_11_f(v) (((v)&0x7U) << 12U) #define gr_gpcs_zcull_sm_in_gpc_number_map1_tile_11_f(v)\
#define gr_gpcs_zcull_sm_in_gpc_number_map1_tile_12_f(v) (((v)&0x7U) << 16U) ((U32(v) & 0x7U) << 12U)
#define gr_gpcs_zcull_sm_in_gpc_number_map1_tile_13_f(v) (((v)&0x7U) << 20U) #define gr_gpcs_zcull_sm_in_gpc_number_map1_tile_12_f(v)\
#define gr_gpcs_zcull_sm_in_gpc_number_map1_tile_14_f(v) (((v)&0x7U) << 24U) ((U32(v) & 0x7U) << 16U)
#define gr_gpcs_zcull_sm_in_gpc_number_map1_tile_15_f(v) (((v)&0x7U) << 28U) #define gr_gpcs_zcull_sm_in_gpc_number_map1_tile_13_f(v)\
((U32(v) & 0x7U) << 20U)
#define gr_gpcs_zcull_sm_in_gpc_number_map1_tile_14_f(v)\
((U32(v) & 0x7U) << 24U)
#define gr_gpcs_zcull_sm_in_gpc_number_map1_tile_15_f(v)\
((U32(v) & 0x7U) << 28U)
#define gr_gpcs_zcull_sm_in_gpc_number_map2_r() (0x00418988U) #define gr_gpcs_zcull_sm_in_gpc_number_map2_r() (0x00418988U)
#define gr_gpcs_zcull_sm_in_gpc_number_map2_tile_16_f(v) (((v)&0x7U) << 0U) #define gr_gpcs_zcull_sm_in_gpc_number_map2_tile_16_f(v) ((U32(v) & 0x7U) << 0U)
#define gr_gpcs_zcull_sm_in_gpc_number_map2_tile_17_f(v) (((v)&0x7U) << 4U) #define gr_gpcs_zcull_sm_in_gpc_number_map2_tile_17_f(v) ((U32(v) & 0x7U) << 4U)
#define gr_gpcs_zcull_sm_in_gpc_number_map2_tile_18_f(v) (((v)&0x7U) << 8U) #define gr_gpcs_zcull_sm_in_gpc_number_map2_tile_18_f(v) ((U32(v) & 0x7U) << 8U)
#define gr_gpcs_zcull_sm_in_gpc_number_map2_tile_19_f(v) (((v)&0x7U) << 12U) #define gr_gpcs_zcull_sm_in_gpc_number_map2_tile_19_f(v)\
#define gr_gpcs_zcull_sm_in_gpc_number_map2_tile_20_f(v) (((v)&0x7U) << 16U) ((U32(v) & 0x7U) << 12U)
#define gr_gpcs_zcull_sm_in_gpc_number_map2_tile_21_f(v) (((v)&0x7U) << 20U) #define gr_gpcs_zcull_sm_in_gpc_number_map2_tile_20_f(v)\
#define gr_gpcs_zcull_sm_in_gpc_number_map2_tile_22_f(v) (((v)&0x7U) << 24U) ((U32(v) & 0x7U) << 16U)
#define gr_gpcs_zcull_sm_in_gpc_number_map2_tile_21_f(v)\
((U32(v) & 0x7U) << 20U)
#define gr_gpcs_zcull_sm_in_gpc_number_map2_tile_22_f(v)\
((U32(v) & 0x7U) << 24U)
#define gr_gpcs_zcull_sm_in_gpc_number_map2_tile_23_s() (3U) #define gr_gpcs_zcull_sm_in_gpc_number_map2_tile_23_s() (3U)
#define gr_gpcs_zcull_sm_in_gpc_number_map2_tile_23_f(v) (((v)&0x7U) << 28U) #define gr_gpcs_zcull_sm_in_gpc_number_map2_tile_23_f(v)\
((U32(v) & 0x7U) << 28U)
#define gr_gpcs_zcull_sm_in_gpc_number_map2_tile_23_m() (U32(0x7U) << 28U) #define gr_gpcs_zcull_sm_in_gpc_number_map2_tile_23_m() (U32(0x7U) << 28U)
#define gr_gpcs_zcull_sm_in_gpc_number_map2_tile_23_v(r) (((r) >> 28U) & 0x7U) #define gr_gpcs_zcull_sm_in_gpc_number_map2_tile_23_v(r) (((r) >> 28U) & 0x7U)
#define gr_gpcs_zcull_sm_in_gpc_number_map3_r() (0x0041898cU) #define gr_gpcs_zcull_sm_in_gpc_number_map3_r() (0x0041898cU)
#define gr_gpcs_zcull_sm_in_gpc_number_map3_tile_24_f(v) (((v)&0x7U) << 0U) #define gr_gpcs_zcull_sm_in_gpc_number_map3_tile_24_f(v) ((U32(v) & 0x7U) << 0U)
#define gr_gpcs_zcull_sm_in_gpc_number_map3_tile_25_f(v) (((v)&0x7U) << 4U) #define gr_gpcs_zcull_sm_in_gpc_number_map3_tile_25_f(v) ((U32(v) & 0x7U) << 4U)
#define gr_gpcs_zcull_sm_in_gpc_number_map3_tile_26_f(v) (((v)&0x7U) << 8U) #define gr_gpcs_zcull_sm_in_gpc_number_map3_tile_26_f(v) ((U32(v) & 0x7U) << 8U)
#define gr_gpcs_zcull_sm_in_gpc_number_map3_tile_27_f(v) (((v)&0x7U) << 12U) #define gr_gpcs_zcull_sm_in_gpc_number_map3_tile_27_f(v)\
#define gr_gpcs_zcull_sm_in_gpc_number_map3_tile_28_f(v) (((v)&0x7U) << 16U) ((U32(v) & 0x7U) << 12U)
#define gr_gpcs_zcull_sm_in_gpc_number_map3_tile_29_f(v) (((v)&0x7U) << 20U) #define gr_gpcs_zcull_sm_in_gpc_number_map3_tile_28_f(v)\
#define gr_gpcs_zcull_sm_in_gpc_number_map3_tile_30_f(v) (((v)&0x7U) << 24U) ((U32(v) & 0x7U) << 16U)
#define gr_gpcs_zcull_sm_in_gpc_number_map3_tile_31_f(v) (((v)&0x7U) << 28U) #define gr_gpcs_zcull_sm_in_gpc_number_map3_tile_29_f(v)\
((U32(v) & 0x7U) << 20U)
#define gr_gpcs_zcull_sm_in_gpc_number_map3_tile_30_f(v)\
((U32(v) & 0x7U) << 24U)
#define gr_gpcs_zcull_sm_in_gpc_number_map3_tile_31_f(v)\
((U32(v) & 0x7U) << 28U)
#define gr_gpcs_gpm_pd_cfg_r() (0x00418c6cU) #define gr_gpcs_gpm_pd_cfg_r() (0x00418c6cU)
#define gr_gpcs_gpm_pd_cfg_timeslice_mode_disable_f() (0x0U) #define gr_gpcs_gpm_pd_cfg_timeslice_mode_disable_f() (0x0U)
#define gr_gpcs_gpm_pd_cfg_timeslice_mode_enable_f() (0x1U) #define gr_gpcs_gpm_pd_cfg_timeslice_mode_enable_f() (0x1U)
#define gr_gpcs_gcc_pagepool_base_r() (0x00419004U) #define gr_gpcs_gcc_pagepool_base_r() (0x00419004U)
#define gr_gpcs_gcc_pagepool_base_addr_39_8_f(v) (((v)&0xffffffffU) << 0U) #define gr_gpcs_gcc_pagepool_base_addr_39_8_f(v) ((U32(v) & 0xffffffffU) << 0U)
#define gr_gpcs_gcc_pagepool_r() (0x00419008U) #define gr_gpcs_gcc_pagepool_r() (0x00419008U)
#define gr_gpcs_gcc_pagepool_total_pages_f(v) (((v)&0xffU) << 0U) #define gr_gpcs_gcc_pagepool_total_pages_f(v) ((U32(v) & 0xffU) << 0U)
#define gr_gpcs_tpcs_pe_vaf_r() (0x0041980cU) #define gr_gpcs_tpcs_pe_vaf_r() (0x0041980cU)
#define gr_gpcs_tpcs_pe_vaf_fast_mode_switch_true_f() (0x10U) #define gr_gpcs_tpcs_pe_vaf_fast_mode_switch_true_f() (0x10U)
#define gr_gpcs_tpcs_pe_pin_cb_global_base_addr_r() (0x00419848U) #define gr_gpcs_tpcs_pe_pin_cb_global_base_addr_r() (0x00419848U)
#define gr_gpcs_tpcs_pe_pin_cb_global_base_addr_v_f(v) (((v)&0xfffffffU) << 0U) #define gr_gpcs_tpcs_pe_pin_cb_global_base_addr_v_f(v)\
#define gr_gpcs_tpcs_pe_pin_cb_global_base_addr_valid_f(v) (((v)&0x1U) << 28U) ((U32(v) & 0xfffffffU) << 0U)
#define gr_gpcs_tpcs_pe_pin_cb_global_base_addr_valid_f(v)\
((U32(v) & 0x1U) << 28U)
#define gr_gpcs_tpcs_pe_pin_cb_global_base_addr_valid_true_f() (0x10000000U) #define gr_gpcs_tpcs_pe_pin_cb_global_base_addr_valid_true_f() (0x10000000U)
#define gr_gpcs_tpcs_mpc_vtg_debug_r() (0x00419c00U) #define gr_gpcs_tpcs_mpc_vtg_debug_r() (0x00419c00U)
#define gr_gpcs_tpcs_mpc_vtg_debug_timeslice_mode_disabled_f() (0x0U) #define gr_gpcs_tpcs_mpc_vtg_debug_timeslice_mode_disabled_f() (0x0U)
@@ -873,7 +895,7 @@
#define gr_gpc0_tpc0_tpccs_tpc_exception_en_sm_v(r) (((r) >> 1U) & 0x1U) #define gr_gpc0_tpc0_tpccs_tpc_exception_en_sm_v(r) (((r) >> 1U) & 0x1U)
#define gr_gpc0_tpc0_tpccs_tpc_exception_en_sm_enabled_f() (0x2U) #define gr_gpc0_tpc0_tpccs_tpc_exception_en_sm_enabled_f() (0x2U)
#define gr_gpcs_gpccs_gpc_exception_en_r() (0x0041ac94U) #define gr_gpcs_gpccs_gpc_exception_en_r() (0x0041ac94U)
#define gr_gpcs_gpccs_gpc_exception_en_tpc_f(v) (((v)&0xffU) << 16U) #define gr_gpcs_gpccs_gpc_exception_en_tpc_f(v) ((U32(v) & 0xffU) << 16U)
#define gr_gpc0_gpccs_gpc_exception_r() (0x00502c90U) #define gr_gpc0_gpccs_gpc_exception_r() (0x00502c90U)
#define gr_gpc0_gpccs_gpc_exception_gcc_v(r) (((r) >> 2U) & 0x1U) #define gr_gpc0_gpccs_gpc_exception_gcc_v(r) (((r) >> 2U) & 0x1U)
#define gr_gpc0_gpccs_gpc_exception_tpc_v(r) (((r) >> 16U) & 0xffU) #define gr_gpc0_gpccs_gpc_exception_tpc_v(r) (((r) >> 16U) & 0xffU)
@@ -945,11 +967,13 @@
#define gr_gpc0_tpc0_sm_halfctl_ctrl_r() (0x00504770U) #define gr_gpc0_tpc0_sm_halfctl_ctrl_r() (0x00504770U)
#define gr_gpcs_tpcs_sm_halfctl_ctrl_r() (0x00419f70U) #define gr_gpcs_tpcs_sm_halfctl_ctrl_r() (0x00419f70U)
#define gr_gpcs_tpcs_sm_halfctl_ctrl_sctl_read_quad_ctl_m() (U32(0x1U) << 4U) #define gr_gpcs_tpcs_sm_halfctl_ctrl_sctl_read_quad_ctl_m() (U32(0x1U) << 4U)
#define gr_gpcs_tpcs_sm_halfctl_ctrl_sctl_read_quad_ctl_f(v) (((v)&0x1U) << 4U) #define gr_gpcs_tpcs_sm_halfctl_ctrl_sctl_read_quad_ctl_f(v)\
((U32(v) & 0x1U) << 4U)
#define gr_gpc0_tpc0_sm_debug_sfe_control_r() (0x0050477cU) #define gr_gpc0_tpc0_sm_debug_sfe_control_r() (0x0050477cU)
#define gr_gpcs_tpcs_sm_debug_sfe_control_r() (0x00419f7cU) #define gr_gpcs_tpcs_sm_debug_sfe_control_r() (0x00419f7cU)
#define gr_gpcs_tpcs_sm_debug_sfe_control_read_half_ctl_m() (U32(0x1U) << 0U) #define gr_gpcs_tpcs_sm_debug_sfe_control_read_half_ctl_m() (U32(0x1U) << 0U)
#define gr_gpcs_tpcs_sm_debug_sfe_control_read_half_ctl_f(v) (((v)&0x1U) << 0U) #define gr_gpcs_tpcs_sm_debug_sfe_control_read_half_ctl_f(v)\
((U32(v) & 0x1U) << 0U)
#define gr_gpcs_tpcs_pes_vsc_vpc_r() (0x0041be08U) #define gr_gpcs_tpcs_pes_vsc_vpc_r() (0x0041be08U)
#define gr_gpcs_tpcs_pes_vsc_vpc_fast_mode_switch_true_f() (0x4U) #define gr_gpcs_tpcs_pes_vsc_vpc_fast_mode_switch_true_f() (0x4U)
#define gr_ppcs_wwdx_map_gpc_map0_r() (0x0041bf00U) #define gr_ppcs_wwdx_map_gpc_map0_r() (0x0041bf00U)
@@ -959,26 +983,34 @@
#define gr_ppcs_wwdx_map_gpc_map4_r() (0x0041bf10U) #define gr_ppcs_wwdx_map_gpc_map4_r() (0x0041bf10U)
#define gr_ppcs_wwdx_map_gpc_map5_r() (0x0041bf14U) #define gr_ppcs_wwdx_map_gpc_map5_r() (0x0041bf14U)
#define gr_ppcs_wwdx_map_table_cfg_r() (0x0041bfd0U) #define gr_ppcs_wwdx_map_table_cfg_r() (0x0041bfd0U)
#define gr_ppcs_wwdx_map_table_cfg_row_offset_f(v) (((v)&0xffU) << 0U) #define gr_ppcs_wwdx_map_table_cfg_row_offset_f(v) ((U32(v) & 0xffU) << 0U)
#define gr_ppcs_wwdx_map_table_cfg_num_entries_f(v) (((v)&0xffU) << 8U) #define gr_ppcs_wwdx_map_table_cfg_num_entries_f(v) ((U32(v) & 0xffU) << 8U)
#define gr_ppcs_wwdx_map_table_cfg_normalized_num_entries_f(v)\ #define gr_ppcs_wwdx_map_table_cfg_normalized_num_entries_f(v)\
(((v)&0x1fU) << 16U) ((U32(v) & 0x1fU) << 16U)
#define gr_ppcs_wwdx_map_table_cfg_normalized_shift_value_f(v)\ #define gr_ppcs_wwdx_map_table_cfg_normalized_shift_value_f(v)\
(((v)&0x7U) << 21U) ((U32(v) & 0x7U) << 21U)
#define gr_ppcs_wwdx_map_table_cfg_coeff5_mod_value_f(v) (((v)&0x1fU) << 24U) #define gr_ppcs_wwdx_map_table_cfg_coeff5_mod_value_f(v)\
((U32(v) & 0x1fU) << 24U)
#define gr_gpcs_ppcs_wwdx_sm_num_rcp_r() (0x0041bfd4U) #define gr_gpcs_ppcs_wwdx_sm_num_rcp_r() (0x0041bfd4U)
#define gr_gpcs_ppcs_wwdx_sm_num_rcp_conservative_f(v) (((v)&0xffffffU) << 0U) #define gr_gpcs_ppcs_wwdx_sm_num_rcp_conservative_f(v)\
((U32(v) & 0xffffffU) << 0U)
#define gr_ppcs_wwdx_map_table_cfg2_r() (0x0041bfe4U) #define gr_ppcs_wwdx_map_table_cfg2_r() (0x0041bfe4U)
#define gr_ppcs_wwdx_map_table_cfg2_coeff6_mod_value_f(v) (((v)&0x1fU) << 0U) #define gr_ppcs_wwdx_map_table_cfg2_coeff6_mod_value_f(v)\
#define gr_ppcs_wwdx_map_table_cfg2_coeff7_mod_value_f(v) (((v)&0x1fU) << 5U) ((U32(v) & 0x1fU) << 0U)
#define gr_ppcs_wwdx_map_table_cfg2_coeff8_mod_value_f(v) (((v)&0x1fU) << 10U) #define gr_ppcs_wwdx_map_table_cfg2_coeff7_mod_value_f(v)\
#define gr_ppcs_wwdx_map_table_cfg2_coeff9_mod_value_f(v) (((v)&0x1fU) << 15U) ((U32(v) & 0x1fU) << 5U)
#define gr_ppcs_wwdx_map_table_cfg2_coeff10_mod_value_f(v) (((v)&0x1fU) << 20U) #define gr_ppcs_wwdx_map_table_cfg2_coeff8_mod_value_f(v)\
#define gr_ppcs_wwdx_map_table_cfg2_coeff11_mod_value_f(v) (((v)&0x1fU) << 25U) ((U32(v) & 0x1fU) << 10U)
#define gr_ppcs_wwdx_map_table_cfg2_coeff9_mod_value_f(v)\
((U32(v) & 0x1fU) << 15U)
#define gr_ppcs_wwdx_map_table_cfg2_coeff10_mod_value_f(v)\
((U32(v) & 0x1fU) << 20U)
#define gr_ppcs_wwdx_map_table_cfg2_coeff11_mod_value_f(v)\
((U32(v) & 0x1fU) << 25U)
#define gr_bes_zrop_settings_r() (0x00408850U) #define gr_bes_zrop_settings_r() (0x00408850U)
#define gr_bes_zrop_settings_num_active_fbps_f(v) (((v)&0xfU) << 0U) #define gr_bes_zrop_settings_num_active_fbps_f(v) ((U32(v) & 0xfU) << 0U)
#define gr_bes_crop_settings_r() (0x00408958U) #define gr_bes_crop_settings_r() (0x00408958U)
#define gr_bes_crop_settings_num_active_fbps_f(v) (((v)&0xfU) << 0U) #define gr_bes_crop_settings_num_active_fbps_f(v) ((U32(v) & 0xfU) << 0U)
#define gr_zcull_bytes_per_aliquot_per_gpu_v() (0x00000020U) #define gr_zcull_bytes_per_aliquot_per_gpu_v() (0x00000020U)
#define gr_zcull_save_restore_header_bytes_per_gpc_v() (0x00000020U) #define gr_zcull_save_restore_header_bytes_per_gpc_v() (0x00000020U)
#define gr_zcull_save_restore_subregion_header_bytes_per_gpc_v() (0x000000c0U) #define gr_zcull_save_restore_subregion_header_bytes_per_gpc_v() (0x000000c0U)
@@ -1031,10 +1063,11 @@
#define gr_gpcs_tpcs_sm_sch_texlock_dot_t_unlock_m() (U32(0x1U) << 16U) #define gr_gpcs_tpcs_sm_sch_texlock_dot_t_unlock_m() (U32(0x1U) << 16U)
#define gr_gpcs_tpcs_sm_sch_texlock_dot_t_unlock_disable_f() (0x0U) #define gr_gpcs_tpcs_sm_sch_texlock_dot_t_unlock_disable_f() (0x0U)
#define gr_gpcs_tpcs_sm_sch_macro_sched_r() (0x00419eacU) #define gr_gpcs_tpcs_sm_sch_macro_sched_r() (0x00419eacU)
#define gr_gpcs_tpcs_sm_sch_macro_sched_lockboost_size_f(v) (((v)&0x1U) << 2U) #define gr_gpcs_tpcs_sm_sch_macro_sched_lockboost_size_f(v)\
((U32(v) & 0x1U) << 2U)
#define gr_gpcs_tpcs_sm_sch_macro_sched_lockboost_size_m() (U32(0x1U) << 2U) #define gr_gpcs_tpcs_sm_sch_macro_sched_lockboost_size_m() (U32(0x1U) << 2U)
#define gr_gpcs_tpcs_sm_dbgr_control0_r() (0x00419e10U) #define gr_gpcs_tpcs_sm_dbgr_control0_r() (0x00419e10U)
#define gr_gpcs_tpcs_sm_dbgr_control0_debugger_mode_f(v) (((v)&0x1U) << 0U) #define gr_gpcs_tpcs_sm_dbgr_control0_debugger_mode_f(v) ((U32(v) & 0x1U) << 0U)
#define gr_gpcs_tpcs_sm_dbgr_control0_debugger_mode_on_v() (0x00000001U) #define gr_gpcs_tpcs_sm_dbgr_control0_debugger_mode_on_v() (0x00000001U)
#define gr_gpcs_tpcs_sm_dbgr_control0_stop_trigger_m() (U32(0x1U) << 31U) #define gr_gpcs_tpcs_sm_dbgr_control0_stop_trigger_m() (U32(0x1U) << 31U)
#define gr_gpcs_tpcs_sm_dbgr_control0_stop_trigger_v(r) (((r) >> 31U) & 0x1U) #define gr_gpcs_tpcs_sm_dbgr_control0_stop_trigger_v(r) (((r) >> 31U) & 0x1U)

12
drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_ltc_gk20a.h
View File

@@ -78,9 +78,11 @@
#define ltc_ltcs_ltss_cbc_ctrl1_clear_active_f() (0x4U) #define ltc_ltcs_ltss_cbc_ctrl1_clear_active_f() (0x4U)
#define ltc_ltc0_lts0_cbc_ctrl1_r() (0x001410c8U) #define ltc_ltc0_lts0_cbc_ctrl1_r() (0x001410c8U)
#define ltc_ltcs_ltss_cbc_ctrl2_r() (0x0017e8ccU) #define ltc_ltcs_ltss_cbc_ctrl2_r() (0x0017e8ccU)
#define ltc_ltcs_ltss_cbc_ctrl2_clear_lower_bound_f(v) (((v)&0x1ffffU) << 0U) #define ltc_ltcs_ltss_cbc_ctrl2_clear_lower_bound_f(v)\
((U32(v) & 0x1ffffU) << 0U)
#define ltc_ltcs_ltss_cbc_ctrl3_r() (0x0017e8d0U) #define ltc_ltcs_ltss_cbc_ctrl3_r() (0x0017e8d0U)
#define ltc_ltcs_ltss_cbc_ctrl3_clear_upper_bound_f(v) (((v)&0x1ffffU) << 0U) #define ltc_ltcs_ltss_cbc_ctrl3_clear_upper_bound_f(v)\
((U32(v) & 0x1ffffU) << 0U)
#define ltc_ltcs_ltss_cbc_ctrl3_clear_upper_bound_init_v() (0x0001ffffU) #define ltc_ltcs_ltss_cbc_ctrl3_clear_upper_bound_init_v() (0x0001ffffU)
#define ltc_ltcs_ltss_cbc_base_r() (0x0017e8d4U) #define ltc_ltcs_ltss_cbc_base_r() (0x0017e8d4U)
#define ltc_ltcs_ltss_cbc_base_alignment_shift_v() (0x0000000bU) #define ltc_ltcs_ltss_cbc_base_alignment_shift_v() (0x0000000bU)
@@ -92,16 +94,16 @@
#define ltc_ltcs_ltss_cbc_param_slices_per_fbp_v(r) (((r) >> 28U) & 0xfU) #define ltc_ltcs_ltss_cbc_param_slices_per_fbp_v(r) (((r) >> 28U) & 0xfU)
#define ltc_ltcs_ltss_tstg_set_mgmt_r() (0x0017e91cU) #define ltc_ltcs_ltss_tstg_set_mgmt_r() (0x0017e91cU)
#define ltc_ltcs_ltss_tstg_set_mgmt_max_ways_evict_last_f(v)\ #define ltc_ltcs_ltss_tstg_set_mgmt_max_ways_evict_last_f(v)\
(((v)&0x1fU) << 16U) ((U32(v) & 0x1fU) << 16U)
#define ltc_ltcs_ltss_dstg_zbc_index_r() (0x0017ea44U) #define ltc_ltcs_ltss_dstg_zbc_index_r() (0x0017ea44U)
#define ltc_ltcs_ltss_dstg_zbc_index_address_f(v) (((v)&0xfU) << 0U) #define ltc_ltcs_ltss_dstg_zbc_index_address_f(v) ((U32(v) & 0xfU) << 0U)
#define ltc_ltcs_ltss_dstg_zbc_color_clear_value_r(i)\ #define ltc_ltcs_ltss_dstg_zbc_color_clear_value_r(i)\
(nvgpu_safe_add_u32(0x0017ea48U, nvgpu_safe_mult_u32((i), 4U))) (nvgpu_safe_add_u32(0x0017ea48U, nvgpu_safe_mult_u32((i), 4U)))
#define ltc_ltcs_ltss_dstg_zbc_color_clear_value__size_1_v() (0x00000004U) #define ltc_ltcs_ltss_dstg_zbc_color_clear_value__size_1_v() (0x00000004U)
#define ltc_ltcs_ltss_dstg_zbc_depth_clear_value_r() (0x0017ea58U) #define ltc_ltcs_ltss_dstg_zbc_depth_clear_value_r() (0x0017ea58U)
#define ltc_ltcs_ltss_dstg_zbc_depth_clear_value_field_s() (32U) #define ltc_ltcs_ltss_dstg_zbc_depth_clear_value_field_s() (32U)
#define ltc_ltcs_ltss_dstg_zbc_depth_clear_value_field_f(v)\ #define ltc_ltcs_ltss_dstg_zbc_depth_clear_value_field_f(v)\
(((v)&0xffffffffU) << 0U) ((U32(v) & 0xffffffffU) << 0U)
#define ltc_ltcs_ltss_dstg_zbc_depth_clear_value_field_m()\ #define ltc_ltcs_ltss_dstg_zbc_depth_clear_value_field_m()\
(U32(0xffffffffU) << 0U) (U32(0xffffffffU) << 0U)
#define ltc_ltcs_ltss_dstg_zbc_depth_clear_value_field_v(r)\ #define ltc_ltcs_ltss_dstg_zbc_depth_clear_value_field_v(r)\

8
drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_mc_gk20a.h
View File

@@ -79,7 +79,7 @@
#define mc_intr_en_0_inta_hardware_f() (0x1U) #define mc_intr_en_0_inta_hardware_f() (0x1U)
#define mc_intr_mask_1_r() (0x00000644U) #define mc_intr_mask_1_r() (0x00000644U)
#define mc_intr_mask_1_pmu_s() (1U) #define mc_intr_mask_1_pmu_s() (1U)
#define mc_intr_mask_1_pmu_f(v) (((v)&0x1U) << 24U) #define mc_intr_mask_1_pmu_f(v) ((U32(v) & 0x1U) << 24U)
#define mc_intr_mask_1_pmu_m() (U32(0x1U) << 24U) #define mc_intr_mask_1_pmu_m() (U32(0x1U) << 24U)
#define mc_intr_mask_1_pmu_v(r) (((r) >> 24U) & 0x1U) #define mc_intr_mask_1_pmu_v(r) (((r) >> 24U) & 0x1U)
#define mc_intr_mask_1_pmu_enabled_f() (0x1000000U) #define mc_intr_mask_1_pmu_enabled_f() (0x1000000U)
@@ -90,7 +90,7 @@
#define mc_enable_xbar_enabled_f() (0x4U) #define mc_enable_xbar_enabled_f() (0x4U)
#define mc_enable_l2_enabled_f() (0x8U) #define mc_enable_l2_enabled_f() (0x8U)
#define mc_enable_pmedia_s() (1U) #define mc_enable_pmedia_s() (1U)
#define mc_enable_pmedia_f(v) (((v)&0x1U) << 4U) #define mc_enable_pmedia_f(v) ((U32(v) & 0x1U) << 4U)
#define mc_enable_pmedia_m() (U32(0x1U) << 4U) #define mc_enable_pmedia_m() (U32(0x1U) << 4U)
#define mc_enable_pmedia_v(r) (((r) >> 4U) & 0x1U) #define mc_enable_pmedia_v(r) (((r) >> 4U) & 0x1U)
#define mc_enable_priv_ring_enabled_f() (0x20U) #define mc_enable_priv_ring_enabled_f() (0x20U)
@@ -108,12 +108,12 @@
#define mc_enable_hub_enabled_f() (0x20000000U) #define mc_enable_hub_enabled_f() (0x20000000U)
#define mc_enable_pb_r() (0x00000204U) #define mc_enable_pb_r() (0x00000204U)
#define mc_enable_pb_0_s() (1U) #define mc_enable_pb_0_s() (1U)
#define mc_enable_pb_0_f(v) (((v)&0x1U) << 0U) #define mc_enable_pb_0_f(v) ((U32(v) & 0x1U) << 0U)
#define mc_enable_pb_0_m() (U32(0x1U) << 0U) #define mc_enable_pb_0_m() (U32(0x1U) << 0U)
#define mc_enable_pb_0_v(r) (((r) >> 0U) & 0x1U) #define mc_enable_pb_0_v(r) (((r) >> 0U) & 0x1U)
#define mc_enable_pb_0_enabled_v() (0x00000001U) #define mc_enable_pb_0_enabled_v() (0x00000001U)
#define mc_enable_pb_sel_f(v, i)\ #define mc_enable_pb_sel_f(v, i)\
(((v) & 0x1) << (0U + i*1U)) ((U32(v) & 0x1U) << (0U + (i)*1U))
#define mc_elpg_enable_r() (0x0000020cU) #define mc_elpg_enable_r() (0x0000020cU)
#define mc_elpg_enable_xbar_enabled_f() (0x4U) #define mc_elpg_enable_xbar_enabled_f() (0x4U)
#define mc_elpg_enable_pfb_enabled_f() (0x100000U) #define mc_elpg_enable_pfb_enabled_f() (0x100000U)

20
drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_pbdma_gk20a.h
View File

@@ -61,17 +61,17 @@
#define pbdma_gp_entry1_r() (0x10000004U) #define pbdma_gp_entry1_r() (0x10000004U)
#define pbdma_gp_entry1_get_hi_v(r) (((r) >> 0U) & 0xffU) #define pbdma_gp_entry1_get_hi_v(r) (((r) >> 0U) & 0xffU)
#define pbdma_gp_entry1_length_f(v) (((v)&0x1fffffU) << 10U) #define pbdma_gp_entry1_length_f(v) ((U32(v) & 0x1fffffU) << 10U)
#define pbdma_gp_entry1_length_v(r) (((r) >> 10U) & 0x1fffffU) #define pbdma_gp_entry1_length_v(r) (((r) >> 10U) & 0x1fffffU)
#define pbdma_gp_base_r(i)\ #define pbdma_gp_base_r(i)\
(nvgpu_safe_add_u32(0x00040048U, nvgpu_safe_mult_u32((i), 8192U))) (nvgpu_safe_add_u32(0x00040048U, nvgpu_safe_mult_u32((i), 8192U)))
#define pbdma_gp_base__size_1_v() (0x00000001U) #define pbdma_gp_base__size_1_v() (0x00000001U)
#define pbdma_gp_base_offset_f(v) (((v)&0x1fffffffU) << 3U) #define pbdma_gp_base_offset_f(v) ((U32(v) & 0x1fffffffU) << 3U)
#define pbdma_gp_base_rsvd_s() (3U) #define pbdma_gp_base_rsvd_s() (3U)
#define pbdma_gp_base_hi_r(i)\ #define pbdma_gp_base_hi_r(i)\
(nvgpu_safe_add_u32(0x0004004cU, nvgpu_safe_mult_u32((i), 8192U))) (nvgpu_safe_add_u32(0x0004004cU, nvgpu_safe_mult_u32((i), 8192U)))
#define pbdma_gp_base_hi_offset_f(v) (((v)&0xffU) << 0U) #define pbdma_gp_base_hi_offset_f(v) ((U32(v) & 0xffU) << 0U)
#define pbdma_gp_base_hi_limit2_f(v) (((v)&0x1fU) << 16U) #define pbdma_gp_base_hi_limit2_f(v) ((U32(v) & 0x1fU) << 16U)
#define pbdma_gp_fetch_r(i)\ #define pbdma_gp_fetch_r(i)\
(nvgpu_safe_add_u32(0x00040050U, nvgpu_safe_mult_u32((i), 8192U))) (nvgpu_safe_add_u32(0x00040050U, nvgpu_safe_mult_u32((i), 8192U)))
#define pbdma_gp_get_r(i)\ #define pbdma_gp_get_r(i)\
@@ -117,12 +117,12 @@
(nvgpu_safe_add_u32(0x00040114U, nvgpu_safe_mult_u32((i), 8192U))) (nvgpu_safe_add_u32(0x00040114U, nvgpu_safe_mult_u32((i), 8192U)))
#define pbdma_subdevice_r(i)\ #define pbdma_subdevice_r(i)\
(nvgpu_safe_add_u32(0x00040094U, nvgpu_safe_mult_u32((i), 8192U))) (nvgpu_safe_add_u32(0x00040094U, nvgpu_safe_mult_u32((i), 8192U)))
#define pbdma_subdevice_id_f(v) (((v)&0xfffU) << 0U) #define pbdma_subdevice_id_f(v) ((U32(v) & 0xfffU) << 0U)
#define pbdma_subdevice_status_active_f() (0x10000000U) #define pbdma_subdevice_status_active_f() (0x10000000U)
#define pbdma_subdevice_channel_dma_enable_f() (0x20000000U) #define pbdma_subdevice_channel_dma_enable_f() (0x20000000U)
#define pbdma_method0_r(i)\ #define pbdma_method0_r(i)\
(nvgpu_safe_add_u32(0x000400c0U, nvgpu_safe_mult_u32((i), 8192U))) (nvgpu_safe_add_u32(0x000400c0U, nvgpu_safe_mult_u32((i), 8192U)))
#define pbdma_method0_addr_f(v) (((v)&0xfffU) << 2U) #define pbdma_method0_addr_f(v) ((U32(v) & 0xfffU) << 2U)
#define pbdma_method0_addr_v(r) (((r) >> 2U) & 0xfffU) #define pbdma_method0_addr_v(r) (((r) >> 2U) & 0xfffU)
#define pbdma_method0_subch_v(r) (((r) >> 16U) & 0x7U) #define pbdma_method0_subch_v(r) (((r) >> 16U) & 0x7U)
#define pbdma_method0_first_true_f() (0x400000U) #define pbdma_method0_first_true_f() (0x400000U)
@@ -142,10 +142,10 @@
(nvgpu_safe_add_u32(0x00040030U, nvgpu_safe_mult_u32((i), 8192U))) (nvgpu_safe_add_u32(0x00040030U, nvgpu_safe_mult_u32((i), 8192U)))
#define pbdma_acquire_retry_man_2_f() (0x2U) #define pbdma_acquire_retry_man_2_f() (0x2U)
#define pbdma_acquire_retry_exp_2_f() (0x100U) #define pbdma_acquire_retry_exp_2_f() (0x100U)
#define pbdma_acquire_timeout_exp_f(v) (((v)&0xfU) << 11U) #define pbdma_acquire_timeout_exp_f(v) ((U32(v) & 0xfU) << 11U)
#define pbdma_acquire_timeout_exp_max_v() (0x0000000fU) #define pbdma_acquire_timeout_exp_max_v() (0x0000000fU)
#define pbdma_acquire_timeout_exp_max_f() (0x7800U) #define pbdma_acquire_timeout_exp_max_f() (0x7800U)
#define pbdma_acquire_timeout_man_f(v) (((v)&0xffffU) << 15U) #define pbdma_acquire_timeout_man_f(v) ((U32(v) & 0xffffU) << 15U)
#define pbdma_acquire_timeout_man_max_v() (0x0000ffffU) #define pbdma_acquire_timeout_man_max_v() (0x0000ffffU)
#define pbdma_acquire_timeout_man_max_f() (0x7fff8000U) #define pbdma_acquire_timeout_man_max_f() (0x7fff8000U)
#define pbdma_acquire_timeout_en_enable_f() (0x80000000U) #define pbdma_acquire_timeout_en_enable_f() (0x80000000U)
@@ -163,10 +163,10 @@
#define pbdma_userd_target_vid_mem_f() (0x0U) #define pbdma_userd_target_vid_mem_f() (0x0U)
#define pbdma_userd_target_sys_mem_coh_f() (0x2U) #define pbdma_userd_target_sys_mem_coh_f() (0x2U)
#define pbdma_userd_target_sys_mem_ncoh_f() (0x3U) #define pbdma_userd_target_sys_mem_ncoh_f() (0x3U)
#define pbdma_userd_addr_f(v) (((v)&0x7fffffU) << 9U) #define pbdma_userd_addr_f(v) ((U32(v) & 0x7fffffU) << 9U)
#define pbdma_userd_hi_r(i)\ #define pbdma_userd_hi_r(i)\
(nvgpu_safe_add_u32(0x0004000cU, nvgpu_safe_mult_u32((i), 8192U))) (nvgpu_safe_add_u32(0x0004000cU, nvgpu_safe_mult_u32((i), 8192U)))
#define pbdma_userd_hi_addr_f(v) (((v)&0xffU) << 0U) #define pbdma_userd_hi_addr_f(v) ((U32(v) & 0xffU) << 0U)
#define pbdma_hce_ctrl_r(i)\ #define pbdma_hce_ctrl_r(i)\
(nvgpu_safe_add_u32(0x000400e4U, nvgpu_safe_mult_u32((i), 8192U))) (nvgpu_safe_add_u32(0x000400e4U, nvgpu_safe_mult_u32((i), 8192U)))
#define pbdma_hce_ctrl_hce_priv_mode_yes_f() (0x20U) #define pbdma_hce_ctrl_hce_priv_mode_yes_f() (0x20U)

20
drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_perf_gk20a.h
View File

@@ -63,13 +63,13 @@
#define perf_pmasys_control_membuf_status_v(r) (((r) >> 4U) & 0x1U) #define perf_pmasys_control_membuf_status_v(r) (((r) >> 4U) & 0x1U)
#define perf_pmasys_control_membuf_status_overflowed_v() (0x00000001U) #define perf_pmasys_control_membuf_status_overflowed_v() (0x00000001U)
#define perf_pmasys_control_membuf_status_overflowed_f() (0x10U) #define perf_pmasys_control_membuf_status_overflowed_f() (0x10U)
#define perf_pmasys_control_membuf_clear_status_f(v) (((v)&0x1U) << 5U) #define perf_pmasys_control_membuf_clear_status_f(v) ((U32(v) & 0x1U) << 5U)
#define perf_pmasys_control_membuf_clear_status_v(r) (((r) >> 5U) & 0x1U) #define perf_pmasys_control_membuf_clear_status_v(r) (((r) >> 5U) & 0x1U)
#define perf_pmasys_control_membuf_clear_status_doit_v() (0x00000001U) #define perf_pmasys_control_membuf_clear_status_doit_v() (0x00000001U)
#define perf_pmasys_control_membuf_clear_status_doit_f() (0x20U) #define perf_pmasys_control_membuf_clear_status_doit_f() (0x20U)
#define perf_pmasys_mem_block_r() (0x001b4070U) #define perf_pmasys_mem_block_r() (0x001b4070U)
#define perf_pmasys_mem_block_base_f(v) (((v)&0xfffffffU) << 0U) #define perf_pmasys_mem_block_base_f(v) ((U32(v) & 0xfffffffU) << 0U)
#define perf_pmasys_mem_block_target_f(v) (((v)&0x3U) << 28U) #define perf_pmasys_mem_block_target_f(v) ((U32(v) & 0x3U) << 28U)
#define perf_pmasys_mem_block_target_v(r) (((r) >> 28U) & 0x3U) #define perf_pmasys_mem_block_target_v(r) (((r) >> 28U) & 0x3U)
#define perf_pmasys_mem_block_target_lfb_v() (0x00000000U) #define perf_pmasys_mem_block_target_lfb_v() (0x00000000U)
#define perf_pmasys_mem_block_target_lfb_f() (0x0U) #define perf_pmasys_mem_block_target_lfb_f() (0x0U)
@@ -77,24 +77,24 @@
#define perf_pmasys_mem_block_target_sys_coh_f() (0x20000000U) #define perf_pmasys_mem_block_target_sys_coh_f() (0x20000000U)
#define perf_pmasys_mem_block_target_sys_ncoh_v() (0x00000003U) #define perf_pmasys_mem_block_target_sys_ncoh_v() (0x00000003U)
#define perf_pmasys_mem_block_target_sys_ncoh_f() (0x30000000U) #define perf_pmasys_mem_block_target_sys_ncoh_f() (0x30000000U)
#define perf_pmasys_mem_block_valid_f(v) (((v)&0x1U) << 31U) #define perf_pmasys_mem_block_valid_f(v) ((U32(v) & 0x1U) << 31U)
#define perf_pmasys_mem_block_valid_v(r) (((r) >> 31U) & 0x1U) #define perf_pmasys_mem_block_valid_v(r) (((r) >> 31U) & 0x1U)
#define perf_pmasys_mem_block_valid_true_v() (0x00000001U) #define perf_pmasys_mem_block_valid_true_v() (0x00000001U)
#define perf_pmasys_mem_block_valid_true_f() (0x80000000U) #define perf_pmasys_mem_block_valid_true_f() (0x80000000U)
#define perf_pmasys_mem_block_valid_false_v() (0x00000000U) #define perf_pmasys_mem_block_valid_false_v() (0x00000000U)
#define perf_pmasys_mem_block_valid_false_f() (0x0U) #define perf_pmasys_mem_block_valid_false_f() (0x0U)
#define perf_pmasys_outbase_r() (0x001b4074U) #define perf_pmasys_outbase_r() (0x001b4074U)
#define perf_pmasys_outbase_ptr_f(v) (((v)&0x7ffffffU) << 5U) #define perf_pmasys_outbase_ptr_f(v) ((U32(v) & 0x7ffffffU) << 5U)
#define perf_pmasys_outbaseupper_r() (0x001b4078U) #define perf_pmasys_outbaseupper_r() (0x001b4078U)
#define perf_pmasys_outbaseupper_ptr_f(v) (((v)&0xffU) << 0U) #define perf_pmasys_outbaseupper_ptr_f(v) ((U32(v) & 0xffU) << 0U)
#define perf_pmasys_outsize_r() (0x001b407cU) #define perf_pmasys_outsize_r() (0x001b407cU)
#define perf_pmasys_outsize_numbytes_f(v) (((v)&0x7ffffffU) << 5U) #define perf_pmasys_outsize_numbytes_f(v) ((U32(v) & 0x7ffffffU) << 5U)
#define perf_pmasys_mem_bytes_r() (0x001b4084U) #define perf_pmasys_mem_bytes_r() (0x001b4084U)
#define perf_pmasys_mem_bytes_numbytes_f(v) (((v)&0xfffffffU) << 4U) #define perf_pmasys_mem_bytes_numbytes_f(v) ((U32(v) & 0xfffffffU) << 4U)
#define perf_pmasys_mem_bump_r() (0x001b4088U) #define perf_pmasys_mem_bump_r() (0x001b4088U)
#define perf_pmasys_mem_bump_numbytes_f(v) (((v)&0xfffffffU) << 4U) #define perf_pmasys_mem_bump_numbytes_f(v) ((U32(v) & 0xfffffffU) << 4U)
#define perf_pmasys_enginestatus_r() (0x001b40a4U) #define perf_pmasys_enginestatus_r() (0x001b40a4U)
#define perf_pmasys_enginestatus_rbufempty_f(v) (((v)&0x1U) << 4U) #define perf_pmasys_enginestatus_rbufempty_f(v) ((U32(v) & 0x1U) << 4U)
#define perf_pmasys_enginestatus_rbufempty_empty_v() (0x00000001U) #define perf_pmasys_enginestatus_rbufempty_empty_v() (0x00000001U)
#define perf_pmasys_enginestatus_rbufempty_empty_f() (0x10U) #define perf_pmasys_enginestatus_rbufempty_empty_f() (0x10U)
#endif #endif

130
drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_pwr_gk20a.h
View File

@@ -68,44 +68,44 @@
#define pwr_falcon_irqstat_swgen0_true_f() (0x40U) #define pwr_falcon_irqstat_swgen0_true_f() (0x40U)
#define pwr_falcon_irqmode_r() (0x0010a00cU) #define pwr_falcon_irqmode_r() (0x0010a00cU)
#define pwr_falcon_irqmset_r() (0x0010a010U) #define pwr_falcon_irqmset_r() (0x0010a010U)
#define pwr_falcon_irqmset_gptmr_f(v) (((v)&0x1U) << 0U) #define pwr_falcon_irqmset_gptmr_f(v) ((U32(v) & 0x1U) << 0U)
#define pwr_falcon_irqmset_wdtmr_f(v) (((v)&0x1U) << 1U) #define pwr_falcon_irqmset_wdtmr_f(v) ((U32(v) & 0x1U) << 1U)
#define pwr_falcon_irqmset_mthd_f(v) (((v)&0x1U) << 2U) #define pwr_falcon_irqmset_mthd_f(v) ((U32(v) & 0x1U) << 2U)
#define pwr_falcon_irqmset_ctxsw_f(v) (((v)&0x1U) << 3U) #define pwr_falcon_irqmset_ctxsw_f(v) ((U32(v) & 0x1U) << 3U)
#define pwr_falcon_irqmset_halt_f(v) (((v)&0x1U) << 4U) #define pwr_falcon_irqmset_halt_f(v) ((U32(v) & 0x1U) << 4U)
#define pwr_falcon_irqmset_exterr_f(v) (((v)&0x1U) << 5U) #define pwr_falcon_irqmset_exterr_f(v) ((U32(v) & 0x1U) << 5U)
#define pwr_falcon_irqmset_swgen0_f(v) (((v)&0x1U) << 6U) #define pwr_falcon_irqmset_swgen0_f(v) ((U32(v) & 0x1U) << 6U)
#define pwr_falcon_irqmset_swgen1_f(v) (((v)&0x1U) << 7U) #define pwr_falcon_irqmset_swgen1_f(v) ((U32(v) & 0x1U) << 7U)
#define pwr_falcon_irqmclr_r() (0x0010a014U) #define pwr_falcon_irqmclr_r() (0x0010a014U)
#define pwr_falcon_irqmclr_gptmr_f(v) (((v)&0x1U) << 0U) #define pwr_falcon_irqmclr_gptmr_f(v) ((U32(v) & 0x1U) << 0U)
#define pwr_falcon_irqmclr_wdtmr_f(v) (((v)&0x1U) << 1U) #define pwr_falcon_irqmclr_wdtmr_f(v) ((U32(v) & 0x1U) << 1U)
#define pwr_falcon_irqmclr_mthd_f(v) (((v)&0x1U) << 2U) #define pwr_falcon_irqmclr_mthd_f(v) ((U32(v) & 0x1U) << 2U)
#define pwr_falcon_irqmclr_ctxsw_f(v) (((v)&0x1U) << 3U) #define pwr_falcon_irqmclr_ctxsw_f(v) ((U32(v) & 0x1U) << 3U)
#define pwr_falcon_irqmclr_halt_f(v) (((v)&0x1U) << 4U) #define pwr_falcon_irqmclr_halt_f(v) ((U32(v) & 0x1U) << 4U)
#define pwr_falcon_irqmclr_exterr_f(v) (((v)&0x1U) << 5U) #define pwr_falcon_irqmclr_exterr_f(v) ((U32(v) & 0x1U) << 5U)
#define pwr_falcon_irqmclr_swgen0_f(v) (((v)&0x1U) << 6U) #define pwr_falcon_irqmclr_swgen0_f(v) ((U32(v) & 0x1U) << 6U)
#define pwr_falcon_irqmclr_swgen1_f(v) (((v)&0x1U) << 7U) #define pwr_falcon_irqmclr_swgen1_f(v) ((U32(v) & 0x1U) << 7U)
#define pwr_falcon_irqmclr_ext_f(v) (((v)&0xffU) << 8U) #define pwr_falcon_irqmclr_ext_f(v) ((U32(v) & 0xffU) << 8U)
#define pwr_falcon_irqmask_r() (0x0010a018U) #define pwr_falcon_irqmask_r() (0x0010a018U)
#define pwr_falcon_irqdest_r() (0x0010a01cU) #define pwr_falcon_irqdest_r() (0x0010a01cU)
#define pwr_falcon_irqdest_host_gptmr_f(v) (((v)&0x1U) << 0U) #define pwr_falcon_irqdest_host_gptmr_f(v) ((U32(v) & 0x1U) << 0U)
#define pwr_falcon_irqdest_host_wdtmr_f(v) (((v)&0x1U) << 1U) #define pwr_falcon_irqdest_host_wdtmr_f(v) ((U32(v) & 0x1U) << 1U)
#define pwr_falcon_irqdest_host_mthd_f(v) (((v)&0x1U) << 2U) #define pwr_falcon_irqdest_host_mthd_f(v) ((U32(v) & 0x1U) << 2U)
#define pwr_falcon_irqdest_host_ctxsw_f(v) (((v)&0x1U) << 3U) #define pwr_falcon_irqdest_host_ctxsw_f(v) ((U32(v) & 0x1U) << 3U)
#define pwr_falcon_irqdest_host_halt_f(v) (((v)&0x1U) << 4U) #define pwr_falcon_irqdest_host_halt_f(v) ((U32(v) & 0x1U) << 4U)
#define pwr_falcon_irqdest_host_exterr_f(v) (((v)&0x1U) << 5U) #define pwr_falcon_irqdest_host_exterr_f(v) ((U32(v) & 0x1U) << 5U)
#define pwr_falcon_irqdest_host_swgen0_f(v) (((v)&0x1U) << 6U) #define pwr_falcon_irqdest_host_swgen0_f(v) ((U32(v) & 0x1U) << 6U)
#define pwr_falcon_irqdest_host_swgen1_f(v) (((v)&0x1U) << 7U) #define pwr_falcon_irqdest_host_swgen1_f(v) ((U32(v) & 0x1U) << 7U)
#define pwr_falcon_irqdest_host_ext_f(v) (((v)&0xffU) << 8U) #define pwr_falcon_irqdest_host_ext_f(v) ((U32(v) & 0xffU) << 8U)
#define pwr_falcon_irqdest_target_gptmr_f(v) (((v)&0x1U) << 16U) #define pwr_falcon_irqdest_target_gptmr_f(v) ((U32(v) & 0x1U) << 16U)
#define pwr_falcon_irqdest_target_wdtmr_f(v) (((v)&0x1U) << 17U) #define pwr_falcon_irqdest_target_wdtmr_f(v) ((U32(v) & 0x1U) << 17U)
#define pwr_falcon_irqdest_target_mthd_f(v) (((v)&0x1U) << 18U) #define pwr_falcon_irqdest_target_mthd_f(v) ((U32(v) & 0x1U) << 18U)
#define pwr_falcon_irqdest_target_ctxsw_f(v) (((v)&0x1U) << 19U) #define pwr_falcon_irqdest_target_ctxsw_f(v) ((U32(v) & 0x1U) << 19U)
#define pwr_falcon_irqdest_target_halt_f(v) (((v)&0x1U) << 20U) #define pwr_falcon_irqdest_target_halt_f(v) ((U32(v) & 0x1U) << 20U)
#define pwr_falcon_irqdest_target_exterr_f(v) (((v)&0x1U) << 21U) #define pwr_falcon_irqdest_target_exterr_f(v) ((U32(v) & 0x1U) << 21U)
#define pwr_falcon_irqdest_target_swgen0_f(v) (((v)&0x1U) << 22U) #define pwr_falcon_irqdest_target_swgen0_f(v) ((U32(v) & 0x1U) << 22U)
#define pwr_falcon_irqdest_target_swgen1_f(v) (((v)&0x1U) << 23U) #define pwr_falcon_irqdest_target_swgen1_f(v) ((U32(v) & 0x1U) << 23U)
#define pwr_falcon_irqdest_target_ext_f(v) (((v)&0xffU) << 24U) #define pwr_falcon_irqdest_target_ext_f(v) ((U32(v) & 0xffU) << 24U)
#define pwr_falcon_curctx_r() (0x0010a050U) #define pwr_falcon_curctx_r() (0x0010a050U)
#define pwr_falcon_nxtctx_r() (0x0010a054U) #define pwr_falcon_nxtctx_r() (0x0010a054U)
#define pwr_falcon_mailbox0_r() (0x0010a040U) #define pwr_falcon_mailbox0_r() (0x0010a040U)
@@ -118,21 +118,21 @@
#define pwr_falcon_os_r() (0x0010a080U) #define pwr_falcon_os_r() (0x0010a080U)
#define pwr_falcon_engctl_r() (0x0010a0a4U) #define pwr_falcon_engctl_r() (0x0010a0a4U)
#define pwr_falcon_cpuctl_r() (0x0010a100U) #define pwr_falcon_cpuctl_r() (0x0010a100U)
#define pwr_falcon_cpuctl_startcpu_f(v) (((v)&0x1U) << 1U) #define pwr_falcon_cpuctl_startcpu_f(v) ((U32(v) & 0x1U) << 1U)
#define pwr_falcon_cpuctl_halt_intr_f(v) (((v)&0x1U) << 4U) #define pwr_falcon_cpuctl_halt_intr_f(v) ((U32(v) & 0x1U) << 4U)
#define pwr_falcon_cpuctl_halt_intr_m() (U32(0x1U) << 4U) #define pwr_falcon_cpuctl_halt_intr_m() (U32(0x1U) << 4U)
#define pwr_falcon_cpuctl_halt_intr_v(r) (((r) >> 4U) & 0x1U) #define pwr_falcon_cpuctl_halt_intr_v(r) (((r) >> 4U) & 0x1U)
#define pwr_falcon_imemc_r(i)\ #define pwr_falcon_imemc_r(i)\
(nvgpu_safe_add_u32(0x0010a180U, nvgpu_safe_mult_u32((i), 16U))) (nvgpu_safe_add_u32(0x0010a180U, nvgpu_safe_mult_u32((i), 16U)))
#define pwr_falcon_imemc_offs_f(v) (((v)&0x3fU) << 2U) #define pwr_falcon_imemc_offs_f(v) ((U32(v) & 0x3fU) << 2U)
#define pwr_falcon_imemc_blk_f(v) (((v)&0xffU) << 8U) #define pwr_falcon_imemc_blk_f(v) ((U32(v) & 0xffU) << 8U)
#define pwr_falcon_imemc_aincw_f(v) (((v)&0x1U) << 24U) #define pwr_falcon_imemc_aincw_f(v) ((U32(v) & 0x1U) << 24U)
#define pwr_falcon_imemd_r(i)\ #define pwr_falcon_imemd_r(i)\
(nvgpu_safe_add_u32(0x0010a184U, nvgpu_safe_mult_u32((i), 16U))) (nvgpu_safe_add_u32(0x0010a184U, nvgpu_safe_mult_u32((i), 16U)))
#define pwr_falcon_imemt_r(i)\ #define pwr_falcon_imemt_r(i)\
(nvgpu_safe_add_u32(0x0010a188U, nvgpu_safe_mult_u32((i), 16U))) (nvgpu_safe_add_u32(0x0010a188U, nvgpu_safe_mult_u32((i), 16U)))
#define pwr_falcon_bootvec_r() (0x0010a104U) #define pwr_falcon_bootvec_r() (0x0010a104U)
#define pwr_falcon_bootvec_vec_f(v) (((v)&0xffffffffU) << 0U) #define pwr_falcon_bootvec_vec_f(v) ((U32(v) & 0xffffffffU) << 0U)
#define pwr_falcon_dmactl_r() (0x0010a10cU) #define pwr_falcon_dmactl_r() (0x0010a10cU)
#define pwr_falcon_dmactl_dmem_scrubbing_m() (U32(0x1U) << 1U) #define pwr_falcon_dmactl_dmem_scrubbing_m() (U32(0x1U) << 1U)
#define pwr_falcon_dmactl_imem_scrubbing_m() (U32(0x1U) << 2U) #define pwr_falcon_dmactl_imem_scrubbing_m() (U32(0x1U) << 2U)
@@ -142,10 +142,10 @@
#define pwr_falcon_dmatrfbase_r() (0x0010a110U) #define pwr_falcon_dmatrfbase_r() (0x0010a110U)
#define pwr_falcon_dmatrfmoffs_r() (0x0010a114U) #define pwr_falcon_dmatrfmoffs_r() (0x0010a114U)
#define pwr_falcon_dmatrfcmd_r() (0x0010a118U) #define pwr_falcon_dmatrfcmd_r() (0x0010a118U)
#define pwr_falcon_dmatrfcmd_imem_f(v) (((v)&0x1U) << 4U) #define pwr_falcon_dmatrfcmd_imem_f(v) ((U32(v) & 0x1U) << 4U)
#define pwr_falcon_dmatrfcmd_write_f(v) (((v)&0x1U) << 5U) #define pwr_falcon_dmatrfcmd_write_f(v) ((U32(v) & 0x1U) << 5U)
#define pwr_falcon_dmatrfcmd_size_f(v) (((v)&0x7U) << 8U) #define pwr_falcon_dmatrfcmd_size_f(v) ((U32(v) & 0x7U) << 8U)
#define pwr_falcon_dmatrfcmd_ctxdma_f(v) (((v)&0x7U) << 12U) #define pwr_falcon_dmatrfcmd_ctxdma_f(v) ((U32(v) & 0x7U) << 12U)
#define pwr_falcon_dmatrffboffs_r() (0x0010a11cU) #define pwr_falcon_dmatrffboffs_r() (0x0010a11cU)
#define pwr_falcon_exterraddr_r() (0x0010a168U) #define pwr_falcon_exterraddr_r() (0x0010a168U)
#define pwr_falcon_exterrstat_r() (0x0010a16cU) #define pwr_falcon_exterrstat_r() (0x0010a16cU)
@@ -154,59 +154,59 @@
#define pwr_falcon_exterrstat_valid_true_v() (0x00000001U) #define pwr_falcon_exterrstat_valid_true_v() (0x00000001U)
#define pwr_pmu_falcon_icd_cmd_r() (0x0010a200U) #define pwr_pmu_falcon_icd_cmd_r() (0x0010a200U)
#define pwr_pmu_falcon_icd_cmd_opc_s() (4U) #define pwr_pmu_falcon_icd_cmd_opc_s() (4U)
#define pwr_pmu_falcon_icd_cmd_opc_f(v) (((v)&0xfU) << 0U) #define pwr_pmu_falcon_icd_cmd_opc_f(v) ((U32(v) & 0xfU) << 0U)
#define pwr_pmu_falcon_icd_cmd_opc_m() (U32(0xfU) << 0U) #define pwr_pmu_falcon_icd_cmd_opc_m() (U32(0xfU) << 0U)
#define pwr_pmu_falcon_icd_cmd_opc_v(r) (((r) >> 0U) & 0xfU) #define pwr_pmu_falcon_icd_cmd_opc_v(r) (((r) >> 0U) & 0xfU)
#define pwr_pmu_falcon_icd_cmd_opc_rreg_f() (0x8U) #define pwr_pmu_falcon_icd_cmd_opc_rreg_f() (0x8U)
#define pwr_pmu_falcon_icd_cmd_opc_rstat_f() (0xeU) #define pwr_pmu_falcon_icd_cmd_opc_rstat_f() (0xeU)
#define pwr_pmu_falcon_icd_cmd_idx_f(v) (((v)&0x1fU) << 8U) #define pwr_pmu_falcon_icd_cmd_idx_f(v) ((U32(v) & 0x1fU) << 8U)
#define pwr_pmu_falcon_icd_rdata_r() (0x0010a20cU) #define pwr_pmu_falcon_icd_rdata_r() (0x0010a20cU)
#define pwr_falcon_dmemc_r(i)\ #define pwr_falcon_dmemc_r(i)\
(nvgpu_safe_add_u32(0x0010a1c0U, nvgpu_safe_mult_u32((i), 8U))) (nvgpu_safe_add_u32(0x0010a1c0U, nvgpu_safe_mult_u32((i), 8U)))
#define pwr_falcon_dmemc_offs_f(v) (((v)&0x3fU) << 2U) #define pwr_falcon_dmemc_offs_f(v) ((U32(v) & 0x3fU) << 2U)
#define pwr_falcon_dmemc_offs_m() (U32(0x3fU) << 2U) #define pwr_falcon_dmemc_offs_m() (U32(0x3fU) << 2U)
#define pwr_falcon_dmemc_blk_f(v) (((v)&0xffU) << 8U) #define pwr_falcon_dmemc_blk_f(v) ((U32(v) & 0xffU) << 8U)
#define pwr_falcon_dmemc_blk_m() (U32(0xffU) << 8U) #define pwr_falcon_dmemc_blk_m() (U32(0xffU) << 8U)
#define pwr_falcon_dmemc_aincw_f(v) (((v)&0x1U) << 24U) #define pwr_falcon_dmemc_aincw_f(v) ((U32(v) & 0x1U) << 24U)
#define pwr_falcon_dmemc_aincr_f(v) (((v)&0x1U) << 25U) #define pwr_falcon_dmemc_aincr_f(v) ((U32(v) & 0x1U) << 25U)
#define pwr_falcon_dmemd_r(i)\ #define pwr_falcon_dmemd_r(i)\
(nvgpu_safe_add_u32(0x0010a1c4U, nvgpu_safe_mult_u32((i), 8U))) (nvgpu_safe_add_u32(0x0010a1c4U, nvgpu_safe_mult_u32((i), 8U)))
#define pwr_pmu_new_instblk_r() (0x0010a480U) #define pwr_pmu_new_instblk_r() (0x0010a480U)
#define pwr_pmu_new_instblk_ptr_f(v) (((v)&0xfffffffU) << 0U) #define pwr_pmu_new_instblk_ptr_f(v) ((U32(v) & 0xfffffffU) << 0U)
#define pwr_pmu_new_instblk_target_fb_f() (0x0U) #define pwr_pmu_new_instblk_target_fb_f() (0x0U)
#define pwr_pmu_new_instblk_target_sys_coh_f() (0x20000000U) #define pwr_pmu_new_instblk_target_sys_coh_f() (0x20000000U)
#define pwr_pmu_new_instblk_target_sys_ncoh_f() (0x30000000U) #define pwr_pmu_new_instblk_target_sys_ncoh_f() (0x30000000U)
#define pwr_pmu_new_instblk_valid_f(v) (((v)&0x1U) << 30U) #define pwr_pmu_new_instblk_valid_f(v) ((U32(v) & 0x1U) << 30U)
#define pwr_pmu_mutex_id_r() (0x0010a488U) #define pwr_pmu_mutex_id_r() (0x0010a488U)
#define pwr_pmu_mutex_id_value_v(r) (((r) >> 0U) & 0xffU) #define pwr_pmu_mutex_id_value_v(r) (((r) >> 0U) & 0xffU)
#define pwr_pmu_mutex_id_value_init_v() (0x00000000U) #define pwr_pmu_mutex_id_value_init_v() (0x00000000U)
#define pwr_pmu_mutex_id_value_not_avail_v() (0x000000ffU) #define pwr_pmu_mutex_id_value_not_avail_v() (0x000000ffU)
#define pwr_pmu_mutex_id_release_r() (0x0010a48cU) #define pwr_pmu_mutex_id_release_r() (0x0010a48cU)
#define pwr_pmu_mutex_id_release_value_f(v) (((v)&0xffU) << 0U) #define pwr_pmu_mutex_id_release_value_f(v) ((U32(v) & 0xffU) << 0U)
#define pwr_pmu_mutex_id_release_value_m() (U32(0xffU) << 0U) #define pwr_pmu_mutex_id_release_value_m() (U32(0xffU) << 0U)
#define pwr_pmu_mutex_id_release_value_init_v() (0x00000000U) #define pwr_pmu_mutex_id_release_value_init_v() (0x00000000U)
#define pwr_pmu_mutex_id_release_value_init_f() (0x0U) #define pwr_pmu_mutex_id_release_value_init_f() (0x0U)
#define pwr_pmu_mutex_r(i)\ #define pwr_pmu_mutex_r(i)\
(nvgpu_safe_add_u32(0x0010a580U, nvgpu_safe_mult_u32((i), 4U))) (nvgpu_safe_add_u32(0x0010a580U, nvgpu_safe_mult_u32((i), 4U)))
#define pwr_pmu_mutex__size_1_v() (0x00000010U) #define pwr_pmu_mutex__size_1_v() (0x00000010U)
#define pwr_pmu_mutex_value_f(v) (((v)&0xffU) << 0U) #define pwr_pmu_mutex_value_f(v) ((U32(v) & 0xffU) << 0U)
#define pwr_pmu_mutex_value_v(r) (((r) >> 0U) & 0xffU) #define pwr_pmu_mutex_value_v(r) (((r) >> 0U) & 0xffU)
#define pwr_pmu_mutex_value_initial_lock_f() (0x0U) #define pwr_pmu_mutex_value_initial_lock_f() (0x0U)
#define pwr_pmu_queue_head_r(i)\ #define pwr_pmu_queue_head_r(i)\
(nvgpu_safe_add_u32(0x0010a4a0U, nvgpu_safe_mult_u32((i), 4U))) (nvgpu_safe_add_u32(0x0010a4a0U, nvgpu_safe_mult_u32((i), 4U)))
#define pwr_pmu_queue_head__size_1_v() (0x00000004U) #define pwr_pmu_queue_head__size_1_v() (0x00000004U)
#define pwr_pmu_queue_head_address_f(v) (((v)&0xffffffffU) << 0U) #define pwr_pmu_queue_head_address_f(v) ((U32(v) & 0xffffffffU) << 0U)
#define pwr_pmu_queue_head_address_v(r) (((r) >> 0U) & 0xffffffffU) #define pwr_pmu_queue_head_address_v(r) (((r) >> 0U) & 0xffffffffU)
#define pwr_pmu_queue_tail_r(i)\ #define pwr_pmu_queue_tail_r(i)\
(nvgpu_safe_add_u32(0x0010a4b0U, nvgpu_safe_mult_u32((i), 4U))) (nvgpu_safe_add_u32(0x0010a4b0U, nvgpu_safe_mult_u32((i), 4U)))
#define pwr_pmu_queue_tail__size_1_v() (0x00000004U) #define pwr_pmu_queue_tail__size_1_v() (0x00000004U)
#define pwr_pmu_queue_tail_address_f(v) (((v)&0xffffffffU) << 0U) #define pwr_pmu_queue_tail_address_f(v) ((U32(v) & 0xffffffffU) << 0U)
#define pwr_pmu_queue_tail_address_v(r) (((r) >> 0U) & 0xffffffffU) #define pwr_pmu_queue_tail_address_v(r) (((r) >> 0U) & 0xffffffffU)
#define pwr_pmu_msgq_head_r() (0x0010a4c8U) #define pwr_pmu_msgq_head_r() (0x0010a4c8U)
#define pwr_pmu_msgq_head_val_f(v) (((v)&0xffffffffU) << 0U) #define pwr_pmu_msgq_head_val_f(v) ((U32(v) & 0xffffffffU) << 0U)
#define pwr_pmu_msgq_head_val_v(r) (((r) >> 0U) & 0xffffffffU) #define pwr_pmu_msgq_head_val_v(r) (((r) >> 0U) & 0xffffffffU)
#define pwr_pmu_msgq_tail_r() (0x0010a4ccU) #define pwr_pmu_msgq_tail_r() (0x0010a4ccU)
#define pwr_pmu_msgq_tail_val_f(v) (((v)&0xffffffffU) << 0U) #define pwr_pmu_msgq_tail_val_f(v) ((U32(v) & 0xffffffffU) << 0U)
#define pwr_pmu_msgq_tail_val_v(r) (((r) >> 0U) & 0xffffffffU) #define pwr_pmu_msgq_tail_val_v(r) (((r) >> 0U) & 0xffffffffU)
#define pwr_pmu_idle_mask_r(i)\ #define pwr_pmu_idle_mask_r(i)\
(nvgpu_safe_add_u32(0x0010a504U, nvgpu_safe_mult_u32((i), 16U))) (nvgpu_safe_add_u32(0x0010a504U, nvgpu_safe_mult_u32((i), 16U)))
@@ -214,9 +214,9 @@
#define pwr_pmu_idle_mask_ce_2_enabled_f() (0x200000U) #define pwr_pmu_idle_mask_ce_2_enabled_f() (0x200000U)
#define pwr_pmu_idle_count_r(i)\ #define pwr_pmu_idle_count_r(i)\
(nvgpu_safe_add_u32(0x0010a508U, nvgpu_safe_mult_u32((i), 16U))) (nvgpu_safe_add_u32(0x0010a508U, nvgpu_safe_mult_u32((i), 16U)))
#define pwr_pmu_idle_count_value_f(v) (((v)&0x7fffffffU) << 0U) #define pwr_pmu_idle_count_value_f(v) ((U32(v) & 0x7fffffffU) << 0U)
#define pwr_pmu_idle_count_value_v(r) (((r) >> 0U) & 0x7fffffffU) #define pwr_pmu_idle_count_value_v(r) (((r) >> 0U) & 0x7fffffffU)
#define pwr_pmu_idle_count_reset_f(v) (((v)&0x1U) << 31U) #define pwr_pmu_idle_count_reset_f(v) ((U32(v) & 0x1U) << 31U)
#define pwr_pmu_idle_ctrl_r(i)\ #define pwr_pmu_idle_ctrl_r(i)\
(nvgpu_safe_add_u32(0x0010a50cU, nvgpu_safe_mult_u32((i), 16U))) (nvgpu_safe_add_u32(0x0010a50cU, nvgpu_safe_mult_u32((i), 16U)))
#define pwr_pmu_idle_ctrl_value_m() (U32(0x3U) << 0U) #define pwr_pmu_idle_ctrl_value_m() (U32(0x3U) << 0U)
@@ -226,13 +226,13 @@
#define pwr_pmu_idle_ctrl_filter_disabled_f() (0x0U) #define pwr_pmu_idle_ctrl_filter_disabled_f() (0x0U)
#define pwr_pmu_idle_threshold_r(i)\ #define pwr_pmu_idle_threshold_r(i)\
(nvgpu_safe_add_u32(0x0010a8a0U, nvgpu_safe_mult_u32((i), 4U))) (nvgpu_safe_add_u32(0x0010a8a0U, nvgpu_safe_mult_u32((i), 4U)))
#define pwr_pmu_idle_threshold_value_f(v) (((v)&0x7fffffffU) << 0U) #define pwr_pmu_idle_threshold_value_f(v) ((U32(v) & 0x7fffffffU) << 0U)
#define pwr_pmu_idle_intr_r() (0x0010a9e8U) #define pwr_pmu_idle_intr_r() (0x0010a9e8U)
#define pwr_pmu_idle_intr_en_f(v) (((v)&0x1U) << 0U) #define pwr_pmu_idle_intr_en_f(v) ((U32(v) & 0x1U) << 0U)
#define pwr_pmu_idle_intr_en_disabled_v() (0x00000000U) #define pwr_pmu_idle_intr_en_disabled_v() (0x00000000U)
#define pwr_pmu_idle_intr_en_enabled_v() (0x00000001U) #define pwr_pmu_idle_intr_en_enabled_v() (0x00000001U)
#define pwr_pmu_idle_intr_status_r() (0x0010a9ecU) #define pwr_pmu_idle_intr_status_r() (0x0010a9ecU)
#define pwr_pmu_idle_intr_status_intr_f(v) (((v)&0x1U) << 0U) #define pwr_pmu_idle_intr_status_intr_f(v) ((U32(v) & 0x1U) << 0U)
#define pwr_pmu_idle_intr_status_intr_m() (U32(0x1U) << 0U) #define pwr_pmu_idle_intr_status_intr_m() (U32(0x1U) << 0U)
#define pwr_pmu_idle_intr_status_intr_v(r) (((r) >> 0U) & 0x1U) #define pwr_pmu_idle_intr_status_intr_v(r) (((r) >> 0U) & 0x1U)
#define pwr_pmu_idle_mask_supp_r(i)\ #define pwr_pmu_idle_mask_supp_r(i)\
@@ -273,7 +273,7 @@
#define pwr_fbif_transcfg_target_coherent_sysmem_f() (0x1U) #define pwr_fbif_transcfg_target_coherent_sysmem_f() (0x1U)
#define pwr_fbif_transcfg_target_noncoherent_sysmem_f() (0x2U) #define pwr_fbif_transcfg_target_noncoherent_sysmem_f() (0x2U)
#define pwr_fbif_transcfg_mem_type_s() (1U) #define pwr_fbif_transcfg_mem_type_s() (1U)
#define pwr_fbif_transcfg_mem_type_f(v) (((v)&0x1U) << 2U) #define pwr_fbif_transcfg_mem_type_f(v) ((U32(v) & 0x1U) << 2U)
#define pwr_fbif_transcfg_mem_type_m() (U32(0x1U) << 2U) #define pwr_fbif_transcfg_mem_type_m() (U32(0x1U) << 2U)
#define pwr_fbif_transcfg_mem_type_v(r) (((r) >> 2U) & 0x1U) #define pwr_fbif_transcfg_mem_type_v(r) (((r) >> 2U) & 0x1U)
#define pwr_fbif_transcfg_mem_type_virtual_f() (0x0U) #define pwr_fbif_transcfg_mem_type_virtual_f() (0x0U)

28
drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_ram_gk20a.h
View File

@@ -61,20 +61,20 @@
#define ram_in_ramfc_s() (4096U) #define ram_in_ramfc_s() (4096U)
#define ram_in_ramfc_w() (0U) #define ram_in_ramfc_w() (0U)
#define ram_in_page_dir_base_target_f(v) (((v)&0x3U) << 0U) #define ram_in_page_dir_base_target_f(v) ((U32(v) & 0x3U) << 0U)
#define ram_in_page_dir_base_target_w() (128U) #define ram_in_page_dir_base_target_w() (128U)
#define ram_in_page_dir_base_target_vid_mem_f() (0x0U) #define ram_in_page_dir_base_target_vid_mem_f() (0x0U)
#define ram_in_page_dir_base_target_sys_mem_coh_f() (0x2U) #define ram_in_page_dir_base_target_sys_mem_coh_f() (0x2U)
#define ram_in_page_dir_base_target_sys_mem_ncoh_f() (0x3U) #define ram_in_page_dir_base_target_sys_mem_ncoh_f() (0x3U)
#define ram_in_page_dir_base_vol_w() (128U) #define ram_in_page_dir_base_vol_w() (128U)
#define ram_in_page_dir_base_vol_true_f() (0x4U) #define ram_in_page_dir_base_vol_true_f() (0x4U)
#define ram_in_page_dir_base_lo_f(v) (((v)&0xfffffU) << 12U) #define ram_in_page_dir_base_lo_f(v) ((U32(v) & 0xfffffU) << 12U)
#define ram_in_page_dir_base_lo_w() (128U) #define ram_in_page_dir_base_lo_w() (128U)
#define ram_in_page_dir_base_hi_f(v) (((v)&0xffU) << 0U) #define ram_in_page_dir_base_hi_f(v) ((U32(v) & 0xffU) << 0U)
#define ram_in_page_dir_base_hi_w() (129U) #define ram_in_page_dir_base_hi_w() (129U)
#define ram_in_adr_limit_lo_f(v) (((v)&0xfffffU) << 12U) #define ram_in_adr_limit_lo_f(v) ((U32(v) & 0xfffffU) << 12U)
#define ram_in_adr_limit_lo_w() (130U) #define ram_in_adr_limit_lo_w() (130U)
#define ram_in_adr_limit_hi_f(v) (((v)&0xffU) << 0U) #define ram_in_adr_limit_hi_f(v) ((U32(v) & 0xffU) << 0U)
#define ram_in_adr_limit_hi_w() (131U) #define ram_in_adr_limit_hi_w() (131U)
#define ram_in_engine_cs_w() (132U) #define ram_in_engine_cs_w() (132U)
#define ram_in_engine_cs_wfi_v() (0x00000000U) #define ram_in_engine_cs_wfi_v() (0x00000000U)
@@ -89,9 +89,9 @@
#define ram_in_gr_wfi_mode_physical_f() (0x0U) #define ram_in_gr_wfi_mode_physical_f() (0x0U)
#define ram_in_gr_wfi_mode_virtual_v() (0x00000001U) #define ram_in_gr_wfi_mode_virtual_v() (0x00000001U)
#define ram_in_gr_wfi_mode_virtual_f() (0x4U) #define ram_in_gr_wfi_mode_virtual_f() (0x4U)
#define ram_in_gr_wfi_ptr_lo_f(v) (((v)&0xfffffU) << 12U) #define ram_in_gr_wfi_ptr_lo_f(v) ((U32(v) & 0xfffffU) << 12U)
#define ram_in_gr_wfi_ptr_lo_w() (132U) #define ram_in_gr_wfi_ptr_lo_w() (132U)
#define ram_in_gr_wfi_ptr_hi_f(v) (((v)&0xffU) << 0U) #define ram_in_gr_wfi_ptr_hi_f(v) ((U32(v) & 0xffU) << 0U)
#define ram_in_gr_wfi_ptr_hi_w() (133U) #define ram_in_gr_wfi_ptr_hi_w() (133U)
#define ram_in_base_shift_v() (0x0000000cU) #define ram_in_base_shift_v() (0x0000000cU)
#define ram_in_alloc_size_v() (0x00001000U) #define ram_in_alloc_size_v() (0x00001000U)
@@ -126,7 +126,7 @@
#define ram_fc_target_w() (43U) #define ram_fc_target_w() (43U)
#define ram_fc_hce_ctrl_w() (57U) #define ram_fc_hce_ctrl_w() (57U)
#define ram_fc_chid_w() (58U) #define ram_fc_chid_w() (58U)
#define ram_fc_chid_id_f(v) (((v)&0xfffU) << 0U) #define ram_fc_chid_id_f(v) ((U32(v) & 0xfffU) << 0U)
#define ram_fc_chid_id_w() (0U) #define ram_fc_chid_id_w() (0U)
#define ram_fc_runlist_timeslice_w() (62U) #define ram_fc_runlist_timeslice_w() (62U)
#define ram_fc_pb_timeslice_w() (63U) #define ram_fc_pb_timeslice_w() (63U)
@@ -145,16 +145,16 @@
#define ram_userd_gp_top_level_get_w() (22U) #define ram_userd_gp_top_level_get_w() (22U)
#define ram_userd_gp_top_level_get_hi_w() (23U) #define ram_userd_gp_top_level_get_hi_w() (23U)
#define ram_rl_entry_size_v() (0x00000008U) #define ram_rl_entry_size_v() (0x00000008U)
#define ram_rl_entry_chid_f(v) (((v)&0xfffU) << 0U) #define ram_rl_entry_chid_f(v) ((U32(v) & 0xfffU) << 0U)
#define ram_rl_entry_id_f(v) (((v)&0xfffU) << 0U) #define ram_rl_entry_id_f(v) ((U32(v) & 0xfffU) << 0U)
#define ram_rl_entry_type_f(v) (((v)&0x1U) << 13U) #define ram_rl_entry_type_f(v) ((U32(v) & 0x1U) << 13U)
#define ram_rl_entry_type_chid_f() (0x0U) #define ram_rl_entry_type_chid_f() (0x0U)
#define ram_rl_entry_type_tsg_f() (0x2000U) #define ram_rl_entry_type_tsg_f() (0x2000U)
#define ram_rl_entry_timeslice_scale_f(v) (((v)&0xfU) << 14U) #define ram_rl_entry_timeslice_scale_f(v) ((U32(v) & 0xfU) << 14U)
#define ram_rl_entry_timeslice_scale_v(r) (((r) >> 14U) & 0xfU) #define ram_rl_entry_timeslice_scale_v(r) (((r) >> 14U) & 0xfU)
#define ram_rl_entry_timeslice_scale_3_f() (0xc000U) #define ram_rl_entry_timeslice_scale_3_f() (0xc000U)
#define ram_rl_entry_timeslice_timeout_f(v) (((v)&0xffU) << 18U) #define ram_rl_entry_timeslice_timeout_f(v) ((U32(v) & 0xffU) << 18U)
#define ram_rl_entry_timeslice_timeout_v(r) (((r) >> 18U) & 0xffU) #define ram_rl_entry_timeslice_timeout_v(r) (((r) >> 18U) & 0xffU)
#define ram_rl_entry_timeslice_timeout_128_f() (0x2000000U) #define ram_rl_entry_timeslice_timeout_128_f() (0x2000000U)
#define ram_rl_entry_tsg_length_f(v) (((v)&0x3fU) << 26U) #define ram_rl_entry_tsg_length_f(v) ((U32(v) & 0x3fU) << 26U)
#endif #endif

45
drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_therm_gk20a.h
View File

@@ -64,22 +64,22 @@
#define therm_use_a_ext_therm_1_enable_f() (0x2U) #define therm_use_a_ext_therm_1_enable_f() (0x2U)
#define therm_use_a_ext_therm_2_enable_f() (0x4U) #define therm_use_a_ext_therm_2_enable_f() (0x4U)
#define therm_evt_ext_therm_0_r() (0x00020700U) #define therm_evt_ext_therm_0_r() (0x00020700U)
#define therm_evt_ext_therm_0_slow_factor_f(v) (((v)&0x3fU) << 8U) #define therm_evt_ext_therm_0_slow_factor_f(v) ((U32(v) & 0x3fU) << 8U)
#define therm_evt_ext_therm_0_slow_factor_init_v() (0x00000000U) #define therm_evt_ext_therm_0_slow_factor_init_v() (0x00000000U)
#define therm_evt_ext_therm_0_priority_f(v) (((v)&0x1fU) << 24U) #define therm_evt_ext_therm_0_priority_f(v) ((U32(v) & 0x1fU) << 24U)
#define therm_evt_ext_therm_1_r() (0x00020704U) #define therm_evt_ext_therm_1_r() (0x00020704U)
#define therm_evt_ext_therm_1_slow_factor_f(v) (((v)&0x3fU) << 8U) #define therm_evt_ext_therm_1_slow_factor_f(v) ((U32(v) & 0x3fU) << 8U)
#define therm_evt_ext_therm_1_slow_factor_init_v() (0x00000000U) #define therm_evt_ext_therm_1_slow_factor_init_v() (0x00000000U)
#define therm_evt_ext_therm_1_priority_f(v) (((v)&0x1fU) << 24U) #define therm_evt_ext_therm_1_priority_f(v) ((U32(v) & 0x1fU) << 24U)
#define therm_evt_ext_therm_2_r() (0x00020708U) #define therm_evt_ext_therm_2_r() (0x00020708U)
#define therm_evt_ext_therm_2_slow_factor_f(v) (((v)&0x3fU) << 8U) #define therm_evt_ext_therm_2_slow_factor_f(v) ((U32(v) & 0x3fU) << 8U)
#define therm_evt_ext_therm_2_slow_factor_init_v() (0x00000000U) #define therm_evt_ext_therm_2_slow_factor_init_v() (0x00000000U)
#define therm_evt_ext_therm_2_priority_f(v) (((v)&0x1fU) << 24U) #define therm_evt_ext_therm_2_priority_f(v) ((U32(v) & 0x1fU) << 24U)
#define therm_weight_1_r() (0x00020024U) #define therm_weight_1_r() (0x00020024U)
#define therm_config1_r() (0x00020050U) #define therm_config1_r() (0x00020050U)
#define therm_config2_r() (0x00020130U) #define therm_config2_r() (0x00020130U)
#define therm_config2_slowdown_factor_extended_f(v) (((v)&0x1U) << 24U) #define therm_config2_slowdown_factor_extended_f(v) ((U32(v) & 0x1U) << 24U)
#define therm_config2_grad_enable_f(v) (((v)&0x1U) << 31U) #define therm_config2_grad_enable_f(v) ((U32(v) & 0x1U) << 31U)
#define therm_gate_ctrl_r(i)\ #define therm_gate_ctrl_r(i)\
(nvgpu_safe_add_u32(0x00020200U, nvgpu_safe_mult_u32((i), 4U))) (nvgpu_safe_add_u32(0x00020200U, nvgpu_safe_mult_u32((i), 4U)))
#define therm_gate_ctrl_eng_clk_m() (U32(0x3U) << 0U) #define therm_gate_ctrl_eng_clk_m() (U32(0x3U) << 0U)
@@ -93,13 +93,13 @@
#define therm_gate_ctrl_eng_pwr_auto_f() (0x10U) #define therm_gate_ctrl_eng_pwr_auto_f() (0x10U)
#define therm_gate_ctrl_eng_pwr_off_v() (0x00000002U) #define therm_gate_ctrl_eng_pwr_off_v() (0x00000002U)
#define therm_gate_ctrl_eng_pwr_off_f() (0x20U) #define therm_gate_ctrl_eng_pwr_off_f() (0x20U)
#define therm_gate_ctrl_eng_idle_filt_exp_f(v) (((v)&0x1fU) << 8U) #define therm_gate_ctrl_eng_idle_filt_exp_f(v) ((U32(v) & 0x1fU) << 8U)
#define therm_gate_ctrl_eng_idle_filt_exp_m() (U32(0x1fU) << 8U) #define therm_gate_ctrl_eng_idle_filt_exp_m() (U32(0x1fU) << 8U)
#define therm_gate_ctrl_eng_idle_filt_mant_f(v) (((v)&0x7U) << 13U) #define therm_gate_ctrl_eng_idle_filt_mant_f(v) ((U32(v) & 0x7U) << 13U)
#define therm_gate_ctrl_eng_idle_filt_mant_m() (U32(0x7U) << 13U) #define therm_gate_ctrl_eng_idle_filt_mant_m() (U32(0x7U) << 13U)
#define therm_gate_ctrl_eng_delay_before_f(v) (((v)&0xfU) << 16U) #define therm_gate_ctrl_eng_delay_before_f(v) ((U32(v) & 0xfU) << 16U)
#define therm_gate_ctrl_eng_delay_before_m() (U32(0xfU) << 16U) #define therm_gate_ctrl_eng_delay_before_m() (U32(0xfU) << 16U)
#define therm_gate_ctrl_eng_delay_after_f(v) (((v)&0xfU) << 20U) #define therm_gate_ctrl_eng_delay_after_f(v) ((U32(v) & 0xfU) << 20U)
#define therm_gate_ctrl_eng_delay_after_m() (U32(0xfU) << 20U) #define therm_gate_ctrl_eng_delay_after_m() (U32(0xfU) << 20U)
#define therm_fecs_idle_filter_r() (0x00020288U) #define therm_fecs_idle_filter_r() (0x00020288U)
#define therm_fecs_idle_filter_value_m() (U32(0xffffffffU) << 0U) #define therm_fecs_idle_filter_value_m() (U32(0xffffffffU) << 0U)
@@ -107,37 +107,40 @@
#define therm_hubmmu_idle_filter_value_m() (U32(0xffffffffU) << 0U) #define therm_hubmmu_idle_filter_value_m() (U32(0xffffffffU) << 0U)
#define therm_clk_slowdown_r(i)\ #define therm_clk_slowdown_r(i)\
(nvgpu_safe_add_u32(0x00020160U, nvgpu_safe_mult_u32((i), 4U))) (nvgpu_safe_add_u32(0x00020160U, nvgpu_safe_mult_u32((i), 4U)))
#define therm_clk_slowdown_idle_factor_f(v) (((v)&0x3fU) << 16U) #define therm_clk_slowdown_idle_factor_f(v) ((U32(v) & 0x3fU) << 16U)
#define therm_clk_slowdown_idle_factor_m() (U32(0x3fU) << 16U) #define therm_clk_slowdown_idle_factor_m() (U32(0x3fU) << 16U)
#define therm_clk_slowdown_idle_factor_v(r) (((r) >> 16U) & 0x3fU) #define therm_clk_slowdown_idle_factor_v(r) (((r) >> 16U) & 0x3fU)
#define therm_clk_slowdown_idle_factor_disabled_f() (0x0U) #define therm_clk_slowdown_idle_factor_disabled_f() (0x0U)
#define therm_grad_stepping_table_r(i)\ #define therm_grad_stepping_table_r(i)\
(nvgpu_safe_add_u32(0x000202c8U, nvgpu_safe_mult_u32((i), 4U))) (nvgpu_safe_add_u32(0x000202c8U, nvgpu_safe_mult_u32((i), 4U)))
#define therm_grad_stepping_table_slowdown_factor0_f(v) (((v)&0x3fU) << 0U) #define therm_grad_stepping_table_slowdown_factor0_f(v) ((U32(v) & 0x3fU) << 0U)
#define therm_grad_stepping_table_slowdown_factor0_m() (U32(0x3fU) << 0U) #define therm_grad_stepping_table_slowdown_factor0_m() (U32(0x3fU) << 0U)
#define therm_grad_stepping_table_slowdown_factor0_fpdiv_by1p5_f() (0x1U) #define therm_grad_stepping_table_slowdown_factor0_fpdiv_by1p5_f() (0x1U)
#define therm_grad_stepping_table_slowdown_factor0_fpdiv_by2_f() (0x2U) #define therm_grad_stepping_table_slowdown_factor0_fpdiv_by2_f() (0x2U)
#define therm_grad_stepping_table_slowdown_factor0_fpdiv_by4_f() (0x6U) #define therm_grad_stepping_table_slowdown_factor0_fpdiv_by4_f() (0x6U)
#define therm_grad_stepping_table_slowdown_factor0_fpdiv_by8_f() (0xeU) #define therm_grad_stepping_table_slowdown_factor0_fpdiv_by8_f() (0xeU)
#define therm_grad_stepping_table_slowdown_factor1_f(v) (((v)&0x3fU) << 6U) #define therm_grad_stepping_table_slowdown_factor1_f(v) ((U32(v) & 0x3fU) << 6U)
#define therm_grad_stepping_table_slowdown_factor1_m() (U32(0x3fU) << 6U) #define therm_grad_stepping_table_slowdown_factor1_m() (U32(0x3fU) << 6U)
#define therm_grad_stepping_table_slowdown_factor2_f(v) (((v)&0x3fU) << 12U) #define therm_grad_stepping_table_slowdown_factor2_f(v)\
((U32(v) & 0x3fU) << 12U)
#define therm_grad_stepping_table_slowdown_factor2_m() (U32(0x3fU) << 12U) #define therm_grad_stepping_table_slowdown_factor2_m() (U32(0x3fU) << 12U)
#define therm_grad_stepping_table_slowdown_factor3_f(v) (((v)&0x3fU) << 18U) #define therm_grad_stepping_table_slowdown_factor3_f(v)\
((U32(v) & 0x3fU) << 18U)
#define therm_grad_stepping_table_slowdown_factor3_m() (U32(0x3fU) << 18U) #define therm_grad_stepping_table_slowdown_factor3_m() (U32(0x3fU) << 18U)
#define therm_grad_stepping_table_slowdown_factor4_f(v) (((v)&0x3fU) << 24U) #define therm_grad_stepping_table_slowdown_factor4_f(v)\
((U32(v) & 0x3fU) << 24U)
#define therm_grad_stepping_table_slowdown_factor4_m() (U32(0x3fU) << 24U) #define therm_grad_stepping_table_slowdown_factor4_m() (U32(0x3fU) << 24U)
#define therm_grad_stepping0_r() (0x000202c0U) #define therm_grad_stepping0_r() (0x000202c0U)
#define therm_grad_stepping0_feature_s() (1U) #define therm_grad_stepping0_feature_s() (1U)
#define therm_grad_stepping0_feature_f(v) (((v)&0x1U) << 0U) #define therm_grad_stepping0_feature_f(v) ((U32(v) & 0x1U) << 0U)
#define therm_grad_stepping0_feature_m() (U32(0x1U) << 0U) #define therm_grad_stepping0_feature_m() (U32(0x1U) << 0U)
#define therm_grad_stepping0_feature_v(r) (((r) >> 0U) & 0x1U) #define therm_grad_stepping0_feature_v(r) (((r) >> 0U) & 0x1U)
#define therm_grad_stepping0_feature_enable_f() (0x1U) #define therm_grad_stepping0_feature_enable_f() (0x1U)
#define therm_grad_stepping1_r() (0x000202c4U) #define therm_grad_stepping1_r() (0x000202c4U)
#define therm_grad_stepping1_pdiv_duration_f(v) (((v)&0x1ffffU) << 0U) #define therm_grad_stepping1_pdiv_duration_f(v) ((U32(v) & 0x1ffffU) << 0U)
#define therm_clk_timing_r(i)\ #define therm_clk_timing_r(i)\
(nvgpu_safe_add_u32(0x000203c0U, nvgpu_safe_mult_u32((i), 4U))) (nvgpu_safe_add_u32(0x000203c0U, nvgpu_safe_mult_u32((i), 4U)))
#define therm_clk_timing_grad_slowdown_f(v) (((v)&0x1U) << 16U) #define therm_clk_timing_grad_slowdown_f(v) ((U32(v) & 0x1U) << 16U)
#define therm_clk_timing_grad_slowdown_m() (U32(0x1U) << 16U) #define therm_clk_timing_grad_slowdown_m() (U32(0x1U) << 16U)
#define therm_clk_timing_grad_slowdown_enabled_f() (0x10000U) #define therm_clk_timing_grad_slowdown_enabled_f() (0x10000U)
#endif #endif

4
drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_timer_gk20a.h
View File

@@ -60,10 +60,10 @@
#include <nvgpu/safe_ops.h> #include <nvgpu/safe_ops.h>
#define timer_pri_timeout_r() (0x00009080U) #define timer_pri_timeout_r() (0x00009080U)
#define timer_pri_timeout_period_f(v) (((v)&0xffffffU) << 0U) #define timer_pri_timeout_period_f(v) ((U32(v) & 0xffffffU) << 0U)
#define timer_pri_timeout_period_m() (U32(0xffffffU) << 0U) #define timer_pri_timeout_period_m() (U32(0xffffffU) << 0U)
#define timer_pri_timeout_period_v(r) (((r) >> 0U) & 0xffffffU) #define timer_pri_timeout_period_v(r) (((r) >> 0U) & 0xffffffU)
#define timer_pri_timeout_en_f(v) (((v)&0x1U) << 31U) #define timer_pri_timeout_en_f(v) ((U32(v) & 0x1U) << 31U)
#define timer_pri_timeout_en_m() (U32(0x1U) << 31U) #define timer_pri_timeout_en_m() (U32(0x1U) << 31U)
#define timer_pri_timeout_en_v(r) (((r) >> 31U) & 0x1U) #define timer_pri_timeout_en_v(r) (((r) >> 31U) & 0x1U)
#define timer_pri_timeout_en_en_enabled_f() (0x80000000U) #define timer_pri_timeout_en_en_enabled_f() (0x80000000U)

17
drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_trim_gk20a.h
View File

@@ -73,13 +73,13 @@
#define trim_sys_gpcpll_cfg_pll_lock_v(r) (((r) >> 17U) & 0x1U) #define trim_sys_gpcpll_cfg_pll_lock_v(r) (((r) >> 17U) & 0x1U)
#define trim_sys_gpcpll_cfg_pll_lock_true_f() (0x20000U) #define trim_sys_gpcpll_cfg_pll_lock_true_f() (0x20000U)
#define trim_sys_gpcpll_coeff_r() (0x00137004U) #define trim_sys_gpcpll_coeff_r() (0x00137004U)
#define trim_sys_gpcpll_coeff_mdiv_f(v) (((v)&0xffU) << 0U) #define trim_sys_gpcpll_coeff_mdiv_f(v) ((U32(v) & 0xffU) << 0U)
#define trim_sys_gpcpll_coeff_mdiv_m() (U32(0xffU) << 0U) #define trim_sys_gpcpll_coeff_mdiv_m() (U32(0xffU) << 0U)
#define trim_sys_gpcpll_coeff_mdiv_v(r) (((r) >> 0U) & 0xffU) #define trim_sys_gpcpll_coeff_mdiv_v(r) (((r) >> 0U) & 0xffU)
#define trim_sys_gpcpll_coeff_ndiv_f(v) (((v)&0xffU) << 8U) #define trim_sys_gpcpll_coeff_ndiv_f(v) ((U32(v) & 0xffU) << 8U)
#define trim_sys_gpcpll_coeff_ndiv_m() (U32(0xffU) << 8U) #define trim_sys_gpcpll_coeff_ndiv_m() (U32(0xffU) << 8U)
#define trim_sys_gpcpll_coeff_ndiv_v(r) (((r) >> 8U) & 0xffU) #define trim_sys_gpcpll_coeff_ndiv_v(r) (((r) >> 8U) & 0xffU)
#define trim_sys_gpcpll_coeff_pldiv_f(v) (((v)&0x3fU) << 16U) #define trim_sys_gpcpll_coeff_pldiv_f(v) ((U32(v) & 0x3fU) << 16U)
#define trim_sys_gpcpll_coeff_pldiv_m() (U32(0x3fU) << 16U) #define trim_sys_gpcpll_coeff_pldiv_m() (U32(0x3fU) << 16U)
#define trim_sys_gpcpll_coeff_pldiv_v(r) (((r) >> 16U) & 0x3fU) #define trim_sys_gpcpll_coeff_pldiv_v(r) (((r) >> 16U) & 0x3fU)
#define trim_sys_sel_vco_r() (0x00137100U) #define trim_sys_sel_vco_r() (0x00137100U)
@@ -90,12 +90,12 @@
#define trim_sys_sel_vco_gpc2clk_out_vco_f() (0x1U) #define trim_sys_sel_vco_gpc2clk_out_vco_f() (0x1U)
#define trim_sys_gpc2clk_out_r() (0x00137250U) #define trim_sys_gpc2clk_out_r() (0x00137250U)
#define trim_sys_gpc2clk_out_bypdiv_s() (6U) #define trim_sys_gpc2clk_out_bypdiv_s() (6U)
#define trim_sys_gpc2clk_out_bypdiv_f(v) (((v)&0x3fU) << 0U) #define trim_sys_gpc2clk_out_bypdiv_f(v) ((U32(v) & 0x3fU) << 0U)
#define trim_sys_gpc2clk_out_bypdiv_m() (U32(0x3fU) << 0U) #define trim_sys_gpc2clk_out_bypdiv_m() (U32(0x3fU) << 0U)
#define trim_sys_gpc2clk_out_bypdiv_v(r) (((r) >> 0U) & 0x3fU) #define trim_sys_gpc2clk_out_bypdiv_v(r) (((r) >> 0U) & 0x3fU)
#define trim_sys_gpc2clk_out_bypdiv_by31_f() (0x3cU) #define trim_sys_gpc2clk_out_bypdiv_by31_f() (0x3cU)
#define trim_sys_gpc2clk_out_vcodiv_s() (6U) #define trim_sys_gpc2clk_out_vcodiv_s() (6U)
#define trim_sys_gpc2clk_out_vcodiv_f(v) (((v)&0x3fU) << 8U) #define trim_sys_gpc2clk_out_vcodiv_f(v) ((U32(v) & 0x3fU) << 8U)
#define trim_sys_gpc2clk_out_vcodiv_m() (U32(0x3fU) << 8U) #define trim_sys_gpc2clk_out_vcodiv_m() (U32(0x3fU) << 8U)
#define trim_sys_gpc2clk_out_vcodiv_v(r) (((r) >> 8U) & 0x3fU) #define trim_sys_gpc2clk_out_vcodiv_v(r) (((r) >> 8U) & 0x3fU)
#define trim_sys_gpc2clk_out_vcodiv_by1_f() (0x0U) #define trim_sys_gpc2clk_out_vcodiv_by1_f() (0x0U)
@@ -103,7 +103,8 @@
#define trim_sys_gpc2clk_out_sdiv14_indiv4_mode_f() (0x80000000U) #define trim_sys_gpc2clk_out_sdiv14_indiv4_mode_f() (0x80000000U)
#define trim_gpc_clk_cntr_ncgpcclk_cfg_r(i)\ #define trim_gpc_clk_cntr_ncgpcclk_cfg_r(i)\
(nvgpu_safe_add_u32(0x00134124U, nvgpu_safe_mult_u32((i), 512U))) (nvgpu_safe_add_u32(0x00134124U, nvgpu_safe_mult_u32((i), 512U)))
#define trim_gpc_clk_cntr_ncgpcclk_cfg_noofipclks_f(v) (((v)&0x3fffU) << 0U) #define trim_gpc_clk_cntr_ncgpcclk_cfg_noofipclks_f(v)\
((U32(v) & 0x3fffU) << 0U)
#define trim_gpc_clk_cntr_ncgpcclk_cfg_write_en_asserted_f() (0x10000U) #define trim_gpc_clk_cntr_ncgpcclk_cfg_write_en_asserted_f() (0x10000U)
#define trim_gpc_clk_cntr_ncgpcclk_cfg_enable_asserted_f() (0x100000U) #define trim_gpc_clk_cntr_ncgpcclk_cfg_enable_asserted_f() (0x100000U)
#define trim_gpc_clk_cntr_ncgpcclk_cfg_reset_asserted_f() (0x1000000U) #define trim_gpc_clk_cntr_ncgpcclk_cfg_reset_asserted_f() (0x1000000U)
@@ -111,10 +112,10 @@
(nvgpu_safe_add_u32(0x00134128U, nvgpu_safe_mult_u32((i), 512U))) (nvgpu_safe_add_u32(0x00134128U, nvgpu_safe_mult_u32((i), 512U)))
#define trim_gpc_clk_cntr_ncgpcclk_cnt_value_v(r) (((r) >> 0U) & 0xfffffU) #define trim_gpc_clk_cntr_ncgpcclk_cnt_value_v(r) (((r) >> 0U) & 0xfffffU)
#define trim_sys_gpcpll_cfg2_r() (0x0013700cU) #define trim_sys_gpcpll_cfg2_r() (0x0013700cU)
#define trim_sys_gpcpll_cfg2_pll_stepa_f(v) (((v)&0xffU) << 24U) #define trim_sys_gpcpll_cfg2_pll_stepa_f(v) ((U32(v) & 0xffU) << 24U)
#define trim_sys_gpcpll_cfg2_pll_stepa_m() (U32(0xffU) << 24U) #define trim_sys_gpcpll_cfg2_pll_stepa_m() (U32(0xffU) << 24U)
#define trim_sys_gpcpll_cfg3_r() (0x00137018U) #define trim_sys_gpcpll_cfg3_r() (0x00137018U)
#define trim_sys_gpcpll_cfg3_pll_stepb_f(v) (((v)&0xffU) << 16U) #define trim_sys_gpcpll_cfg3_pll_stepb_f(v) ((U32(v) & 0xffU) << 16U)
#define trim_sys_gpcpll_cfg3_pll_stepb_m() (U32(0xffU) << 16U) #define trim_sys_gpcpll_cfg3_pll_stepb_m() (U32(0xffU) << 16U)
#define trim_sys_gpcpll_ndiv_slowdown_r() (0x0013701cU) #define trim_sys_gpcpll_ndiv_slowdown_r() (0x0013701cU)
#define trim_sys_gpcpll_ndiv_slowdown_slowdown_using_pll_m() (U32(0x1U) << 22U) #define trim_sys_gpcpll_ndiv_slowdown_slowdown_using_pll_m() (U32(0x1U) << 22U)

6
drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_bus_gm20b.h
View File

@@ -60,19 +60,19 @@
#include <nvgpu/safe_ops.h> #include <nvgpu/safe_ops.h>
#define bus_bar0_window_r() (0x00001700U) #define bus_bar0_window_r() (0x00001700U)
#define bus_bar0_window_base_f(v) (((v)&0xffffffU) << 0U) #define bus_bar0_window_base_f(v) ((U32(v) & 0xffffffU) << 0U)
#define bus_bar0_window_target_vid_mem_f() (0x0U) #define bus_bar0_window_target_vid_mem_f() (0x0U)
#define bus_bar0_window_target_sys_mem_coherent_f() (0x2000000U) #define bus_bar0_window_target_sys_mem_coherent_f() (0x2000000U)
#define bus_bar0_window_target_sys_mem_noncoherent_f() (0x3000000U) #define bus_bar0_window_target_sys_mem_noncoherent_f() (0x3000000U)
#define bus_bar0_window_target_bar0_window_base_shift_v() (0x00000010U) #define bus_bar0_window_target_bar0_window_base_shift_v() (0x00000010U)
#define bus_bar1_block_r() (0x00001704U) #define bus_bar1_block_r() (0x00001704U)
#define bus_bar1_block_ptr_f(v) (((v)&0xfffffffU) << 0U) #define bus_bar1_block_ptr_f(v) ((U32(v) & 0xfffffffU) << 0U)
#define bus_bar1_block_target_vid_mem_f() (0x0U) #define bus_bar1_block_target_vid_mem_f() (0x0U)
#define bus_bar1_block_target_sys_mem_coh_f() (0x20000000U) #define bus_bar1_block_target_sys_mem_coh_f() (0x20000000U)
#define bus_bar1_block_target_sys_mem_ncoh_f() (0x30000000U) #define bus_bar1_block_target_sys_mem_ncoh_f() (0x30000000U)
#define bus_bar1_block_mode_virtual_f() (0x80000000U) #define bus_bar1_block_mode_virtual_f() (0x80000000U)
#define bus_bar2_block_r() (0x00001714U) #define bus_bar2_block_r() (0x00001714U)
#define bus_bar2_block_ptr_f(v) (((v)&0xfffffffU) << 0U) #define bus_bar2_block_ptr_f(v) ((U32(v) & 0xfffffffU) << 0U)
#define bus_bar2_block_target_vid_mem_f() (0x0U) #define bus_bar2_block_target_vid_mem_f() (0x0U)
#define bus_bar2_block_target_sys_mem_coh_f() (0x20000000U) #define bus_bar2_block_target_sys_mem_coh_f() (0x20000000U)
#define bus_bar2_block_target_sys_mem_ncoh_f() (0x30000000U) #define bus_bar2_block_target_sys_mem_ncoh_f() (0x30000000U)

4
drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_ccsr_gm20b.h
View File

@@ -62,7 +62,7 @@
#define ccsr_channel_inst_r(i)\ #define ccsr_channel_inst_r(i)\
(nvgpu_safe_add_u32(0x00800000U, nvgpu_safe_mult_u32((i), 8U))) (nvgpu_safe_add_u32(0x00800000U, nvgpu_safe_mult_u32((i), 8U)))
#define ccsr_channel_inst__size_1_v() (0x00000200U) #define ccsr_channel_inst__size_1_v() (0x00000200U)
#define ccsr_channel_inst_ptr_f(v) (((v)&0xfffffffU) << 0U) #define ccsr_channel_inst_ptr_f(v) ((U32(v) & 0xfffffffU) << 0U)
#define ccsr_channel_inst_target_vid_mem_f() (0x0U) #define ccsr_channel_inst_target_vid_mem_f() (0x0U)
#define ccsr_channel_inst_target_sys_mem_coh_f() (0x20000000U) #define ccsr_channel_inst_target_sys_mem_coh_f() (0x20000000U)
#define ccsr_channel_inst_target_sys_mem_ncoh_f() (0x30000000U) #define ccsr_channel_inst_target_sys_mem_ncoh_f() (0x30000000U)
@@ -73,7 +73,7 @@
#define ccsr_channel__size_1_v() (0x00000200U) #define ccsr_channel__size_1_v() (0x00000200U)
#define ccsr_channel_enable_v(r) (((r) >> 0U) & 0x1U) #define ccsr_channel_enable_v(r) (((r) >> 0U) & 0x1U)
#define ccsr_channel_enable_in_use_v() (0x00000001U) #define ccsr_channel_enable_in_use_v() (0x00000001U)
#define ccsr_channel_enable_set_f(v) (((v)&0x1U) << 10U) #define ccsr_channel_enable_set_f(v) ((U32(v) & 0x1U) << 10U)
#define ccsr_channel_enable_set_true_f() (0x400U) #define ccsr_channel_enable_set_true_f() (0x400U)
#define ccsr_channel_enable_clr_true_f() (0x800U) #define ccsr_channel_enable_clr_true_f() (0x800U)
#define ccsr_channel_status_v(r) (((r) >> 24U) & 0xfU) #define ccsr_channel_status_v(r) (((r) >> 24U) & 0xfU)

17
drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_ctxsw_prog_gm20b.h
View File

@@ -80,7 +80,7 @@
#define ctxsw_prog_main_image_pm_smpc_mode_m() (U32(0x7U) << 3U) #define ctxsw_prog_main_image_pm_smpc_mode_m() (U32(0x7U) << 3U)
#define ctxsw_prog_main_image_pm_smpc_mode_ctxsw_f() (0x8U) #define ctxsw_prog_main_image_pm_smpc_mode_ctxsw_f() (0x8U)
#define ctxsw_prog_main_image_pm_smpc_mode_no_ctxsw_f() (0x0U) #define ctxsw_prog_main_image_pm_smpc_mode_no_ctxsw_f() (0x0U)
#define ctxsw_prog_main_image_pm_pc_sampling_f(v) (((v)&0x1U) << 6U) #define ctxsw_prog_main_image_pm_pc_sampling_f(v) ((U32(v) & 0x1U) << 6U)
#define ctxsw_prog_main_image_pm_pc_sampling_m() (U32(0x1U) << 6U) #define ctxsw_prog_main_image_pm_pc_sampling_m() (U32(0x1U) << 6U)
#define ctxsw_prog_main_image_pm_ptr_o() (0x0000002cU) #define ctxsw_prog_main_image_pm_ptr_o() (0x0000002cU)
#define ctxsw_prog_main_image_num_save_ops_o() (0x000000f4U) #define ctxsw_prog_main_image_num_save_ops_o() (0x000000f4U)
@@ -107,7 +107,7 @@
#define ctxsw_prog_main_image_priv_access_map_config_o() (0x000000a0U) #define ctxsw_prog_main_image_priv_access_map_config_o() (0x000000a0U)
#define ctxsw_prog_main_image_priv_access_map_config_mode_s() (2U) #define ctxsw_prog_main_image_priv_access_map_config_mode_s() (2U)
#define ctxsw_prog_main_image_priv_access_map_config_mode_f(v)\ #define ctxsw_prog_main_image_priv_access_map_config_mode_f(v)\
(((v)&0x3U) << 0U) ((U32(v) & 0x3U) << 0U)
#define ctxsw_prog_main_image_priv_access_map_config_mode_m() (U32(0x3U) << 0U) #define ctxsw_prog_main_image_priv_access_map_config_mode_m() (U32(0x3U) << 0U)
#define ctxsw_prog_main_image_priv_access_map_config_mode_v(r)\ #define ctxsw_prog_main_image_priv_access_map_config_mode_v(r)\
(((r) >> 0U) & 0x3U) (((r) >> 0U) & 0x3U)
@@ -120,7 +120,7 @@
#define ctxsw_prog_main_image_misc_options_verif_features_disabled_f() (0x0U) #define ctxsw_prog_main_image_misc_options_verif_features_disabled_f() (0x0U)
#define ctxsw_prog_main_image_context_timestamp_buffer_control_o() (0x000000acU) #define ctxsw_prog_main_image_context_timestamp_buffer_control_o() (0x000000acU)
#define ctxsw_prog_main_image_context_timestamp_buffer_control_num_records_f(v)\ #define ctxsw_prog_main_image_context_timestamp_buffer_control_num_records_f(v)\
(((v)&0xffffU) << 0U) ((U32(v) & 0xffffU) << 0U)
#define ctxsw_prog_main_image_context_timestamp_buffer_ptr_hi_o() (0x000000b0U) #define ctxsw_prog_main_image_context_timestamp_buffer_ptr_hi_o() (0x000000b0U)
#define ctxsw_prog_main_image_context_timestamp_buffer_ptr_hi_v_m()\ #define ctxsw_prog_main_image_context_timestamp_buffer_ptr_hi_v_m()\
(U32(0xfffffffU) << 0U) (U32(0xfffffffU) << 0U)
@@ -134,7 +134,7 @@
(0x30000000U) (0x30000000U)
#define ctxsw_prog_main_image_context_timestamp_buffer_ptr_o() (0x000000b4U) #define ctxsw_prog_main_image_context_timestamp_buffer_ptr_o() (0x000000b4U)
#define ctxsw_prog_main_image_context_timestamp_buffer_ptr_v_f(v)\ #define ctxsw_prog_main_image_context_timestamp_buffer_ptr_v_f(v)\
(((v)&0xffffffffU) << 0U) ((U32(v) & 0xffffffffU) << 0U)
#define ctxsw_prog_record_timestamp_record_size_in_bytes_v() (0x00000080U) #define ctxsw_prog_record_timestamp_record_size_in_bytes_v() (0x00000080U)
#define ctxsw_prog_record_timestamp_record_size_in_words_v() (0x00000020U) #define ctxsw_prog_record_timestamp_record_size_in_words_v() (0x00000020U)
#define ctxsw_prog_record_timestamp_magic_value_lo_o() (0x00000000U) #define ctxsw_prog_record_timestamp_magic_value_lo_o() (0x00000000U)
@@ -147,10 +147,12 @@
#define ctxsw_prog_record_timestamp_new_context_ptr_o() (0x00000014U) #define ctxsw_prog_record_timestamp_new_context_ptr_o() (0x00000014U)
#define ctxsw_prog_record_timestamp_timestamp_lo_o() (0x00000018U) #define ctxsw_prog_record_timestamp_timestamp_lo_o() (0x00000018U)
#define ctxsw_prog_record_timestamp_timestamp_hi_o() (0x0000001cU) #define ctxsw_prog_record_timestamp_timestamp_hi_o() (0x0000001cU)
#define ctxsw_prog_record_timestamp_timestamp_hi_v_f(v) (((v)&0xffffffU) << 0U) #define ctxsw_prog_record_timestamp_timestamp_hi_v_f(v)\
((U32(v) & 0xffffffU) << 0U)
#define ctxsw_prog_record_timestamp_timestamp_hi_v_v(r)\ #define ctxsw_prog_record_timestamp_timestamp_hi_v_v(r)\
(((r) >> 0U) & 0xffffffU) (((r) >> 0U) & 0xffffffU)
#define ctxsw_prog_record_timestamp_timestamp_hi_tag_f(v) (((v)&0xffU) << 24U) #define ctxsw_prog_record_timestamp_timestamp_hi_tag_f(v)\
((U32(v) & 0xffU) << 24U)
#define ctxsw_prog_record_timestamp_timestamp_hi_tag_m() (U32(0xffU) << 24U) #define ctxsw_prog_record_timestamp_timestamp_hi_tag_m() (U32(0xffU) << 24U)
#define ctxsw_prog_record_timestamp_timestamp_hi_tag_v(r) (((r) >> 24U) & 0xffU) #define ctxsw_prog_record_timestamp_timestamp_hi_tag_v(r) (((r) >> 24U) & 0xffU)
#define ctxsw_prog_record_timestamp_timestamp_hi_tag_ctxsw_req_by_host_v()\ #define ctxsw_prog_record_timestamp_timestamp_hi_tag_ctxsw_req_by_host_v()\
@@ -189,6 +191,7 @@
#define ctxsw_prog_record_timestamp_timestamp_hi_tag_invalid_timestamp_f()\ #define ctxsw_prog_record_timestamp_timestamp_hi_tag_invalid_timestamp_f()\
(0xff000000U) (0xff000000U)
#define ctxsw_prog_main_image_preemption_options_o() (0x00000060U) #define ctxsw_prog_main_image_preemption_options_o() (0x00000060U)
#define ctxsw_prog_main_image_preemption_options_control_f(v) (((v)&0x3U) << 0U) #define ctxsw_prog_main_image_preemption_options_control_f(v)\
((U32(v) & 0x3U) << 0U)
#define ctxsw_prog_main_image_preemption_options_control_cta_enabled_f() (0x1U) #define ctxsw_prog_main_image_preemption_options_control_cta_enabled_f() (0x1U)
#endif #endif

122
drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_falcon_gm20b.h
View File

@@ -68,44 +68,44 @@
#define falcon_falcon_irqstat_swgen0_true_f() (0x40U) #define falcon_falcon_irqstat_swgen0_true_f() (0x40U)
#define falcon_falcon_irqmode_r() (0x0000000cU) #define falcon_falcon_irqmode_r() (0x0000000cU)
#define falcon_falcon_irqmset_r() (0x00000010U) #define falcon_falcon_irqmset_r() (0x00000010U)
#define falcon_falcon_irqmset_gptmr_f(v) (((v)&0x1U) << 0U) #define falcon_falcon_irqmset_gptmr_f(v) ((U32(v) & 0x1U) << 0U)
#define falcon_falcon_irqmset_wdtmr_f(v) (((v)&0x1U) << 1U) #define falcon_falcon_irqmset_wdtmr_f(v) ((U32(v) & 0x1U) << 1U)
#define falcon_falcon_irqmset_mthd_f(v) (((v)&0x1U) << 2U) #define falcon_falcon_irqmset_mthd_f(v) ((U32(v) & 0x1U) << 2U)
#define falcon_falcon_irqmset_ctxsw_f(v) (((v)&0x1U) << 3U) #define falcon_falcon_irqmset_ctxsw_f(v) ((U32(v) & 0x1U) << 3U)
#define falcon_falcon_irqmset_halt_f(v) (((v)&0x1U) << 4U) #define falcon_falcon_irqmset_halt_f(v) ((U32(v) & 0x1U) << 4U)
#define falcon_falcon_irqmset_exterr_f(v) (((v)&0x1U) << 5U) #define falcon_falcon_irqmset_exterr_f(v) ((U32(v) & 0x1U) << 5U)
#define falcon_falcon_irqmset_swgen0_f(v) (((v)&0x1U) << 6U) #define falcon_falcon_irqmset_swgen0_f(v) ((U32(v) & 0x1U) << 6U)
#define falcon_falcon_irqmset_swgen1_f(v) (((v)&0x1U) << 7U) #define falcon_falcon_irqmset_swgen1_f(v) ((U32(v) & 0x1U) << 7U)
#define falcon_falcon_irqmclr_r() (0x00000014U) #define falcon_falcon_irqmclr_r() (0x00000014U)
#define falcon_falcon_irqmclr_gptmr_f(v) (((v)&0x1U) << 0U) #define falcon_falcon_irqmclr_gptmr_f(v) ((U32(v) & 0x1U) << 0U)
#define falcon_falcon_irqmclr_wdtmr_f(v) (((v)&0x1U) << 1U) #define falcon_falcon_irqmclr_wdtmr_f(v) ((U32(v) & 0x1U) << 1U)
#define falcon_falcon_irqmclr_mthd_f(v) (((v)&0x1U) << 2U) #define falcon_falcon_irqmclr_mthd_f(v) ((U32(v) & 0x1U) << 2U)
#define falcon_falcon_irqmclr_ctxsw_f(v) (((v)&0x1U) << 3U) #define falcon_falcon_irqmclr_ctxsw_f(v) ((U32(v) & 0x1U) << 3U)
#define falcon_falcon_irqmclr_halt_f(v) (((v)&0x1U) << 4U) #define falcon_falcon_irqmclr_halt_f(v) ((U32(v) & 0x1U) << 4U)
#define falcon_falcon_irqmclr_exterr_f(v) (((v)&0x1U) << 5U) #define falcon_falcon_irqmclr_exterr_f(v) ((U32(v) & 0x1U) << 5U)
#define falcon_falcon_irqmclr_swgen0_f(v) (((v)&0x1U) << 6U) #define falcon_falcon_irqmclr_swgen0_f(v) ((U32(v) & 0x1U) << 6U)
#define falcon_falcon_irqmclr_swgen1_f(v) (((v)&0x1U) << 7U) #define falcon_falcon_irqmclr_swgen1_f(v) ((U32(v) & 0x1U) << 7U)
#define falcon_falcon_irqmclr_ext_f(v) (((v)&0xffU) << 8U) #define falcon_falcon_irqmclr_ext_f(v) ((U32(v) & 0xffU) << 8U)
#define falcon_falcon_irqmask_r() (0x00000018U) #define falcon_falcon_irqmask_r() (0x00000018U)
#define falcon_falcon_irqdest_r() (0x0000001cU) #define falcon_falcon_irqdest_r() (0x0000001cU)
#define falcon_falcon_irqdest_host_gptmr_f(v) (((v)&0x1U) << 0U) #define falcon_falcon_irqdest_host_gptmr_f(v) ((U32(v) & 0x1U) << 0U)
#define falcon_falcon_irqdest_host_wdtmr_f(v) (((v)&0x1U) << 1U) #define falcon_falcon_irqdest_host_wdtmr_f(v) ((U32(v) & 0x1U) << 1U)
#define falcon_falcon_irqdest_host_mthd_f(v) (((v)&0x1U) << 2U) #define falcon_falcon_irqdest_host_mthd_f(v) ((U32(v) & 0x1U) << 2U)
#define falcon_falcon_irqdest_host_ctxsw_f(v) (((v)&0x1U) << 3U) #define falcon_falcon_irqdest_host_ctxsw_f(v) ((U32(v) & 0x1U) << 3U)
#define falcon_falcon_irqdest_host_halt_f(v) (((v)&0x1U) << 4U) #define falcon_falcon_irqdest_host_halt_f(v) ((U32(v) & 0x1U) << 4U)
#define falcon_falcon_irqdest_host_exterr_f(v) (((v)&0x1U) << 5U) #define falcon_falcon_irqdest_host_exterr_f(v) ((U32(v) & 0x1U) << 5U)
#define falcon_falcon_irqdest_host_swgen0_f(v) (((v)&0x1U) << 6U) #define falcon_falcon_irqdest_host_swgen0_f(v) ((U32(v) & 0x1U) << 6U)
#define falcon_falcon_irqdest_host_swgen1_f(v) (((v)&0x1U) << 7U) #define falcon_falcon_irqdest_host_swgen1_f(v) ((U32(v) & 0x1U) << 7U)
#define falcon_falcon_irqdest_host_ext_f(v) (((v)&0xffU) << 8U) #define falcon_falcon_irqdest_host_ext_f(v) ((U32(v) & 0xffU) << 8U)
#define falcon_falcon_irqdest_target_gptmr_f(v) (((v)&0x1U) << 16U) #define falcon_falcon_irqdest_target_gptmr_f(v) ((U32(v) & 0x1U) << 16U)
#define falcon_falcon_irqdest_target_wdtmr_f(v) (((v)&0x1U) << 17U) #define falcon_falcon_irqdest_target_wdtmr_f(v) ((U32(v) & 0x1U) << 17U)
#define falcon_falcon_irqdest_target_mthd_f(v) (((v)&0x1U) << 18U) #define falcon_falcon_irqdest_target_mthd_f(v) ((U32(v) & 0x1U) << 18U)
#define falcon_falcon_irqdest_target_ctxsw_f(v) (((v)&0x1U) << 19U) #define falcon_falcon_irqdest_target_ctxsw_f(v) ((U32(v) & 0x1U) << 19U)
#define falcon_falcon_irqdest_target_halt_f(v) (((v)&0x1U) << 20U) #define falcon_falcon_irqdest_target_halt_f(v) ((U32(v) & 0x1U) << 20U)
#define falcon_falcon_irqdest_target_exterr_f(v) (((v)&0x1U) << 21U) #define falcon_falcon_irqdest_target_exterr_f(v) ((U32(v) & 0x1U) << 21U)
#define falcon_falcon_irqdest_target_swgen0_f(v) (((v)&0x1U) << 22U) #define falcon_falcon_irqdest_target_swgen0_f(v) ((U32(v) & 0x1U) << 22U)
#define falcon_falcon_irqdest_target_swgen1_f(v) (((v)&0x1U) << 23U) #define falcon_falcon_irqdest_target_swgen1_f(v) ((U32(v) & 0x1U) << 23U)
#define falcon_falcon_irqdest_target_ext_f(v) (((v)&0xffU) << 24U) #define falcon_falcon_irqdest_target_ext_f(v) ((U32(v) & 0xffU) << 24U)
#define falcon_falcon_curctx_r() (0x00000050U) #define falcon_falcon_curctx_r() (0x00000050U)
#define falcon_falcon_nxtctx_r() (0x00000054U) #define falcon_falcon_nxtctx_r() (0x00000054U)
#define falcon_falcon_mailbox0_r() (0x00000040U) #define falcon_falcon_mailbox0_r() (0x00000040U)
@@ -118,24 +118,24 @@
#define falcon_falcon_os_r() (0x00000080U) #define falcon_falcon_os_r() (0x00000080U)
#define falcon_falcon_engctl_r() (0x000000a4U) #define falcon_falcon_engctl_r() (0x000000a4U)
#define falcon_falcon_cpuctl_r() (0x00000100U) #define falcon_falcon_cpuctl_r() (0x00000100U)
#define falcon_falcon_cpuctl_startcpu_f(v) (((v)&0x1U) << 1U) #define falcon_falcon_cpuctl_startcpu_f(v) ((U32(v) & 0x1U) << 1U)
#define falcon_falcon_cpuctl_sreset_f(v) (((v)&0x1U) << 2U) #define falcon_falcon_cpuctl_sreset_f(v) ((U32(v) & 0x1U) << 2U)
#define falcon_falcon_cpuctl_hreset_f(v) (((v)&0x1U) << 3U) #define falcon_falcon_cpuctl_hreset_f(v) ((U32(v) & 0x1U) << 3U)
#define falcon_falcon_cpuctl_halt_intr_f(v) (((v)&0x1U) << 4U) #define falcon_falcon_cpuctl_halt_intr_f(v) ((U32(v) & 0x1U) << 4U)
#define falcon_falcon_cpuctl_halt_intr_m() (U32(0x1U) << 4U) #define falcon_falcon_cpuctl_halt_intr_m() (U32(0x1U) << 4U)
#define falcon_falcon_cpuctl_halt_intr_v(r) (((r) >> 4U) & 0x1U) #define falcon_falcon_cpuctl_halt_intr_v(r) (((r) >> 4U) & 0x1U)
#define falcon_falcon_cpuctl_stopped_m() (U32(0x1U) << 5U) #define falcon_falcon_cpuctl_stopped_m() (U32(0x1U) << 5U)
#define falcon_falcon_cpuctl_cpuctl_alias_en_f(v) (((v)&0x1U) << 6U) #define falcon_falcon_cpuctl_cpuctl_alias_en_f(v) ((U32(v) & 0x1U) << 6U)
#define falcon_falcon_cpuctl_cpuctl_alias_en_m() (U32(0x1U) << 6U) #define falcon_falcon_cpuctl_cpuctl_alias_en_m() (U32(0x1U) << 6U)
#define falcon_falcon_cpuctl_cpuctl_alias_en_v(r) (((r) >> 6U) & 0x1U) #define falcon_falcon_cpuctl_cpuctl_alias_en_v(r) (((r) >> 6U) & 0x1U)
#define falcon_falcon_cpuctl_alias_r() (0x00000130U) #define falcon_falcon_cpuctl_alias_r() (0x00000130U)
#define falcon_falcon_cpuctl_alias_startcpu_f(v) (((v)&0x1U) << 1U) #define falcon_falcon_cpuctl_alias_startcpu_f(v) ((U32(v) & 0x1U) << 1U)
#define falcon_falcon_imemc_r(i)\ #define falcon_falcon_imemc_r(i)\
(nvgpu_safe_add_u32(0x00000180U, nvgpu_safe_mult_u32((i), 16U))) (nvgpu_safe_add_u32(0x00000180U, nvgpu_safe_mult_u32((i), 16U)))
#define falcon_falcon_imemc_offs_f(v) (((v)&0x3fU) << 2U) #define falcon_falcon_imemc_offs_f(v) ((U32(v) & 0x3fU) << 2U)
#define falcon_falcon_imemc_blk_f(v) (((v)&0xffU) << 8U) #define falcon_falcon_imemc_blk_f(v) ((U32(v) & 0xffU) << 8U)
#define falcon_falcon_imemc_aincw_f(v) (((v)&0x1U) << 24U) #define falcon_falcon_imemc_aincw_f(v) ((U32(v) & 0x1U) << 24U)
#define falcon_falcon_imemc_secure_f(v) (((v)&0x1U) << 28U) #define falcon_falcon_imemc_secure_f(v) ((U32(v) & 0x1U) << 28U)
#define falcon_falcon_imemd_r(i)\ #define falcon_falcon_imemd_r(i)\
(nvgpu_safe_add_u32(0x00000184U, nvgpu_safe_mult_u32((i), 16U))) (nvgpu_safe_add_u32(0x00000184U, nvgpu_safe_mult_u32((i), 16U)))
#define falcon_falcon_imemt_r(i)\ #define falcon_falcon_imemt_r(i)\
@@ -143,11 +143,11 @@
#define falcon_falcon_sctl_r() (0x00000240U) #define falcon_falcon_sctl_r() (0x00000240U)
#define falcon_falcon_mmu_phys_sec_r() (0x00100ce4U) #define falcon_falcon_mmu_phys_sec_r() (0x00100ce4U)
#define falcon_falcon_bootvec_r() (0x00000104U) #define falcon_falcon_bootvec_r() (0x00000104U)
#define falcon_falcon_bootvec_vec_f(v) (((v)&0xffffffffU) << 0U) #define falcon_falcon_bootvec_vec_f(v) ((U32(v) & 0xffffffffU) << 0U)
#define falcon_falcon_dmactl_r() (0x0000010cU) #define falcon_falcon_dmactl_r() (0x0000010cU)
#define falcon_falcon_dmactl_dmem_scrubbing_m() (U32(0x1U) << 1U) #define falcon_falcon_dmactl_dmem_scrubbing_m() (U32(0x1U) << 1U)
#define falcon_falcon_dmactl_imem_scrubbing_m() (U32(0x1U) << 2U) #define falcon_falcon_dmactl_imem_scrubbing_m() (U32(0x1U) << 2U)
#define falcon_falcon_dmactl_require_ctx_f(v) (((v)&0x1U) << 0U) #define falcon_falcon_dmactl_require_ctx_f(v) ((U32(v) & 0x1U) << 0U)
#define falcon_falcon_hwcfg_r() (0x00000108U) #define falcon_falcon_hwcfg_r() (0x00000108U)
#define falcon_falcon_hwcfg_imem_size_v(r) (((r) >> 0U) & 0x1ffU) #define falcon_falcon_hwcfg_imem_size_v(r) (((r) >> 0U) & 0x1ffU)
#define falcon_falcon_hwcfg_dmem_size_v(r) (((r) >> 9U) & 0x1ffU) #define falcon_falcon_hwcfg_dmem_size_v(r) (((r) >> 9U) & 0x1ffU)
@@ -157,18 +157,18 @@
#define falcon_falcon_dmatrfbase_r() (0x00000110U) #define falcon_falcon_dmatrfbase_r() (0x00000110U)
#define falcon_falcon_dmatrfmoffs_r() (0x00000114U) #define falcon_falcon_dmatrfmoffs_r() (0x00000114U)
#define falcon_falcon_dmatrfcmd_r() (0x00000118U) #define falcon_falcon_dmatrfcmd_r() (0x00000118U)
#define falcon_falcon_dmatrfcmd_imem_f(v) (((v)&0x1U) << 4U) #define falcon_falcon_dmatrfcmd_imem_f(v) ((U32(v) & 0x1U) << 4U)
#define falcon_falcon_dmatrfcmd_write_f(v) (((v)&0x1U) << 5U) #define falcon_falcon_dmatrfcmd_write_f(v) ((U32(v) & 0x1U) << 5U)
#define falcon_falcon_dmatrfcmd_size_f(v) (((v)&0x7U) << 8U) #define falcon_falcon_dmatrfcmd_size_f(v) ((U32(v) & 0x7U) << 8U)
#define falcon_falcon_dmatrfcmd_ctxdma_f(v) (((v)&0x7U) << 12U) #define falcon_falcon_dmatrfcmd_ctxdma_f(v) ((U32(v) & 0x7U) << 12U)
#define falcon_falcon_dmatrffboffs_r() (0x0000011cU) #define falcon_falcon_dmatrffboffs_r() (0x0000011cU)
#define falcon_falcon_imctl_debug_r() (0x0000015cU) #define falcon_falcon_imctl_debug_r() (0x0000015cU)
#define falcon_falcon_imctl_debug_addr_blk_f(v) (((v)&0xffffffU) << 0U) #define falcon_falcon_imctl_debug_addr_blk_f(v) ((U32(v) & 0xffffffU) << 0U)
#define falcon_falcon_imctl_debug_cmd_f(v) (((v)&0x7U) << 24U) #define falcon_falcon_imctl_debug_cmd_f(v) ((U32(v) & 0x7U) << 24U)
#define falcon_falcon_imstat_r() (0x00000144U) #define falcon_falcon_imstat_r() (0x00000144U)
#define falcon_falcon_traceidx_r() (0x00000148U) #define falcon_falcon_traceidx_r() (0x00000148U)
#define falcon_falcon_traceidx_maxidx_v(r) (((r) >> 16U) & 0xffU) #define falcon_falcon_traceidx_maxidx_v(r) (((r) >> 16U) & 0xffU)
#define falcon_falcon_traceidx_idx_f(v) (((v)&0xffU) << 0U) #define falcon_falcon_traceidx_idx_f(v) ((U32(v) & 0xffU) << 0U)
#define falcon_falcon_tracepc_r() (0x0000014cU) #define falcon_falcon_tracepc_r() (0x0000014cU)
#define falcon_falcon_tracepc_pc_v(r) (((r) >> 0U) & 0xffffffU) #define falcon_falcon_tracepc_pc_v(r) (((r) >> 0U) & 0xffffffU)
#define falcon_falcon_exterraddr_r() (0x0010a168U) #define falcon_falcon_exterraddr_r() (0x0010a168U)
@@ -178,26 +178,26 @@
#define falcon_falcon_exterrstat_valid_true_v() (0x00000001U) #define falcon_falcon_exterrstat_valid_true_v() (0x00000001U)
#define falcon_falcon_icd_cmd_r() (0x00000200U) #define falcon_falcon_icd_cmd_r() (0x00000200U)
#define falcon_falcon_icd_cmd_opc_s() (4U) #define falcon_falcon_icd_cmd_opc_s() (4U)
#define falcon_falcon_icd_cmd_opc_f(v) (((v)&0xfU) << 0U) #define falcon_falcon_icd_cmd_opc_f(v) ((U32(v) & 0xfU) << 0U)
#define falcon_falcon_icd_cmd_opc_m() (U32(0xfU) << 0U) #define falcon_falcon_icd_cmd_opc_m() (U32(0xfU) << 0U)
#define falcon_falcon_icd_cmd_opc_v(r) (((r) >> 0U) & 0xfU) #define falcon_falcon_icd_cmd_opc_v(r) (((r) >> 0U) & 0xfU)
#define falcon_falcon_icd_cmd_opc_rreg_f() (0x8U) #define falcon_falcon_icd_cmd_opc_rreg_f() (0x8U)
#define falcon_falcon_icd_cmd_opc_rstat_f() (0xeU) #define falcon_falcon_icd_cmd_opc_rstat_f() (0xeU)
#define falcon_falcon_icd_cmd_idx_f(v) (((v)&0x1fU) << 8U) #define falcon_falcon_icd_cmd_idx_f(v) ((U32(v) & 0x1fU) << 8U)
#define falcon_falcon_icd_rdata_r() (0x0000020cU) #define falcon_falcon_icd_rdata_r() (0x0000020cU)
#define falcon_falcon_dmemc_r(i)\ #define falcon_falcon_dmemc_r(i)\
(nvgpu_safe_add_u32(0x000001c0U, nvgpu_safe_mult_u32((i), 8U))) (nvgpu_safe_add_u32(0x000001c0U, nvgpu_safe_mult_u32((i), 8U)))
#define falcon_falcon_dmemc_offs_f(v) (((v)&0x3fU) << 2U) #define falcon_falcon_dmemc_offs_f(v) ((U32(v) & 0x3fU) << 2U)
#define falcon_falcon_dmemc_offs_m() (U32(0x3fU) << 2U) #define falcon_falcon_dmemc_offs_m() (U32(0x3fU) << 2U)
#define falcon_falcon_dmemc_blk_f(v) (((v)&0xffU) << 8U) #define falcon_falcon_dmemc_blk_f(v) ((U32(v) & 0xffU) << 8U)
#define falcon_falcon_dmemc_blk_m() (U32(0xffU) << 8U) #define falcon_falcon_dmemc_blk_m() (U32(0xffU) << 8U)
#define falcon_falcon_dmemc_aincw_f(v) (((v)&0x1U) << 24U) #define falcon_falcon_dmemc_aincw_f(v) ((U32(v) & 0x1U) << 24U)
#define falcon_falcon_dmemc_aincr_f(v) (((v)&0x1U) << 25U) #define falcon_falcon_dmemc_aincr_f(v) ((U32(v) & 0x1U) << 25U)
#define falcon_falcon_dmemd_r(i)\ #define falcon_falcon_dmemd_r(i)\
(nvgpu_safe_add_u32(0x000001c4U, nvgpu_safe_mult_u32((i), 8U))) (nvgpu_safe_add_u32(0x000001c4U, nvgpu_safe_mult_u32((i), 8U)))
#define falcon_falcon_debug1_r() (0x00000090U) #define falcon_falcon_debug1_r() (0x00000090U)
#define falcon_falcon_debug1_ctxsw_mode_s() (1U) #define falcon_falcon_debug1_ctxsw_mode_s() (1U)
#define falcon_falcon_debug1_ctxsw_mode_f(v) (((v)&0x1U) << 16U) #define falcon_falcon_debug1_ctxsw_mode_f(v) ((U32(v) & 0x1U) << 16U)
#define falcon_falcon_debug1_ctxsw_mode_m() (U32(0x1U) << 16U) #define falcon_falcon_debug1_ctxsw_mode_m() (U32(0x1U) << 16U)
#define falcon_falcon_debug1_ctxsw_mode_v(r) (((r) >> 16U) & 0x1U) #define falcon_falcon_debug1_ctxsw_mode_v(r) (((r) >> 16U) & 0x1U)
#define falcon_falcon_debug1_ctxsw_mode_init_f() (0x0U) #define falcon_falcon_debug1_ctxsw_mode_init_f() (0x0U)

16
drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_fb_gm20b.h
View File

@@ -73,18 +73,18 @@
#define fb_mmu_invalidate_pdb_r() (0x00100cb8U) #define fb_mmu_invalidate_pdb_r() (0x00100cb8U)
#define fb_mmu_invalidate_pdb_aperture_vid_mem_f() (0x0U) #define fb_mmu_invalidate_pdb_aperture_vid_mem_f() (0x0U)
#define fb_mmu_invalidate_pdb_aperture_sys_mem_f() (0x2U) #define fb_mmu_invalidate_pdb_aperture_sys_mem_f() (0x2U)
#define fb_mmu_invalidate_pdb_addr_f(v) (((v)&0xfffffffU) << 4U) #define fb_mmu_invalidate_pdb_addr_f(v) ((U32(v) & 0xfffffffU) << 4U)
#define fb_mmu_invalidate_r() (0x00100cbcU) #define fb_mmu_invalidate_r() (0x00100cbcU)
#define fb_mmu_invalidate_all_va_true_f() (0x1U) #define fb_mmu_invalidate_all_va_true_f() (0x1U)
#define fb_mmu_invalidate_all_pdb_true_f() (0x2U) #define fb_mmu_invalidate_all_pdb_true_f() (0x2U)
#define fb_mmu_invalidate_trigger_s() (1U) #define fb_mmu_invalidate_trigger_s() (1U)
#define fb_mmu_invalidate_trigger_f(v) (((v)&0x1U) << 31U) #define fb_mmu_invalidate_trigger_f(v) ((U32(v) & 0x1U) << 31U)
#define fb_mmu_invalidate_trigger_m() (U32(0x1U) << 31U) #define fb_mmu_invalidate_trigger_m() (U32(0x1U) << 31U)
#define fb_mmu_invalidate_trigger_v(r) (((r) >> 31U) & 0x1U) #define fb_mmu_invalidate_trigger_v(r) (((r) >> 31U) & 0x1U)
#define fb_mmu_invalidate_trigger_true_f() (0x80000000U) #define fb_mmu_invalidate_trigger_true_f() (0x80000000U)
#define fb_mmu_debug_wr_r() (0x00100cc8U) #define fb_mmu_debug_wr_r() (0x00100cc8U)
#define fb_mmu_debug_wr_aperture_s() (2U) #define fb_mmu_debug_wr_aperture_s() (2U)
#define fb_mmu_debug_wr_aperture_f(v) (((v)&0x3U) << 0U) #define fb_mmu_debug_wr_aperture_f(v) ((U32(v) & 0x3U) << 0U)
#define fb_mmu_debug_wr_aperture_m() (U32(0x3U) << 0U) #define fb_mmu_debug_wr_aperture_m() (U32(0x3U) << 0U)
#define fb_mmu_debug_wr_aperture_v(r) (((r) >> 0U) & 0x3U) #define fb_mmu_debug_wr_aperture_v(r) (((r) >> 0U) & 0x3U)
#define fb_mmu_debug_wr_aperture_vid_mem_f() (0x0U) #define fb_mmu_debug_wr_aperture_vid_mem_f() (0x0U)
@@ -93,14 +93,14 @@
#define fb_mmu_debug_wr_vol_false_f() (0x0U) #define fb_mmu_debug_wr_vol_false_f() (0x0U)
#define fb_mmu_debug_wr_vol_true_v() (0x00000001U) #define fb_mmu_debug_wr_vol_true_v() (0x00000001U)
#define fb_mmu_debug_wr_vol_true_f() (0x4U) #define fb_mmu_debug_wr_vol_true_f() (0x4U)
#define fb_mmu_debug_wr_addr_f(v) (((v)&0xfffffffU) << 4U) #define fb_mmu_debug_wr_addr_f(v) ((U32(v) & 0xfffffffU) << 4U)
#define fb_mmu_debug_wr_addr_alignment_v() (0x0000000cU) #define fb_mmu_debug_wr_addr_alignment_v() (0x0000000cU)
#define fb_mmu_debug_rd_r() (0x00100cccU) #define fb_mmu_debug_rd_r() (0x00100cccU)
#define fb_mmu_debug_rd_aperture_vid_mem_f() (0x0U) #define fb_mmu_debug_rd_aperture_vid_mem_f() (0x0U)
#define fb_mmu_debug_rd_aperture_sys_mem_coh_f() (0x2U) #define fb_mmu_debug_rd_aperture_sys_mem_coh_f() (0x2U)
#define fb_mmu_debug_rd_aperture_sys_mem_ncoh_f() (0x3U) #define fb_mmu_debug_rd_aperture_sys_mem_ncoh_f() (0x3U)
#define fb_mmu_debug_rd_vol_false_f() (0x0U) #define fb_mmu_debug_rd_vol_false_f() (0x0U)
#define fb_mmu_debug_rd_addr_f(v) (((v)&0xfffffffU) << 4U) #define fb_mmu_debug_rd_addr_f(v) ((U32(v) & 0xfffffffU) << 4U)
#define fb_mmu_debug_rd_addr_alignment_v() (0x0000000cU) #define fb_mmu_debug_rd_addr_alignment_v() (0x0000000cU)
#define fb_mmu_debug_ctrl_r() (0x00100cc4U) #define fb_mmu_debug_ctrl_r() (0x00100cc4U)
#define fb_mmu_debug_ctrl_debug_v(r) (((r) >> 16U) & 0x1U) #define fb_mmu_debug_ctrl_debug_v(r) (((r) >> 16U) & 0x1U)
@@ -110,18 +110,18 @@
#define fb_mmu_debug_ctrl_debug_disabled_v() (0x00000000U) #define fb_mmu_debug_ctrl_debug_disabled_v() (0x00000000U)
#define fb_mmu_debug_ctrl_debug_disabled_f() (0x0U) #define fb_mmu_debug_ctrl_debug_disabled_f() (0x0U)
#define fb_mmu_vpr_info_r() (0x00100cd0U) #define fb_mmu_vpr_info_r() (0x00100cd0U)
#define fb_mmu_vpr_info_index_f(v) (((v)&0x3U) << 0U) #define fb_mmu_vpr_info_index_f(v) ((U32(v) & 0x3U) << 0U)
#define fb_mmu_vpr_info_index_v(r) (((r) >> 0U) & 0x3U) #define fb_mmu_vpr_info_index_v(r) (((r) >> 0U) & 0x3U)
#define fb_mmu_vpr_info_index_addr_lo_v() (0x00000000U) #define fb_mmu_vpr_info_index_addr_lo_v() (0x00000000U)
#define fb_mmu_vpr_info_index_addr_hi_v() (0x00000001U) #define fb_mmu_vpr_info_index_addr_hi_v() (0x00000001U)
#define fb_mmu_vpr_info_index_cya_lo_v() (0x00000002U) #define fb_mmu_vpr_info_index_cya_lo_v() (0x00000002U)
#define fb_mmu_vpr_info_index_cya_hi_v() (0x00000003U) #define fb_mmu_vpr_info_index_cya_hi_v() (0x00000003U)
#define fb_mmu_vpr_info_fetch_f(v) (((v)&0x1U) << 2U) #define fb_mmu_vpr_info_fetch_f(v) ((U32(v) & 0x1U) << 2U)
#define fb_mmu_vpr_info_fetch_v(r) (((r) >> 2U) & 0x1U) #define fb_mmu_vpr_info_fetch_v(r) (((r) >> 2U) & 0x1U)
#define fb_mmu_vpr_info_fetch_false_v() (0x00000000U) #define fb_mmu_vpr_info_fetch_false_v() (0x00000000U)
#define fb_mmu_vpr_info_fetch_true_v() (0x00000001U) #define fb_mmu_vpr_info_fetch_true_v() (0x00000001U)
#define fb_mmu_wpr_info_r() (0x00100cd4U) #define fb_mmu_wpr_info_r() (0x00100cd4U)
#define fb_mmu_wpr_info_index_f(v) (((v)&0xfU) << 0U) #define fb_mmu_wpr_info_index_f(v) ((U32(v) & 0xfU) << 0U)
#define fb_mmu_wpr_info_index_allow_read_v() (0x00000000U) #define fb_mmu_wpr_info_index_allow_read_v() (0x00000000U)
#define fb_mmu_wpr_info_index_allow_write_v() (0x00000001U) #define fb_mmu_wpr_info_index_allow_write_v() (0x00000001U)
#define fb_mmu_wpr_info_index_wpr1_addr_lo_v() (0x00000002U) #define fb_mmu_wpr_info_index_wpr1_addr_lo_v() (0x00000002U)

26
drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_fifo_gm20b.h
View File

@@ -60,24 +60,24 @@
#include <nvgpu/safe_ops.h> #include <nvgpu/safe_ops.h>
#define fifo_bar1_base_r() (0x00002254U) #define fifo_bar1_base_r() (0x00002254U)
#define fifo_bar1_base_ptr_f(v) (((v)&0xfffffffU) << 0U) #define fifo_bar1_base_ptr_f(v) ((U32(v) & 0xfffffffU) << 0U)
#define fifo_bar1_base_ptr_align_shift_v() (0x0000000cU) #define fifo_bar1_base_ptr_align_shift_v() (0x0000000cU)
#define fifo_bar1_base_valid_false_f() (0x0U) #define fifo_bar1_base_valid_false_f() (0x0U)
#define fifo_bar1_base_valid_true_f() (0x10000000U) #define fifo_bar1_base_valid_true_f() (0x10000000U)
#define fifo_runlist_base_r() (0x00002270U) #define fifo_runlist_base_r() (0x00002270U)
#define fifo_runlist_base_ptr_f(v) (((v)&0xfffffffU) << 0U) #define fifo_runlist_base_ptr_f(v) ((U32(v) & 0xfffffffU) << 0U)
#define fifo_runlist_base_target_vid_mem_f() (0x0U) #define fifo_runlist_base_target_vid_mem_f() (0x0U)
#define fifo_runlist_base_target_sys_mem_coh_f() (0x20000000U) #define fifo_runlist_base_target_sys_mem_coh_f() (0x20000000U)
#define fifo_runlist_base_target_sys_mem_ncoh_f() (0x30000000U) #define fifo_runlist_base_target_sys_mem_ncoh_f() (0x30000000U)
#define fifo_runlist_r() (0x00002274U) #define fifo_runlist_r() (0x00002274U)
#define fifo_runlist_engine_f(v) (((v)&0xfU) << 20U) #define fifo_runlist_engine_f(v) ((U32(v) & 0xfU) << 20U)
#define fifo_eng_runlist_base_r(i)\ #define fifo_eng_runlist_base_r(i)\
(nvgpu_safe_add_u32(0x00002280U, nvgpu_safe_mult_u32((i), 8U))) (nvgpu_safe_add_u32(0x00002280U, nvgpu_safe_mult_u32((i), 8U)))
#define fifo_eng_runlist_base__size_1_v() (0x00000001U) #define fifo_eng_runlist_base__size_1_v() (0x00000001U)
#define fifo_eng_runlist_r(i)\ #define fifo_eng_runlist_r(i)\
(nvgpu_safe_add_u32(0x00002284U, nvgpu_safe_mult_u32((i), 8U))) (nvgpu_safe_add_u32(0x00002284U, nvgpu_safe_mult_u32((i), 8U)))
#define fifo_eng_runlist__size_1_v() (0x00000001U) #define fifo_eng_runlist__size_1_v() (0x00000001U)
#define fifo_eng_runlist_length_f(v) (((v)&0xffffU) << 0U) #define fifo_eng_runlist_length_f(v) ((U32(v) & 0xffffU) << 0U)
#define fifo_eng_runlist_length_max_v() (0x0000ffffU) #define fifo_eng_runlist_length_max_v() (0x0000ffffU)
#define fifo_eng_runlist_pending_true_f() (0x100000U) #define fifo_eng_runlist_pending_true_f() (0x100000U)
#define fifo_pb_timeslice_r(i)\ #define fifo_pb_timeslice_r(i)\
@@ -105,14 +105,14 @@
#define fifo_intr_0_runlist_event_pending_f() (0x40000000U) #define fifo_intr_0_runlist_event_pending_f() (0x40000000U)
#define fifo_intr_0_channel_intr_pending_f() (0x80000000U) #define fifo_intr_0_channel_intr_pending_f() (0x80000000U)
#define fifo_intr_en_0_r() (0x00002140U) #define fifo_intr_en_0_r() (0x00002140U)
#define fifo_intr_en_0_sched_error_f(v) (((v)&0x1U) << 8U) #define fifo_intr_en_0_sched_error_f(v) ((U32(v) & 0x1U) << 8U)
#define fifo_intr_en_0_sched_error_m() (U32(0x1U) << 8U) #define fifo_intr_en_0_sched_error_m() (U32(0x1U) << 8U)
#define fifo_intr_en_0_mmu_fault_f(v) (((v)&0x1U) << 28U) #define fifo_intr_en_0_mmu_fault_f(v) ((U32(v) & 0x1U) << 28U)
#define fifo_intr_en_0_mmu_fault_m() (U32(0x1U) << 28U) #define fifo_intr_en_0_mmu_fault_m() (U32(0x1U) << 28U)
#define fifo_intr_en_1_r() (0x00002528U) #define fifo_intr_en_1_r() (0x00002528U)
#define fifo_intr_bind_error_r() (0x0000252cU) #define fifo_intr_bind_error_r() (0x0000252cU)
#define fifo_intr_sched_error_r() (0x0000254cU) #define fifo_intr_sched_error_r() (0x0000254cU)
#define fifo_intr_sched_error_code_f(v) (((v)&0xffU) << 0U) #define fifo_intr_sched_error_code_f(v) ((U32(v) & 0xffU) << 0U)
#define fifo_intr_sched_error_code_ctxsw_timeout_v() (0x0000000aU) #define fifo_intr_sched_error_code_ctxsw_timeout_v() (0x0000000aU)
#define fifo_intr_chsw_error_r() (0x0000256cU) #define fifo_intr_chsw_error_r() (0x0000256cU)
#define fifo_intr_mmu_fault_id_r() (0x0000259cU) #define fifo_intr_mmu_fault_id_r() (0x0000259cU)
@@ -136,7 +136,7 @@
#define fifo_intr_mmu_fault_info_client_v(r) (((r) >> 8U) & 0x3fU) #define fifo_intr_mmu_fault_info_client_v(r) (((r) >> 8U) & 0x3fU)
#define fifo_intr_pbdma_id_r() (0x000025a0U) #define fifo_intr_pbdma_id_r() (0x000025a0U)
#define fifo_intr_pbdma_id_status_f(v, i)\ #define fifo_intr_pbdma_id_status_f(v, i)\
(((v) & 0x1) << (0U + i*1U)) ((U32(v) & 0x1U) << (0U + (i)*1U))
#define fifo_intr_pbdma_id_status_v(r, i)\ #define fifo_intr_pbdma_id_status_v(r, i)\
(((r) >> (0U + i*1U)) & 0x1U) (((r) >> (0U + i*1U)) & 0x1U)
#define fifo_intr_pbdma_id_status__size_1_v() (0x00000001U) #define fifo_intr_pbdma_id_status__size_1_v() (0x00000001U)
@@ -147,7 +147,7 @@
#define fifo_error_sched_disable_r() (0x0000262cU) #define fifo_error_sched_disable_r() (0x0000262cU)
#define fifo_sched_disable_r() (0x00002630U) #define fifo_sched_disable_r() (0x00002630U)
#define fifo_sched_disable_runlist_f(v, i)\ #define fifo_sched_disable_runlist_f(v, i)\
(((v) & 0x1) << (0U + i*1U)) ((U32(v) & 0x1U) << (0U + (i)*1U))
#define fifo_sched_disable_runlist_m(i)\ #define fifo_sched_disable_runlist_m(i)\
(U32(0x1U) << (0U + (i)*1U)) (U32(0x1U) << (0U + (i)*1U))
#define fifo_sched_disable_true_v() (0x00000001U) #define fifo_sched_disable_true_v() (0x00000001U)
@@ -155,12 +155,12 @@
#define fifo_preempt_pending_true_f() (0x100000U) #define fifo_preempt_pending_true_f() (0x100000U)
#define fifo_preempt_type_channel_f() (0x0U) #define fifo_preempt_type_channel_f() (0x0U)
#define fifo_preempt_type_tsg_f() (0x1000000U) #define fifo_preempt_type_tsg_f() (0x1000000U)
#define fifo_preempt_chid_f(v) (((v)&0xfffU) << 0U) #define fifo_preempt_chid_f(v) ((U32(v) & 0xfffU) << 0U)
#define fifo_preempt_id_f(v) (((v)&0xfffU) << 0U) #define fifo_preempt_id_f(v) ((U32(v) & 0xfffU) << 0U)
#define fifo_trigger_mmu_fault_r(i)\ #define fifo_trigger_mmu_fault_r(i)\
(nvgpu_safe_add_u32(0x00002a30U, nvgpu_safe_mult_u32((i), 4U))) (nvgpu_safe_add_u32(0x00002a30U, nvgpu_safe_mult_u32((i), 4U)))
#define fifo_trigger_mmu_fault_id_f(v) (((v)&0x1fU) << 0U) #define fifo_trigger_mmu_fault_id_f(v) ((U32(v) & 0x1fU) << 0U)
#define fifo_trigger_mmu_fault_enable_f(v) (((v)&0x1U) << 8U) #define fifo_trigger_mmu_fault_enable_f(v) ((U32(v) & 0x1U) << 8U)
#define fifo_engine_status_r(i)\ #define fifo_engine_status_r(i)\
(nvgpu_safe_add_u32(0x00002640U, nvgpu_safe_mult_u32((i), 8U))) (nvgpu_safe_add_u32(0x00002640U, nvgpu_safe_mult_u32((i), 8U)))
#define fifo_engine_status__size_1_v() (0x00000002U) #define fifo_engine_status__size_1_v() (0x00000002U)

6
drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_fuse_gm20b.h
View File

@@ -65,17 +65,17 @@
#define fuse_ctrl_opt_tpc_gpc_r(i)\ #define fuse_ctrl_opt_tpc_gpc_r(i)\
(nvgpu_safe_add_u32(0x00021838U, nvgpu_safe_mult_u32((i), 4U))) (nvgpu_safe_add_u32(0x00021838U, nvgpu_safe_mult_u32((i), 4U)))
#define fuse_ctrl_opt_ram_svop_pdp_r() (0x00021944U) #define fuse_ctrl_opt_ram_svop_pdp_r() (0x00021944U)
#define fuse_ctrl_opt_ram_svop_pdp_data_f(v) (((v)&0x3U) << 0U) #define fuse_ctrl_opt_ram_svop_pdp_data_f(v) ((U32(v) & 0x3U) << 0U)
#define fuse_ctrl_opt_ram_svop_pdp_data_m() (U32(0x3U) << 0U) #define fuse_ctrl_opt_ram_svop_pdp_data_m() (U32(0x3U) << 0U)
#define fuse_ctrl_opt_ram_svop_pdp_data_v(r) (((r) >> 0U) & 0x3U) #define fuse_ctrl_opt_ram_svop_pdp_data_v(r) (((r) >> 0U) & 0x3U)
#define fuse_ctrl_opt_ram_svop_pdp_override_r() (0x00021948U) #define fuse_ctrl_opt_ram_svop_pdp_override_r() (0x00021948U)
#define fuse_ctrl_opt_ram_svop_pdp_override_data_f(v) (((v)&0x1U) << 0U) #define fuse_ctrl_opt_ram_svop_pdp_override_data_f(v) ((U32(v) & 0x1U) << 0U)
#define fuse_ctrl_opt_ram_svop_pdp_override_data_m() (U32(0x1U) << 0U) #define fuse_ctrl_opt_ram_svop_pdp_override_data_m() (U32(0x1U) << 0U)
#define fuse_ctrl_opt_ram_svop_pdp_override_data_v(r) (((r) >> 0U) & 0x1U) #define fuse_ctrl_opt_ram_svop_pdp_override_data_v(r) (((r) >> 0U) & 0x1U)
#define fuse_ctrl_opt_ram_svop_pdp_override_data_yes_f() (0x1U) #define fuse_ctrl_opt_ram_svop_pdp_override_data_yes_f() (0x1U)
#define fuse_ctrl_opt_ram_svop_pdp_override_data_no_f() (0x0U) #define fuse_ctrl_opt_ram_svop_pdp_override_data_no_f() (0x0U)
#define fuse_status_opt_fbio_r() (0x00021c14U) #define fuse_status_opt_fbio_r() (0x00021c14U)
#define fuse_status_opt_fbio_data_f(v) (((v)&0xffffU) << 0U) #define fuse_status_opt_fbio_data_f(v) ((U32(v) & 0xffffU) << 0U)
#define fuse_status_opt_fbio_data_m() (U32(0xffffU) << 0U) #define fuse_status_opt_fbio_data_m() (U32(0xffffU) << 0U)
#define fuse_status_opt_fbio_data_v(r) (((r) >> 0U) & 0xffffU) #define fuse_status_opt_fbio_data_v(r) (((r) >> 0U) & 0xffffU)
#define fuse_status_opt_rop_l2_fbp_r(i)\ #define fuse_status_opt_rop_l2_fbp_r(i)\

12
drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_gmmu_gm20b.h
View File

@@ -66,7 +66,7 @@
#define gmmu_pde_aperture_big_sys_mem_ncoh_f() (0x3U) #define gmmu_pde_aperture_big_sys_mem_ncoh_f() (0x3U)
#define gmmu_pde_size_w() (0U) #define gmmu_pde_size_w() (0U)
#define gmmu_pde_size_full_f() (0x0U) #define gmmu_pde_size_full_f() (0x0U)
#define gmmu_pde_address_big_sys_f(v) (((v)&0xfffffffU) << 4U) #define gmmu_pde_address_big_sys_f(v) ((U32(v) & 0xfffffffU) << 4U)
#define gmmu_pde_address_big_sys_w() (0U) #define gmmu_pde_address_big_sys_w() (0U)
#define gmmu_pde_aperture_small_w() (1U) #define gmmu_pde_aperture_small_w() (1U)
#define gmmu_pde_aperture_small_invalid_f() (0x0U) #define gmmu_pde_aperture_small_invalid_f() (0x0U)
@@ -79,7 +79,7 @@
#define gmmu_pde_vol_big_w() (1U) #define gmmu_pde_vol_big_w() (1U)
#define gmmu_pde_vol_big_true_f() (0x8U) #define gmmu_pde_vol_big_true_f() (0x8U)
#define gmmu_pde_vol_big_false_f() (0x0U) #define gmmu_pde_vol_big_false_f() (0x0U)
#define gmmu_pde_address_small_sys_f(v) (((v)&0xfffffffU) << 4U) #define gmmu_pde_address_small_sys_f(v) ((U32(v) & 0xfffffffU) << 4U)
#define gmmu_pde_address_small_sys_w() (1U) #define gmmu_pde_address_small_sys_w() (1U)
#define gmmu_pde_address_shift_v() (0x0000000cU) #define gmmu_pde_address_shift_v() (0x0000000cU)
#define gmmu_pde__size_v() (0x00000008U) #define gmmu_pde__size_v() (0x00000008U)
@@ -90,9 +90,9 @@
#define gmmu_pte_privilege_w() (0U) #define gmmu_pte_privilege_w() (0U)
#define gmmu_pte_privilege_true_f() (0x2U) #define gmmu_pte_privilege_true_f() (0x2U)
#define gmmu_pte_privilege_false_f() (0x0U) #define gmmu_pte_privilege_false_f() (0x0U)
#define gmmu_pte_address_sys_f(v) (((v)&0xfffffffU) << 4U) #define gmmu_pte_address_sys_f(v) ((U32(v) & 0xfffffffU) << 4U)
#define gmmu_pte_address_sys_w() (0U) #define gmmu_pte_address_sys_w() (0U)
#define gmmu_pte_address_vid_f(v) (((v)&0x1ffffffU) << 4U) #define gmmu_pte_address_vid_f(v) ((U32(v) & 0x1ffffffU) << 4U)
#define gmmu_pte_address_vid_w() (0U) #define gmmu_pte_address_vid_w() (0U)
#define gmmu_pte_vol_w() (1U) #define gmmu_pte_vol_w() (1U)
#define gmmu_pte_vol_true_f() (0x1U) #define gmmu_pte_vol_true_f() (0x1U)
@@ -108,10 +108,10 @@
#define gmmu_pte_read_disable_w() (1U) #define gmmu_pte_read_disable_w() (1U)
#define gmmu_pte_read_disable_true_f() (0x40000000U) #define gmmu_pte_read_disable_true_f() (0x40000000U)
#define gmmu_pte_comptagline_s() (17U) #define gmmu_pte_comptagline_s() (17U)
#define gmmu_pte_comptagline_f(v) (((v)&0x1ffffU) << 12U) #define gmmu_pte_comptagline_f(v) ((U32(v) & 0x1ffffU) << 12U)
#define gmmu_pte_comptagline_w() (1U) #define gmmu_pte_comptagline_w() (1U)
#define gmmu_pte_address_shift_v() (0x0000000cU) #define gmmu_pte_address_shift_v() (0x0000000cU)
#define gmmu_pte_kind_f(v) (((v)&0xffU) << 4U) #define gmmu_pte_kind_f(v) ((U32(v) & 0xffU) << 4U)
#define gmmu_pte_kind_w() (1U) #define gmmu_pte_kind_w() (1U)
#define gmmu_pte_kind_invalid_v() (0x000000ffU) #define gmmu_pte_kind_invalid_v() (0x000000ffU)
#define gmmu_pte_kind_pitch_v() (0x00000000U) #define gmmu_pte_kind_pitch_v() (0x00000000U)

464
drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_gr_gm20b.h
View File

@@ -68,7 +68,7 @@
#define gr_intr_illegal_method_reset_f() (0x10U) #define gr_intr_illegal_method_reset_f() (0x10U)
#define gr_intr_illegal_notify_pending_f() (0x40U) #define gr_intr_illegal_notify_pending_f() (0x40U)
#define gr_intr_illegal_notify_reset_f() (0x40U) #define gr_intr_illegal_notify_reset_f() (0x40U)
#define gr_intr_firmware_method_f(v) (((v)&0x1U) << 8U) #define gr_intr_firmware_method_f(v) ((U32(v) & 0x1U) << 8U)
#define gr_intr_firmware_method_pending_f() (0x100U) #define gr_intr_firmware_method_pending_f() (0x100U)
#define gr_intr_firmware_method_reset_f() (0x100U) #define gr_intr_firmware_method_reset_f() (0x100U)
#define gr_intr_illegal_class_pending_f() (0x20U) #define gr_intr_illegal_class_pending_f() (0x20U)
@@ -103,10 +103,10 @@
#define gr_exception1_en_r() (0x00400130U) #define gr_exception1_en_r() (0x00400130U)
#define gr_exception2_en_r() (0x00400134U) #define gr_exception2_en_r() (0x00400134U)
#define gr_gpfifo_ctl_r() (0x00400500U) #define gr_gpfifo_ctl_r() (0x00400500U)
#define gr_gpfifo_ctl_access_f(v) (((v)&0x1U) << 0U) #define gr_gpfifo_ctl_access_f(v) ((U32(v) & 0x1U) << 0U)
#define gr_gpfifo_ctl_access_disabled_f() (0x0U) #define gr_gpfifo_ctl_access_disabled_f() (0x0U)
#define gr_gpfifo_ctl_access_enabled_f() (0x1U) #define gr_gpfifo_ctl_access_enabled_f() (0x1U)
#define gr_gpfifo_ctl_semaphore_access_f(v) (((v)&0x1U) << 16U) #define gr_gpfifo_ctl_semaphore_access_f(v) ((U32(v) & 0x1U) << 16U)
#define gr_gpfifo_ctl_semaphore_access_enabled_v() (0x00000001U) #define gr_gpfifo_ctl_semaphore_access_enabled_v() (0x00000001U)
#define gr_gpfifo_ctl_semaphore_access_enabled_f() (0x10000U) #define gr_gpfifo_ctl_semaphore_access_enabled_f() (0x10000U)
#define gr_gpfifo_status_r() (0x00400504U) #define gr_gpfifo_status_r() (0x00400504U)
@@ -182,7 +182,7 @@
#define gr_fe_hww_esr_en_enable_f() (0x80000000U) #define gr_fe_hww_esr_en_enable_f() (0x80000000U)
#define gr_fe_hww_esr_info_r() (0x004041b0U) #define gr_fe_hww_esr_info_r() (0x004041b0U)
#define gr_fe_go_idle_timeout_r() (0x00404154U) #define gr_fe_go_idle_timeout_r() (0x00404154U)
#define gr_fe_go_idle_timeout_count_f(v) (((v)&0xffffffffU) << 0U) #define gr_fe_go_idle_timeout_count_f(v) ((U32(v) & 0xffffffffU) << 0U)
#define gr_fe_go_idle_timeout_count_disabled_f() (0x0U) #define gr_fe_go_idle_timeout_count_disabled_f() (0x0U)
#define gr_fe_go_idle_timeout_count_prod_f() (0x800U) #define gr_fe_go_idle_timeout_count_prod_f() (0x800U)
#define gr_fe_object_table_r(i)\ #define gr_fe_object_table_r(i)\
@@ -200,11 +200,11 @@
#define gr_memfmt_hww_esr_reset_active_f() (0x40000000U) #define gr_memfmt_hww_esr_reset_active_f() (0x40000000U)
#define gr_memfmt_hww_esr_en_enable_f() (0x80000000U) #define gr_memfmt_hww_esr_en_enable_f() (0x80000000U)
#define gr_fecs_cpuctl_r() (0x00409100U) #define gr_fecs_cpuctl_r() (0x00409100U)
#define gr_fecs_cpuctl_startcpu_f(v) (((v)&0x1U) << 1U) #define gr_fecs_cpuctl_startcpu_f(v) ((U32(v) & 0x1U) << 1U)
#define gr_fecs_cpuctl_alias_r() (0x00409130U) #define gr_fecs_cpuctl_alias_r() (0x00409130U)
#define gr_fecs_cpuctl_alias_startcpu_f(v) (((v)&0x1U) << 1U) #define gr_fecs_cpuctl_alias_startcpu_f(v) ((U32(v) & 0x1U) << 1U)
#define gr_fecs_dmactl_r() (0x0040910cU) #define gr_fecs_dmactl_r() (0x0040910cU)
#define gr_fecs_dmactl_require_ctx_f(v) (((v)&0x1U) << 0U) #define gr_fecs_dmactl_require_ctx_f(v) ((U32(v) & 0x1U) << 0U)
#define gr_fecs_dmactl_dmem_scrubbing_m() (U32(0x1U) << 1U) #define gr_fecs_dmactl_dmem_scrubbing_m() (U32(0x1U) << 1U)
#define gr_fecs_dmactl_imem_scrubbing_m() (U32(0x1U) << 2U) #define gr_fecs_dmactl_imem_scrubbing_m() (U32(0x1U) << 2U)
#define gr_fecs_os_r() (0x00409080U) #define gr_fecs_os_r() (0x00409080U)
@@ -222,66 +222,66 @@
#define gr_fecs_debuginfo_r() (0x00409094U) #define gr_fecs_debuginfo_r() (0x00409094U)
#define gr_fecs_icd_cmd_r() (0x00409200U) #define gr_fecs_icd_cmd_r() (0x00409200U)
#define gr_fecs_icd_cmd_opc_s() (4U) #define gr_fecs_icd_cmd_opc_s() (4U)
#define gr_fecs_icd_cmd_opc_f(v) (((v)&0xfU) << 0U) #define gr_fecs_icd_cmd_opc_f(v) ((U32(v) & 0xfU) << 0U)
#define gr_fecs_icd_cmd_opc_m() (U32(0xfU) << 0U) #define gr_fecs_icd_cmd_opc_m() (U32(0xfU) << 0U)
#define gr_fecs_icd_cmd_opc_v(r) (((r) >> 0U) & 0xfU) #define gr_fecs_icd_cmd_opc_v(r) (((r) >> 0U) & 0xfU)
#define gr_fecs_icd_cmd_opc_rreg_f() (0x8U) #define gr_fecs_icd_cmd_opc_rreg_f() (0x8U)
#define gr_fecs_icd_cmd_opc_rstat_f() (0xeU) #define gr_fecs_icd_cmd_opc_rstat_f() (0xeU)
#define gr_fecs_icd_cmd_idx_f(v) (((v)&0x1fU) << 8U) #define gr_fecs_icd_cmd_idx_f(v) ((U32(v) & 0x1fU) << 8U)
#define gr_fecs_icd_rdata_r() (0x0040920cU) #define gr_fecs_icd_rdata_r() (0x0040920cU)
#define gr_fecs_imemc_r(i)\ #define gr_fecs_imemc_r(i)\
(nvgpu_safe_add_u32(0x00409180U, nvgpu_safe_mult_u32((i), 16U))) (nvgpu_safe_add_u32(0x00409180U, nvgpu_safe_mult_u32((i), 16U)))
#define gr_fecs_imemc_offs_f(v) (((v)&0x3fU) << 2U) #define gr_fecs_imemc_offs_f(v) ((U32(v) & 0x3fU) << 2U)
#define gr_fecs_imemc_blk_f(v) (((v)&0xffU) << 8U) #define gr_fecs_imemc_blk_f(v) ((U32(v) & 0xffU) << 8U)
#define gr_fecs_imemc_aincw_f(v) (((v)&0x1U) << 24U) #define gr_fecs_imemc_aincw_f(v) ((U32(v) & 0x1U) << 24U)
#define gr_fecs_imemd_r(i)\ #define gr_fecs_imemd_r(i)\
(nvgpu_safe_add_u32(0x00409184U, nvgpu_safe_mult_u32((i), 16U))) (nvgpu_safe_add_u32(0x00409184U, nvgpu_safe_mult_u32((i), 16U)))
#define gr_fecs_imemt_r(i)\ #define gr_fecs_imemt_r(i)\
(nvgpu_safe_add_u32(0x00409188U, nvgpu_safe_mult_u32((i), 16U))) (nvgpu_safe_add_u32(0x00409188U, nvgpu_safe_mult_u32((i), 16U)))
#define gr_fecs_imemt_tag_f(v) (((v)&0xffffU) << 0U) #define gr_fecs_imemt_tag_f(v) ((U32(v) & 0xffffU) << 0U)
#define gr_fecs_dmemc_r(i)\ #define gr_fecs_dmemc_r(i)\
(nvgpu_safe_add_u32(0x004091c0U, nvgpu_safe_mult_u32((i), 8U))) (nvgpu_safe_add_u32(0x004091c0U, nvgpu_safe_mult_u32((i), 8U)))
#define gr_fecs_dmemc_offs_s() (6U) #define gr_fecs_dmemc_offs_s() (6U)
#define gr_fecs_dmemc_offs_f(v) (((v)&0x3fU) << 2U) #define gr_fecs_dmemc_offs_f(v) ((U32(v) & 0x3fU) << 2U)
#define gr_fecs_dmemc_offs_m() (U32(0x3fU) << 2U) #define gr_fecs_dmemc_offs_m() (U32(0x3fU) << 2U)
#define gr_fecs_dmemc_offs_v(r) (((r) >> 2U) & 0x3fU) #define gr_fecs_dmemc_offs_v(r) (((r) >> 2U) & 0x3fU)
#define gr_fecs_dmemc_blk_f(v) (((v)&0xffU) << 8U) #define gr_fecs_dmemc_blk_f(v) ((U32(v) & 0xffU) << 8U)
#define gr_fecs_dmemc_aincw_f(v) (((v)&0x1U) << 24U) #define gr_fecs_dmemc_aincw_f(v) ((U32(v) & 0x1U) << 24U)
#define gr_fecs_dmemd_r(i)\ #define gr_fecs_dmemd_r(i)\
(nvgpu_safe_add_u32(0x004091c4U, nvgpu_safe_mult_u32((i), 8U))) (nvgpu_safe_add_u32(0x004091c4U, nvgpu_safe_mult_u32((i), 8U)))
#define gr_fecs_dmatrfbase_r() (0x00409110U) #define gr_fecs_dmatrfbase_r() (0x00409110U)
#define gr_fecs_dmatrfmoffs_r() (0x00409114U) #define gr_fecs_dmatrfmoffs_r() (0x00409114U)
#define gr_fecs_dmatrffboffs_r() (0x0040911cU) #define gr_fecs_dmatrffboffs_r() (0x0040911cU)
#define gr_fecs_dmatrfcmd_r() (0x00409118U) #define gr_fecs_dmatrfcmd_r() (0x00409118U)
#define gr_fecs_dmatrfcmd_imem_f(v) (((v)&0x1U) << 4U) #define gr_fecs_dmatrfcmd_imem_f(v) ((U32(v) & 0x1U) << 4U)
#define gr_fecs_dmatrfcmd_write_f(v) (((v)&0x1U) << 5U) #define gr_fecs_dmatrfcmd_write_f(v) ((U32(v) & 0x1U) << 5U)
#define gr_fecs_dmatrfcmd_size_f(v) (((v)&0x7U) << 8U) #define gr_fecs_dmatrfcmd_size_f(v) ((U32(v) & 0x7U) << 8U)
#define gr_fecs_dmatrfcmd_ctxdma_f(v) (((v)&0x7U) << 12U) #define gr_fecs_dmatrfcmd_ctxdma_f(v) ((U32(v) & 0x7U) << 12U)
#define gr_fecs_bootvec_r() (0x00409104U) #define gr_fecs_bootvec_r() (0x00409104U)
#define gr_fecs_bootvec_vec_f(v) (((v)&0xffffffffU) << 0U) #define gr_fecs_bootvec_vec_f(v) ((U32(v) & 0xffffffffU) << 0U)
#define gr_fecs_irqsset_r() (0x00409000U) #define gr_fecs_irqsset_r() (0x00409000U)
#define gr_fecs_falcon_hwcfg_r() (0x00409108U) #define gr_fecs_falcon_hwcfg_r() (0x00409108U)
#define gr_gpcs_gpccs_irqsset_r() (0x0041a000U) #define gr_gpcs_gpccs_irqsset_r() (0x0041a000U)
#define gr_gpcs_gpccs_falcon_hwcfg_r() (0x0041a108U) #define gr_gpcs_gpccs_falcon_hwcfg_r() (0x0041a108U)
#define gr_fecs_falcon_rm_r() (0x00409084U) #define gr_fecs_falcon_rm_r() (0x00409084U)
#define gr_fecs_current_ctx_r() (0x00409b00U) #define gr_fecs_current_ctx_r() (0x00409b00U)
#define gr_fecs_current_ctx_ptr_f(v) (((v)&0xfffffffU) << 0U) #define gr_fecs_current_ctx_ptr_f(v) ((U32(v) & 0xfffffffU) << 0U)
#define gr_fecs_current_ctx_ptr_v(r) (((r) >> 0U) & 0xfffffffU) #define gr_fecs_current_ctx_ptr_v(r) (((r) >> 0U) & 0xfffffffU)
#define gr_fecs_current_ctx_target_s() (2U) #define gr_fecs_current_ctx_target_s() (2U)
#define gr_fecs_current_ctx_target_f(v) (((v)&0x3U) << 28U) #define gr_fecs_current_ctx_target_f(v) ((U32(v) & 0x3U) << 28U)
#define gr_fecs_current_ctx_target_m() (U32(0x3U) << 28U) #define gr_fecs_current_ctx_target_m() (U32(0x3U) << 28U)
#define gr_fecs_current_ctx_target_v(r) (((r) >> 28U) & 0x3U) #define gr_fecs_current_ctx_target_v(r) (((r) >> 28U) & 0x3U)
#define gr_fecs_current_ctx_target_vid_mem_f() (0x0U) #define gr_fecs_current_ctx_target_vid_mem_f() (0x0U)
#define gr_fecs_current_ctx_target_sys_mem_coh_f() (0x20000000U) #define gr_fecs_current_ctx_target_sys_mem_coh_f() (0x20000000U)
#define gr_fecs_current_ctx_target_sys_mem_ncoh_f() (0x30000000U) #define gr_fecs_current_ctx_target_sys_mem_ncoh_f() (0x30000000U)
#define gr_fecs_current_ctx_valid_s() (1U) #define gr_fecs_current_ctx_valid_s() (1U)
#define gr_fecs_current_ctx_valid_f(v) (((v)&0x1U) << 31U) #define gr_fecs_current_ctx_valid_f(v) ((U32(v) & 0x1U) << 31U)
#define gr_fecs_current_ctx_valid_m() (U32(0x1U) << 31U) #define gr_fecs_current_ctx_valid_m() (U32(0x1U) << 31U)
#define gr_fecs_current_ctx_valid_v(r) (((r) >> 31U) & 0x1U) #define gr_fecs_current_ctx_valid_v(r) (((r) >> 31U) & 0x1U)
#define gr_fecs_current_ctx_valid_false_f() (0x0U) #define gr_fecs_current_ctx_valid_false_f() (0x0U)
#define gr_fecs_method_data_r() (0x00409500U) #define gr_fecs_method_data_r() (0x00409500U)
#define gr_fecs_method_push_r() (0x00409504U) #define gr_fecs_method_push_r() (0x00409504U)
#define gr_fecs_method_push_adr_f(v) (((v)&0xfffU) << 0U) #define gr_fecs_method_push_adr_f(v) ((U32(v) & 0xfffU) << 0U)
#define gr_fecs_method_push_adr_bind_pointer_v() (0x00000003U) #define gr_fecs_method_push_adr_bind_pointer_v() (0x00000003U)
#define gr_fecs_method_push_adr_bind_pointer_f() (0x3U) #define gr_fecs_method_push_adr_bind_pointer_f() (0x3U)
#define gr_fecs_method_push_adr_discover_image_size_v() (0x00000010U) #define gr_fecs_method_push_adr_discover_image_size_v() (0x00000010U)
@@ -298,13 +298,15 @@
#define gr_fecs_method_push_adr_write_timestamp_record_v() (0x0000003dU) #define gr_fecs_method_push_adr_write_timestamp_record_v() (0x0000003dU)
#define gr_fecs_method_push_adr_halt_pipeline_v() (0x00000004U) #define gr_fecs_method_push_adr_halt_pipeline_v() (0x00000004U)
#define gr_fecs_host_int_status_r() (0x00409c18U) #define gr_fecs_host_int_status_r() (0x00409c18U)
#define gr_fecs_host_int_status_fault_during_ctxsw_f(v) (((v)&0x1U) << 16U) #define gr_fecs_host_int_status_fault_during_ctxsw_f(v) ((U32(v) & 0x1U) << 16U)
#define gr_fecs_host_int_status_umimp_firmware_method_f(v) (((v)&0x1U) << 17U) #define gr_fecs_host_int_status_umimp_firmware_method_f(v)\
#define gr_fecs_host_int_status_umimp_illegal_method_f(v) (((v)&0x1U) << 18U) ((U32(v) & 0x1U) << 17U)
#define gr_fecs_host_int_status_umimp_illegal_method_f(v)\
((U32(v) & 0x1U) << 18U)
#define gr_fecs_host_int_status_watchdog_active_f() (0x80000U) #define gr_fecs_host_int_status_watchdog_active_f() (0x80000U)
#define gr_fecs_host_int_status_ctxsw_intr_f(v) (((v)&0xffffU) << 0U) #define gr_fecs_host_int_status_ctxsw_intr_f(v) ((U32(v) & 0xffffU) << 0U)
#define gr_fecs_host_int_clear_r() (0x00409c20U) #define gr_fecs_host_int_clear_r() (0x00409c20U)
#define gr_fecs_host_int_clear_ctxsw_intr1_f(v) (((v)&0x1U) << 1U) #define gr_fecs_host_int_clear_ctxsw_intr1_f(v) ((U32(v) & 0x1U) << 1U)
#define gr_fecs_host_int_clear_ctxsw_intr1_clear_f() (0x2U) #define gr_fecs_host_int_clear_ctxsw_intr1_clear_f() (0x2U)
#define gr_fecs_host_int_enable_r() (0x00409c24U) #define gr_fecs_host_int_enable_r() (0x00409c24U)
#define gr_fecs_host_int_enable_ctxsw_intr1_enable_f() (0x2U) #define gr_fecs_host_int_enable_ctxsw_intr1_enable_f() (0x2U)
@@ -324,7 +326,7 @@
#define gr_fecs_ctxsw_reset_ctl_gpc_context_reset_enabled_f() (0x0U) #define gr_fecs_ctxsw_reset_ctl_gpc_context_reset_enabled_f() (0x0U)
#define gr_fecs_ctxsw_reset_ctl_gpc_context_reset_disabled_f() (0x200U) #define gr_fecs_ctxsw_reset_ctl_gpc_context_reset_disabled_f() (0x200U)
#define gr_fecs_ctxsw_reset_ctl_be_context_reset_s() (1U) #define gr_fecs_ctxsw_reset_ctl_be_context_reset_s() (1U)
#define gr_fecs_ctxsw_reset_ctl_be_context_reset_f(v) (((v)&0x1U) << 10U) #define gr_fecs_ctxsw_reset_ctl_be_context_reset_f(v) ((U32(v) & 0x1U) << 10U)
#define gr_fecs_ctxsw_reset_ctl_be_context_reset_m() (U32(0x1U) << 10U) #define gr_fecs_ctxsw_reset_ctl_be_context_reset_m() (U32(0x1U) << 10U)
#define gr_fecs_ctxsw_reset_ctl_be_context_reset_v(r) (((r) >> 10U) & 0x1U) #define gr_fecs_ctxsw_reset_ctl_be_context_reset_v(r) (((r) >> 10U) & 0x1U)
#define gr_fecs_ctxsw_reset_ctl_be_context_reset_enabled_f() (0x0U) #define gr_fecs_ctxsw_reset_ctl_be_context_reset_enabled_f() (0x0U)
@@ -333,60 +335,60 @@
#define gr_fecs_ctxsw_mailbox_r(i)\ #define gr_fecs_ctxsw_mailbox_r(i)\
(nvgpu_safe_add_u32(0x00409800U, nvgpu_safe_mult_u32((i), 4U))) (nvgpu_safe_add_u32(0x00409800U, nvgpu_safe_mult_u32((i), 4U)))
#define gr_fecs_ctxsw_mailbox__size_1_v() (0x00000010U) #define gr_fecs_ctxsw_mailbox__size_1_v() (0x00000010U)
#define gr_fecs_ctxsw_mailbox_value_f(v) (((v)&0xffffffffU) << 0U) #define gr_fecs_ctxsw_mailbox_value_f(v) ((U32(v) & 0xffffffffU) << 0U)
#define gr_fecs_ctxsw_mailbox_value_pass_v() (0x00000001U) #define gr_fecs_ctxsw_mailbox_value_pass_v() (0x00000001U)
#define gr_fecs_ctxsw_mailbox_value_fail_v() (0x00000002U) #define gr_fecs_ctxsw_mailbox_value_fail_v() (0x00000002U)
#define gr_fecs_ctxsw_mailbox_set_r(i)\ #define gr_fecs_ctxsw_mailbox_set_r(i)\
(nvgpu_safe_add_u32(0x004098c0U, nvgpu_safe_mult_u32((i), 4U))) (nvgpu_safe_add_u32(0x004098c0U, nvgpu_safe_mult_u32((i), 4U)))
#define gr_fecs_ctxsw_mailbox_set_value_f(v) (((v)&0xffffffffU) << 0U) #define gr_fecs_ctxsw_mailbox_set_value_f(v) ((U32(v) & 0xffffffffU) << 0U)
#define gr_fecs_ctxsw_mailbox_clear_r(i)\ #define gr_fecs_ctxsw_mailbox_clear_r(i)\
(nvgpu_safe_add_u32(0x00409840U, nvgpu_safe_mult_u32((i), 4U))) (nvgpu_safe_add_u32(0x00409840U, nvgpu_safe_mult_u32((i), 4U)))
#define gr_fecs_ctxsw_mailbox_clear_value_f(v) (((v)&0xffffffffU) << 0U) #define gr_fecs_ctxsw_mailbox_clear_value_f(v) ((U32(v) & 0xffffffffU) << 0U)
#define gr_fecs_fs_r() (0x00409604U) #define gr_fecs_fs_r() (0x00409604U)
#define gr_fecs_fs_num_available_gpcs_s() (5U) #define gr_fecs_fs_num_available_gpcs_s() (5U)
#define gr_fecs_fs_num_available_gpcs_f(v) (((v)&0x1fU) << 0U) #define gr_fecs_fs_num_available_gpcs_f(v) ((U32(v) & 0x1fU) << 0U)
#define gr_fecs_fs_num_available_gpcs_m() (U32(0x1fU) << 0U) #define gr_fecs_fs_num_available_gpcs_m() (U32(0x1fU) << 0U)
#define gr_fecs_fs_num_available_gpcs_v(r) (((r) >> 0U) & 0x1fU) #define gr_fecs_fs_num_available_gpcs_v(r) (((r) >> 0U) & 0x1fU)
#define gr_fecs_fs_num_available_fbps_s() (5U) #define gr_fecs_fs_num_available_fbps_s() (5U)
#define gr_fecs_fs_num_available_fbps_f(v) (((v)&0x1fU) << 16U) #define gr_fecs_fs_num_available_fbps_f(v) ((U32(v) & 0x1fU) << 16U)
#define gr_fecs_fs_num_available_fbps_m() (U32(0x1fU) << 16U) #define gr_fecs_fs_num_available_fbps_m() (U32(0x1fU) << 16U)
#define gr_fecs_fs_num_available_fbps_v(r) (((r) >> 16U) & 0x1fU) #define gr_fecs_fs_num_available_fbps_v(r) (((r) >> 16U) & 0x1fU)
#define gr_fecs_cfg_r() (0x00409620U) #define gr_fecs_cfg_r() (0x00409620U)
#define gr_fecs_cfg_imem_sz_v(r) (((r) >> 0U) & 0xffU) #define gr_fecs_cfg_imem_sz_v(r) (((r) >> 0U) & 0xffU)
#define gr_fecs_rc_lanes_r() (0x00409880U) #define gr_fecs_rc_lanes_r() (0x00409880U)
#define gr_fecs_rc_lanes_num_chains_s() (6U) #define gr_fecs_rc_lanes_num_chains_s() (6U)
#define gr_fecs_rc_lanes_num_chains_f(v) (((v)&0x3fU) << 0U) #define gr_fecs_rc_lanes_num_chains_f(v) ((U32(v) & 0x3fU) << 0U)
#define gr_fecs_rc_lanes_num_chains_m() (U32(0x3fU) << 0U) #define gr_fecs_rc_lanes_num_chains_m() (U32(0x3fU) << 0U)
#define gr_fecs_rc_lanes_num_chains_v(r) (((r) >> 0U) & 0x3fU) #define gr_fecs_rc_lanes_num_chains_v(r) (((r) >> 0U) & 0x3fU)
#define gr_fecs_ctxsw_status_1_r() (0x00409400U) #define gr_fecs_ctxsw_status_1_r() (0x00409400U)
#define gr_fecs_ctxsw_status_1_arb_busy_s() (1U) #define gr_fecs_ctxsw_status_1_arb_busy_s() (1U)
#define gr_fecs_ctxsw_status_1_arb_busy_f(v) (((v)&0x1U) << 12U) #define gr_fecs_ctxsw_status_1_arb_busy_f(v) ((U32(v) & 0x1U) << 12U)
#define gr_fecs_ctxsw_status_1_arb_busy_m() (U32(0x1U) << 12U) #define gr_fecs_ctxsw_status_1_arb_busy_m() (U32(0x1U) << 12U)
#define gr_fecs_ctxsw_status_1_arb_busy_v(r) (((r) >> 12U) & 0x1U) #define gr_fecs_ctxsw_status_1_arb_busy_v(r) (((r) >> 12U) & 0x1U)
#define gr_fecs_arb_ctx_adr_r() (0x00409a24U) #define gr_fecs_arb_ctx_adr_r() (0x00409a24U)
#define gr_fecs_new_ctx_r() (0x00409b04U) #define gr_fecs_new_ctx_r() (0x00409b04U)
#define gr_fecs_new_ctx_ptr_s() (28U) #define gr_fecs_new_ctx_ptr_s() (28U)
#define gr_fecs_new_ctx_ptr_f(v) (((v)&0xfffffffU) << 0U) #define gr_fecs_new_ctx_ptr_f(v) ((U32(v) & 0xfffffffU) << 0U)
#define gr_fecs_new_ctx_ptr_m() (U32(0xfffffffU) << 0U) #define gr_fecs_new_ctx_ptr_m() (U32(0xfffffffU) << 0U)
#define gr_fecs_new_ctx_ptr_v(r) (((r) >> 0U) & 0xfffffffU) #define gr_fecs_new_ctx_ptr_v(r) (((r) >> 0U) & 0xfffffffU)
#define gr_fecs_new_ctx_target_s() (2U) #define gr_fecs_new_ctx_target_s() (2U)
#define gr_fecs_new_ctx_target_f(v) (((v)&0x3U) << 28U) #define gr_fecs_new_ctx_target_f(v) ((U32(v) & 0x3U) << 28U)
#define gr_fecs_new_ctx_target_m() (U32(0x3U) << 28U) #define gr_fecs_new_ctx_target_m() (U32(0x3U) << 28U)
#define gr_fecs_new_ctx_target_v(r) (((r) >> 28U) & 0x3U) #define gr_fecs_new_ctx_target_v(r) (((r) >> 28U) & 0x3U)
#define gr_fecs_new_ctx_target_vid_mem_f() (0x0U) #define gr_fecs_new_ctx_target_vid_mem_f() (0x0U)
#define gr_fecs_new_ctx_target_sys_mem_ncoh_f() (0x30000000U) #define gr_fecs_new_ctx_target_sys_mem_ncoh_f() (0x30000000U)
#define gr_fecs_new_ctx_target_sys_mem_coh_f() (0x20000000U) #define gr_fecs_new_ctx_target_sys_mem_coh_f() (0x20000000U)
#define gr_fecs_new_ctx_valid_s() (1U) #define gr_fecs_new_ctx_valid_s() (1U)
#define gr_fecs_new_ctx_valid_f(v) (((v)&0x1U) << 31U) #define gr_fecs_new_ctx_valid_f(v) ((U32(v) & 0x1U) << 31U)
#define gr_fecs_new_ctx_valid_m() (U32(0x1U) << 31U) #define gr_fecs_new_ctx_valid_m() (U32(0x1U) << 31U)
#define gr_fecs_new_ctx_valid_v(r) (((r) >> 31U) & 0x1U) #define gr_fecs_new_ctx_valid_v(r) (((r) >> 31U) & 0x1U)
#define gr_fecs_arb_ctx_ptr_r() (0x00409a0cU) #define gr_fecs_arb_ctx_ptr_r() (0x00409a0cU)
#define gr_fecs_arb_ctx_ptr_ptr_s() (28U) #define gr_fecs_arb_ctx_ptr_ptr_s() (28U)
#define gr_fecs_arb_ctx_ptr_ptr_f(v) (((v)&0xfffffffU) << 0U) #define gr_fecs_arb_ctx_ptr_ptr_f(v) ((U32(v) & 0xfffffffU) << 0U)
#define gr_fecs_arb_ctx_ptr_ptr_m() (U32(0xfffffffU) << 0U) #define gr_fecs_arb_ctx_ptr_ptr_m() (U32(0xfffffffU) << 0U)
#define gr_fecs_arb_ctx_ptr_ptr_v(r) (((r) >> 0U) & 0xfffffffU) #define gr_fecs_arb_ctx_ptr_ptr_v(r) (((r) >> 0U) & 0xfffffffU)
#define gr_fecs_arb_ctx_ptr_target_s() (2U) #define gr_fecs_arb_ctx_ptr_target_s() (2U)
#define gr_fecs_arb_ctx_ptr_target_f(v) (((v)&0x3U) << 28U) #define gr_fecs_arb_ctx_ptr_target_f(v) ((U32(v) & 0x3U) << 28U)
#define gr_fecs_arb_ctx_ptr_target_m() (U32(0x3U) << 28U) #define gr_fecs_arb_ctx_ptr_target_m() (U32(0x3U) << 28U)
#define gr_fecs_arb_ctx_ptr_target_v(r) (((r) >> 28U) & 0x3U) #define gr_fecs_arb_ctx_ptr_target_v(r) (((r) >> 28U) & 0x3U)
#define gr_fecs_arb_ctx_ptr_target_vid_mem_f() (0x0U) #define gr_fecs_arb_ctx_ptr_target_vid_mem_f() (0x0U)
@@ -394,7 +396,7 @@
#define gr_fecs_arb_ctx_ptr_target_sys_mem_coh_f() (0x20000000U) #define gr_fecs_arb_ctx_ptr_target_sys_mem_coh_f() (0x20000000U)
#define gr_fecs_arb_ctx_cmd_r() (0x00409a10U) #define gr_fecs_arb_ctx_cmd_r() (0x00409a10U)
#define gr_fecs_arb_ctx_cmd_cmd_s() (5U) #define gr_fecs_arb_ctx_cmd_cmd_s() (5U)
#define gr_fecs_arb_ctx_cmd_cmd_f(v) (((v)&0x1fU) << 0U) #define gr_fecs_arb_ctx_cmd_cmd_f(v) ((U32(v) & 0x1fU) << 0U)
#define gr_fecs_arb_ctx_cmd_cmd_m() (U32(0x1fU) << 0U) #define gr_fecs_arb_ctx_cmd_cmd_m() (U32(0x1fU) << 0U)
#define gr_fecs_arb_ctx_cmd_cmd_v(r) (((r) >> 0U) & 0x1fU) #define gr_fecs_arb_ctx_cmd_cmd_v(r) (((r) >> 0U) & 0x1fU)
#define gr_fecs_ctxsw_status_fe_0_r() (0x00409c00U) #define gr_fecs_ctxsw_status_fe_0_r() (0x00409c00U)
@@ -409,58 +411,58 @@
#define gr_rstr2d_gpc_map4_r() (0x0040781cU) #define gr_rstr2d_gpc_map4_r() (0x0040781cU)
#define gr_rstr2d_gpc_map5_r() (0x00407820U) #define gr_rstr2d_gpc_map5_r() (0x00407820U)
#define gr_rstr2d_map_table_cfg_r() (0x004078bcU) #define gr_rstr2d_map_table_cfg_r() (0x004078bcU)
#define gr_rstr2d_map_table_cfg_row_offset_f(v) (((v)&0xffU) << 0U) #define gr_rstr2d_map_table_cfg_row_offset_f(v) ((U32(v) & 0xffU) << 0U)
#define gr_rstr2d_map_table_cfg_num_entries_f(v) (((v)&0xffU) << 8U) #define gr_rstr2d_map_table_cfg_num_entries_f(v) ((U32(v) & 0xffU) << 8U)
#define gr_pd_hww_esr_r() (0x00406018U) #define gr_pd_hww_esr_r() (0x00406018U)
#define gr_pd_hww_esr_reset_active_f() (0x40000000U) #define gr_pd_hww_esr_reset_active_f() (0x40000000U)
#define gr_pd_hww_esr_en_enable_f() (0x80000000U) #define gr_pd_hww_esr_en_enable_f() (0x80000000U)
#define gr_pd_num_tpc_per_gpc_r(i)\ #define gr_pd_num_tpc_per_gpc_r(i)\
(nvgpu_safe_add_u32(0x00406028U, nvgpu_safe_mult_u32((i), 4U))) (nvgpu_safe_add_u32(0x00406028U, nvgpu_safe_mult_u32((i), 4U)))
#define gr_pd_num_tpc_per_gpc__size_1_v() (0x00000004U) #define gr_pd_num_tpc_per_gpc__size_1_v() (0x00000004U)
#define gr_pd_num_tpc_per_gpc_count0_f(v) (((v)&0xfU) << 0U) #define gr_pd_num_tpc_per_gpc_count0_f(v) ((U32(v) & 0xfU) << 0U)
#define gr_pd_num_tpc_per_gpc_count1_f(v) (((v)&0xfU) << 4U) #define gr_pd_num_tpc_per_gpc_count1_f(v) ((U32(v) & 0xfU) << 4U)
#define gr_pd_num_tpc_per_gpc_count2_f(v) (((v)&0xfU) << 8U) #define gr_pd_num_tpc_per_gpc_count2_f(v) ((U32(v) & 0xfU) << 8U)
#define gr_pd_num_tpc_per_gpc_count3_f(v) (((v)&0xfU) << 12U) #define gr_pd_num_tpc_per_gpc_count3_f(v) ((U32(v) & 0xfU) << 12U)
#define gr_pd_num_tpc_per_gpc_count4_f(v) (((v)&0xfU) << 16U) #define gr_pd_num_tpc_per_gpc_count4_f(v) ((U32(v) & 0xfU) << 16U)
#define gr_pd_num_tpc_per_gpc_count5_f(v) (((v)&0xfU) << 20U) #define gr_pd_num_tpc_per_gpc_count5_f(v) ((U32(v) & 0xfU) << 20U)
#define gr_pd_num_tpc_per_gpc_count6_f(v) (((v)&0xfU) << 24U) #define gr_pd_num_tpc_per_gpc_count6_f(v) ((U32(v) & 0xfU) << 24U)
#define gr_pd_num_tpc_per_gpc_count7_f(v) (((v)&0xfU) << 28U) #define gr_pd_num_tpc_per_gpc_count7_f(v) ((U32(v) & 0xfU) << 28U)
#define gr_pd_ab_dist_cfg0_r() (0x004064c0U) #define gr_pd_ab_dist_cfg0_r() (0x004064c0U)
#define gr_pd_ab_dist_cfg0_timeslice_enable_en_f() (0x80000000U) #define gr_pd_ab_dist_cfg0_timeslice_enable_en_f() (0x80000000U)
#define gr_pd_ab_dist_cfg0_timeslice_enable_dis_f() (0x0U) #define gr_pd_ab_dist_cfg0_timeslice_enable_dis_f() (0x0U)
#define gr_pd_ab_dist_cfg1_r() (0x004064c4U) #define gr_pd_ab_dist_cfg1_r() (0x004064c4U)
#define gr_pd_ab_dist_cfg1_max_batches_init_f() (0xffffU) #define gr_pd_ab_dist_cfg1_max_batches_init_f() (0xffffU)
#define gr_pd_ab_dist_cfg1_max_output_f(v) (((v)&0xffffU) << 16U) #define gr_pd_ab_dist_cfg1_max_output_f(v) ((U32(v) & 0xffffU) << 16U)
#define gr_pd_ab_dist_cfg1_max_output_granularity_v() (0x00000080U) #define gr_pd_ab_dist_cfg1_max_output_granularity_v() (0x00000080U)
#define gr_pd_ab_dist_cfg2_r() (0x004064c8U) #define gr_pd_ab_dist_cfg2_r() (0x004064c8U)
#define gr_pd_ab_dist_cfg2_token_limit_f(v) (((v)&0xfffU) << 0U) #define gr_pd_ab_dist_cfg2_token_limit_f(v) ((U32(v) & 0xfffU) << 0U)
#define gr_pd_ab_dist_cfg2_token_limit_init_v() (0x000001c0U) #define gr_pd_ab_dist_cfg2_token_limit_init_v() (0x000001c0U)
#define gr_pd_ab_dist_cfg2_state_limit_f(v) (((v)&0xfffU) << 16U) #define gr_pd_ab_dist_cfg2_state_limit_f(v) ((U32(v) & 0xfffU) << 16U)
#define gr_pd_ab_dist_cfg2_state_limit_scc_bundle_granularity_v() (0x00000020U) #define gr_pd_ab_dist_cfg2_state_limit_scc_bundle_granularity_v() (0x00000020U)
#define gr_pd_ab_dist_cfg2_state_limit_min_gpm_fifo_depths_v() (0x00000182U) #define gr_pd_ab_dist_cfg2_state_limit_min_gpm_fifo_depths_v() (0x00000182U)
#define gr_pd_pagepool_r() (0x004064ccU) #define gr_pd_pagepool_r() (0x004064ccU)
#define gr_pd_pagepool_total_pages_f(v) (((v)&0xffU) << 0U) #define gr_pd_pagepool_total_pages_f(v) ((U32(v) & 0xffU) << 0U)
#define gr_pd_pagepool_valid_true_f() (0x80000000U) #define gr_pd_pagepool_valid_true_f() (0x80000000U)
#define gr_pd_dist_skip_table_r(i)\ #define gr_pd_dist_skip_table_r(i)\
(nvgpu_safe_add_u32(0x004064d0U, nvgpu_safe_mult_u32((i), 4U))) (nvgpu_safe_add_u32(0x004064d0U, nvgpu_safe_mult_u32((i), 4U)))
#define gr_pd_dist_skip_table__size_1_v() (0x00000008U) #define gr_pd_dist_skip_table__size_1_v() (0x00000008U)
#define gr_pd_dist_skip_table_gpc_4n0_mask_f(v) (((v)&0xffU) << 0U) #define gr_pd_dist_skip_table_gpc_4n0_mask_f(v) ((U32(v) & 0xffU) << 0U)
#define gr_pd_dist_skip_table_gpc_4n1_mask_f(v) (((v)&0xffU) << 8U) #define gr_pd_dist_skip_table_gpc_4n1_mask_f(v) ((U32(v) & 0xffU) << 8U)
#define gr_pd_dist_skip_table_gpc_4n2_mask_f(v) (((v)&0xffU) << 16U) #define gr_pd_dist_skip_table_gpc_4n2_mask_f(v) ((U32(v) & 0xffU) << 16U)
#define gr_pd_dist_skip_table_gpc_4n3_mask_f(v) (((v)&0xffU) << 24U) #define gr_pd_dist_skip_table_gpc_4n3_mask_f(v) ((U32(v) & 0xffU) << 24U)
#define gr_ds_debug_r() (0x00405800U) #define gr_ds_debug_r() (0x00405800U)
#define gr_ds_debug_timeslice_mode_disable_f() (0x0U) #define gr_ds_debug_timeslice_mode_disable_f() (0x0U)
#define gr_ds_debug_timeslice_mode_enable_f() (0x8000000U) #define gr_ds_debug_timeslice_mode_enable_f() (0x8000000U)
#define gr_ds_zbc_color_r_r() (0x00405804U) #define gr_ds_zbc_color_r_r() (0x00405804U)
#define gr_ds_zbc_color_r_val_f(v) (((v)&0xffffffffU) << 0U) #define gr_ds_zbc_color_r_val_f(v) ((U32(v) & 0xffffffffU) << 0U)
#define gr_ds_zbc_color_g_r() (0x00405808U) #define gr_ds_zbc_color_g_r() (0x00405808U)
#define gr_ds_zbc_color_g_val_f(v) (((v)&0xffffffffU) << 0U) #define gr_ds_zbc_color_g_val_f(v) ((U32(v) & 0xffffffffU) << 0U)
#define gr_ds_zbc_color_b_r() (0x0040580cU) #define gr_ds_zbc_color_b_r() (0x0040580cU)
#define gr_ds_zbc_color_b_val_f(v) (((v)&0xffffffffU) << 0U) #define gr_ds_zbc_color_b_val_f(v) ((U32(v) & 0xffffffffU) << 0U)
#define gr_ds_zbc_color_a_r() (0x00405810U) #define gr_ds_zbc_color_a_r() (0x00405810U)
#define gr_ds_zbc_color_a_val_f(v) (((v)&0xffffffffU) << 0U) #define gr_ds_zbc_color_a_val_f(v) ((U32(v) & 0xffffffffU) << 0U)
#define gr_ds_zbc_color_fmt_r() (0x00405814U) #define gr_ds_zbc_color_fmt_r() (0x00405814U)
#define gr_ds_zbc_color_fmt_val_f(v) (((v)&0x7fU) << 0U) #define gr_ds_zbc_color_fmt_val_f(v) ((U32(v) & 0x7fU) << 0U)
#define gr_ds_zbc_color_fmt_val_invalid_f() (0x0U) #define gr_ds_zbc_color_fmt_val_invalid_f() (0x0U)
#define gr_ds_zbc_color_fmt_val_zero_v() (0x00000001U) #define gr_ds_zbc_color_fmt_val_zero_v() (0x00000001U)
#define gr_ds_zbc_color_fmt_val_unorm_one_v() (0x00000002U) #define gr_ds_zbc_color_fmt_val_unorm_one_v() (0x00000002U)
@@ -468,28 +470,28 @@
#define gr_ds_zbc_color_fmt_val_a8_b8_g8_r8_v() (0x00000028U) #define gr_ds_zbc_color_fmt_val_a8_b8_g8_r8_v() (0x00000028U)
#define gr_ds_zbc_z_r() (0x00405818U) #define gr_ds_zbc_z_r() (0x00405818U)
#define gr_ds_zbc_z_val_s() (32U) #define gr_ds_zbc_z_val_s() (32U)
#define gr_ds_zbc_z_val_f(v) (((v)&0xffffffffU) << 0U) #define gr_ds_zbc_z_val_f(v) ((U32(v) & 0xffffffffU) << 0U)
#define gr_ds_zbc_z_val_m() (U32(0xffffffffU) << 0U) #define gr_ds_zbc_z_val_m() (U32(0xffffffffU) << 0U)
#define gr_ds_zbc_z_val_v(r) (((r) >> 0U) & 0xffffffffU) #define gr_ds_zbc_z_val_v(r) (((r) >> 0U) & 0xffffffffU)
#define gr_ds_zbc_z_val__init_v() (0x00000000U) #define gr_ds_zbc_z_val__init_v() (0x00000000U)
#define gr_ds_zbc_z_val__init_f() (0x0U) #define gr_ds_zbc_z_val__init_f() (0x0U)
#define gr_ds_zbc_z_fmt_r() (0x0040581cU) #define gr_ds_zbc_z_fmt_r() (0x0040581cU)
#define gr_ds_zbc_z_fmt_val_f(v) (((v)&0x1U) << 0U) #define gr_ds_zbc_z_fmt_val_f(v) ((U32(v) & 0x1U) << 0U)
#define gr_ds_zbc_z_fmt_val_invalid_f() (0x0U) #define gr_ds_zbc_z_fmt_val_invalid_f() (0x0U)
#define gr_ds_zbc_z_fmt_val_fp32_v() (0x00000001U) #define gr_ds_zbc_z_fmt_val_fp32_v() (0x00000001U)
#define gr_ds_zbc_tbl_index_r() (0x00405820U) #define gr_ds_zbc_tbl_index_r() (0x00405820U)
#define gr_ds_zbc_tbl_index_val_f(v) (((v)&0xfU) << 0U) #define gr_ds_zbc_tbl_index_val_f(v) ((U32(v) & 0xfU) << 0U)
#define gr_ds_zbc_tbl_ld_r() (0x00405824U) #define gr_ds_zbc_tbl_ld_r() (0x00405824U)
#define gr_ds_zbc_tbl_ld_select_c_f() (0x0U) #define gr_ds_zbc_tbl_ld_select_c_f() (0x0U)
#define gr_ds_zbc_tbl_ld_select_z_f() (0x1U) #define gr_ds_zbc_tbl_ld_select_z_f() (0x1U)
#define gr_ds_zbc_tbl_ld_action_write_f() (0x0U) #define gr_ds_zbc_tbl_ld_action_write_f() (0x0U)
#define gr_ds_zbc_tbl_ld_trigger_active_f() (0x4U) #define gr_ds_zbc_tbl_ld_trigger_active_f() (0x4U)
#define gr_ds_tga_constraintlogic_r() (0x00405830U) #define gr_ds_tga_constraintlogic_r() (0x00405830U)
#define gr_ds_tga_constraintlogic_beta_cbsize_f(v) (((v)&0xffffU) << 16U) #define gr_ds_tga_constraintlogic_beta_cbsize_f(v) ((U32(v) & 0xffffU) << 16U)
#define gr_ds_tga_constraintlogic_alpha_cbsize_f(v) (((v)&0xffffU) << 0U) #define gr_ds_tga_constraintlogic_alpha_cbsize_f(v) ((U32(v) & 0xffffU) << 0U)
#define gr_ds_hww_esr_r() (0x00405840U) #define gr_ds_hww_esr_r() (0x00405840U)
#define gr_ds_hww_esr_reset_s() (1U) #define gr_ds_hww_esr_reset_s() (1U)
#define gr_ds_hww_esr_reset_f(v) (((v)&0x1U) << 30U) #define gr_ds_hww_esr_reset_f(v) ((U32(v) & 0x1U) << 30U)
#define gr_ds_hww_esr_reset_m() (U32(0x1U) << 30U) #define gr_ds_hww_esr_reset_m() (U32(0x1U) << 30U)
#define gr_ds_hww_esr_reset_v(r) (((r) >> 30U) & 0x1U) #define gr_ds_hww_esr_reset_v(r) (((r) >> 30U) & 0x1U)
#define gr_ds_hww_esr_reset_task_v() (0x00000001U) #define gr_ds_hww_esr_reset_task_v() (0x00000001U)
@@ -497,7 +499,7 @@
#define gr_ds_hww_esr_en_enabled_f() (0x80000000U) #define gr_ds_hww_esr_en_enabled_f() (0x80000000U)
#define gr_ds_hww_esr_2_r() (0x00405848U) #define gr_ds_hww_esr_2_r() (0x00405848U)
#define gr_ds_hww_esr_2_reset_s() (1U) #define gr_ds_hww_esr_2_reset_s() (1U)
#define gr_ds_hww_esr_2_reset_f(v) (((v)&0x1U) << 30U) #define gr_ds_hww_esr_2_reset_f(v) ((U32(v) & 0x1U) << 30U)
#define gr_ds_hww_esr_2_reset_m() (U32(0x1U) << 30U) #define gr_ds_hww_esr_2_reset_m() (U32(0x1U) << 30U)
#define gr_ds_hww_esr_2_reset_v(r) (((r) >> 30U) & 0x1U) #define gr_ds_hww_esr_2_reset_v(r) (((r) >> 30U) & 0x1U)
#define gr_ds_hww_esr_2_reset_task_v() (0x00000001U) #define gr_ds_hww_esr_2_reset_task_v() (0x00000001U)
@@ -533,25 +535,25 @@
#define gr_ds_num_tpc_per_gpc_r(i)\ #define gr_ds_num_tpc_per_gpc_r(i)\
(nvgpu_safe_add_u32(0x00405870U, nvgpu_safe_mult_u32((i), 4U))) (nvgpu_safe_add_u32(0x00405870U, nvgpu_safe_mult_u32((i), 4U)))
#define gr_scc_bundle_cb_base_r() (0x00408004U) #define gr_scc_bundle_cb_base_r() (0x00408004U)
#define gr_scc_bundle_cb_base_addr_39_8_f(v) (((v)&0xffffffffU) << 0U) #define gr_scc_bundle_cb_base_addr_39_8_f(v) ((U32(v) & 0xffffffffU) << 0U)
#define gr_scc_bundle_cb_base_addr_39_8_align_bits_v() (0x00000008U) #define gr_scc_bundle_cb_base_addr_39_8_align_bits_v() (0x00000008U)
#define gr_scc_bundle_cb_size_r() (0x00408008U) #define gr_scc_bundle_cb_size_r() (0x00408008U)
#define gr_scc_bundle_cb_size_div_256b_f(v) (((v)&0x7ffU) << 0U) #define gr_scc_bundle_cb_size_div_256b_f(v) ((U32(v) & 0x7ffU) << 0U)
#define gr_scc_bundle_cb_size_div_256b__prod_v() (0x00000018U) #define gr_scc_bundle_cb_size_div_256b__prod_v() (0x00000018U)
#define gr_scc_bundle_cb_size_div_256b_byte_granularity_v() (0x00000100U) #define gr_scc_bundle_cb_size_div_256b_byte_granularity_v() (0x00000100U)
#define gr_scc_bundle_cb_size_valid_false_v() (0x00000000U) #define gr_scc_bundle_cb_size_valid_false_v() (0x00000000U)
#define gr_scc_bundle_cb_size_valid_false_f() (0x0U) #define gr_scc_bundle_cb_size_valid_false_f() (0x0U)
#define gr_scc_bundle_cb_size_valid_true_f() (0x80000000U) #define gr_scc_bundle_cb_size_valid_true_f() (0x80000000U)
#define gr_scc_pagepool_base_r() (0x0040800cU) #define gr_scc_pagepool_base_r() (0x0040800cU)
#define gr_scc_pagepool_base_addr_39_8_f(v) (((v)&0xffffffffU) << 0U) #define gr_scc_pagepool_base_addr_39_8_f(v) ((U32(v) & 0xffffffffU) << 0U)
#define gr_scc_pagepool_base_addr_39_8_align_bits_v() (0x00000008U) #define gr_scc_pagepool_base_addr_39_8_align_bits_v() (0x00000008U)
#define gr_scc_pagepool_r() (0x00408010U) #define gr_scc_pagepool_r() (0x00408010U)
#define gr_scc_pagepool_total_pages_f(v) (((v)&0xffU) << 0U) #define gr_scc_pagepool_total_pages_f(v) ((U32(v) & 0xffU) << 0U)
#define gr_scc_pagepool_total_pages_hwmax_v() (0x00000000U) #define gr_scc_pagepool_total_pages_hwmax_v() (0x00000000U)
#define gr_scc_pagepool_total_pages_hwmax_value_v() (0x00000080U) #define gr_scc_pagepool_total_pages_hwmax_value_v() (0x00000080U)
#define gr_scc_pagepool_total_pages_byte_granularity_v() (0x00000100U) #define gr_scc_pagepool_total_pages_byte_granularity_v() (0x00000100U)
#define gr_scc_pagepool_max_valid_pages_s() (8U) #define gr_scc_pagepool_max_valid_pages_s() (8U)
#define gr_scc_pagepool_max_valid_pages_f(v) (((v)&0xffU) << 8U) #define gr_scc_pagepool_max_valid_pages_f(v) ((U32(v) & 0xffU) << 8U)
#define gr_scc_pagepool_max_valid_pages_m() (U32(0xffU) << 8U) #define gr_scc_pagepool_max_valid_pages_m() (U32(0xffU) << 8U)
#define gr_scc_pagepool_max_valid_pages_v(r) (((r) >> 8U) & 0xffU) #define gr_scc_pagepool_max_valid_pages_v(r) (((r) >> 8U) & 0xffU)
#define gr_scc_pagepool_valid_true_f() (0x80000000U) #define gr_scc_pagepool_valid_true_f() (0x80000000U)
@@ -561,20 +563,20 @@
#define gr_sked_hww_esr_r() (0x00407020U) #define gr_sked_hww_esr_r() (0x00407020U)
#define gr_sked_hww_esr_reset_active_f() (0x40000000U) #define gr_sked_hww_esr_reset_active_f() (0x40000000U)
#define gr_cwd_fs_r() (0x00405b00U) #define gr_cwd_fs_r() (0x00405b00U)
#define gr_cwd_fs_num_gpcs_f(v) (((v)&0xffU) << 0U) #define gr_cwd_fs_num_gpcs_f(v) ((U32(v) & 0xffU) << 0U)
#define gr_cwd_fs_num_tpcs_f(v) (((v)&0xffU) << 8U) #define gr_cwd_fs_num_tpcs_f(v) ((U32(v) & 0xffU) << 8U)
#define gr_cwd_gpc_tpc_id_r(i)\ #define gr_cwd_gpc_tpc_id_r(i)\
(nvgpu_safe_add_u32(0x00405b60U, nvgpu_safe_mult_u32((i), 4U))) (nvgpu_safe_add_u32(0x00405b60U, nvgpu_safe_mult_u32((i), 4U)))
#define gr_cwd_gpc_tpc_id_tpc0_s() (4U) #define gr_cwd_gpc_tpc_id_tpc0_s() (4U)
#define gr_cwd_gpc_tpc_id_tpc0_f(v) (((v)&0xfU) << 0U) #define gr_cwd_gpc_tpc_id_tpc0_f(v) ((U32(v) & 0xfU) << 0U)
#define gr_cwd_gpc_tpc_id_gpc0_s() (4U) #define gr_cwd_gpc_tpc_id_gpc0_s() (4U)
#define gr_cwd_gpc_tpc_id_gpc0_f(v) (((v)&0xfU) << 4U) #define gr_cwd_gpc_tpc_id_gpc0_f(v) ((U32(v) & 0xfU) << 4U)
#define gr_cwd_gpc_tpc_id_tpc1_f(v) (((v)&0xfU) << 8U) #define gr_cwd_gpc_tpc_id_tpc1_f(v) ((U32(v) & 0xfU) << 8U)
#define gr_cwd_sm_id_r(i)\ #define gr_cwd_sm_id_r(i)\
(nvgpu_safe_add_u32(0x00405ba0U, nvgpu_safe_mult_u32((i), 4U))) (nvgpu_safe_add_u32(0x00405ba0U, nvgpu_safe_mult_u32((i), 4U)))
#define gr_cwd_sm_id__size_1_v() (0x00000006U) #define gr_cwd_sm_id__size_1_v() (0x00000006U)
#define gr_cwd_sm_id_tpc0_f(v) (((v)&0xffU) << 0U) #define gr_cwd_sm_id_tpc0_f(v) ((U32(v) & 0xffU) << 0U)
#define gr_cwd_sm_id_tpc1_f(v) (((v)&0xffU) << 8U) #define gr_cwd_sm_id_tpc1_f(v) ((U32(v) & 0xffU) << 8U)
#define gr_gpc0_fs_gpc_r() (0x00502608U) #define gr_gpc0_fs_gpc_r() (0x00502608U)
#define gr_gpc0_fs_gpc_num_available_tpcs_v(r) (((r) >> 0U) & 0x1fU) #define gr_gpc0_fs_gpc_num_available_tpcs_v(r) (((r) >> 0U) & 0x1fU)
#define gr_gpc0_fs_gpc_num_available_zculls_v(r) (((r) >> 16U) & 0x1fU) #define gr_gpc0_fs_gpc_num_available_zculls_v(r) (((r) >> 16U) & 0x1fU)
@@ -582,44 +584,45 @@
#define gr_gpc0_cfg_imem_sz_v(r) (((r) >> 0U) & 0xffU) #define gr_gpc0_cfg_imem_sz_v(r) (((r) >> 0U) & 0xffU)
#define gr_gpccs_rc_lanes_r() (0x00502880U) #define gr_gpccs_rc_lanes_r() (0x00502880U)
#define gr_gpccs_rc_lanes_num_chains_s() (6U) #define gr_gpccs_rc_lanes_num_chains_s() (6U)
#define gr_gpccs_rc_lanes_num_chains_f(v) (((v)&0x3fU) << 0U) #define gr_gpccs_rc_lanes_num_chains_f(v) ((U32(v) & 0x3fU) << 0U)
#define gr_gpccs_rc_lanes_num_chains_m() (U32(0x3fU) << 0U) #define gr_gpccs_rc_lanes_num_chains_m() (U32(0x3fU) << 0U)
#define gr_gpccs_rc_lanes_num_chains_v(r) (((r) >> 0U) & 0x3fU) #define gr_gpccs_rc_lanes_num_chains_v(r) (((r) >> 0U) & 0x3fU)
#define gr_gpccs_rc_lane_size_r(i)\ #define gr_gpccs_rc_lane_size_r(i)\
(nvgpu_safe_add_u32(0x00502910U, nvgpu_safe_mult_u32((i), 0U))) (nvgpu_safe_add_u32(0x00502910U, nvgpu_safe_mult_u32((i), 0U)))
#define gr_gpccs_rc_lane_size__size_1_v() (0x00000010U) #define gr_gpccs_rc_lane_size__size_1_v() (0x00000010U)
#define gr_gpccs_rc_lane_size_v_s() (24U) #define gr_gpccs_rc_lane_size_v_s() (24U)
#define gr_gpccs_rc_lane_size_v_f(v) (((v)&0xffffffU) << 0U) #define gr_gpccs_rc_lane_size_v_f(v) ((U32(v) & 0xffffffU) << 0U)
#define gr_gpccs_rc_lane_size_v_m() (U32(0xffffffU) << 0U) #define gr_gpccs_rc_lane_size_v_m() (U32(0xffffffU) << 0U)
#define gr_gpccs_rc_lane_size_v_v(r) (((r) >> 0U) & 0xffffffU) #define gr_gpccs_rc_lane_size_v_v(r) (((r) >> 0U) & 0xffffffU)
#define gr_gpccs_rc_lane_size_v_0_v() (0x00000000U) #define gr_gpccs_rc_lane_size_v_0_v() (0x00000000U)
#define gr_gpccs_rc_lane_size_v_0_f() (0x0U) #define gr_gpccs_rc_lane_size_v_0_f() (0x0U)
#define gr_gpc0_zcull_fs_r() (0x00500910U) #define gr_gpc0_zcull_fs_r() (0x00500910U)
#define gr_gpc0_zcull_fs_num_sms_f(v) (((v)&0x1ffU) << 0U) #define gr_gpc0_zcull_fs_num_sms_f(v) ((U32(v) & 0x1ffU) << 0U)
#define gr_gpc0_zcull_fs_num_active_banks_f(v) (((v)&0xfU) << 16U) #define gr_gpc0_zcull_fs_num_active_banks_f(v) ((U32(v) & 0xfU) << 16U)
#define gr_gpc0_zcull_ram_addr_r() (0x00500914U) #define gr_gpc0_zcull_ram_addr_r() (0x00500914U)
#define gr_gpc0_zcull_ram_addr_tiles_per_hypertile_row_per_gpc_f(v)\ #define gr_gpc0_zcull_ram_addr_tiles_per_hypertile_row_per_gpc_f(v)\
(((v)&0xfU) << 0U) ((U32(v) & 0xfU) << 0U)
#define gr_gpc0_zcull_ram_addr_row_offset_f(v) (((v)&0xfU) << 8U) #define gr_gpc0_zcull_ram_addr_row_offset_f(v) ((U32(v) & 0xfU) << 8U)
#define gr_gpc0_zcull_sm_num_rcp_r() (0x00500918U) #define gr_gpc0_zcull_sm_num_rcp_r() (0x00500918U)
#define gr_gpc0_zcull_sm_num_rcp_conservative_f(v) (((v)&0xffffffU) << 0U) #define gr_gpc0_zcull_sm_num_rcp_conservative_f(v) ((U32(v) & 0xffffffU) << 0U)
#define gr_gpc0_zcull_sm_num_rcp_conservative__max_v() (0x00800000U) #define gr_gpc0_zcull_sm_num_rcp_conservative__max_v() (0x00800000U)
#define gr_gpc0_zcull_total_ram_size_r() (0x00500920U) #define gr_gpc0_zcull_total_ram_size_r() (0x00500920U)
#define gr_gpc0_zcull_total_ram_size_num_aliquots_f(v) (((v)&0xffffU) << 0U) #define gr_gpc0_zcull_total_ram_size_num_aliquots_f(v)\
((U32(v) & 0xffffU) << 0U)
#define gr_gpc0_zcull_zcsize_r(i)\ #define gr_gpc0_zcull_zcsize_r(i)\
(nvgpu_safe_add_u32(0x00500a04U, nvgpu_safe_mult_u32((i), 32U))) (nvgpu_safe_add_u32(0x00500a04U, nvgpu_safe_mult_u32((i), 32U)))
#define gr_gpc0_zcull_zcsize_height_subregion__multiple_v() (0x00000040U) #define gr_gpc0_zcull_zcsize_height_subregion__multiple_v() (0x00000040U)
#define gr_gpc0_zcull_zcsize_width_subregion__multiple_v() (0x00000010U) #define gr_gpc0_zcull_zcsize_width_subregion__multiple_v() (0x00000010U)
#define gr_gpc0_gpm_pd_sm_id_r(i)\ #define gr_gpc0_gpm_pd_sm_id_r(i)\
(nvgpu_safe_add_u32(0x00500c10U, nvgpu_safe_mult_u32((i), 4U))) (nvgpu_safe_add_u32(0x00500c10U, nvgpu_safe_mult_u32((i), 4U)))
#define gr_gpc0_gpm_pd_sm_id_id_f(v) (((v)&0xffU) << 0U) #define gr_gpc0_gpm_pd_sm_id_id_f(v) ((U32(v) & 0xffU) << 0U)
#define gr_gpc0_gpm_pd_pes_tpc_id_mask_r(i)\ #define gr_gpc0_gpm_pd_pes_tpc_id_mask_r(i)\
(nvgpu_safe_add_u32(0x00500c30U, nvgpu_safe_mult_u32((i), 4U))) (nvgpu_safe_add_u32(0x00500c30U, nvgpu_safe_mult_u32((i), 4U)))
#define gr_gpc0_gpm_pd_pes_tpc_id_mask_mask_v(r) (((r) >> 0U) & 0xffU) #define gr_gpc0_gpm_pd_pes_tpc_id_mask_mask_v(r) (((r) >> 0U) & 0xffU)
#define gr_gpc0_tpc0_pe_cfg_smid_r() (0x00504088U) #define gr_gpc0_tpc0_pe_cfg_smid_r() (0x00504088U)
#define gr_gpc0_tpc0_pe_cfg_smid_value_f(v) (((v)&0xffffU) << 0U) #define gr_gpc0_tpc0_pe_cfg_smid_value_f(v) ((U32(v) & 0xffffU) << 0U)
#define gr_gpc0_tpc0_sm_cfg_r() (0x00504698U) #define gr_gpc0_tpc0_sm_cfg_r() (0x00504698U)
#define gr_gpc0_tpc0_sm_cfg_sm_id_f(v) (((v)&0xffffU) << 0U) #define gr_gpc0_tpc0_sm_cfg_sm_id_f(v) ((U32(v) & 0xffffU) << 0U)
#define gr_gpc0_tpc0_sm_cfg_sm_id_v(r) (((r) >> 0U) & 0xffffU) #define gr_gpc0_tpc0_sm_cfg_sm_id_v(r) (((r) >> 0U) & 0xffffU)
#define gr_gpc0_tpc0_sm_arch_r() (0x0050469cU) #define gr_gpc0_tpc0_sm_arch_r() (0x0050469cU)
#define gr_gpc0_tpc0_sm_arch_warp_count_v(r) (((r) >> 0U) & 0xffU) #define gr_gpc0_tpc0_sm_arch_warp_count_v(r) (((r) >> 0U) & 0xffU)
@@ -629,82 +632,83 @@
#define gr_gpc0_ppc0_pes_vsc_strem_master_pe_m() (U32(0x1U) << 0U) #define gr_gpc0_ppc0_pes_vsc_strem_master_pe_m() (U32(0x1U) << 0U)
#define gr_gpc0_ppc0_pes_vsc_strem_master_pe_true_f() (0x1U) #define gr_gpc0_ppc0_pes_vsc_strem_master_pe_true_f() (0x1U)
#define gr_gpc0_ppc0_cbm_beta_cb_size_r() (0x005030c0U) #define gr_gpc0_ppc0_cbm_beta_cb_size_r() (0x005030c0U)
#define gr_gpc0_ppc0_cbm_beta_cb_size_v_f(v) (((v)&0xffffU) << 0U) #define gr_gpc0_ppc0_cbm_beta_cb_size_v_f(v) ((U32(v) & 0xffffU) << 0U)
#define gr_gpc0_ppc0_cbm_beta_cb_size_v_m() (U32(0xffffU) << 0U) #define gr_gpc0_ppc0_cbm_beta_cb_size_v_m() (U32(0xffffU) << 0U)
#define gr_gpc0_ppc0_cbm_beta_cb_size_v_default_v() (0x00000400U) #define gr_gpc0_ppc0_cbm_beta_cb_size_v_default_v() (0x00000400U)
#define gr_gpc0_ppc0_cbm_beta_cb_size_v_granularity_v() (0x00000020U) #define gr_gpc0_ppc0_cbm_beta_cb_size_v_granularity_v() (0x00000020U)
#define gr_gpc0_ppc0_cbm_beta_cb_offset_r() (0x005030f4U) #define gr_gpc0_ppc0_cbm_beta_cb_offset_r() (0x005030f4U)
#define gr_gpc0_ppc0_cbm_alpha_cb_size_r() (0x005030e4U) #define gr_gpc0_ppc0_cbm_alpha_cb_size_r() (0x005030e4U)
#define gr_gpc0_ppc0_cbm_alpha_cb_size_v_f(v) (((v)&0xffffU) << 0U) #define gr_gpc0_ppc0_cbm_alpha_cb_size_v_f(v) ((U32(v) & 0xffffU) << 0U)
#define gr_gpc0_ppc0_cbm_alpha_cb_size_v_m() (U32(0xffffU) << 0U) #define gr_gpc0_ppc0_cbm_alpha_cb_size_v_m() (U32(0xffffU) << 0U)
#define gr_gpc0_ppc0_cbm_alpha_cb_size_v_default_v() (0x00000800U) #define gr_gpc0_ppc0_cbm_alpha_cb_size_v_default_v() (0x00000800U)
#define gr_gpc0_ppc0_cbm_alpha_cb_size_v_granularity_v() (0x00000020U) #define gr_gpc0_ppc0_cbm_alpha_cb_size_v_granularity_v() (0x00000020U)
#define gr_gpc0_ppc0_cbm_alpha_cb_offset_r() (0x005030f8U) #define gr_gpc0_ppc0_cbm_alpha_cb_offset_r() (0x005030f8U)
#define gr_gpcs_tpcs_tex_m_dbg2_r() (0x00419a3cU) #define gr_gpcs_tpcs_tex_m_dbg2_r() (0x00419a3cU)
#define gr_gpcs_tpcs_tex_m_dbg2_lg_rd_coalesce_en_f(v) (((v)&0x1U) << 2U) #define gr_gpcs_tpcs_tex_m_dbg2_lg_rd_coalesce_en_f(v) ((U32(v) & 0x1U) << 2U)
#define gr_gpcs_tpcs_tex_m_dbg2_lg_rd_coalesce_en_m() (U32(0x1U) << 2U) #define gr_gpcs_tpcs_tex_m_dbg2_lg_rd_coalesce_en_m() (U32(0x1U) << 2U)
#define gr_gpcs_tpcs_tex_m_dbg2_su_rd_coalesce_en_f(v) (((v)&0x1U) << 4U) #define gr_gpcs_tpcs_tex_m_dbg2_su_rd_coalesce_en_f(v) ((U32(v) & 0x1U) << 4U)
#define gr_gpcs_tpcs_tex_m_dbg2_su_rd_coalesce_en_m() (U32(0x1U) << 4U) #define gr_gpcs_tpcs_tex_m_dbg2_su_rd_coalesce_en_m() (U32(0x1U) << 4U)
#define gr_gpccs_falcon_addr_r() (0x0041a0acU) #define gr_gpccs_falcon_addr_r() (0x0041a0acU)
#define gr_gpccs_falcon_addr_lsb_s() (6U) #define gr_gpccs_falcon_addr_lsb_s() (6U)
#define gr_gpccs_falcon_addr_lsb_f(v) (((v)&0x3fU) << 0U) #define gr_gpccs_falcon_addr_lsb_f(v) ((U32(v) & 0x3fU) << 0U)
#define gr_gpccs_falcon_addr_lsb_m() (U32(0x3fU) << 0U) #define gr_gpccs_falcon_addr_lsb_m() (U32(0x3fU) << 0U)
#define gr_gpccs_falcon_addr_lsb_v(r) (((r) >> 0U) & 0x3fU) #define gr_gpccs_falcon_addr_lsb_v(r) (((r) >> 0U) & 0x3fU)
#define gr_gpccs_falcon_addr_lsb_init_v() (0x00000000U) #define gr_gpccs_falcon_addr_lsb_init_v() (0x00000000U)
#define gr_gpccs_falcon_addr_lsb_init_f() (0x0U) #define gr_gpccs_falcon_addr_lsb_init_f() (0x0U)
#define gr_gpccs_falcon_addr_msb_s() (6U) #define gr_gpccs_falcon_addr_msb_s() (6U)
#define gr_gpccs_falcon_addr_msb_f(v) (((v)&0x3fU) << 6U) #define gr_gpccs_falcon_addr_msb_f(v) ((U32(v) & 0x3fU) << 6U)
#define gr_gpccs_falcon_addr_msb_m() (U32(0x3fU) << 6U) #define gr_gpccs_falcon_addr_msb_m() (U32(0x3fU) << 6U)
#define gr_gpccs_falcon_addr_msb_v(r) (((r) >> 6U) & 0x3fU) #define gr_gpccs_falcon_addr_msb_v(r) (((r) >> 6U) & 0x3fU)
#define gr_gpccs_falcon_addr_msb_init_v() (0x00000000U) #define gr_gpccs_falcon_addr_msb_init_v() (0x00000000U)
#define gr_gpccs_falcon_addr_msb_init_f() (0x0U) #define gr_gpccs_falcon_addr_msb_init_f() (0x0U)
#define gr_gpccs_falcon_addr_ext_s() (12U) #define gr_gpccs_falcon_addr_ext_s() (12U)
#define gr_gpccs_falcon_addr_ext_f(v) (((v)&0xfffU) << 0U) #define gr_gpccs_falcon_addr_ext_f(v) ((U32(v) & 0xfffU) << 0U)
#define gr_gpccs_falcon_addr_ext_m() (U32(0xfffU) << 0U) #define gr_gpccs_falcon_addr_ext_m() (U32(0xfffU) << 0U)
#define gr_gpccs_falcon_addr_ext_v(r) (((r) >> 0U) & 0xfffU) #define gr_gpccs_falcon_addr_ext_v(r) (((r) >> 0U) & 0xfffU)
#define gr_gpccs_cpuctl_r() (0x0041a100U) #define gr_gpccs_cpuctl_r() (0x0041a100U)
#define gr_gpccs_cpuctl_startcpu_f(v) (((v)&0x1U) << 1U) #define gr_gpccs_cpuctl_startcpu_f(v) ((U32(v) & 0x1U) << 1U)
#define gr_gpccs_dmactl_r() (0x0041a10cU) #define gr_gpccs_dmactl_r() (0x0041a10cU)
#define gr_gpccs_dmactl_require_ctx_f(v) (((v)&0x1U) << 0U) #define gr_gpccs_dmactl_require_ctx_f(v) ((U32(v) & 0x1U) << 0U)
#define gr_gpccs_dmactl_dmem_scrubbing_m() (U32(0x1U) << 1U) #define gr_gpccs_dmactl_dmem_scrubbing_m() (U32(0x1U) << 1U)
#define gr_gpccs_dmactl_imem_scrubbing_m() (U32(0x1U) << 2U) #define gr_gpccs_dmactl_imem_scrubbing_m() (U32(0x1U) << 2U)
#define gr_gpccs_imemc_r(i)\ #define gr_gpccs_imemc_r(i)\
(nvgpu_safe_add_u32(0x0041a180U, nvgpu_safe_mult_u32((i), 16U))) (nvgpu_safe_add_u32(0x0041a180U, nvgpu_safe_mult_u32((i), 16U)))
#define gr_gpccs_imemc_offs_f(v) (((v)&0x3fU) << 2U) #define gr_gpccs_imemc_offs_f(v) ((U32(v) & 0x3fU) << 2U)
#define gr_gpccs_imemc_blk_f(v) (((v)&0xffU) << 8U) #define gr_gpccs_imemc_blk_f(v) ((U32(v) & 0xffU) << 8U)
#define gr_gpccs_imemc_aincw_f(v) (((v)&0x1U) << 24U) #define gr_gpccs_imemc_aincw_f(v) ((U32(v) & 0x1U) << 24U)
#define gr_gpccs_imemd_r(i)\ #define gr_gpccs_imemd_r(i)\
(nvgpu_safe_add_u32(0x0041a184U, nvgpu_safe_mult_u32((i), 16U))) (nvgpu_safe_add_u32(0x0041a184U, nvgpu_safe_mult_u32((i), 16U)))
#define gr_gpccs_imemt_r(i)\ #define gr_gpccs_imemt_r(i)\
(nvgpu_safe_add_u32(0x0041a188U, nvgpu_safe_mult_u32((i), 16U))) (nvgpu_safe_add_u32(0x0041a188U, nvgpu_safe_mult_u32((i), 16U)))
#define gr_gpccs_imemt__size_1_v() (0x00000004U) #define gr_gpccs_imemt__size_1_v() (0x00000004U)
#define gr_gpccs_imemt_tag_f(v) (((v)&0xffffU) << 0U) #define gr_gpccs_imemt_tag_f(v) ((U32(v) & 0xffffU) << 0U)
#define gr_gpccs_dmemc_r(i)\ #define gr_gpccs_dmemc_r(i)\
(nvgpu_safe_add_u32(0x0041a1c0U, nvgpu_safe_mult_u32((i), 8U))) (nvgpu_safe_add_u32(0x0041a1c0U, nvgpu_safe_mult_u32((i), 8U)))
#define gr_gpccs_dmemc_offs_f(v) (((v)&0x3fU) << 2U) #define gr_gpccs_dmemc_offs_f(v) ((U32(v) & 0x3fU) << 2U)
#define gr_gpccs_dmemc_blk_f(v) (((v)&0xffU) << 8U) #define gr_gpccs_dmemc_blk_f(v) ((U32(v) & 0xffU) << 8U)
#define gr_gpccs_dmemc_aincw_f(v) (((v)&0x1U) << 24U) #define gr_gpccs_dmemc_aincw_f(v) ((U32(v) & 0x1U) << 24U)
#define gr_gpccs_dmemd_r(i)\ #define gr_gpccs_dmemd_r(i)\
(nvgpu_safe_add_u32(0x0041a1c4U, nvgpu_safe_mult_u32((i), 8U))) (nvgpu_safe_add_u32(0x0041a1c4U, nvgpu_safe_mult_u32((i), 8U)))
#define gr_gpccs_ctxsw_mailbox_r(i)\ #define gr_gpccs_ctxsw_mailbox_r(i)\
(nvgpu_safe_add_u32(0x0041a800U, nvgpu_safe_mult_u32((i), 4U))) (nvgpu_safe_add_u32(0x0041a800U, nvgpu_safe_mult_u32((i), 4U)))
#define gr_gpccs_ctxsw_mailbox_value_f(v) (((v)&0xffffffffU) << 0U) #define gr_gpccs_ctxsw_mailbox_value_f(v) ((U32(v) & 0xffffffffU) << 0U)
#define gr_gpcs_swdx_bundle_cb_base_r() (0x00418e24U) #define gr_gpcs_swdx_bundle_cb_base_r() (0x00418e24U)
#define gr_gpcs_swdx_bundle_cb_base_addr_39_8_s() (32U) #define gr_gpcs_swdx_bundle_cb_base_addr_39_8_s() (32U)
#define gr_gpcs_swdx_bundle_cb_base_addr_39_8_f(v) (((v)&0xffffffffU) << 0U) #define gr_gpcs_swdx_bundle_cb_base_addr_39_8_f(v)\
((U32(v) & 0xffffffffU) << 0U)
#define gr_gpcs_swdx_bundle_cb_base_addr_39_8_m() (U32(0xffffffffU) << 0U) #define gr_gpcs_swdx_bundle_cb_base_addr_39_8_m() (U32(0xffffffffU) << 0U)
#define gr_gpcs_swdx_bundle_cb_base_addr_39_8_v(r) (((r) >> 0U) & 0xffffffffU) #define gr_gpcs_swdx_bundle_cb_base_addr_39_8_v(r) (((r) >> 0U) & 0xffffffffU)
#define gr_gpcs_swdx_bundle_cb_base_addr_39_8_init_v() (0x00000000U) #define gr_gpcs_swdx_bundle_cb_base_addr_39_8_init_v() (0x00000000U)
#define gr_gpcs_swdx_bundle_cb_base_addr_39_8_init_f() (0x0U) #define gr_gpcs_swdx_bundle_cb_base_addr_39_8_init_f() (0x0U)
#define gr_gpcs_swdx_bundle_cb_size_r() (0x00418e28U) #define gr_gpcs_swdx_bundle_cb_size_r() (0x00418e28U)
#define gr_gpcs_swdx_bundle_cb_size_div_256b_s() (11U) #define gr_gpcs_swdx_bundle_cb_size_div_256b_s() (11U)
#define gr_gpcs_swdx_bundle_cb_size_div_256b_f(v) (((v)&0x7ffU) << 0U) #define gr_gpcs_swdx_bundle_cb_size_div_256b_f(v) ((U32(v) & 0x7ffU) << 0U)
#define gr_gpcs_swdx_bundle_cb_size_div_256b_m() (U32(0x7ffU) << 0U) #define gr_gpcs_swdx_bundle_cb_size_div_256b_m() (U32(0x7ffU) << 0U)
#define gr_gpcs_swdx_bundle_cb_size_div_256b_v(r) (((r) >> 0U) & 0x7ffU) #define gr_gpcs_swdx_bundle_cb_size_div_256b_v(r) (((r) >> 0U) & 0x7ffU)
#define gr_gpcs_swdx_bundle_cb_size_div_256b_init_v() (0x00000018U) #define gr_gpcs_swdx_bundle_cb_size_div_256b_init_v() (0x00000018U)
#define gr_gpcs_swdx_bundle_cb_size_div_256b_init_f() (0x18U) #define gr_gpcs_swdx_bundle_cb_size_div_256b_init_f() (0x18U)
#define gr_gpcs_swdx_bundle_cb_size_valid_s() (1U) #define gr_gpcs_swdx_bundle_cb_size_valid_s() (1U)
#define gr_gpcs_swdx_bundle_cb_size_valid_f(v) (((v)&0x1U) << 31U) #define gr_gpcs_swdx_bundle_cb_size_valid_f(v) ((U32(v) & 0x1U) << 31U)
#define gr_gpcs_swdx_bundle_cb_size_valid_m() (U32(0x1U) << 31U) #define gr_gpcs_swdx_bundle_cb_size_valid_m() (U32(0x1U) << 31U)
#define gr_gpcs_swdx_bundle_cb_size_valid_v(r) (((r) >> 31U) & 0x1U) #define gr_gpcs_swdx_bundle_cb_size_valid_v(r) (((r) >> 31U) & 0x1U)
#define gr_gpcs_swdx_bundle_cb_size_valid_false_v() (0x00000000U) #define gr_gpcs_swdx_bundle_cb_size_valid_false_v() (0x00000000U)
@@ -713,120 +717,140 @@
#define gr_gpcs_swdx_bundle_cb_size_valid_true_f() (0x80000000U) #define gr_gpcs_swdx_bundle_cb_size_valid_true_f() (0x80000000U)
#define gr_gpcs_swdx_tc_beta_cb_size_r(i)\ #define gr_gpcs_swdx_tc_beta_cb_size_r(i)\
(nvgpu_safe_add_u32(0x00418ea0U, nvgpu_safe_mult_u32((i), 4U))) (nvgpu_safe_add_u32(0x00418ea0U, nvgpu_safe_mult_u32((i), 4U)))
#define gr_gpcs_swdx_tc_beta_cb_size_v_f(v) (((v)&0xffffU) << 0U) #define gr_gpcs_swdx_tc_beta_cb_size_v_f(v) ((U32(v) & 0xffffU) << 0U)
#define gr_gpcs_swdx_tc_beta_cb_size_v_m() (U32(0xffffU) << 0U) #define gr_gpcs_swdx_tc_beta_cb_size_v_m() (U32(0xffffU) << 0U)
#define gr_gpcs_swdx_tc_beta_cb_size_div3_f(v) (((v)&0xffffU) << 16U) #define gr_gpcs_swdx_tc_beta_cb_size_div3_f(v) ((U32(v) & 0xffffU) << 16U)
#define gr_gpcs_swdx_tc_beta_cb_size_div3_m() (U32(0xffffU) << 16U) #define gr_gpcs_swdx_tc_beta_cb_size_div3_m() (U32(0xffffU) << 16U)
#define gr_gpcs_swdx_rm_pagepool_r() (0x00418e30U) #define gr_gpcs_swdx_rm_pagepool_r() (0x00418e30U)
#define gr_gpcs_swdx_rm_pagepool_total_pages_f(v) (((v)&0xffU) << 0U) #define gr_gpcs_swdx_rm_pagepool_total_pages_f(v) ((U32(v) & 0xffU) << 0U)
#define gr_gpcs_swdx_rm_pagepool_valid_true_f() (0x80000000U) #define gr_gpcs_swdx_rm_pagepool_valid_true_f() (0x80000000U)
#define gr_gpcs_setup_attrib_cb_base_r() (0x00418810U) #define gr_gpcs_setup_attrib_cb_base_r() (0x00418810U)
#define gr_gpcs_setup_attrib_cb_base_addr_39_12_f(v) (((v)&0xfffffffU) << 0U) #define gr_gpcs_setup_attrib_cb_base_addr_39_12_f(v)\
((U32(v) & 0xfffffffU) << 0U)
#define gr_gpcs_setup_attrib_cb_base_addr_39_12_align_bits_v() (0x0000000cU) #define gr_gpcs_setup_attrib_cb_base_addr_39_12_align_bits_v() (0x0000000cU)
#define gr_gpcs_setup_attrib_cb_base_valid_true_f() (0x80000000U) #define gr_gpcs_setup_attrib_cb_base_valid_true_f() (0x80000000U)
#define gr_crstr_gpc_map0_r() (0x00418b08U) #define gr_crstr_gpc_map0_r() (0x00418b08U)
#define gr_crstr_gpc_map0_tile0_f(v) (((v)&0x7U) << 0U) #define gr_crstr_gpc_map0_tile0_f(v) ((U32(v) & 0x7U) << 0U)
#define gr_crstr_gpc_map0_tile1_f(v) (((v)&0x7U) << 5U) #define gr_crstr_gpc_map0_tile1_f(v) ((U32(v) & 0x7U) << 5U)
#define gr_crstr_gpc_map0_tile2_f(v) (((v)&0x7U) << 10U) #define gr_crstr_gpc_map0_tile2_f(v) ((U32(v) & 0x7U) << 10U)
#define gr_crstr_gpc_map0_tile3_f(v) (((v)&0x7U) << 15U) #define gr_crstr_gpc_map0_tile3_f(v) ((U32(v) & 0x7U) << 15U)
#define gr_crstr_gpc_map0_tile4_f(v) (((v)&0x7U) << 20U) #define gr_crstr_gpc_map0_tile4_f(v) ((U32(v) & 0x7U) << 20U)
#define gr_crstr_gpc_map0_tile5_f(v) (((v)&0x7U) << 25U) #define gr_crstr_gpc_map0_tile5_f(v) ((U32(v) & 0x7U) << 25U)
#define gr_crstr_gpc_map1_r() (0x00418b0cU) #define gr_crstr_gpc_map1_r() (0x00418b0cU)
#define gr_crstr_gpc_map1_tile6_f(v) (((v)&0x7U) << 0U) #define gr_crstr_gpc_map1_tile6_f(v) ((U32(v) & 0x7U) << 0U)
#define gr_crstr_gpc_map1_tile7_f(v) (((v)&0x7U) << 5U) #define gr_crstr_gpc_map1_tile7_f(v) ((U32(v) & 0x7U) << 5U)
#define gr_crstr_gpc_map1_tile8_f(v) (((v)&0x7U) << 10U) #define gr_crstr_gpc_map1_tile8_f(v) ((U32(v) & 0x7U) << 10U)
#define gr_crstr_gpc_map1_tile9_f(v) (((v)&0x7U) << 15U) #define gr_crstr_gpc_map1_tile9_f(v) ((U32(v) & 0x7U) << 15U)
#define gr_crstr_gpc_map1_tile10_f(v) (((v)&0x7U) << 20U) #define gr_crstr_gpc_map1_tile10_f(v) ((U32(v) & 0x7U) << 20U)
#define gr_crstr_gpc_map1_tile11_f(v) (((v)&0x7U) << 25U) #define gr_crstr_gpc_map1_tile11_f(v) ((U32(v) & 0x7U) << 25U)
#define gr_crstr_gpc_map2_r() (0x00418b10U) #define gr_crstr_gpc_map2_r() (0x00418b10U)
#define gr_crstr_gpc_map2_tile12_f(v) (((v)&0x7U) << 0U) #define gr_crstr_gpc_map2_tile12_f(v) ((U32(v) & 0x7U) << 0U)
#define gr_crstr_gpc_map2_tile13_f(v) (((v)&0x7U) << 5U) #define gr_crstr_gpc_map2_tile13_f(v) ((U32(v) & 0x7U) << 5U)
#define gr_crstr_gpc_map2_tile14_f(v) (((v)&0x7U) << 10U) #define gr_crstr_gpc_map2_tile14_f(v) ((U32(v) & 0x7U) << 10U)
#define gr_crstr_gpc_map2_tile15_f(v) (((v)&0x7U) << 15U) #define gr_crstr_gpc_map2_tile15_f(v) ((U32(v) & 0x7U) << 15U)
#define gr_crstr_gpc_map2_tile16_f(v) (((v)&0x7U) << 20U) #define gr_crstr_gpc_map2_tile16_f(v) ((U32(v) & 0x7U) << 20U)
#define gr_crstr_gpc_map2_tile17_f(v) (((v)&0x7U) << 25U) #define gr_crstr_gpc_map2_tile17_f(v) ((U32(v) & 0x7U) << 25U)
#define gr_crstr_gpc_map3_r() (0x00418b14U) #define gr_crstr_gpc_map3_r() (0x00418b14U)
#define gr_crstr_gpc_map3_tile18_f(v) (((v)&0x7U) << 0U) #define gr_crstr_gpc_map3_tile18_f(v) ((U32(v) & 0x7U) << 0U)
#define gr_crstr_gpc_map3_tile19_f(v) (((v)&0x7U) << 5U) #define gr_crstr_gpc_map3_tile19_f(v) ((U32(v) & 0x7U) << 5U)
#define gr_crstr_gpc_map3_tile20_f(v) (((v)&0x7U) << 10U) #define gr_crstr_gpc_map3_tile20_f(v) ((U32(v) & 0x7U) << 10U)
#define gr_crstr_gpc_map3_tile21_f(v) (((v)&0x7U) << 15U) #define gr_crstr_gpc_map3_tile21_f(v) ((U32(v) & 0x7U) << 15U)
#define gr_crstr_gpc_map3_tile22_f(v) (((v)&0x7U) << 20U) #define gr_crstr_gpc_map3_tile22_f(v) ((U32(v) & 0x7U) << 20U)
#define gr_crstr_gpc_map3_tile23_f(v) (((v)&0x7U) << 25U) #define gr_crstr_gpc_map3_tile23_f(v) ((U32(v) & 0x7U) << 25U)
#define gr_crstr_gpc_map4_r() (0x00418b18U) #define gr_crstr_gpc_map4_r() (0x00418b18U)
#define gr_crstr_gpc_map4_tile24_f(v) (((v)&0x7U) << 0U) #define gr_crstr_gpc_map4_tile24_f(v) ((U32(v) & 0x7U) << 0U)
#define gr_crstr_gpc_map4_tile25_f(v) (((v)&0x7U) << 5U) #define gr_crstr_gpc_map4_tile25_f(v) ((U32(v) & 0x7U) << 5U)
#define gr_crstr_gpc_map4_tile26_f(v) (((v)&0x7U) << 10U) #define gr_crstr_gpc_map4_tile26_f(v) ((U32(v) & 0x7U) << 10U)
#define gr_crstr_gpc_map4_tile27_f(v) (((v)&0x7U) << 15U) #define gr_crstr_gpc_map4_tile27_f(v) ((U32(v) & 0x7U) << 15U)
#define gr_crstr_gpc_map4_tile28_f(v) (((v)&0x7U) << 20U) #define gr_crstr_gpc_map4_tile28_f(v) ((U32(v) & 0x7U) << 20U)
#define gr_crstr_gpc_map4_tile29_f(v) (((v)&0x7U) << 25U) #define gr_crstr_gpc_map4_tile29_f(v) ((U32(v) & 0x7U) << 25U)
#define gr_crstr_gpc_map5_r() (0x00418b1cU) #define gr_crstr_gpc_map5_r() (0x00418b1cU)
#define gr_crstr_gpc_map5_tile30_f(v) (((v)&0x7U) << 0U) #define gr_crstr_gpc_map5_tile30_f(v) ((U32(v) & 0x7U) << 0U)
#define gr_crstr_gpc_map5_tile31_f(v) (((v)&0x7U) << 5U) #define gr_crstr_gpc_map5_tile31_f(v) ((U32(v) & 0x7U) << 5U)
#define gr_crstr_gpc_map5_tile32_f(v) (((v)&0x7U) << 10U) #define gr_crstr_gpc_map5_tile32_f(v) ((U32(v) & 0x7U) << 10U)
#define gr_crstr_gpc_map5_tile33_f(v) (((v)&0x7U) << 15U) #define gr_crstr_gpc_map5_tile33_f(v) ((U32(v) & 0x7U) << 15U)
#define gr_crstr_gpc_map5_tile34_f(v) (((v)&0x7U) << 20U) #define gr_crstr_gpc_map5_tile34_f(v) ((U32(v) & 0x7U) << 20U)
#define gr_crstr_gpc_map5_tile35_f(v) (((v)&0x7U) << 25U) #define gr_crstr_gpc_map5_tile35_f(v) ((U32(v) & 0x7U) << 25U)
#define gr_crstr_map_table_cfg_r() (0x00418bb8U) #define gr_crstr_map_table_cfg_r() (0x00418bb8U)
#define gr_crstr_map_table_cfg_row_offset_f(v) (((v)&0xffU) << 0U) #define gr_crstr_map_table_cfg_row_offset_f(v) ((U32(v) & 0xffU) << 0U)
#define gr_crstr_map_table_cfg_num_entries_f(v) (((v)&0xffU) << 8U) #define gr_crstr_map_table_cfg_num_entries_f(v) ((U32(v) & 0xffU) << 8U)
#define gr_gpcs_zcull_sm_in_gpc_number_map0_r() (0x00418980U) #define gr_gpcs_zcull_sm_in_gpc_number_map0_r() (0x00418980U)
#define gr_gpcs_zcull_sm_in_gpc_number_map0_tile_0_f(v) (((v)&0x7U) << 0U) #define gr_gpcs_zcull_sm_in_gpc_number_map0_tile_0_f(v) ((U32(v) & 0x7U) << 0U)
#define gr_gpcs_zcull_sm_in_gpc_number_map0_tile_1_f(v) (((v)&0x7U) << 4U) #define gr_gpcs_zcull_sm_in_gpc_number_map0_tile_1_f(v) ((U32(v) & 0x7U) << 4U)
#define gr_gpcs_zcull_sm_in_gpc_number_map0_tile_2_f(v) (((v)&0x7U) << 8U) #define gr_gpcs_zcull_sm_in_gpc_number_map0_tile_2_f(v) ((U32(v) & 0x7U) << 8U)
#define gr_gpcs_zcull_sm_in_gpc_number_map0_tile_3_f(v) (((v)&0x7U) << 12U) #define gr_gpcs_zcull_sm_in_gpc_number_map0_tile_3_f(v) ((U32(v) & 0x7U) << 12U)
#define gr_gpcs_zcull_sm_in_gpc_number_map0_tile_4_f(v) (((v)&0x7U) << 16U) #define gr_gpcs_zcull_sm_in_gpc_number_map0_tile_4_f(v) ((U32(v) & 0x7U) << 16U)
#define gr_gpcs_zcull_sm_in_gpc_number_map0_tile_5_f(v) (((v)&0x7U) << 20U) #define gr_gpcs_zcull_sm_in_gpc_number_map0_tile_5_f(v) ((U32(v) & 0x7U) << 20U)
#define gr_gpcs_zcull_sm_in_gpc_number_map0_tile_6_f(v) (((v)&0x7U) << 24U) #define gr_gpcs_zcull_sm_in_gpc_number_map0_tile_6_f(v) ((U32(v) & 0x7U) << 24U)
#define gr_gpcs_zcull_sm_in_gpc_number_map0_tile_7_f(v) (((v)&0x7U) << 28U) #define gr_gpcs_zcull_sm_in_gpc_number_map0_tile_7_f(v) ((U32(v) & 0x7U) << 28U)
#define gr_gpcs_zcull_sm_in_gpc_number_map1_r() (0x00418984U) #define gr_gpcs_zcull_sm_in_gpc_number_map1_r() (0x00418984U)
#define gr_gpcs_zcull_sm_in_gpc_number_map1_tile_8_f(v) (((v)&0x7U) << 0U) #define gr_gpcs_zcull_sm_in_gpc_number_map1_tile_8_f(v) ((U32(v) & 0x7U) << 0U)
#define gr_gpcs_zcull_sm_in_gpc_number_map1_tile_9_f(v) (((v)&0x7U) << 4U) #define gr_gpcs_zcull_sm_in_gpc_number_map1_tile_9_f(v) ((U32(v) & 0x7U) << 4U)
#define gr_gpcs_zcull_sm_in_gpc_number_map1_tile_10_f(v) (((v)&0x7U) << 8U) #define gr_gpcs_zcull_sm_in_gpc_number_map1_tile_10_f(v) ((U32(v) & 0x7U) << 8U)
#define gr_gpcs_zcull_sm_in_gpc_number_map1_tile_11_f(v) (((v)&0x7U) << 12U) #define gr_gpcs_zcull_sm_in_gpc_number_map1_tile_11_f(v)\
#define gr_gpcs_zcull_sm_in_gpc_number_map1_tile_12_f(v) (((v)&0x7U) << 16U) ((U32(v) & 0x7U) << 12U)
#define gr_gpcs_zcull_sm_in_gpc_number_map1_tile_13_f(v) (((v)&0x7U) << 20U) #define gr_gpcs_zcull_sm_in_gpc_number_map1_tile_12_f(v)\
#define gr_gpcs_zcull_sm_in_gpc_number_map1_tile_14_f(v) (((v)&0x7U) << 24U) ((U32(v) & 0x7U) << 16U)
#define gr_gpcs_zcull_sm_in_gpc_number_map1_tile_15_f(v) (((v)&0x7U) << 28U) #define gr_gpcs_zcull_sm_in_gpc_number_map1_tile_13_f(v)\
((U32(v) & 0x7U) << 20U)
#define gr_gpcs_zcull_sm_in_gpc_number_map1_tile_14_f(v)\
((U32(v) & 0x7U) << 24U)
#define gr_gpcs_zcull_sm_in_gpc_number_map1_tile_15_f(v)\
((U32(v) & 0x7U) << 28U)
#define gr_gpcs_zcull_sm_in_gpc_number_map2_r() (0x00418988U) #define gr_gpcs_zcull_sm_in_gpc_number_map2_r() (0x00418988U)
#define gr_gpcs_zcull_sm_in_gpc_number_map2_tile_16_f(v) (((v)&0x7U) << 0U) #define gr_gpcs_zcull_sm_in_gpc_number_map2_tile_16_f(v) ((U32(v) & 0x7U) << 0U)
#define gr_gpcs_zcull_sm_in_gpc_number_map2_tile_17_f(v) (((v)&0x7U) << 4U) #define gr_gpcs_zcull_sm_in_gpc_number_map2_tile_17_f(v) ((U32(v) & 0x7U) << 4U)
#define gr_gpcs_zcull_sm_in_gpc_number_map2_tile_18_f(v) (((v)&0x7U) << 8U) #define gr_gpcs_zcull_sm_in_gpc_number_map2_tile_18_f(v) ((U32(v) & 0x7U) << 8U)
#define gr_gpcs_zcull_sm_in_gpc_number_map2_tile_19_f(v) (((v)&0x7U) << 12U) #define gr_gpcs_zcull_sm_in_gpc_number_map2_tile_19_f(v)\
#define gr_gpcs_zcull_sm_in_gpc_number_map2_tile_20_f(v) (((v)&0x7U) << 16U) ((U32(v) & 0x7U) << 12U)
#define gr_gpcs_zcull_sm_in_gpc_number_map2_tile_21_f(v) (((v)&0x7U) << 20U) #define gr_gpcs_zcull_sm_in_gpc_number_map2_tile_20_f(v)\
#define gr_gpcs_zcull_sm_in_gpc_number_map2_tile_22_f(v) (((v)&0x7U) << 24U) ((U32(v) & 0x7U) << 16U)
#define gr_gpcs_zcull_sm_in_gpc_number_map2_tile_21_f(v)\
((U32(v) & 0x7U) << 20U)
#define gr_gpcs_zcull_sm_in_gpc_number_map2_tile_22_f(v)\
((U32(v) & 0x7U) << 24U)
#define gr_gpcs_zcull_sm_in_gpc_number_map2_tile_23_s() (3U) #define gr_gpcs_zcull_sm_in_gpc_number_map2_tile_23_s() (3U)
#define gr_gpcs_zcull_sm_in_gpc_number_map2_tile_23_f(v) (((v)&0x7U) << 28U) #define gr_gpcs_zcull_sm_in_gpc_number_map2_tile_23_f(v)\
((U32(v) & 0x7U) << 28U)
#define gr_gpcs_zcull_sm_in_gpc_number_map2_tile_23_m() (U32(0x7U) << 28U) #define gr_gpcs_zcull_sm_in_gpc_number_map2_tile_23_m() (U32(0x7U) << 28U)
#define gr_gpcs_zcull_sm_in_gpc_number_map2_tile_23_v(r) (((r) >> 28U) & 0x7U) #define gr_gpcs_zcull_sm_in_gpc_number_map2_tile_23_v(r) (((r) >> 28U) & 0x7U)
#define gr_gpcs_zcull_sm_in_gpc_number_map3_r() (0x0041898cU) #define gr_gpcs_zcull_sm_in_gpc_number_map3_r() (0x0041898cU)
#define gr_gpcs_zcull_sm_in_gpc_number_map3_tile_24_f(v) (((v)&0x7U) << 0U) #define gr_gpcs_zcull_sm_in_gpc_number_map3_tile_24_f(v) ((U32(v) & 0x7U) << 0U)
#define gr_gpcs_zcull_sm_in_gpc_number_map3_tile_25_f(v) (((v)&0x7U) << 4U) #define gr_gpcs_zcull_sm_in_gpc_number_map3_tile_25_f(v) ((U32(v) & 0x7U) << 4U)
#define gr_gpcs_zcull_sm_in_gpc_number_map3_tile_26_f(v) (((v)&0x7U) << 8U) #define gr_gpcs_zcull_sm_in_gpc_number_map3_tile_26_f(v) ((U32(v) & 0x7U) << 8U)
#define gr_gpcs_zcull_sm_in_gpc_number_map3_tile_27_f(v) (((v)&0x7U) << 12U) #define gr_gpcs_zcull_sm_in_gpc_number_map3_tile_27_f(v)\
#define gr_gpcs_zcull_sm_in_gpc_number_map3_tile_28_f(v) (((v)&0x7U) << 16U) ((U32(v) & 0x7U) << 12U)
#define gr_gpcs_zcull_sm_in_gpc_number_map3_tile_29_f(v) (((v)&0x7U) << 20U) #define gr_gpcs_zcull_sm_in_gpc_number_map3_tile_28_f(v)\
#define gr_gpcs_zcull_sm_in_gpc_number_map3_tile_30_f(v) (((v)&0x7U) << 24U) ((U32(v) & 0x7U) << 16U)
#define gr_gpcs_zcull_sm_in_gpc_number_map3_tile_31_f(v) (((v)&0x7U) << 28U) #define gr_gpcs_zcull_sm_in_gpc_number_map3_tile_29_f(v)\
((U32(v) & 0x7U) << 20U)
#define gr_gpcs_zcull_sm_in_gpc_number_map3_tile_30_f(v)\
((U32(v) & 0x7U) << 24U)
#define gr_gpcs_zcull_sm_in_gpc_number_map3_tile_31_f(v)\
((U32(v) & 0x7U) << 28U)
#define gr_gpcs_gpm_pd_cfg_r() (0x00418c6cU) #define gr_gpcs_gpm_pd_cfg_r() (0x00418c6cU)
#define gr_gpcs_gpm_pd_cfg_timeslice_mode_disable_f() (0x0U) #define gr_gpcs_gpm_pd_cfg_timeslice_mode_disable_f() (0x0U)
#define gr_gpcs_gpm_pd_cfg_timeslice_mode_enable_f() (0x1U) #define gr_gpcs_gpm_pd_cfg_timeslice_mode_enable_f() (0x1U)
#define gr_gpcs_gcc_pagepool_base_r() (0x00419004U) #define gr_gpcs_gcc_pagepool_base_r() (0x00419004U)
#define gr_gpcs_gcc_pagepool_base_addr_39_8_f(v) (((v)&0xffffffffU) << 0U) #define gr_gpcs_gcc_pagepool_base_addr_39_8_f(v) ((U32(v) & 0xffffffffU) << 0U)
#define gr_gpcs_gcc_pagepool_r() (0x00419008U) #define gr_gpcs_gcc_pagepool_r() (0x00419008U)
#define gr_gpcs_gcc_pagepool_total_pages_f(v) (((v)&0xffU) << 0U) #define gr_gpcs_gcc_pagepool_total_pages_f(v) ((U32(v) & 0xffU) << 0U)
#define gr_gpcs_tpcs_pe_vaf_r() (0x0041980cU) #define gr_gpcs_tpcs_pe_vaf_r() (0x0041980cU)
#define gr_gpcs_tpcs_pe_vaf_fast_mode_switch_true_f() (0x10U) #define gr_gpcs_tpcs_pe_vaf_fast_mode_switch_true_f() (0x10U)
#define gr_gpcs_tpcs_pe_pin_cb_global_base_addr_r() (0x00419848U) #define gr_gpcs_tpcs_pe_pin_cb_global_base_addr_r() (0x00419848U)
#define gr_gpcs_tpcs_pe_pin_cb_global_base_addr_v_f(v) (((v)&0xfffffffU) << 0U) #define gr_gpcs_tpcs_pe_pin_cb_global_base_addr_v_f(v)\
#define gr_gpcs_tpcs_pe_pin_cb_global_base_addr_valid_f(v) (((v)&0x1U) << 28U) ((U32(v) & 0xfffffffU) << 0U)
#define gr_gpcs_tpcs_pe_pin_cb_global_base_addr_valid_f(v)\
((U32(v) & 0x1U) << 28U)
#define gr_gpcs_tpcs_pe_pin_cb_global_base_addr_valid_true_f() (0x10000000U) #define gr_gpcs_tpcs_pe_pin_cb_global_base_addr_valid_true_f() (0x10000000U)
#define gr_gpcs_tpcs_mpc_vtg_debug_r() (0x00419c00U) #define gr_gpcs_tpcs_mpc_vtg_debug_r() (0x00419c00U)
#define gr_gpcs_tpcs_mpc_vtg_debug_timeslice_mode_disabled_f() (0x0U) #define gr_gpcs_tpcs_mpc_vtg_debug_timeslice_mode_disabled_f() (0x0U)
#define gr_gpcs_tpcs_mpc_vtg_debug_timeslice_mode_enabled_f() (0x8U) #define gr_gpcs_tpcs_mpc_vtg_debug_timeslice_mode_enabled_f() (0x8U)
#define gr_gpcs_tpcs_mpc_vtg_cb_global_base_addr_r() (0x00419c2cU) #define gr_gpcs_tpcs_mpc_vtg_cb_global_base_addr_r() (0x00419c2cU)
#define gr_gpcs_tpcs_mpc_vtg_cb_global_base_addr_v_f(v) (((v)&0xfffffffU) << 0U) #define gr_gpcs_tpcs_mpc_vtg_cb_global_base_addr_v_f(v)\
#define gr_gpcs_tpcs_mpc_vtg_cb_global_base_addr_valid_f(v) (((v)&0x1U) << 28U) ((U32(v) & 0xfffffffU) << 0U)
#define gr_gpcs_tpcs_mpc_vtg_cb_global_base_addr_valid_f(v)\
((U32(v) & 0x1U) << 28U)
#define gr_gpcs_tpcs_mpc_vtg_cb_global_base_addr_valid_true_f() (0x10000000U) #define gr_gpcs_tpcs_mpc_vtg_cb_global_base_addr_valid_true_f() (0x10000000U)
#define gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_r() (0x00419e44U) #define gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_r() (0x00419e44U)
#define gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_stack_error_report_f() (0x2U) #define gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_stack_error_report_f() (0x2U)
@@ -889,7 +913,7 @@
#define gr_gpc0_tpc0_tpccs_tpc_exception_en_sm_enabled_f() (0x2U) #define gr_gpc0_tpc0_tpccs_tpc_exception_en_sm_enabled_f() (0x2U)
#define gr_gpc0_tpc0_tpccs_tpc_exception_en_sm_v(r) (((r) >> 1U) & 0x1U) #define gr_gpc0_tpc0_tpccs_tpc_exception_en_sm_v(r) (((r) >> 1U) & 0x1U)
#define gr_gpcs_gpccs_gpc_exception_en_r() (0x0041ac94U) #define gr_gpcs_gpccs_gpc_exception_en_r() (0x0041ac94U)
#define gr_gpcs_gpccs_gpc_exception_en_tpc_f(v) (((v)&0xffU) << 16U) #define gr_gpcs_gpccs_gpc_exception_en_tpc_f(v) ((U32(v) & 0xffU) << 16U)
#define gr_gpc0_gpccs_gpc_exception_r() (0x00502c90U) #define gr_gpc0_gpccs_gpc_exception_r() (0x00502c90U)
#define gr_gpc0_gpccs_gpc_exception_gcc_v(r) (((r) >> 2U) & 0x1U) #define gr_gpc0_gpccs_gpc_exception_gcc_v(r) (((r) >> 2U) & 0x1U)
#define gr_gpc0_gpccs_gpc_exception_tpc_v(r) (((r) >> 16U) & 0xffU) #define gr_gpc0_gpccs_gpc_exception_tpc_v(r) (((r) >> 16U) & 0xffU)
@@ -967,11 +991,13 @@
#define gr_gpc0_tpc0_sm_halfctl_ctrl_r() (0x00504770U) #define gr_gpc0_tpc0_sm_halfctl_ctrl_r() (0x00504770U)
#define gr_gpcs_tpcs_sm_halfctl_ctrl_r() (0x00419f70U) #define gr_gpcs_tpcs_sm_halfctl_ctrl_r() (0x00419f70U)
#define gr_gpcs_tpcs_sm_halfctl_ctrl_sctl_read_quad_ctl_m() (U32(0x1U) << 4U) #define gr_gpcs_tpcs_sm_halfctl_ctrl_sctl_read_quad_ctl_m() (U32(0x1U) << 4U)
#define gr_gpcs_tpcs_sm_halfctl_ctrl_sctl_read_quad_ctl_f(v) (((v)&0x1U) << 4U) #define gr_gpcs_tpcs_sm_halfctl_ctrl_sctl_read_quad_ctl_f(v)\
((U32(v) & 0x1U) << 4U)
#define gr_gpc0_tpc0_sm_debug_sfe_control_r() (0x0050477cU) #define gr_gpc0_tpc0_sm_debug_sfe_control_r() (0x0050477cU)
#define gr_gpcs_tpcs_sm_debug_sfe_control_r() (0x00419f7cU) #define gr_gpcs_tpcs_sm_debug_sfe_control_r() (0x00419f7cU)
#define gr_gpcs_tpcs_sm_debug_sfe_control_read_half_ctl_m() (U32(0x1U) << 0U) #define gr_gpcs_tpcs_sm_debug_sfe_control_read_half_ctl_m() (U32(0x1U) << 0U)
#define gr_gpcs_tpcs_sm_debug_sfe_control_read_half_ctl_f(v) (((v)&0x1U) << 0U) #define gr_gpcs_tpcs_sm_debug_sfe_control_read_half_ctl_f(v)\
((U32(v) & 0x1U) << 0U)
#define gr_gpcs_tpcs_pes_vsc_vpc_r() (0x0041be08U) #define gr_gpcs_tpcs_pes_vsc_vpc_r() (0x0041be08U)
#define gr_gpcs_tpcs_pes_vsc_vpc_fast_mode_switch_true_f() (0x4U) #define gr_gpcs_tpcs_pes_vsc_vpc_fast_mode_switch_true_f() (0x4U)
#define gr_ppcs_wwdx_map_gpc_map0_r() (0x0041bf00U) #define gr_ppcs_wwdx_map_gpc_map0_r() (0x0041bf00U)
@@ -981,29 +1007,37 @@
#define gr_ppcs_wwdx_map_gpc_map4_r() (0x0041bf10U) #define gr_ppcs_wwdx_map_gpc_map4_r() (0x0041bf10U)
#define gr_ppcs_wwdx_map_gpc_map5_r() (0x0041bf14U) #define gr_ppcs_wwdx_map_gpc_map5_r() (0x0041bf14U)
#define gr_ppcs_wwdx_map_table_cfg_r() (0x0041bfd0U) #define gr_ppcs_wwdx_map_table_cfg_r() (0x0041bfd0U)
#define gr_ppcs_wwdx_map_table_cfg_row_offset_f(v) (((v)&0xffU) << 0U) #define gr_ppcs_wwdx_map_table_cfg_row_offset_f(v) ((U32(v) & 0xffU) << 0U)
#define gr_ppcs_wwdx_map_table_cfg_num_entries_f(v) (((v)&0xffU) << 8U) #define gr_ppcs_wwdx_map_table_cfg_num_entries_f(v) ((U32(v) & 0xffU) << 8U)
#define gr_ppcs_wwdx_map_table_cfg_normalized_num_entries_f(v)\ #define gr_ppcs_wwdx_map_table_cfg_normalized_num_entries_f(v)\
(((v)&0x1fU) << 16U) ((U32(v) & 0x1fU) << 16U)
#define gr_ppcs_wwdx_map_table_cfg_normalized_shift_value_f(v)\ #define gr_ppcs_wwdx_map_table_cfg_normalized_shift_value_f(v)\
(((v)&0x7U) << 21U) ((U32(v) & 0x7U) << 21U)
#define gr_ppcs_wwdx_map_table_cfg_coeff5_mod_value_f(v) (((v)&0x1fU) << 24U) #define gr_ppcs_wwdx_map_table_cfg_coeff5_mod_value_f(v)\
((U32(v) & 0x1fU) << 24U)
#define gr_gpcs_ppcs_wwdx_sm_num_rcp_r() (0x0041bfd4U) #define gr_gpcs_ppcs_wwdx_sm_num_rcp_r() (0x0041bfd4U)
#define gr_gpcs_ppcs_wwdx_sm_num_rcp_conservative_f(v) (((v)&0xffffffU) << 0U) #define gr_gpcs_ppcs_wwdx_sm_num_rcp_conservative_f(v)\
((U32(v) & 0xffffffU) << 0U)
#define gr_ppcs_wwdx_map_table_cfg2_r() (0x0041bfe4U) #define gr_ppcs_wwdx_map_table_cfg2_r() (0x0041bfe4U)
#define gr_ppcs_wwdx_map_table_cfg2_coeff6_mod_value_f(v) (((v)&0x1fU) << 0U) #define gr_ppcs_wwdx_map_table_cfg2_coeff6_mod_value_f(v)\
#define gr_ppcs_wwdx_map_table_cfg2_coeff7_mod_value_f(v) (((v)&0x1fU) << 5U) ((U32(v) & 0x1fU) << 0U)
#define gr_ppcs_wwdx_map_table_cfg2_coeff8_mod_value_f(v) (((v)&0x1fU) << 10U) #define gr_ppcs_wwdx_map_table_cfg2_coeff7_mod_value_f(v)\
#define gr_ppcs_wwdx_map_table_cfg2_coeff9_mod_value_f(v) (((v)&0x1fU) << 15U) ((U32(v) & 0x1fU) << 5U)
#define gr_ppcs_wwdx_map_table_cfg2_coeff10_mod_value_f(v) (((v)&0x1fU) << 20U) #define gr_ppcs_wwdx_map_table_cfg2_coeff8_mod_value_f(v)\
#define gr_ppcs_wwdx_map_table_cfg2_coeff11_mod_value_f(v) (((v)&0x1fU) << 25U) ((U32(v) & 0x1fU) << 10U)
#define gr_ppcs_wwdx_map_table_cfg2_coeff9_mod_value_f(v)\
((U32(v) & 0x1fU) << 15U)
#define gr_ppcs_wwdx_map_table_cfg2_coeff10_mod_value_f(v)\
((U32(v) & 0x1fU) << 20U)
#define gr_ppcs_wwdx_map_table_cfg2_coeff11_mod_value_f(v)\
((U32(v) & 0x1fU) << 25U)
#define gr_bes_zrop_settings_r() (0x00408850U) #define gr_bes_zrop_settings_r() (0x00408850U)
#define gr_bes_zrop_settings_num_active_ltcs_f(v) (((v)&0xfU) << 0U) #define gr_bes_zrop_settings_num_active_ltcs_f(v) ((U32(v) & 0xfU) << 0U)
#define gr_be0_crop_debug3_r() (0x00410108U) #define gr_be0_crop_debug3_r() (0x00410108U)
#define gr_bes_crop_debug3_r() (0x00408908U) #define gr_bes_crop_debug3_r() (0x00408908U)
#define gr_bes_crop_debug3_comp_vdc_4to2_disable_m() (U32(0x1U) << 31U) #define gr_bes_crop_debug3_comp_vdc_4to2_disable_m() (U32(0x1U) << 31U)
#define gr_bes_crop_settings_r() (0x00408958U) #define gr_bes_crop_settings_r() (0x00408958U)
#define gr_bes_crop_settings_num_active_ltcs_f(v) (((v)&0xfU) << 0U) #define gr_bes_crop_settings_num_active_ltcs_f(v) ((U32(v) & 0xfU) << 0U)
#define gr_zcull_bytes_per_aliquot_per_gpu_v() (0x00000020U) #define gr_zcull_bytes_per_aliquot_per_gpu_v() (0x00000020U)
#define gr_zcull_save_restore_header_bytes_per_gpc_v() (0x00000020U) #define gr_zcull_save_restore_header_bytes_per_gpc_v() (0x00000020U)
#define gr_zcull_save_restore_subregion_header_bytes_per_gpc_v() (0x000000c0U) #define gr_zcull_save_restore_subregion_header_bytes_per_gpc_v() (0x000000c0U)
@@ -1064,7 +1098,7 @@
#define gr_gpcs_pri_mmu_debug_rd_r() (0x004188b8U) #define gr_gpcs_pri_mmu_debug_rd_r() (0x004188b8U)
#define gr_gpcs_mmu_num_active_ltcs_r() (0x004188acU) #define gr_gpcs_mmu_num_active_ltcs_r() (0x004188acU)
#define gr_gpcs_tpcs_sm_dbgr_control0_r() (0x00419e10U) #define gr_gpcs_tpcs_sm_dbgr_control0_r() (0x00419e10U)
#define gr_gpcs_tpcs_sm_dbgr_control0_debugger_mode_f(v) (((v)&0x1U) << 0U) #define gr_gpcs_tpcs_sm_dbgr_control0_debugger_mode_f(v) ((U32(v) & 0x1U) << 0U)
#define gr_gpcs_tpcs_sm_dbgr_control0_debugger_mode_on_v() (0x00000001U) #define gr_gpcs_tpcs_sm_dbgr_control0_debugger_mode_on_v() (0x00000001U)
#define gr_gpcs_tpcs_sm_dbgr_control0_stop_trigger_m() (U32(0x1U) << 31U) #define gr_gpcs_tpcs_sm_dbgr_control0_stop_trigger_m() (U32(0x1U) << 31U)
#define gr_gpcs_tpcs_sm_dbgr_control0_stop_trigger_v(r) (((r) >> 31U) & 0x1U) #define gr_gpcs_tpcs_sm_dbgr_control0_stop_trigger_v(r) (((r) >> 31U) & 0x1U)

12
drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_ltc_gm20b.h
View File

@@ -82,9 +82,11 @@
#define ltc_ltcs_ltss_cbc_ctrl1_clear_active_f() (0x4U) #define ltc_ltcs_ltss_cbc_ctrl1_clear_active_f() (0x4U)
#define ltc_ltc0_lts0_cbc_ctrl1_r() (0x0014046cU) #define ltc_ltc0_lts0_cbc_ctrl1_r() (0x0014046cU)
#define ltc_ltcs_ltss_cbc_ctrl2_r() (0x0017e270U) #define ltc_ltcs_ltss_cbc_ctrl2_r() (0x0017e270U)
#define ltc_ltcs_ltss_cbc_ctrl2_clear_lower_bound_f(v) (((v)&0x1ffffU) << 0U) #define ltc_ltcs_ltss_cbc_ctrl2_clear_lower_bound_f(v)\
((U32(v) & 0x1ffffU) << 0U)
#define ltc_ltcs_ltss_cbc_ctrl3_r() (0x0017e274U) #define ltc_ltcs_ltss_cbc_ctrl3_r() (0x0017e274U)
#define ltc_ltcs_ltss_cbc_ctrl3_clear_upper_bound_f(v) (((v)&0x1ffffU) << 0U) #define ltc_ltcs_ltss_cbc_ctrl3_clear_upper_bound_f(v)\
((U32(v) & 0x1ffffU) << 0U)
#define ltc_ltcs_ltss_cbc_ctrl3_clear_upper_bound_init_v() (0x0001ffffU) #define ltc_ltcs_ltss_cbc_ctrl3_clear_upper_bound_init_v() (0x0001ffffU)
#define ltc_ltcs_ltss_cbc_base_r() (0x0017e278U) #define ltc_ltcs_ltss_cbc_base_r() (0x0017e278U)
#define ltc_ltcs_ltss_cbc_base_alignment_shift_v() (0x0000000bU) #define ltc_ltcs_ltss_cbc_base_alignment_shift_v() (0x0000000bU)
@@ -98,16 +100,16 @@
#define ltc_ltcs_ltss_cbc_param_slices_per_ltc_v(r) (((r) >> 28U) & 0xfU) #define ltc_ltcs_ltss_cbc_param_slices_per_ltc_v(r) (((r) >> 28U) & 0xfU)
#define ltc_ltcs_ltss_tstg_set_mgmt_r() (0x0017e2acU) #define ltc_ltcs_ltss_tstg_set_mgmt_r() (0x0017e2acU)
#define ltc_ltcs_ltss_tstg_set_mgmt_max_ways_evict_last_f(v)\ #define ltc_ltcs_ltss_tstg_set_mgmt_max_ways_evict_last_f(v)\
(((v)&0x1fU) << 16U) ((U32(v) & 0x1fU) << 16U)
#define ltc_ltcs_ltss_dstg_zbc_index_r() (0x0017e338U) #define ltc_ltcs_ltss_dstg_zbc_index_r() (0x0017e338U)
#define ltc_ltcs_ltss_dstg_zbc_index_address_f(v) (((v)&0xfU) << 0U) #define ltc_ltcs_ltss_dstg_zbc_index_address_f(v) ((U32(v) & 0xfU) << 0U)
#define ltc_ltcs_ltss_dstg_zbc_color_clear_value_r(i)\ #define ltc_ltcs_ltss_dstg_zbc_color_clear_value_r(i)\
(nvgpu_safe_add_u32(0x0017e33cU, nvgpu_safe_mult_u32((i), 4U))) (nvgpu_safe_add_u32(0x0017e33cU, nvgpu_safe_mult_u32((i), 4U)))
#define ltc_ltcs_ltss_dstg_zbc_color_clear_value__size_1_v() (0x00000004U) #define ltc_ltcs_ltss_dstg_zbc_color_clear_value__size_1_v() (0x00000004U)
#define ltc_ltcs_ltss_dstg_zbc_depth_clear_value_r() (0x0017e34cU) #define ltc_ltcs_ltss_dstg_zbc_depth_clear_value_r() (0x0017e34cU)
#define ltc_ltcs_ltss_dstg_zbc_depth_clear_value_field_s() (32U) #define ltc_ltcs_ltss_dstg_zbc_depth_clear_value_field_s() (32U)
#define ltc_ltcs_ltss_dstg_zbc_depth_clear_value_field_f(v)\ #define ltc_ltcs_ltss_dstg_zbc_depth_clear_value_field_f(v)\
(((v)&0xffffffffU) << 0U) ((U32(v) & 0xffffffffU) << 0U)
#define ltc_ltcs_ltss_dstg_zbc_depth_clear_value_field_m()\ #define ltc_ltcs_ltss_dstg_zbc_depth_clear_value_field_m()\
(U32(0xffffffffU) << 0U) (U32(0xffffffffU) << 0U)
#define ltc_ltcs_ltss_dstg_zbc_depth_clear_value_field_v(r)\ #define ltc_ltcs_ltss_dstg_zbc_depth_clear_value_field_v(r)\

8
drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_mc_gm20b.h
View File

@@ -78,7 +78,7 @@
#define mc_intr_en_0_inta_hardware_f() (0x1U) #define mc_intr_en_0_inta_hardware_f() (0x1U)
#define mc_intr_mask_1_r() (0x00000644U) #define mc_intr_mask_1_r() (0x00000644U)
#define mc_intr_mask_1_pmu_s() (1U) #define mc_intr_mask_1_pmu_s() (1U)
#define mc_intr_mask_1_pmu_f(v) (((v)&0x1U) << 24U) #define mc_intr_mask_1_pmu_f(v) ((U32(v) & 0x1U) << 24U)
#define mc_intr_mask_1_pmu_m() (U32(0x1U) << 24U) #define mc_intr_mask_1_pmu_m() (U32(0x1U) << 24U)
#define mc_intr_mask_1_pmu_v(r) (((r) >> 24U) & 0x1U) #define mc_intr_mask_1_pmu_v(r) (((r) >> 24U) & 0x1U)
#define mc_intr_mask_1_pmu_enabled_f() (0x1000000U) #define mc_intr_mask_1_pmu_enabled_f() (0x1000000U)
@@ -89,7 +89,7 @@
#define mc_enable_xbar_enabled_f() (0x4U) #define mc_enable_xbar_enabled_f() (0x4U)
#define mc_enable_l2_enabled_f() (0x8U) #define mc_enable_l2_enabled_f() (0x8U)
#define mc_enable_pmedia_s() (1U) #define mc_enable_pmedia_s() (1U)
#define mc_enable_pmedia_f(v) (((v)&0x1U) << 4U) #define mc_enable_pmedia_f(v) ((U32(v) & 0x1U) << 4U)
#define mc_enable_pmedia_m() (U32(0x1U) << 4U) #define mc_enable_pmedia_m() (U32(0x1U) << 4U)
#define mc_enable_pmedia_v(r) (((r) >> 4U) & 0x1U) #define mc_enable_pmedia_v(r) (((r) >> 4U) & 0x1U)
#define mc_enable_priv_ring_enabled_f() (0x20U) #define mc_enable_priv_ring_enabled_f() (0x20U)
@@ -108,12 +108,12 @@
#define mc_intr_ltc_r() (0x0000017cU) #define mc_intr_ltc_r() (0x0000017cU)
#define mc_enable_pb_r() (0x00000204U) #define mc_enable_pb_r() (0x00000204U)
#define mc_enable_pb_0_s() (1U) #define mc_enable_pb_0_s() (1U)
#define mc_enable_pb_0_f(v) (((v)&0x1U) << 0U) #define mc_enable_pb_0_f(v) ((U32(v) & 0x1U) << 0U)
#define mc_enable_pb_0_m() (U32(0x1U) << 0U) #define mc_enable_pb_0_m() (U32(0x1U) << 0U)
#define mc_enable_pb_0_v(r) (((r) >> 0U) & 0x1U) #define mc_enable_pb_0_v(r) (((r) >> 0U) & 0x1U)
#define mc_enable_pb_0_enabled_v() (0x00000001U) #define mc_enable_pb_0_enabled_v() (0x00000001U)
#define mc_enable_pb_sel_f(v, i)\ #define mc_enable_pb_sel_f(v, i)\
(((v) & 0x1) << (0U + i*1U)) ((U32(v) & 0x1U) << (0U + (i)*1U))
#define mc_elpg_enable_r() (0x0000020cU) #define mc_elpg_enable_r() (0x0000020cU)
#define mc_elpg_enable_xbar_enabled_f() (0x4U) #define mc_elpg_enable_xbar_enabled_f() (0x4U)
#define mc_elpg_enable_pfb_enabled_f() (0x100000U) #define mc_elpg_enable_pfb_enabled_f() (0x100000U)

20
drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_pbdma_gm20b.h
View File

@@ -61,17 +61,17 @@
#define pbdma_gp_entry1_r() (0x10000004U) #define pbdma_gp_entry1_r() (0x10000004U)
#define pbdma_gp_entry1_get_hi_v(r) (((r) >> 0U) & 0xffU) #define pbdma_gp_entry1_get_hi_v(r) (((r) >> 0U) & 0xffU)
#define pbdma_gp_entry1_length_f(v) (((v)&0x1fffffU) << 10U) #define pbdma_gp_entry1_length_f(v) ((U32(v) & 0x1fffffU) << 10U)
#define pbdma_gp_entry1_length_v(r) (((r) >> 10U) & 0x1fffffU) #define pbdma_gp_entry1_length_v(r) (((r) >> 10U) & 0x1fffffU)
#define pbdma_gp_base_r(i)\ #define pbdma_gp_base_r(i)\
(nvgpu_safe_add_u32(0x00040048U, nvgpu_safe_mult_u32((i), 8192U))) (nvgpu_safe_add_u32(0x00040048U, nvgpu_safe_mult_u32((i), 8192U)))
#define pbdma_gp_base__size_1_v() (0x00000001U) #define pbdma_gp_base__size_1_v() (0x00000001U)
#define pbdma_gp_base_offset_f(v) (((v)&0x1fffffffU) << 3U) #define pbdma_gp_base_offset_f(v) ((U32(v) & 0x1fffffffU) << 3U)
#define pbdma_gp_base_rsvd_s() (3U) #define pbdma_gp_base_rsvd_s() (3U)
#define pbdma_gp_base_hi_r(i)\ #define pbdma_gp_base_hi_r(i)\
(nvgpu_safe_add_u32(0x0004004cU, nvgpu_safe_mult_u32((i), 8192U))) (nvgpu_safe_add_u32(0x0004004cU, nvgpu_safe_mult_u32((i), 8192U)))
#define pbdma_gp_base_hi_offset_f(v) (((v)&0xffU) << 0U) #define pbdma_gp_base_hi_offset_f(v) ((U32(v) & 0xffU) << 0U)
#define pbdma_gp_base_hi_limit2_f(v) (((v)&0x1fU) << 16U) #define pbdma_gp_base_hi_limit2_f(v) ((U32(v) & 0x1fU) << 16U)
#define pbdma_gp_fetch_r(i)\ #define pbdma_gp_fetch_r(i)\
(nvgpu_safe_add_u32(0x00040050U, nvgpu_safe_mult_u32((i), 8192U))) (nvgpu_safe_add_u32(0x00040050U, nvgpu_safe_mult_u32((i), 8192U)))
#define pbdma_gp_get_r(i)\ #define pbdma_gp_get_r(i)\
@@ -117,13 +117,13 @@
(nvgpu_safe_add_u32(0x00040114U, nvgpu_safe_mult_u32((i), 8192U))) (nvgpu_safe_add_u32(0x00040114U, nvgpu_safe_mult_u32((i), 8192U)))
#define pbdma_subdevice_r(i)\ #define pbdma_subdevice_r(i)\
(nvgpu_safe_add_u32(0x00040094U, nvgpu_safe_mult_u32((i), 8192U))) (nvgpu_safe_add_u32(0x00040094U, nvgpu_safe_mult_u32((i), 8192U)))
#define pbdma_subdevice_id_f(v) (((v)&0xfffU) << 0U) #define pbdma_subdevice_id_f(v) ((U32(v) & 0xfffU) << 0U)
#define pbdma_subdevice_status_active_f() (0x10000000U) #define pbdma_subdevice_status_active_f() (0x10000000U)
#define pbdma_subdevice_channel_dma_enable_f() (0x20000000U) #define pbdma_subdevice_channel_dma_enable_f() (0x20000000U)
#define pbdma_method0_r(i)\ #define pbdma_method0_r(i)\
(nvgpu_safe_add_u32(0x000400c0U, nvgpu_safe_mult_u32((i), 8192U))) (nvgpu_safe_add_u32(0x000400c0U, nvgpu_safe_mult_u32((i), 8192U)))
#define pbdma_method0_fifo_size_v() (0x00000004U) #define pbdma_method0_fifo_size_v() (0x00000004U)
#define pbdma_method0_addr_f(v) (((v)&0xfffU) << 2U) #define pbdma_method0_addr_f(v) ((U32(v) & 0xfffU) << 2U)
#define pbdma_method0_addr_v(r) (((r) >> 2U) & 0xfffU) #define pbdma_method0_addr_v(r) (((r) >> 2U) & 0xfffU)
#define pbdma_method0_subch_v(r) (((r) >> 16U) & 0x7U) #define pbdma_method0_subch_v(r) (((r) >> 16U) & 0x7U)
#define pbdma_method0_first_true_f() (0x400000U) #define pbdma_method0_first_true_f() (0x400000U)
@@ -143,10 +143,10 @@
(nvgpu_safe_add_u32(0x00040030U, nvgpu_safe_mult_u32((i), 8192U))) (nvgpu_safe_add_u32(0x00040030U, nvgpu_safe_mult_u32((i), 8192U)))
#define pbdma_acquire_retry_man_2_f() (0x2U) #define pbdma_acquire_retry_man_2_f() (0x2U)
#define pbdma_acquire_retry_exp_2_f() (0x100U) #define pbdma_acquire_retry_exp_2_f() (0x100U)
#define pbdma_acquire_timeout_exp_f(v) (((v)&0xfU) << 11U) #define pbdma_acquire_timeout_exp_f(v) ((U32(v) & 0xfU) << 11U)
#define pbdma_acquire_timeout_exp_max_v() (0x0000000fU) #define pbdma_acquire_timeout_exp_max_v() (0x0000000fU)
#define pbdma_acquire_timeout_exp_max_f() (0x7800U) #define pbdma_acquire_timeout_exp_max_f() (0x7800U)
#define pbdma_acquire_timeout_man_f(v) (((v)&0xffffU) << 15U) #define pbdma_acquire_timeout_man_f(v) ((U32(v) & 0xffffU) << 15U)
#define pbdma_acquire_timeout_man_max_v() (0x0000ffffU) #define pbdma_acquire_timeout_man_max_v() (0x0000ffffU)
#define pbdma_acquire_timeout_man_max_f() (0x7fff8000U) #define pbdma_acquire_timeout_man_max_f() (0x7fff8000U)
#define pbdma_acquire_timeout_en_enable_f() (0x80000000U) #define pbdma_acquire_timeout_en_enable_f() (0x80000000U)
@@ -164,10 +164,10 @@
#define pbdma_userd_target_vid_mem_f() (0x0U) #define pbdma_userd_target_vid_mem_f() (0x0U)
#define pbdma_userd_target_sys_mem_coh_f() (0x2U) #define pbdma_userd_target_sys_mem_coh_f() (0x2U)
#define pbdma_userd_target_sys_mem_ncoh_f() (0x3U) #define pbdma_userd_target_sys_mem_ncoh_f() (0x3U)
#define pbdma_userd_addr_f(v) (((v)&0x7fffffU) << 9U) #define pbdma_userd_addr_f(v) ((U32(v) & 0x7fffffU) << 9U)
#define pbdma_userd_hi_r(i)\ #define pbdma_userd_hi_r(i)\
(nvgpu_safe_add_u32(0x0004000cU, nvgpu_safe_mult_u32((i), 8192U))) (nvgpu_safe_add_u32(0x0004000cU, nvgpu_safe_mult_u32((i), 8192U)))
#define pbdma_userd_hi_addr_f(v) (((v)&0xffU) << 0U) #define pbdma_userd_hi_addr_f(v) ((U32(v) & 0xffU) << 0U)
#define pbdma_hce_ctrl_r(i)\ #define pbdma_hce_ctrl_r(i)\
(nvgpu_safe_add_u32(0x000400e4U, nvgpu_safe_mult_u32((i), 8192U))) (nvgpu_safe_add_u32(0x000400e4U, nvgpu_safe_mult_u32((i), 8192U)))
#define pbdma_hce_ctrl_hce_priv_mode_yes_f() (0x20U) #define pbdma_hce_ctrl_hce_priv_mode_yes_f() (0x20U)

20
drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_perf_gm20b.h
View File

@@ -65,13 +65,13 @@
#define perf_pmasys_control_membuf_status_v(r) (((r) >> 4U) & 0x1U) #define perf_pmasys_control_membuf_status_v(r) (((r) >> 4U) & 0x1U)
#define perf_pmasys_control_membuf_status_overflowed_v() (0x00000001U) #define perf_pmasys_control_membuf_status_overflowed_v() (0x00000001U)
#define perf_pmasys_control_membuf_status_overflowed_f() (0x10U) #define perf_pmasys_control_membuf_status_overflowed_f() (0x10U)
#define perf_pmasys_control_membuf_clear_status_f(v) (((v)&0x1U) << 5U) #define perf_pmasys_control_membuf_clear_status_f(v) ((U32(v) & 0x1U) << 5U)
#define perf_pmasys_control_membuf_clear_status_v(r) (((r) >> 5U) & 0x1U) #define perf_pmasys_control_membuf_clear_status_v(r) (((r) >> 5U) & 0x1U)
#define perf_pmasys_control_membuf_clear_status_doit_v() (0x00000001U) #define perf_pmasys_control_membuf_clear_status_doit_v() (0x00000001U)
#define perf_pmasys_control_membuf_clear_status_doit_f() (0x20U) #define perf_pmasys_control_membuf_clear_status_doit_f() (0x20U)
#define perf_pmasys_mem_block_r() (0x001b4070U) #define perf_pmasys_mem_block_r() (0x001b4070U)
#define perf_pmasys_mem_block_base_f(v) (((v)&0xfffffffU) << 0U) #define perf_pmasys_mem_block_base_f(v) ((U32(v) & 0xfffffffU) << 0U)
#define perf_pmasys_mem_block_target_f(v) (((v)&0x3U) << 28U) #define perf_pmasys_mem_block_target_f(v) ((U32(v) & 0x3U) << 28U)
#define perf_pmasys_mem_block_target_v(r) (((r) >> 28U) & 0x3U) #define perf_pmasys_mem_block_target_v(r) (((r) >> 28U) & 0x3U)
#define perf_pmasys_mem_block_target_lfb_v() (0x00000000U) #define perf_pmasys_mem_block_target_lfb_v() (0x00000000U)
#define perf_pmasys_mem_block_target_lfb_f() (0x0U) #define perf_pmasys_mem_block_target_lfb_f() (0x0U)
@@ -79,24 +79,24 @@
#define perf_pmasys_mem_block_target_sys_coh_f() (0x20000000U) #define perf_pmasys_mem_block_target_sys_coh_f() (0x20000000U)
#define perf_pmasys_mem_block_target_sys_ncoh_v() (0x00000003U) #define perf_pmasys_mem_block_target_sys_ncoh_v() (0x00000003U)
#define perf_pmasys_mem_block_target_sys_ncoh_f() (0x30000000U) #define perf_pmasys_mem_block_target_sys_ncoh_f() (0x30000000U)
#define perf_pmasys_mem_block_valid_f(v) (((v)&0x1U) << 31U) #define perf_pmasys_mem_block_valid_f(v) ((U32(v) & 0x1U) << 31U)
#define perf_pmasys_mem_block_valid_v(r) (((r) >> 31U) & 0x1U) #define perf_pmasys_mem_block_valid_v(r) (((r) >> 31U) & 0x1U)
#define perf_pmasys_mem_block_valid_true_v() (0x00000001U) #define perf_pmasys_mem_block_valid_true_v() (0x00000001U)
#define perf_pmasys_mem_block_valid_true_f() (0x80000000U) #define perf_pmasys_mem_block_valid_true_f() (0x80000000U)
#define perf_pmasys_mem_block_valid_false_v() (0x00000000U) #define perf_pmasys_mem_block_valid_false_v() (0x00000000U)
#define perf_pmasys_mem_block_valid_false_f() (0x0U) #define perf_pmasys_mem_block_valid_false_f() (0x0U)
#define perf_pmasys_outbase_r() (0x001b4074U) #define perf_pmasys_outbase_r() (0x001b4074U)
#define perf_pmasys_outbase_ptr_f(v) (((v)&0x7ffffffU) << 5U) #define perf_pmasys_outbase_ptr_f(v) ((U32(v) & 0x7ffffffU) << 5U)
#define perf_pmasys_outbaseupper_r() (0x001b4078U) #define perf_pmasys_outbaseupper_r() (0x001b4078U)
#define perf_pmasys_outbaseupper_ptr_f(v) (((v)&0xffU) << 0U) #define perf_pmasys_outbaseupper_ptr_f(v) ((U32(v) & 0xffU) << 0U)
#define perf_pmasys_outsize_r() (0x001b407cU) #define perf_pmasys_outsize_r() (0x001b407cU)
#define perf_pmasys_outsize_numbytes_f(v) (((v)&0x7ffffffU) << 5U) #define perf_pmasys_outsize_numbytes_f(v) ((U32(v) & 0x7ffffffU) << 5U)
#define perf_pmasys_mem_bytes_r() (0x001b4084U) #define perf_pmasys_mem_bytes_r() (0x001b4084U)
#define perf_pmasys_mem_bytes_numbytes_f(v) (((v)&0xfffffffU) << 4U) #define perf_pmasys_mem_bytes_numbytes_f(v) ((U32(v) & 0xfffffffU) << 4U)
#define perf_pmasys_mem_bump_r() (0x001b4088U) #define perf_pmasys_mem_bump_r() (0x001b4088U)
#define perf_pmasys_mem_bump_numbytes_f(v) (((v)&0xfffffffU) << 4U) #define perf_pmasys_mem_bump_numbytes_f(v) ((U32(v) & 0xfffffffU) << 4U)
#define perf_pmasys_enginestatus_r() (0x001b40a4U) #define perf_pmasys_enginestatus_r() (0x001b40a4U)
#define perf_pmasys_enginestatus_rbufempty_f(v) (((v)&0x1U) << 4U) #define perf_pmasys_enginestatus_rbufempty_f(v) ((U32(v) & 0x1U) << 4U)
#define perf_pmasys_enginestatus_rbufempty_empty_v() (0x00000001U) #define perf_pmasys_enginestatus_rbufempty_empty_v() (0x00000001U)
#define perf_pmasys_enginestatus_rbufempty_empty_f() (0x10U) #define perf_pmasys_enginestatus_rbufempty_empty_f() (0x10U)
#endif #endif

136
drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_pwr_gm20b.h
View File

@@ -68,44 +68,44 @@
#define pwr_falcon_irqstat_swgen0_true_f() (0x40U) #define pwr_falcon_irqstat_swgen0_true_f() (0x40U)
#define pwr_falcon_irqmode_r() (0x0010a00cU) #define pwr_falcon_irqmode_r() (0x0010a00cU)
#define pwr_falcon_irqmset_r() (0x0010a010U) #define pwr_falcon_irqmset_r() (0x0010a010U)
#define pwr_falcon_irqmset_gptmr_f(v) (((v)&0x1U) << 0U) #define pwr_falcon_irqmset_gptmr_f(v) ((U32(v) & 0x1U) << 0U)
#define pwr_falcon_irqmset_wdtmr_f(v) (((v)&0x1U) << 1U) #define pwr_falcon_irqmset_wdtmr_f(v) ((U32(v) & 0x1U) << 1U)
#define pwr_falcon_irqmset_mthd_f(v) (((v)&0x1U) << 2U) #define pwr_falcon_irqmset_mthd_f(v) ((U32(v) & 0x1U) << 2U)
#define pwr_falcon_irqmset_ctxsw_f(v) (((v)&0x1U) << 3U) #define pwr_falcon_irqmset_ctxsw_f(v) ((U32(v) & 0x1U) << 3U)
#define pwr_falcon_irqmset_halt_f(v) (((v)&0x1U) << 4U) #define pwr_falcon_irqmset_halt_f(v) ((U32(v) & 0x1U) << 4U)
#define pwr_falcon_irqmset_exterr_f(v) (((v)&0x1U) << 5U) #define pwr_falcon_irqmset_exterr_f(v) ((U32(v) & 0x1U) << 5U)
#define pwr_falcon_irqmset_swgen0_f(v) (((v)&0x1U) << 6U) #define pwr_falcon_irqmset_swgen0_f(v) ((U32(v) & 0x1U) << 6U)
#define pwr_falcon_irqmset_swgen1_f(v) (((v)&0x1U) << 7U) #define pwr_falcon_irqmset_swgen1_f(v) ((U32(v) & 0x1U) << 7U)
#define pwr_falcon_irqmclr_r() (0x0010a014U) #define pwr_falcon_irqmclr_r() (0x0010a014U)
#define pwr_falcon_irqmclr_gptmr_f(v) (((v)&0x1U) << 0U) #define pwr_falcon_irqmclr_gptmr_f(v) ((U32(v) & 0x1U) << 0U)
#define pwr_falcon_irqmclr_wdtmr_f(v) (((v)&0x1U) << 1U) #define pwr_falcon_irqmclr_wdtmr_f(v) ((U32(v) & 0x1U) << 1U)
#define pwr_falcon_irqmclr_mthd_f(v) (((v)&0x1U) << 2U) #define pwr_falcon_irqmclr_mthd_f(v) ((U32(v) & 0x1U) << 2U)
#define pwr_falcon_irqmclr_ctxsw_f(v) (((v)&0x1U) << 3U) #define pwr_falcon_irqmclr_ctxsw_f(v) ((U32(v) & 0x1U) << 3U)
#define pwr_falcon_irqmclr_halt_f(v) (((v)&0x1U) << 4U) #define pwr_falcon_irqmclr_halt_f(v) ((U32(v) & 0x1U) << 4U)
#define pwr_falcon_irqmclr_exterr_f(v) (((v)&0x1U) << 5U) #define pwr_falcon_irqmclr_exterr_f(v) ((U32(v) & 0x1U) << 5U)
#define pwr_falcon_irqmclr_swgen0_f(v) (((v)&0x1U) << 6U) #define pwr_falcon_irqmclr_swgen0_f(v) ((U32(v) & 0x1U) << 6U)
#define pwr_falcon_irqmclr_swgen1_f(v) (((v)&0x1U) << 7U) #define pwr_falcon_irqmclr_swgen1_f(v) ((U32(v) & 0x1U) << 7U)
#define pwr_falcon_irqmclr_ext_f(v) (((v)&0xffU) << 8U) #define pwr_falcon_irqmclr_ext_f(v) ((U32(v) & 0xffU) << 8U)
#define pwr_falcon_irqmask_r() (0x0010a018U) #define pwr_falcon_irqmask_r() (0x0010a018U)
#define pwr_falcon_irqdest_r() (0x0010a01cU) #define pwr_falcon_irqdest_r() (0x0010a01cU)
#define pwr_falcon_irqdest_host_gptmr_f(v) (((v)&0x1U) << 0U) #define pwr_falcon_irqdest_host_gptmr_f(v) ((U32(v) & 0x1U) << 0U)
#define pwr_falcon_irqdest_host_wdtmr_f(v) (((v)&0x1U) << 1U) #define pwr_falcon_irqdest_host_wdtmr_f(v) ((U32(v) & 0x1U) << 1U)
#define pwr_falcon_irqdest_host_mthd_f(v) (((v)&0x1U) << 2U) #define pwr_falcon_irqdest_host_mthd_f(v) ((U32(v) & 0x1U) << 2U)
#define pwr_falcon_irqdest_host_ctxsw_f(v) (((v)&0x1U) << 3U) #define pwr_falcon_irqdest_host_ctxsw_f(v) ((U32(v) & 0x1U) << 3U)
#define pwr_falcon_irqdest_host_halt_f(v) (((v)&0x1U) << 4U) #define pwr_falcon_irqdest_host_halt_f(v) ((U32(v) & 0x1U) << 4U)
#define pwr_falcon_irqdest_host_exterr_f(v) (((v)&0x1U) << 5U) #define pwr_falcon_irqdest_host_exterr_f(v) ((U32(v) & 0x1U) << 5U)
#define pwr_falcon_irqdest_host_swgen0_f(v) (((v)&0x1U) << 6U) #define pwr_falcon_irqdest_host_swgen0_f(v) ((U32(v) & 0x1U) << 6U)
#define pwr_falcon_irqdest_host_swgen1_f(v) (((v)&0x1U) << 7U) #define pwr_falcon_irqdest_host_swgen1_f(v) ((U32(v) & 0x1U) << 7U)
#define pwr_falcon_irqdest_host_ext_f(v) (((v)&0xffU) << 8U) #define pwr_falcon_irqdest_host_ext_f(v) ((U32(v) & 0xffU) << 8U)
#define pwr_falcon_irqdest_target_gptmr_f(v) (((v)&0x1U) << 16U) #define pwr_falcon_irqdest_target_gptmr_f(v) ((U32(v) & 0x1U) << 16U)
#define pwr_falcon_irqdest_target_wdtmr_f(v) (((v)&0x1U) << 17U) #define pwr_falcon_irqdest_target_wdtmr_f(v) ((U32(v) & 0x1U) << 17U)
#define pwr_falcon_irqdest_target_mthd_f(v) (((v)&0x1U) << 18U) #define pwr_falcon_irqdest_target_mthd_f(v) ((U32(v) & 0x1U) << 18U)
#define pwr_falcon_irqdest_target_ctxsw_f(v) (((v)&0x1U) << 19U) #define pwr_falcon_irqdest_target_ctxsw_f(v) ((U32(v) & 0x1U) << 19U)
#define pwr_falcon_irqdest_target_halt_f(v) (((v)&0x1U) << 20U) #define pwr_falcon_irqdest_target_halt_f(v) ((U32(v) & 0x1U) << 20U)
#define pwr_falcon_irqdest_target_exterr_f(v) (((v)&0x1U) << 21U) #define pwr_falcon_irqdest_target_exterr_f(v) ((U32(v) & 0x1U) << 21U)
#define pwr_falcon_irqdest_target_swgen0_f(v) (((v)&0x1U) << 22U) #define pwr_falcon_irqdest_target_swgen0_f(v) ((U32(v) & 0x1U) << 22U)
#define pwr_falcon_irqdest_target_swgen1_f(v) (((v)&0x1U) << 23U) #define pwr_falcon_irqdest_target_swgen1_f(v) ((U32(v) & 0x1U) << 23U)
#define pwr_falcon_irqdest_target_ext_f(v) (((v)&0xffU) << 24U) #define pwr_falcon_irqdest_target_ext_f(v) ((U32(v) & 0xffU) << 24U)
#define pwr_falcon_curctx_r() (0x0010a050U) #define pwr_falcon_curctx_r() (0x0010a050U)
#define pwr_falcon_nxtctx_r() (0x0010a054U) #define pwr_falcon_nxtctx_r() (0x0010a054U)
#define pwr_falcon_mailbox0_r() (0x0010a040U) #define pwr_falcon_mailbox0_r() (0x0010a040U)
@@ -118,24 +118,24 @@
#define pwr_falcon_os_r() (0x0010a080U) #define pwr_falcon_os_r() (0x0010a080U)
#define pwr_falcon_engctl_r() (0x0010a0a4U) #define pwr_falcon_engctl_r() (0x0010a0a4U)
#define pwr_falcon_cpuctl_r() (0x0010a100U) #define pwr_falcon_cpuctl_r() (0x0010a100U)
#define pwr_falcon_cpuctl_startcpu_f(v) (((v)&0x1U) << 1U) #define pwr_falcon_cpuctl_startcpu_f(v) ((U32(v) & 0x1U) << 1U)
#define pwr_falcon_cpuctl_halt_intr_f(v) (((v)&0x1U) << 4U) #define pwr_falcon_cpuctl_halt_intr_f(v) ((U32(v) & 0x1U) << 4U)
#define pwr_falcon_cpuctl_halt_intr_m() (U32(0x1U) << 4U) #define pwr_falcon_cpuctl_halt_intr_m() (U32(0x1U) << 4U)
#define pwr_falcon_cpuctl_halt_intr_v(r) (((r) >> 4U) & 0x1U) #define pwr_falcon_cpuctl_halt_intr_v(r) (((r) >> 4U) & 0x1U)
#define pwr_falcon_cpuctl_cpuctl_alias_en_f(v) (((v)&0x1U) << 6U) #define pwr_falcon_cpuctl_cpuctl_alias_en_f(v) ((U32(v) & 0x1U) << 6U)
#define pwr_falcon_cpuctl_cpuctl_alias_en_m() (U32(0x1U) << 6U) #define pwr_falcon_cpuctl_cpuctl_alias_en_m() (U32(0x1U) << 6U)
#define pwr_falcon_cpuctl_cpuctl_alias_en_v(r) (((r) >> 6U) & 0x1U) #define pwr_falcon_cpuctl_cpuctl_alias_en_v(r) (((r) >> 6U) & 0x1U)
#define pwr_falcon_cpuctl_alias_r() (0x0010a130U) #define pwr_falcon_cpuctl_alias_r() (0x0010a130U)
#define pwr_falcon_cpuctl_alias_startcpu_f(v) (((v)&0x1U) << 1U) #define pwr_falcon_cpuctl_alias_startcpu_f(v) ((U32(v) & 0x1U) << 1U)
#define pwr_pmu_scpctl_stat_r() (0x0010ac08U) #define pwr_pmu_scpctl_stat_r() (0x0010ac08U)
#define pwr_pmu_scpctl_stat_debug_mode_f(v) (((v)&0x1U) << 20U) #define pwr_pmu_scpctl_stat_debug_mode_f(v) ((U32(v) & 0x1U) << 20U)
#define pwr_pmu_scpctl_stat_debug_mode_m() (U32(0x1U) << 20U) #define pwr_pmu_scpctl_stat_debug_mode_m() (U32(0x1U) << 20U)
#define pwr_pmu_scpctl_stat_debug_mode_v(r) (((r) >> 20U) & 0x1U) #define pwr_pmu_scpctl_stat_debug_mode_v(r) (((r) >> 20U) & 0x1U)
#define pwr_falcon_imemc_r(i)\ #define pwr_falcon_imemc_r(i)\
(nvgpu_safe_add_u32(0x0010a180U, nvgpu_safe_mult_u32((i), 16U))) (nvgpu_safe_add_u32(0x0010a180U, nvgpu_safe_mult_u32((i), 16U)))
#define pwr_falcon_imemc_offs_f(v) (((v)&0x3fU) << 2U) #define pwr_falcon_imemc_offs_f(v) ((U32(v) & 0x3fU) << 2U)
#define pwr_falcon_imemc_blk_f(v) (((v)&0xffU) << 8U) #define pwr_falcon_imemc_blk_f(v) ((U32(v) & 0xffU) << 8U)
#define pwr_falcon_imemc_aincw_f(v) (((v)&0x1U) << 24U) #define pwr_falcon_imemc_aincw_f(v) ((U32(v) & 0x1U) << 24U)
#define pwr_falcon_imemd_r(i)\ #define pwr_falcon_imemd_r(i)\
(nvgpu_safe_add_u32(0x0010a184U, nvgpu_safe_mult_u32((i), 16U))) (nvgpu_safe_add_u32(0x0010a184U, nvgpu_safe_mult_u32((i), 16U)))
#define pwr_falcon_imemt_r(i)\ #define pwr_falcon_imemt_r(i)\
@@ -143,7 +143,7 @@
#define pwr_falcon_sctl_r() (0x0010a240U) #define pwr_falcon_sctl_r() (0x0010a240U)
#define pwr_falcon_mmu_phys_sec_r() (0x00100ce4U) #define pwr_falcon_mmu_phys_sec_r() (0x00100ce4U)
#define pwr_falcon_bootvec_r() (0x0010a104U) #define pwr_falcon_bootvec_r() (0x0010a104U)
#define pwr_falcon_bootvec_vec_f(v) (((v)&0xffffffffU) << 0U) #define pwr_falcon_bootvec_vec_f(v) ((U32(v) & 0xffffffffU) << 0U)
#define pwr_falcon_dmactl_r() (0x0010a10cU) #define pwr_falcon_dmactl_r() (0x0010a10cU)
#define pwr_falcon_dmactl_dmem_scrubbing_m() (U32(0x1U) << 1U) #define pwr_falcon_dmactl_dmem_scrubbing_m() (U32(0x1U) << 1U)
#define pwr_falcon_dmactl_imem_scrubbing_m() (U32(0x1U) << 2U) #define pwr_falcon_dmactl_imem_scrubbing_m() (U32(0x1U) << 2U)
@@ -153,10 +153,10 @@
#define pwr_falcon_dmatrfbase_r() (0x0010a110U) #define pwr_falcon_dmatrfbase_r() (0x0010a110U)
#define pwr_falcon_dmatrfmoffs_r() (0x0010a114U) #define pwr_falcon_dmatrfmoffs_r() (0x0010a114U)
#define pwr_falcon_dmatrfcmd_r() (0x0010a118U) #define pwr_falcon_dmatrfcmd_r() (0x0010a118U)
#define pwr_falcon_dmatrfcmd_imem_f(v) (((v)&0x1U) << 4U) #define pwr_falcon_dmatrfcmd_imem_f(v) ((U32(v) & 0x1U) << 4U)
#define pwr_falcon_dmatrfcmd_write_f(v) (((v)&0x1U) << 5U) #define pwr_falcon_dmatrfcmd_write_f(v) ((U32(v) & 0x1U) << 5U)
#define pwr_falcon_dmatrfcmd_size_f(v) (((v)&0x7U) << 8U) #define pwr_falcon_dmatrfcmd_size_f(v) ((U32(v) & 0x7U) << 8U)
#define pwr_falcon_dmatrfcmd_ctxdma_f(v) (((v)&0x7U) << 12U) #define pwr_falcon_dmatrfcmd_ctxdma_f(v) ((U32(v) & 0x7U) << 12U)
#define pwr_falcon_dmatrffboffs_r() (0x0010a11cU) #define pwr_falcon_dmatrffboffs_r() (0x0010a11cU)
#define pwr_falcon_exterraddr_r() (0x0010a168U) #define pwr_falcon_exterraddr_r() (0x0010a168U)
#define pwr_falcon_exterrstat_r() (0x0010a16cU) #define pwr_falcon_exterrstat_r() (0x0010a16cU)
@@ -165,59 +165,59 @@
#define pwr_falcon_exterrstat_valid_true_v() (0x00000001U) #define pwr_falcon_exterrstat_valid_true_v() (0x00000001U)
#define pwr_pmu_falcon_icd_cmd_r() (0x0010a200U) #define pwr_pmu_falcon_icd_cmd_r() (0x0010a200U)
#define pwr_pmu_falcon_icd_cmd_opc_s() (4U) #define pwr_pmu_falcon_icd_cmd_opc_s() (4U)
#define pwr_pmu_falcon_icd_cmd_opc_f(v) (((v)&0xfU) << 0U) #define pwr_pmu_falcon_icd_cmd_opc_f(v) ((U32(v) & 0xfU) << 0U)
#define pwr_pmu_falcon_icd_cmd_opc_m() (U32(0xfU) << 0U) #define pwr_pmu_falcon_icd_cmd_opc_m() (U32(0xfU) << 0U)
#define pwr_pmu_falcon_icd_cmd_opc_v(r) (((r) >> 0U) & 0xfU) #define pwr_pmu_falcon_icd_cmd_opc_v(r) (((r) >> 0U) & 0xfU)
#define pwr_pmu_falcon_icd_cmd_opc_rreg_f() (0x8U) #define pwr_pmu_falcon_icd_cmd_opc_rreg_f() (0x8U)
#define pwr_pmu_falcon_icd_cmd_opc_rstat_f() (0xeU) #define pwr_pmu_falcon_icd_cmd_opc_rstat_f() (0xeU)
#define pwr_pmu_falcon_icd_cmd_idx_f(v) (((v)&0x1fU) << 8U) #define pwr_pmu_falcon_icd_cmd_idx_f(v) ((U32(v) & 0x1fU) << 8U)
#define pwr_pmu_falcon_icd_rdata_r() (0x0010a20cU) #define pwr_pmu_falcon_icd_rdata_r() (0x0010a20cU)
#define pwr_falcon_dmemc_r(i)\ #define pwr_falcon_dmemc_r(i)\
(nvgpu_safe_add_u32(0x0010a1c0U, nvgpu_safe_mult_u32((i), 8U))) (nvgpu_safe_add_u32(0x0010a1c0U, nvgpu_safe_mult_u32((i), 8U)))
#define pwr_falcon_dmemc_offs_f(v) (((v)&0x3fU) << 2U) #define pwr_falcon_dmemc_offs_f(v) ((U32(v) & 0x3fU) << 2U)
#define pwr_falcon_dmemc_offs_m() (U32(0x3fU) << 2U) #define pwr_falcon_dmemc_offs_m() (U32(0x3fU) << 2U)
#define pwr_falcon_dmemc_blk_f(v) (((v)&0xffU) << 8U) #define pwr_falcon_dmemc_blk_f(v) ((U32(v) & 0xffU) << 8U)
#define pwr_falcon_dmemc_blk_m() (U32(0xffU) << 8U) #define pwr_falcon_dmemc_blk_m() (U32(0xffU) << 8U)
#define pwr_falcon_dmemc_aincw_f(v) (((v)&0x1U) << 24U) #define pwr_falcon_dmemc_aincw_f(v) ((U32(v) & 0x1U) << 24U)
#define pwr_falcon_dmemc_aincr_f(v) (((v)&0x1U) << 25U) #define pwr_falcon_dmemc_aincr_f(v) ((U32(v) & 0x1U) << 25U)
#define pwr_falcon_dmemd_r(i)\ #define pwr_falcon_dmemd_r(i)\
(nvgpu_safe_add_u32(0x0010a1c4U, nvgpu_safe_mult_u32((i), 8U))) (nvgpu_safe_add_u32(0x0010a1c4U, nvgpu_safe_mult_u32((i), 8U)))
#define pwr_pmu_new_instblk_r() (0x0010a480U) #define pwr_pmu_new_instblk_r() (0x0010a480U)
#define pwr_pmu_new_instblk_ptr_f(v) (((v)&0xfffffffU) << 0U) #define pwr_pmu_new_instblk_ptr_f(v) ((U32(v) & 0xfffffffU) << 0U)
#define pwr_pmu_new_instblk_target_fb_f() (0x0U) #define pwr_pmu_new_instblk_target_fb_f() (0x0U)
#define pwr_pmu_new_instblk_target_sys_coh_f() (0x20000000U) #define pwr_pmu_new_instblk_target_sys_coh_f() (0x20000000U)
#define pwr_pmu_new_instblk_target_sys_ncoh_f() (0x30000000U) #define pwr_pmu_new_instblk_target_sys_ncoh_f() (0x30000000U)
#define pwr_pmu_new_instblk_valid_f(v) (((v)&0x1U) << 30U) #define pwr_pmu_new_instblk_valid_f(v) ((U32(v) & 0x1U) << 30U)
#define pwr_pmu_mutex_id_r() (0x0010a488U) #define pwr_pmu_mutex_id_r() (0x0010a488U)
#define pwr_pmu_mutex_id_value_v(r) (((r) >> 0U) & 0xffU) #define pwr_pmu_mutex_id_value_v(r) (((r) >> 0U) & 0xffU)
#define pwr_pmu_mutex_id_value_init_v() (0x00000000U) #define pwr_pmu_mutex_id_value_init_v() (0x00000000U)
#define pwr_pmu_mutex_id_value_not_avail_v() (0x000000ffU) #define pwr_pmu_mutex_id_value_not_avail_v() (0x000000ffU)
#define pwr_pmu_mutex_id_release_r() (0x0010a48cU) #define pwr_pmu_mutex_id_release_r() (0x0010a48cU)
#define pwr_pmu_mutex_id_release_value_f(v) (((v)&0xffU) << 0U) #define pwr_pmu_mutex_id_release_value_f(v) ((U32(v) & 0xffU) << 0U)
#define pwr_pmu_mutex_id_release_value_m() (U32(0xffU) << 0U) #define pwr_pmu_mutex_id_release_value_m() (U32(0xffU) << 0U)
#define pwr_pmu_mutex_id_release_value_init_v() (0x00000000U) #define pwr_pmu_mutex_id_release_value_init_v() (0x00000000U)
#define pwr_pmu_mutex_id_release_value_init_f() (0x0U) #define pwr_pmu_mutex_id_release_value_init_f() (0x0U)
#define pwr_pmu_mutex_r(i)\ #define pwr_pmu_mutex_r(i)\
(nvgpu_safe_add_u32(0x0010a580U, nvgpu_safe_mult_u32((i), 4U))) (nvgpu_safe_add_u32(0x0010a580U, nvgpu_safe_mult_u32((i), 4U)))
#define pwr_pmu_mutex__size_1_v() (0x00000010U) #define pwr_pmu_mutex__size_1_v() (0x00000010U)
#define pwr_pmu_mutex_value_f(v) (((v)&0xffU) << 0U) #define pwr_pmu_mutex_value_f(v) ((U32(v) & 0xffU) << 0U)
#define pwr_pmu_mutex_value_v(r) (((r) >> 0U) & 0xffU) #define pwr_pmu_mutex_value_v(r) (((r) >> 0U) & 0xffU)
#define pwr_pmu_mutex_value_initial_lock_f() (0x0U) #define pwr_pmu_mutex_value_initial_lock_f() (0x0U)
#define pwr_pmu_queue_head_r(i)\ #define pwr_pmu_queue_head_r(i)\
(nvgpu_safe_add_u32(0x0010a4a0U, nvgpu_safe_mult_u32((i), 4U))) (nvgpu_safe_add_u32(0x0010a4a0U, nvgpu_safe_mult_u32((i), 4U)))
#define pwr_pmu_queue_head__size_1_v() (0x00000004U) #define pwr_pmu_queue_head__size_1_v() (0x00000004U)
#define pwr_pmu_queue_head_address_f(v) (((v)&0xffffffffU) << 0U) #define pwr_pmu_queue_head_address_f(v) ((U32(v) & 0xffffffffU) << 0U)
#define pwr_pmu_queue_head_address_v(r) (((r) >> 0U) & 0xffffffffU) #define pwr_pmu_queue_head_address_v(r) (((r) >> 0U) & 0xffffffffU)
#define pwr_pmu_queue_tail_r(i)\ #define pwr_pmu_queue_tail_r(i)\
(nvgpu_safe_add_u32(0x0010a4b0U, nvgpu_safe_mult_u32((i), 4U))) (nvgpu_safe_add_u32(0x0010a4b0U, nvgpu_safe_mult_u32((i), 4U)))
#define pwr_pmu_queue_tail__size_1_v() (0x00000004U) #define pwr_pmu_queue_tail__size_1_v() (0x00000004U)
#define pwr_pmu_queue_tail_address_f(v) (((v)&0xffffffffU) << 0U) #define pwr_pmu_queue_tail_address_f(v) ((U32(v) & 0xffffffffU) << 0U)
#define pwr_pmu_queue_tail_address_v(r) (((r) >> 0U) & 0xffffffffU) #define pwr_pmu_queue_tail_address_v(r) (((r) >> 0U) & 0xffffffffU)
#define pwr_pmu_msgq_head_r() (0x0010a4c8U) #define pwr_pmu_msgq_head_r() (0x0010a4c8U)
#define pwr_pmu_msgq_head_val_f(v) (((v)&0xffffffffU) << 0U) #define pwr_pmu_msgq_head_val_f(v) ((U32(v) & 0xffffffffU) << 0U)
#define pwr_pmu_msgq_head_val_v(r) (((r) >> 0U) & 0xffffffffU) #define pwr_pmu_msgq_head_val_v(r) (((r) >> 0U) & 0xffffffffU)
#define pwr_pmu_msgq_tail_r() (0x0010a4ccU) #define pwr_pmu_msgq_tail_r() (0x0010a4ccU)
#define pwr_pmu_msgq_tail_val_f(v) (((v)&0xffffffffU) << 0U) #define pwr_pmu_msgq_tail_val_f(v) ((U32(v) & 0xffffffffU) << 0U)
#define pwr_pmu_msgq_tail_val_v(r) (((r) >> 0U) & 0xffffffffU) #define pwr_pmu_msgq_tail_val_v(r) (((r) >> 0U) & 0xffffffffU)
#define pwr_pmu_idle_mask_r(i)\ #define pwr_pmu_idle_mask_r(i)\
(nvgpu_safe_add_u32(0x0010a504U, nvgpu_safe_mult_u32((i), 16U))) (nvgpu_safe_add_u32(0x0010a504U, nvgpu_safe_mult_u32((i), 16U)))
@@ -225,9 +225,9 @@
#define pwr_pmu_idle_mask_ce_2_enabled_f() (0x200000U) #define pwr_pmu_idle_mask_ce_2_enabled_f() (0x200000U)
#define pwr_pmu_idle_count_r(i)\ #define pwr_pmu_idle_count_r(i)\
(nvgpu_safe_add_u32(0x0010a508U, nvgpu_safe_mult_u32((i), 16U))) (nvgpu_safe_add_u32(0x0010a508U, nvgpu_safe_mult_u32((i), 16U)))
#define pwr_pmu_idle_count_value_f(v) (((v)&0x7fffffffU) << 0U) #define pwr_pmu_idle_count_value_f(v) ((U32(v) & 0x7fffffffU) << 0U)
#define pwr_pmu_idle_count_value_v(r) (((r) >> 0U) & 0x7fffffffU) #define pwr_pmu_idle_count_value_v(r) (((r) >> 0U) & 0x7fffffffU)
#define pwr_pmu_idle_count_reset_f(v) (((v)&0x1U) << 31U) #define pwr_pmu_idle_count_reset_f(v) ((U32(v) & 0x1U) << 31U)
#define pwr_pmu_idle_ctrl_r(i)\ #define pwr_pmu_idle_ctrl_r(i)\
(nvgpu_safe_add_u32(0x0010a50cU, nvgpu_safe_mult_u32((i), 16U))) (nvgpu_safe_add_u32(0x0010a50cU, nvgpu_safe_mult_u32((i), 16U)))
#define pwr_pmu_idle_ctrl_value_m() (U32(0x3U) << 0U) #define pwr_pmu_idle_ctrl_value_m() (U32(0x3U) << 0U)
@@ -237,13 +237,13 @@
#define pwr_pmu_idle_ctrl_filter_disabled_f() (0x0U) #define pwr_pmu_idle_ctrl_filter_disabled_f() (0x0U)
#define pwr_pmu_idle_threshold_r(i)\ #define pwr_pmu_idle_threshold_r(i)\
(nvgpu_safe_add_u32(0x0010a8a0U, nvgpu_safe_mult_u32((i), 4U))) (nvgpu_safe_add_u32(0x0010a8a0U, nvgpu_safe_mult_u32((i), 4U)))
#define pwr_pmu_idle_threshold_value_f(v) (((v)&0x7fffffffU) << 0U) #define pwr_pmu_idle_threshold_value_f(v) ((U32(v) & 0x7fffffffU) << 0U)
#define pwr_pmu_idle_intr_r() (0x0010a9e8U) #define pwr_pmu_idle_intr_r() (0x0010a9e8U)
#define pwr_pmu_idle_intr_en_f(v) (((v)&0x1U) << 0U) #define pwr_pmu_idle_intr_en_f(v) ((U32(v) & 0x1U) << 0U)
#define pwr_pmu_idle_intr_en_disabled_v() (0x00000000U) #define pwr_pmu_idle_intr_en_disabled_v() (0x00000000U)
#define pwr_pmu_idle_intr_en_enabled_v() (0x00000001U) #define pwr_pmu_idle_intr_en_enabled_v() (0x00000001U)
#define pwr_pmu_idle_intr_status_r() (0x0010a9ecU) #define pwr_pmu_idle_intr_status_r() (0x0010a9ecU)
#define pwr_pmu_idle_intr_status_intr_f(v) (((v)&0x1U) << 0U) #define pwr_pmu_idle_intr_status_intr_f(v) ((U32(v) & 0x1U) << 0U)
#define pwr_pmu_idle_intr_status_intr_m() (U32(0x1U) << 0U) #define pwr_pmu_idle_intr_status_intr_m() (U32(0x1U) << 0U)
#define pwr_pmu_idle_intr_status_intr_v(r) (((r) >> 0U) & 0x1U) #define pwr_pmu_idle_intr_status_intr_v(r) (((r) >> 0U) & 0x1U)
#define pwr_pmu_idle_intr_status_intr_pending_v() (0x00000001U) #define pwr_pmu_idle_intr_status_intr_pending_v() (0x00000001U)
@@ -287,7 +287,7 @@
#define pwr_fbif_transcfg_target_coherent_sysmem_f() (0x1U) #define pwr_fbif_transcfg_target_coherent_sysmem_f() (0x1U)
#define pwr_fbif_transcfg_target_noncoherent_sysmem_f() (0x2U) #define pwr_fbif_transcfg_target_noncoherent_sysmem_f() (0x2U)
#define pwr_fbif_transcfg_mem_type_s() (1U) #define pwr_fbif_transcfg_mem_type_s() (1U)
#define pwr_fbif_transcfg_mem_type_f(v) (((v)&0x1U) << 2U) #define pwr_fbif_transcfg_mem_type_f(v) ((U32(v) & 0x1U) << 2U)
#define pwr_fbif_transcfg_mem_type_m() (U32(0x1U) << 2U) #define pwr_fbif_transcfg_mem_type_m() (U32(0x1U) << 2U)
#define pwr_fbif_transcfg_mem_type_v(r) (((r) >> 2U) & 0x1U) #define pwr_fbif_transcfg_mem_type_v(r) (((r) >> 2U) & 0x1U)
#define pwr_fbif_transcfg_mem_type_virtual_f() (0x0U) #define pwr_fbif_transcfg_mem_type_virtual_f() (0x0U)

30
drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_ram_gm20b.h
View File

@@ -61,25 +61,25 @@
#define ram_in_ramfc_s() (4096U) #define ram_in_ramfc_s() (4096U)
#define ram_in_ramfc_w() (0U) #define ram_in_ramfc_w() (0U)
#define ram_in_page_dir_base_target_f(v) (((v)&0x3U) << 0U) #define ram_in_page_dir_base_target_f(v) ((U32(v) & 0x3U) << 0U)
#define ram_in_page_dir_base_target_w() (128U) #define ram_in_page_dir_base_target_w() (128U)
#define ram_in_page_dir_base_target_vid_mem_f() (0x0U) #define ram_in_page_dir_base_target_vid_mem_f() (0x0U)
#define ram_in_page_dir_base_target_sys_mem_coh_f() (0x2U) #define ram_in_page_dir_base_target_sys_mem_coh_f() (0x2U)
#define ram_in_page_dir_base_target_sys_mem_ncoh_f() (0x3U) #define ram_in_page_dir_base_target_sys_mem_ncoh_f() (0x3U)
#define ram_in_page_dir_base_vol_w() (128U) #define ram_in_page_dir_base_vol_w() (128U)
#define ram_in_page_dir_base_vol_true_f() (0x4U) #define ram_in_page_dir_base_vol_true_f() (0x4U)
#define ram_in_big_page_size_f(v) (((v)&0x1U) << 11U) #define ram_in_big_page_size_f(v) ((U32(v) & 0x1U) << 11U)
#define ram_in_big_page_size_m() (U32(0x1U) << 11U) #define ram_in_big_page_size_m() (U32(0x1U) << 11U)
#define ram_in_big_page_size_w() (128U) #define ram_in_big_page_size_w() (128U)
#define ram_in_big_page_size_128kb_f() (0x0U) #define ram_in_big_page_size_128kb_f() (0x0U)
#define ram_in_big_page_size_64kb_f() (0x800U) #define ram_in_big_page_size_64kb_f() (0x800U)
#define ram_in_page_dir_base_lo_f(v) (((v)&0xfffffU) << 12U) #define ram_in_page_dir_base_lo_f(v) ((U32(v) & 0xfffffU) << 12U)
#define ram_in_page_dir_base_lo_w() (128U) #define ram_in_page_dir_base_lo_w() (128U)
#define ram_in_page_dir_base_hi_f(v) (((v)&0xffU) << 0U) #define ram_in_page_dir_base_hi_f(v) ((U32(v) & 0xffU) << 0U)
#define ram_in_page_dir_base_hi_w() (129U) #define ram_in_page_dir_base_hi_w() (129U)
#define ram_in_adr_limit_lo_f(v) (((v)&0xfffffU) << 12U) #define ram_in_adr_limit_lo_f(v) ((U32(v) & 0xfffffU) << 12U)
#define ram_in_adr_limit_lo_w() (130U) #define ram_in_adr_limit_lo_w() (130U)
#define ram_in_adr_limit_hi_f(v) (((v)&0xffU) << 0U) #define ram_in_adr_limit_hi_f(v) ((U32(v) & 0xffU) << 0U)
#define ram_in_adr_limit_hi_w() (131U) #define ram_in_adr_limit_hi_w() (131U)
#define ram_in_engine_cs_w() (132U) #define ram_in_engine_cs_w() (132U)
#define ram_in_engine_cs_wfi_v() (0x00000000U) #define ram_in_engine_cs_wfi_v() (0x00000000U)
@@ -94,9 +94,9 @@
#define ram_in_gr_wfi_mode_physical_f() (0x0U) #define ram_in_gr_wfi_mode_physical_f() (0x0U)
#define ram_in_gr_wfi_mode_virtual_v() (0x00000001U) #define ram_in_gr_wfi_mode_virtual_v() (0x00000001U)
#define ram_in_gr_wfi_mode_virtual_f() (0x4U) #define ram_in_gr_wfi_mode_virtual_f() (0x4U)
#define ram_in_gr_wfi_ptr_lo_f(v) (((v)&0xfffffU) << 12U) #define ram_in_gr_wfi_ptr_lo_f(v) ((U32(v) & 0xfffffU) << 12U)
#define ram_in_gr_wfi_ptr_lo_w() (132U) #define ram_in_gr_wfi_ptr_lo_w() (132U)
#define ram_in_gr_wfi_ptr_hi_f(v) (((v)&0xffU) << 0U) #define ram_in_gr_wfi_ptr_hi_f(v) ((U32(v) & 0xffU) << 0U)
#define ram_in_gr_wfi_ptr_hi_w() (133U) #define ram_in_gr_wfi_ptr_hi_w() (133U)
#define ram_in_base_shift_v() (0x0000000cU) #define ram_in_base_shift_v() (0x0000000cU)
#define ram_in_alloc_size_v() (0x00001000U) #define ram_in_alloc_size_v() (0x00001000U)
@@ -131,7 +131,7 @@
#define ram_fc_target_w() (43U) #define ram_fc_target_w() (43U)
#define ram_fc_hce_ctrl_w() (57U) #define ram_fc_hce_ctrl_w() (57U)
#define ram_fc_chid_w() (58U) #define ram_fc_chid_w() (58U)
#define ram_fc_chid_id_f(v) (((v)&0xfffU) << 0U) #define ram_fc_chid_id_f(v) ((U32(v) & 0xfffU) << 0U)
#define ram_fc_chid_id_w() (0U) #define ram_fc_chid_id_w() (0U)
#define ram_fc_runlist_timeslice_w() (62U) #define ram_fc_runlist_timeslice_w() (62U)
#define ram_userd_base_shift_v() (0x00000009U) #define ram_userd_base_shift_v() (0x00000009U)
@@ -148,16 +148,16 @@
#define ram_userd_gp_top_level_get_w() (22U) #define ram_userd_gp_top_level_get_w() (22U)
#define ram_userd_gp_top_level_get_hi_w() (23U) #define ram_userd_gp_top_level_get_hi_w() (23U)
#define ram_rl_entry_size_v() (0x00000008U) #define ram_rl_entry_size_v() (0x00000008U)
#define ram_rl_entry_chid_f(v) (((v)&0xfffU) << 0U) #define ram_rl_entry_chid_f(v) ((U32(v) & 0xfffU) << 0U)
#define ram_rl_entry_id_f(v) (((v)&0xfffU) << 0U) #define ram_rl_entry_id_f(v) ((U32(v) & 0xfffU) << 0U)
#define ram_rl_entry_type_f(v) (((v)&0x1U) << 13U) #define ram_rl_entry_type_f(v) ((U32(v) & 0x1U) << 13U)
#define ram_rl_entry_type_chid_f() (0x0U) #define ram_rl_entry_type_chid_f() (0x0U)
#define ram_rl_entry_type_tsg_f() (0x2000U) #define ram_rl_entry_type_tsg_f() (0x2000U)
#define ram_rl_entry_timeslice_scale_f(v) (((v)&0xfU) << 14U) #define ram_rl_entry_timeslice_scale_f(v) ((U32(v) & 0xfU) << 14U)
#define ram_rl_entry_timeslice_scale_v(r) (((r) >> 14U) & 0xfU) #define ram_rl_entry_timeslice_scale_v(r) (((r) >> 14U) & 0xfU)
#define ram_rl_entry_timeslice_scale_3_f() (0xc000U) #define ram_rl_entry_timeslice_scale_3_f() (0xc000U)
#define ram_rl_entry_timeslice_timeout_f(v) (((v)&0xffU) << 18U) #define ram_rl_entry_timeslice_timeout_f(v) ((U32(v) & 0xffU) << 18U)
#define ram_rl_entry_timeslice_timeout_v(r) (((r) >> 18U) & 0xffU) #define ram_rl_entry_timeslice_timeout_v(r) (((r) >> 18U) & 0xffU)
#define ram_rl_entry_timeslice_timeout_128_f() (0x2000000U) #define ram_rl_entry_timeslice_timeout_128_f() (0x2000000U)
#define ram_rl_entry_tsg_length_f(v) (((v)&0x3fU) << 26U) #define ram_rl_entry_tsg_length_f(v) ((U32(v) & 0x3fU) << 26U)
#endif #endif

39
drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_therm_gm20b.h
View File

@@ -64,19 +64,19 @@
#define therm_use_a_ext_therm_1_enable_f() (0x2U) #define therm_use_a_ext_therm_1_enable_f() (0x2U)
#define therm_use_a_ext_therm_2_enable_f() (0x4U) #define therm_use_a_ext_therm_2_enable_f() (0x4U)
#define therm_evt_ext_therm_0_r() (0x00020700U) #define therm_evt_ext_therm_0_r() (0x00020700U)
#define therm_evt_ext_therm_0_slow_factor_f(v) (((v)&0x3fU) << 8U) #define therm_evt_ext_therm_0_slow_factor_f(v) ((U32(v) & 0x3fU) << 8U)
#define therm_evt_ext_therm_0_slow_factor_init_v() (0x00000000U) #define therm_evt_ext_therm_0_slow_factor_init_v() (0x00000000U)
#define therm_evt_ext_therm_1_r() (0x00020704U) #define therm_evt_ext_therm_1_r() (0x00020704U)
#define therm_evt_ext_therm_1_slow_factor_f(v) (((v)&0x3fU) << 8U) #define therm_evt_ext_therm_1_slow_factor_f(v) ((U32(v) & 0x3fU) << 8U)
#define therm_evt_ext_therm_1_slow_factor_init_v() (0x00000000U) #define therm_evt_ext_therm_1_slow_factor_init_v() (0x00000000U)
#define therm_evt_ext_therm_2_r() (0x00020708U) #define therm_evt_ext_therm_2_r() (0x00020708U)
#define therm_evt_ext_therm_2_slow_factor_f(v) (((v)&0x3fU) << 8U) #define therm_evt_ext_therm_2_slow_factor_f(v) ((U32(v) & 0x3fU) << 8U)
#define therm_evt_ext_therm_2_slow_factor_init_v() (0x00000000U) #define therm_evt_ext_therm_2_slow_factor_init_v() (0x00000000U)
#define therm_weight_1_r() (0x00020024U) #define therm_weight_1_r() (0x00020024U)
#define therm_config1_r() (0x00020050U) #define therm_config1_r() (0x00020050U)
#define therm_config2_r() (0x00020130U) #define therm_config2_r() (0x00020130U)
#define therm_config2_slowdown_factor_extended_f(v) (((v)&0x1U) << 24U) #define therm_config2_slowdown_factor_extended_f(v) ((U32(v) & 0x1U) << 24U)
#define therm_config2_grad_enable_f(v) (((v)&0x1U) << 31U) #define therm_config2_grad_enable_f(v) ((U32(v) & 0x1U) << 31U)
#define therm_gate_ctrl_r(i)\ #define therm_gate_ctrl_r(i)\
(nvgpu_safe_add_u32(0x00020200U, nvgpu_safe_mult_u32((i), 4U))) (nvgpu_safe_add_u32(0x00020200U, nvgpu_safe_mult_u32((i), 4U)))
#define therm_gate_ctrl_eng_clk_m() (U32(0x3U) << 0U) #define therm_gate_ctrl_eng_clk_m() (U32(0x3U) << 0U)
@@ -90,13 +90,13 @@
#define therm_gate_ctrl_eng_pwr_auto_f() (0x10U) #define therm_gate_ctrl_eng_pwr_auto_f() (0x10U)
#define therm_gate_ctrl_eng_pwr_off_v() (0x00000002U) #define therm_gate_ctrl_eng_pwr_off_v() (0x00000002U)
#define therm_gate_ctrl_eng_pwr_off_f() (0x20U) #define therm_gate_ctrl_eng_pwr_off_f() (0x20U)
#define therm_gate_ctrl_eng_idle_filt_exp_f(v) (((v)&0x1fU) << 8U) #define therm_gate_ctrl_eng_idle_filt_exp_f(v) ((U32(v) & 0x1fU) << 8U)
#define therm_gate_ctrl_eng_idle_filt_exp_m() (U32(0x1fU) << 8U) #define therm_gate_ctrl_eng_idle_filt_exp_m() (U32(0x1fU) << 8U)
#define therm_gate_ctrl_eng_idle_filt_mant_f(v) (((v)&0x7U) << 13U) #define therm_gate_ctrl_eng_idle_filt_mant_f(v) ((U32(v) & 0x7U) << 13U)
#define therm_gate_ctrl_eng_idle_filt_mant_m() (U32(0x7U) << 13U) #define therm_gate_ctrl_eng_idle_filt_mant_m() (U32(0x7U) << 13U)
#define therm_gate_ctrl_eng_delay_before_f(v) (((v)&0xfU) << 16U) #define therm_gate_ctrl_eng_delay_before_f(v) ((U32(v) & 0xfU) << 16U)
#define therm_gate_ctrl_eng_delay_before_m() (U32(0xfU) << 16U) #define therm_gate_ctrl_eng_delay_before_m() (U32(0xfU) << 16U)
#define therm_gate_ctrl_eng_delay_after_f(v) (((v)&0xfU) << 20U) #define therm_gate_ctrl_eng_delay_after_f(v) ((U32(v) & 0xfU) << 20U)
#define therm_gate_ctrl_eng_delay_after_m() (U32(0xfU) << 20U) #define therm_gate_ctrl_eng_delay_after_m() (U32(0xfU) << 20U)
#define therm_fecs_idle_filter_r() (0x00020288U) #define therm_fecs_idle_filter_r() (0x00020288U)
#define therm_fecs_idle_filter_value_m() (U32(0xffffffffU) << 0U) #define therm_fecs_idle_filter_value_m() (U32(0xffffffffU) << 0U)
@@ -104,37 +104,40 @@
#define therm_hubmmu_idle_filter_value_m() (U32(0xffffffffU) << 0U) #define therm_hubmmu_idle_filter_value_m() (U32(0xffffffffU) << 0U)
#define therm_clk_slowdown_r(i)\ #define therm_clk_slowdown_r(i)\
(nvgpu_safe_add_u32(0x00020160U, nvgpu_safe_mult_u32((i), 4U))) (nvgpu_safe_add_u32(0x00020160U, nvgpu_safe_mult_u32((i), 4U)))
#define therm_clk_slowdown_idle_factor_f(v) (((v)&0x3fU) << 16U) #define therm_clk_slowdown_idle_factor_f(v) ((U32(v) & 0x3fU) << 16U)
#define therm_clk_slowdown_idle_factor_m() (U32(0x3fU) << 16U) #define therm_clk_slowdown_idle_factor_m() (U32(0x3fU) << 16U)
#define therm_clk_slowdown_idle_factor_v(r) (((r) >> 16U) & 0x3fU) #define therm_clk_slowdown_idle_factor_v(r) (((r) >> 16U) & 0x3fU)
#define therm_clk_slowdown_idle_factor_disabled_f() (0x0U) #define therm_clk_slowdown_idle_factor_disabled_f() (0x0U)
#define therm_grad_stepping_table_r(i)\ #define therm_grad_stepping_table_r(i)\
(nvgpu_safe_add_u32(0x000202c8U, nvgpu_safe_mult_u32((i), 4U))) (nvgpu_safe_add_u32(0x000202c8U, nvgpu_safe_mult_u32((i), 4U)))
#define therm_grad_stepping_table_slowdown_factor0_f(v) (((v)&0x3fU) << 0U) #define therm_grad_stepping_table_slowdown_factor0_f(v) ((U32(v) & 0x3fU) << 0U)
#define therm_grad_stepping_table_slowdown_factor0_m() (U32(0x3fU) << 0U) #define therm_grad_stepping_table_slowdown_factor0_m() (U32(0x3fU) << 0U)
#define therm_grad_stepping_table_slowdown_factor0_fpdiv_by1p5_f() (0x1U) #define therm_grad_stepping_table_slowdown_factor0_fpdiv_by1p5_f() (0x1U)
#define therm_grad_stepping_table_slowdown_factor0_fpdiv_by2_f() (0x2U) #define therm_grad_stepping_table_slowdown_factor0_fpdiv_by2_f() (0x2U)
#define therm_grad_stepping_table_slowdown_factor0_fpdiv_by4_f() (0x6U) #define therm_grad_stepping_table_slowdown_factor0_fpdiv_by4_f() (0x6U)
#define therm_grad_stepping_table_slowdown_factor0_fpdiv_by8_f() (0xeU) #define therm_grad_stepping_table_slowdown_factor0_fpdiv_by8_f() (0xeU)
#define therm_grad_stepping_table_slowdown_factor1_f(v) (((v)&0x3fU) << 6U) #define therm_grad_stepping_table_slowdown_factor1_f(v) ((U32(v) & 0x3fU) << 6U)
#define therm_grad_stepping_table_slowdown_factor1_m() (U32(0x3fU) << 6U) #define therm_grad_stepping_table_slowdown_factor1_m() (U32(0x3fU) << 6U)
#define therm_grad_stepping_table_slowdown_factor2_f(v) (((v)&0x3fU) << 12U) #define therm_grad_stepping_table_slowdown_factor2_f(v)\
((U32(v) & 0x3fU) << 12U)
#define therm_grad_stepping_table_slowdown_factor2_m() (U32(0x3fU) << 12U) #define therm_grad_stepping_table_slowdown_factor2_m() (U32(0x3fU) << 12U)
#define therm_grad_stepping_table_slowdown_factor3_f(v) (((v)&0x3fU) << 18U) #define therm_grad_stepping_table_slowdown_factor3_f(v)\
((U32(v) & 0x3fU) << 18U)
#define therm_grad_stepping_table_slowdown_factor3_m() (U32(0x3fU) << 18U) #define therm_grad_stepping_table_slowdown_factor3_m() (U32(0x3fU) << 18U)
#define therm_grad_stepping_table_slowdown_factor4_f(v) (((v)&0x3fU) << 24U) #define therm_grad_stepping_table_slowdown_factor4_f(v)\
((U32(v) & 0x3fU) << 24U)
#define therm_grad_stepping_table_slowdown_factor4_m() (U32(0x3fU) << 24U) #define therm_grad_stepping_table_slowdown_factor4_m() (U32(0x3fU) << 24U)
#define therm_grad_stepping0_r() (0x000202c0U) #define therm_grad_stepping0_r() (0x000202c0U)
#define therm_grad_stepping0_feature_s() (1U) #define therm_grad_stepping0_feature_s() (1U)
#define therm_grad_stepping0_feature_f(v) (((v)&0x1U) << 0U) #define therm_grad_stepping0_feature_f(v) ((U32(v) & 0x1U) << 0U)
#define therm_grad_stepping0_feature_m() (U32(0x1U) << 0U) #define therm_grad_stepping0_feature_m() (U32(0x1U) << 0U)
#define therm_grad_stepping0_feature_v(r) (((r) >> 0U) & 0x1U) #define therm_grad_stepping0_feature_v(r) (((r) >> 0U) & 0x1U)
#define therm_grad_stepping0_feature_enable_f() (0x1U) #define therm_grad_stepping0_feature_enable_f() (0x1U)
#define therm_grad_stepping1_r() (0x000202c4U) #define therm_grad_stepping1_r() (0x000202c4U)
#define therm_grad_stepping1_pdiv_duration_f(v) (((v)&0x1ffffU) << 0U) #define therm_grad_stepping1_pdiv_duration_f(v) ((U32(v) & 0x1ffffU) << 0U)
#define therm_clk_timing_r(i)\ #define therm_clk_timing_r(i)\
(nvgpu_safe_add_u32(0x000203c0U, nvgpu_safe_mult_u32((i), 4U))) (nvgpu_safe_add_u32(0x000203c0U, nvgpu_safe_mult_u32((i), 4U)))
#define therm_clk_timing_grad_slowdown_f(v) (((v)&0x1U) << 16U) #define therm_clk_timing_grad_slowdown_f(v) ((U32(v) & 0x1U) << 16U)
#define therm_clk_timing_grad_slowdown_m() (U32(0x1U) << 16U) #define therm_clk_timing_grad_slowdown_m() (U32(0x1U) << 16U)
#define therm_clk_timing_grad_slowdown_enabled_f() (0x10000U) #define therm_clk_timing_grad_slowdown_enabled_f() (0x10000U)
#endif #endif

4
drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_timer_gm20b.h
View File

@@ -60,10 +60,10 @@
#include <nvgpu/safe_ops.h> #include <nvgpu/safe_ops.h>
#define timer_pri_timeout_r() (0x00009080U) #define timer_pri_timeout_r() (0x00009080U)
#define timer_pri_timeout_period_f(v) (((v)&0xffffffU) << 0U) #define timer_pri_timeout_period_f(v) ((U32(v) & 0xffffffU) << 0U)
#define timer_pri_timeout_period_m() (U32(0xffffffU) << 0U) #define timer_pri_timeout_period_m() (U32(0xffffffU) << 0U)
#define timer_pri_timeout_period_v(r) (((r) >> 0U) & 0xffffffU) #define timer_pri_timeout_period_v(r) (((r) >> 0U) & 0xffffffU)
#define timer_pri_timeout_en_f(v) (((v)&0x1U) << 31U) #define timer_pri_timeout_en_f(v) ((U32(v) & 0x1U) << 31U)
#define timer_pri_timeout_en_m() (U32(0x1U) << 31U) #define timer_pri_timeout_en_m() (U32(0x1U) << 31U)
#define timer_pri_timeout_en_v(r) (((r) >> 31U) & 0x1U) #define timer_pri_timeout_en_v(r) (((r) >> 31U) & 0x1U)
#define timer_pri_timeout_en_en_enabled_f() (0x80000000U) #define timer_pri_timeout_en_en_enabled_f() (0x80000000U)

35
drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_trim_gm20b.h
View File

@@ -77,13 +77,13 @@
#define trim_sys_gpcpll_cfg_pll_lock_v(r) (((r) >> 17U) & 0x1U) #define trim_sys_gpcpll_cfg_pll_lock_v(r) (((r) >> 17U) & 0x1U)
#define trim_sys_gpcpll_cfg_pll_lock_true_f() (0x20000U) #define trim_sys_gpcpll_cfg_pll_lock_true_f() (0x20000U)
#define trim_sys_gpcpll_coeff_r() (0x00137004U) #define trim_sys_gpcpll_coeff_r() (0x00137004U)
#define trim_sys_gpcpll_coeff_mdiv_f(v) (((v)&0xffU) << 0U) #define trim_sys_gpcpll_coeff_mdiv_f(v) ((U32(v) & 0xffU) << 0U)
#define trim_sys_gpcpll_coeff_mdiv_m() (U32(0xffU) << 0U) #define trim_sys_gpcpll_coeff_mdiv_m() (U32(0xffU) << 0U)
#define trim_sys_gpcpll_coeff_mdiv_v(r) (((r) >> 0U) & 0xffU) #define trim_sys_gpcpll_coeff_mdiv_v(r) (((r) >> 0U) & 0xffU)
#define trim_sys_gpcpll_coeff_ndiv_f(v) (((v)&0xffU) << 8U) #define trim_sys_gpcpll_coeff_ndiv_f(v) ((U32(v) & 0xffU) << 8U)
#define trim_sys_gpcpll_coeff_ndiv_m() (U32(0xffU) << 8U) #define trim_sys_gpcpll_coeff_ndiv_m() (U32(0xffU) << 8U)
#define trim_sys_gpcpll_coeff_ndiv_v(r) (((r) >> 8U) & 0xffU) #define trim_sys_gpcpll_coeff_ndiv_v(r) (((r) >> 8U) & 0xffU)
#define trim_sys_gpcpll_coeff_pldiv_f(v) (((v)&0x3fU) << 16U) #define trim_sys_gpcpll_coeff_pldiv_f(v) ((U32(v) & 0x3fU) << 16U)
#define trim_sys_gpcpll_coeff_pldiv_m() (U32(0x3fU) << 16U) #define trim_sys_gpcpll_coeff_pldiv_m() (U32(0x3fU) << 16U)
#define trim_sys_gpcpll_coeff_pldiv_v(r) (((r) >> 16U) & 0x3fU) #define trim_sys_gpcpll_coeff_pldiv_v(r) (((r) >> 16U) & 0x3fU)
#define trim_sys_sel_vco_r() (0x00137100U) #define trim_sys_sel_vco_r() (0x00137100U)
@@ -94,12 +94,12 @@
#define trim_sys_sel_vco_gpc2clk_out_vco_f() (0x1U) #define trim_sys_sel_vco_gpc2clk_out_vco_f() (0x1U)
#define trim_sys_gpc2clk_out_r() (0x00137250U) #define trim_sys_gpc2clk_out_r() (0x00137250U)
#define trim_sys_gpc2clk_out_bypdiv_s() (6U) #define trim_sys_gpc2clk_out_bypdiv_s() (6U)
#define trim_sys_gpc2clk_out_bypdiv_f(v) (((v)&0x3fU) << 0U) #define trim_sys_gpc2clk_out_bypdiv_f(v) ((U32(v) & 0x3fU) << 0U)
#define trim_sys_gpc2clk_out_bypdiv_m() (U32(0x3fU) << 0U) #define trim_sys_gpc2clk_out_bypdiv_m() (U32(0x3fU) << 0U)
#define trim_sys_gpc2clk_out_bypdiv_v(r) (((r) >> 0U) & 0x3fU) #define trim_sys_gpc2clk_out_bypdiv_v(r) (((r) >> 0U) & 0x3fU)
#define trim_sys_gpc2clk_out_bypdiv_by31_f() (0x3cU) #define trim_sys_gpc2clk_out_bypdiv_by31_f() (0x3cU)
#define trim_sys_gpc2clk_out_vcodiv_s() (6U) #define trim_sys_gpc2clk_out_vcodiv_s() (6U)
#define trim_sys_gpc2clk_out_vcodiv_f(v) (((v)&0x3fU) << 8U) #define trim_sys_gpc2clk_out_vcodiv_f(v) ((U32(v) & 0x3fU) << 8U)
#define trim_sys_gpc2clk_out_vcodiv_m() (U32(0x3fU) << 8U) #define trim_sys_gpc2clk_out_vcodiv_m() (U32(0x3fU) << 8U)
#define trim_sys_gpc2clk_out_vcodiv_v(r) (((r) >> 8U) & 0x3fU) #define trim_sys_gpc2clk_out_vcodiv_v(r) (((r) >> 8U) & 0x3fU)
#define trim_sys_gpc2clk_out_vcodiv_by1_f() (0x0U) #define trim_sys_gpc2clk_out_vcodiv_by1_f() (0x0U)
@@ -107,7 +107,8 @@
#define trim_sys_gpc2clk_out_sdiv14_indiv4_mode_f() (0x80000000U) #define trim_sys_gpc2clk_out_sdiv14_indiv4_mode_f() (0x80000000U)
#define trim_gpc_clk_cntr_ncgpcclk_cfg_r(i)\ #define trim_gpc_clk_cntr_ncgpcclk_cfg_r(i)\
(nvgpu_safe_add_u32(0x00134124U, nvgpu_safe_mult_u32((i), 512U))) (nvgpu_safe_add_u32(0x00134124U, nvgpu_safe_mult_u32((i), 512U)))
#define trim_gpc_clk_cntr_ncgpcclk_cfg_noofipclks_f(v) (((v)&0x3fffU) << 0U) #define trim_gpc_clk_cntr_ncgpcclk_cfg_noofipclks_f(v)\
((U32(v) & 0x3fffU) << 0U)
#define trim_gpc_clk_cntr_ncgpcclk_cfg_write_en_asserted_f() (0x10000U) #define trim_gpc_clk_cntr_ncgpcclk_cfg_write_en_asserted_f() (0x10000U)
#define trim_gpc_clk_cntr_ncgpcclk_cfg_enable_asserted_f() (0x100000U) #define trim_gpc_clk_cntr_ncgpcclk_cfg_enable_asserted_f() (0x100000U)
#define trim_gpc_clk_cntr_ncgpcclk_cfg_reset_asserted_f() (0x1000000U) #define trim_gpc_clk_cntr_ncgpcclk_cfg_reset_asserted_f() (0x1000000U)
@@ -115,42 +116,42 @@
(nvgpu_safe_add_u32(0x00134128U, nvgpu_safe_mult_u32((i), 512U))) (nvgpu_safe_add_u32(0x00134128U, nvgpu_safe_mult_u32((i), 512U)))
#define trim_gpc_clk_cntr_ncgpcclk_cnt_value_v(r) (((r) >> 0U) & 0xfffffU) #define trim_gpc_clk_cntr_ncgpcclk_cnt_value_v(r) (((r) >> 0U) & 0xfffffU)
#define trim_sys_gpcpll_cfg2_r() (0x0013700cU) #define trim_sys_gpcpll_cfg2_r() (0x0013700cU)
#define trim_sys_gpcpll_cfg2_sdm_din_f(v) (((v)&0xffU) << 0U) #define trim_sys_gpcpll_cfg2_sdm_din_f(v) ((U32(v) & 0xffU) << 0U)
#define trim_sys_gpcpll_cfg2_sdm_din_m() (U32(0xffU) << 0U) #define trim_sys_gpcpll_cfg2_sdm_din_m() (U32(0xffU) << 0U)
#define trim_sys_gpcpll_cfg2_sdm_din_v(r) (((r) >> 0U) & 0xffU) #define trim_sys_gpcpll_cfg2_sdm_din_v(r) (((r) >> 0U) & 0xffU)
#define trim_sys_gpcpll_cfg2_sdm_din_new_f(v) (((v)&0xffU) << 8U) #define trim_sys_gpcpll_cfg2_sdm_din_new_f(v) ((U32(v) & 0xffU) << 8U)
#define trim_sys_gpcpll_cfg2_sdm_din_new_m() (U32(0xffU) << 8U) #define trim_sys_gpcpll_cfg2_sdm_din_new_m() (U32(0xffU) << 8U)
#define trim_sys_gpcpll_cfg2_sdm_din_new_v(r) (((r) >> 8U) & 0xffU) #define trim_sys_gpcpll_cfg2_sdm_din_new_v(r) (((r) >> 8U) & 0xffU)
#define trim_sys_gpcpll_cfg2_pll_stepa_f(v) (((v)&0xffU) << 24U) #define trim_sys_gpcpll_cfg2_pll_stepa_f(v) ((U32(v) & 0xffU) << 24U)
#define trim_sys_gpcpll_cfg2_pll_stepa_m() (U32(0xffU) << 24U) #define trim_sys_gpcpll_cfg2_pll_stepa_m() (U32(0xffU) << 24U)
#define trim_sys_gpcpll_cfg3_r() (0x00137018U) #define trim_sys_gpcpll_cfg3_r() (0x00137018U)
#define trim_sys_gpcpll_cfg3_vco_ctrl_f(v) (((v)&0x1ffU) << 0U) #define trim_sys_gpcpll_cfg3_vco_ctrl_f(v) ((U32(v) & 0x1ffU) << 0U)
#define trim_sys_gpcpll_cfg3_vco_ctrl_m() (U32(0x1ffU) << 0U) #define trim_sys_gpcpll_cfg3_vco_ctrl_m() (U32(0x1ffU) << 0U)
#define trim_sys_gpcpll_cfg3_pll_stepb_f(v) (((v)&0xffU) << 16U) #define trim_sys_gpcpll_cfg3_pll_stepb_f(v) ((U32(v) & 0xffU) << 16U)
#define trim_sys_gpcpll_cfg3_pll_stepb_m() (U32(0xffU) << 16U) #define trim_sys_gpcpll_cfg3_pll_stepb_m() (U32(0xffU) << 16U)
#define trim_sys_gpcpll_cfg3_dfs_testout_v(r) (((r) >> 24U) & 0x7fU) #define trim_sys_gpcpll_cfg3_dfs_testout_v(r) (((r) >> 24U) & 0x7fU)
#define trim_sys_gpcpll_dvfs0_r() (0x00137010U) #define trim_sys_gpcpll_dvfs0_r() (0x00137010U)
#define trim_sys_gpcpll_dvfs0_dfs_coeff_f(v) (((v)&0x7fU) << 0U) #define trim_sys_gpcpll_dvfs0_dfs_coeff_f(v) ((U32(v) & 0x7fU) << 0U)
#define trim_sys_gpcpll_dvfs0_dfs_coeff_m() (U32(0x7fU) << 0U) #define trim_sys_gpcpll_dvfs0_dfs_coeff_m() (U32(0x7fU) << 0U)
#define trim_sys_gpcpll_dvfs0_dfs_coeff_v(r) (((r) >> 0U) & 0x7fU) #define trim_sys_gpcpll_dvfs0_dfs_coeff_v(r) (((r) >> 0U) & 0x7fU)
#define trim_sys_gpcpll_dvfs0_dfs_det_max_f(v) (((v)&0x7fU) << 8U) #define trim_sys_gpcpll_dvfs0_dfs_det_max_f(v) ((U32(v) & 0x7fU) << 8U)
#define trim_sys_gpcpll_dvfs0_dfs_det_max_m() (U32(0x7fU) << 8U) #define trim_sys_gpcpll_dvfs0_dfs_det_max_m() (U32(0x7fU) << 8U)
#define trim_sys_gpcpll_dvfs0_dfs_det_max_v(r) (((r) >> 8U) & 0x7fU) #define trim_sys_gpcpll_dvfs0_dfs_det_max_v(r) (((r) >> 8U) & 0x7fU)
#define trim_sys_gpcpll_dvfs0_dfs_dc_offset_f(v) (((v)&0x3fU) << 16U) #define trim_sys_gpcpll_dvfs0_dfs_dc_offset_f(v) ((U32(v) & 0x3fU) << 16U)
#define trim_sys_gpcpll_dvfs0_dfs_dc_offset_m() (U32(0x3fU) << 16U) #define trim_sys_gpcpll_dvfs0_dfs_dc_offset_m() (U32(0x3fU) << 16U)
#define trim_sys_gpcpll_dvfs0_dfs_dc_offset_v(r) (((r) >> 16U) & 0x3fU) #define trim_sys_gpcpll_dvfs0_dfs_dc_offset_v(r) (((r) >> 16U) & 0x3fU)
#define trim_sys_gpcpll_dvfs0_mode_m() (U32(0x1U) << 28U) #define trim_sys_gpcpll_dvfs0_mode_m() (U32(0x1U) << 28U)
#define trim_sys_gpcpll_dvfs0_mode_dvfspll_f() (0x0U) #define trim_sys_gpcpll_dvfs0_mode_dvfspll_f() (0x0U)
#define trim_sys_gpcpll_dvfs1_r() (0x00137014U) #define trim_sys_gpcpll_dvfs1_r() (0x00137014U)
#define trim_sys_gpcpll_dvfs1_dfs_ext_det_f(v) (((v)&0x7fU) << 0U) #define trim_sys_gpcpll_dvfs1_dfs_ext_det_f(v) ((U32(v) & 0x7fU) << 0U)
#define trim_sys_gpcpll_dvfs1_dfs_ext_det_m() (U32(0x7fU) << 0U) #define trim_sys_gpcpll_dvfs1_dfs_ext_det_m() (U32(0x7fU) << 0U)
#define trim_sys_gpcpll_dvfs1_dfs_ext_det_v(r) (((r) >> 0U) & 0x7fU) #define trim_sys_gpcpll_dvfs1_dfs_ext_det_v(r) (((r) >> 0U) & 0x7fU)
#define trim_sys_gpcpll_dvfs1_dfs_ext_strb_m() (U32(0x1U) << 7U) #define trim_sys_gpcpll_dvfs1_dfs_ext_strb_m() (U32(0x1U) << 7U)
#define trim_sys_gpcpll_dvfs1_dfs_ext_cal_f(v) (((v)&0x7fU) << 8U) #define trim_sys_gpcpll_dvfs1_dfs_ext_cal_f(v) ((U32(v) & 0x7fU) << 8U)
#define trim_sys_gpcpll_dvfs1_dfs_ext_cal_m() (U32(0x7fU) << 8U) #define trim_sys_gpcpll_dvfs1_dfs_ext_cal_m() (U32(0x7fU) << 8U)
#define trim_sys_gpcpll_dvfs1_dfs_ext_cal_v(r) (((r) >> 8U) & 0x7fU) #define trim_sys_gpcpll_dvfs1_dfs_ext_cal_v(r) (((r) >> 8U) & 0x7fU)
#define trim_sys_gpcpll_dvfs1_dfs_ext_sel_m() (U32(0x1U) << 15U) #define trim_sys_gpcpll_dvfs1_dfs_ext_sel_m() (U32(0x1U) << 15U)
#define trim_sys_gpcpll_dvfs1_dfs_ctrl_f(v) (((v)&0xfffU) << 16U) #define trim_sys_gpcpll_dvfs1_dfs_ctrl_f(v) ((U32(v) & 0xfffU) << 16U)
#define trim_sys_gpcpll_dvfs1_dfs_ctrl_m() (U32(0xfffU) << 16U) #define trim_sys_gpcpll_dvfs1_dfs_ctrl_m() (U32(0xfffU) << 16U)
#define trim_sys_gpcpll_dvfs1_dfs_ctrl_v(r) (((r) >> 16U) & 0xfffU) #define trim_sys_gpcpll_dvfs1_dfs_ctrl_v(r) (((r) >> 16U) & 0xfffU)
#define trim_sys_gpcpll_dvfs1_en_sdm_m() (U32(0x1U) << 28U) #define trim_sys_gpcpll_dvfs1_en_sdm_m() (U32(0x1U) << 28U)

6
drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_bus_gp106.h
View File

@@ -60,19 +60,19 @@
#include <nvgpu/safe_ops.h> #include <nvgpu/safe_ops.h>
#define bus_bar0_window_r() (0x00001700U) #define bus_bar0_window_r() (0x00001700U)
#define bus_bar0_window_base_f(v) (((v)&0xffffffU) << 0U) #define bus_bar0_window_base_f(v) ((U32(v) & 0xffffffU) << 0U)
#define bus_bar0_window_target_vid_mem_f() (0x0U) #define bus_bar0_window_target_vid_mem_f() (0x0U)
#define bus_bar0_window_target_sys_mem_coherent_f() (0x2000000U) #define bus_bar0_window_target_sys_mem_coherent_f() (0x2000000U)
#define bus_bar0_window_target_sys_mem_noncoherent_f() (0x3000000U) #define bus_bar0_window_target_sys_mem_noncoherent_f() (0x3000000U)
#define bus_bar0_window_target_bar0_window_base_shift_v() (0x00000010U) #define bus_bar0_window_target_bar0_window_base_shift_v() (0x00000010U)
#define bus_bar1_block_r() (0x00001704U) #define bus_bar1_block_r() (0x00001704U)
#define bus_bar1_block_ptr_f(v) (((v)&0xfffffffU) << 0U) #define bus_bar1_block_ptr_f(v) ((U32(v) & 0xfffffffU) << 0U)
#define bus_bar1_block_target_vid_mem_f() (0x0U) #define bus_bar1_block_target_vid_mem_f() (0x0U)
#define bus_bar1_block_target_sys_mem_coh_f() (0x20000000U) #define bus_bar1_block_target_sys_mem_coh_f() (0x20000000U)
#define bus_bar1_block_target_sys_mem_ncoh_f() (0x30000000U) #define bus_bar1_block_target_sys_mem_ncoh_f() (0x30000000U)
#define bus_bar1_block_mode_virtual_f() (0x80000000U) #define bus_bar1_block_mode_virtual_f() (0x80000000U)
#define bus_bar2_block_r() (0x00001714U) #define bus_bar2_block_r() (0x00001714U)
#define bus_bar2_block_ptr_f(v) (((v)&0xfffffffU) << 0U) #define bus_bar2_block_ptr_f(v) ((U32(v) & 0xfffffffU) << 0U)
#define bus_bar2_block_target_vid_mem_f() (0x0U) #define bus_bar2_block_target_vid_mem_f() (0x0U)
#define bus_bar2_block_target_sys_mem_coh_f() (0x20000000U) #define bus_bar2_block_target_sys_mem_coh_f() (0x20000000U)
#define bus_bar2_block_target_sys_mem_ncoh_f() (0x30000000U) #define bus_bar2_block_target_sys_mem_ncoh_f() (0x30000000U)

4
drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_ccsr_gp106.h
View File

@@ -62,7 +62,7 @@
#define ccsr_channel_inst_r(i)\ #define ccsr_channel_inst_r(i)\
(nvgpu_safe_add_u32(0x00800000U, nvgpu_safe_mult_u32((i), 8U))) (nvgpu_safe_add_u32(0x00800000U, nvgpu_safe_mult_u32((i), 8U)))
#define ccsr_channel_inst__size_1_v() (0x00001000U) #define ccsr_channel_inst__size_1_v() (0x00001000U)
#define ccsr_channel_inst_ptr_f(v) (((v)&0xfffffffU) << 0U) #define ccsr_channel_inst_ptr_f(v) ((U32(v) & 0xfffffffU) << 0U)
#define ccsr_channel_inst_target_vid_mem_f() (0x0U) #define ccsr_channel_inst_target_vid_mem_f() (0x0U)
#define ccsr_channel_inst_target_sys_mem_coh_f() (0x20000000U) #define ccsr_channel_inst_target_sys_mem_coh_f() (0x20000000U)
#define ccsr_channel_inst_target_sys_mem_ncoh_f() (0x30000000U) #define ccsr_channel_inst_target_sys_mem_ncoh_f() (0x30000000U)
@@ -73,7 +73,7 @@
#define ccsr_channel__size_1_v() (0x00001000U) #define ccsr_channel__size_1_v() (0x00001000U)
#define ccsr_channel_enable_v(r) (((r) >> 0U) & 0x1U) #define ccsr_channel_enable_v(r) (((r) >> 0U) & 0x1U)
#define ccsr_channel_enable_in_use_v() (0x00000001U) #define ccsr_channel_enable_in_use_v() (0x00000001U)
#define ccsr_channel_enable_set_f(v) (((v)&0x1U) << 10U) #define ccsr_channel_enable_set_f(v) ((U32(v) & 0x1U) << 10U)
#define ccsr_channel_enable_set_true_f() (0x400U) #define ccsr_channel_enable_set_true_f() (0x400U)
#define ccsr_channel_enable_clr_true_f() (0x800U) #define ccsr_channel_enable_clr_true_f() (0x800U)
#define ccsr_channel_status_v(r) (((r) >> 24U) & 0xfU) #define ccsr_channel_status_v(r) (((r) >> 24U) & 0xfU)

6
drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_ctxsw_prog_gp106.h
View File

@@ -105,7 +105,7 @@
#define ctxsw_prog_main_image_priv_access_map_config_o() (0x000000a0U) #define ctxsw_prog_main_image_priv_access_map_config_o() (0x000000a0U)
#define ctxsw_prog_main_image_priv_access_map_config_mode_s() (2U) #define ctxsw_prog_main_image_priv_access_map_config_mode_s() (2U)
#define ctxsw_prog_main_image_priv_access_map_config_mode_f(v)\ #define ctxsw_prog_main_image_priv_access_map_config_mode_f(v)\
(((v)&0x3U) << 0U) ((U32(v) & 0x3U) << 0U)
#define ctxsw_prog_main_image_priv_access_map_config_mode_m() (U32(0x3U) << 0U) #define ctxsw_prog_main_image_priv_access_map_config_mode_m() (U32(0x3U) << 0U)
#define ctxsw_prog_main_image_priv_access_map_config_mode_v(r)\ #define ctxsw_prog_main_image_priv_access_map_config_mode_v(r)\
(((r) >> 0U) & 0x3U) (((r) >> 0U) & 0x3U)
@@ -118,13 +118,13 @@
#define ctxsw_prog_main_image_misc_options_verif_features_disabled_f() (0x0U) #define ctxsw_prog_main_image_misc_options_verif_features_disabled_f() (0x0U)
#define ctxsw_prog_main_image_graphics_preemption_options_o() (0x00000080U) #define ctxsw_prog_main_image_graphics_preemption_options_o() (0x00000080U)
#define ctxsw_prog_main_image_graphics_preemption_options_control_f(v)\ #define ctxsw_prog_main_image_graphics_preemption_options_control_f(v)\
(((v)&0x3U) << 0U) ((U32(v) & 0x3U) << 0U)
#define ctxsw_prog_main_image_graphics_preemption_options_control_gfxp_f()\ #define ctxsw_prog_main_image_graphics_preemption_options_control_gfxp_f()\
(0x1U) (0x1U)
#define ctxsw_prog_main_image_full_preemption_ptr_o() (0x00000068U) #define ctxsw_prog_main_image_full_preemption_ptr_o() (0x00000068U)
#define ctxsw_prog_main_image_compute_preemption_options_o() (0x00000084U) #define ctxsw_prog_main_image_compute_preemption_options_o() (0x00000084U)
#define ctxsw_prog_main_image_compute_preemption_options_control_f(v)\ #define ctxsw_prog_main_image_compute_preemption_options_control_f(v)\
(((v)&0x3U) << 0U) ((U32(v) & 0x3U) << 0U)
#define ctxsw_prog_main_image_compute_preemption_options_control_cta_f() (0x1U) #define ctxsw_prog_main_image_compute_preemption_options_control_cta_f() (0x1U)
#define ctxsw_prog_main_image_compute_preemption_options_control_cilp_f() (0x2U) #define ctxsw_prog_main_image_compute_preemption_options_control_cilp_f() (0x2U)
#endif #endif

122
drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_falcon_gp106.h
View File

@@ -68,44 +68,44 @@
#define falcon_falcon_irqstat_swgen0_true_f() (0x40U) #define falcon_falcon_irqstat_swgen0_true_f() (0x40U)
#define falcon_falcon_irqmode_r() (0x0000000cU) #define falcon_falcon_irqmode_r() (0x0000000cU)
#define falcon_falcon_irqmset_r() (0x00000010U) #define falcon_falcon_irqmset_r() (0x00000010U)
#define falcon_falcon_irqmset_gptmr_f(v) (((v)&0x1U) << 0U) #define falcon_falcon_irqmset_gptmr_f(v) ((U32(v) & 0x1U) << 0U)
#define falcon_falcon_irqmset_wdtmr_f(v) (((v)&0x1U) << 1U) #define falcon_falcon_irqmset_wdtmr_f(v) ((U32(v) & 0x1U) << 1U)
#define falcon_falcon_irqmset_mthd_f(v) (((v)&0x1U) << 2U) #define falcon_falcon_irqmset_mthd_f(v) ((U32(v) & 0x1U) << 2U)
#define falcon_falcon_irqmset_ctxsw_f(v) (((v)&0x1U) << 3U) #define falcon_falcon_irqmset_ctxsw_f(v) ((U32(v) & 0x1U) << 3U)
#define falcon_falcon_irqmset_halt_f(v) (((v)&0x1U) << 4U) #define falcon_falcon_irqmset_halt_f(v) ((U32(v) & 0x1U) << 4U)
#define falcon_falcon_irqmset_exterr_f(v) (((v)&0x1U) << 5U) #define falcon_falcon_irqmset_exterr_f(v) ((U32(v) & 0x1U) << 5U)
#define falcon_falcon_irqmset_swgen0_f(v) (((v)&0x1U) << 6U) #define falcon_falcon_irqmset_swgen0_f(v) ((U32(v) & 0x1U) << 6U)
#define falcon_falcon_irqmset_swgen1_f(v) (((v)&0x1U) << 7U) #define falcon_falcon_irqmset_swgen1_f(v) ((U32(v) & 0x1U) << 7U)
#define falcon_falcon_irqmclr_r() (0x00000014U) #define falcon_falcon_irqmclr_r() (0x00000014U)
#define falcon_falcon_irqmclr_gptmr_f(v) (((v)&0x1U) << 0U) #define falcon_falcon_irqmclr_gptmr_f(v) ((U32(v) & 0x1U) << 0U)
#define falcon_falcon_irqmclr_wdtmr_f(v) (((v)&0x1U) << 1U) #define falcon_falcon_irqmclr_wdtmr_f(v) ((U32(v) & 0x1U) << 1U)
#define falcon_falcon_irqmclr_mthd_f(v) (((v)&0x1U) << 2U) #define falcon_falcon_irqmclr_mthd_f(v) ((U32(v) & 0x1U) << 2U)
#define falcon_falcon_irqmclr_ctxsw_f(v) (((v)&0x1U) << 3U) #define falcon_falcon_irqmclr_ctxsw_f(v) ((U32(v) & 0x1U) << 3U)
#define falcon_falcon_irqmclr_halt_f(v) (((v)&0x1U) << 4U) #define falcon_falcon_irqmclr_halt_f(v) ((U32(v) & 0x1U) << 4U)
#define falcon_falcon_irqmclr_exterr_f(v) (((v)&0x1U) << 5U) #define falcon_falcon_irqmclr_exterr_f(v) ((U32(v) & 0x1U) << 5U)
#define falcon_falcon_irqmclr_swgen0_f(v) (((v)&0x1U) << 6U) #define falcon_falcon_irqmclr_swgen0_f(v) ((U32(v) & 0x1U) << 6U)
#define falcon_falcon_irqmclr_swgen1_f(v) (((v)&0x1U) << 7U) #define falcon_falcon_irqmclr_swgen1_f(v) ((U32(v) & 0x1U) << 7U)
#define falcon_falcon_irqmclr_ext_f(v) (((v)&0xffU) << 8U) #define falcon_falcon_irqmclr_ext_f(v) ((U32(v) & 0xffU) << 8U)
#define falcon_falcon_irqmask_r() (0x00000018U) #define falcon_falcon_irqmask_r() (0x00000018U)
#define falcon_falcon_irqdest_r() (0x0000001cU) #define falcon_falcon_irqdest_r() (0x0000001cU)
#define falcon_falcon_irqdest_host_gptmr_f(v) (((v)&0x1U) << 0U) #define falcon_falcon_irqdest_host_gptmr_f(v) ((U32(v) & 0x1U) << 0U)
#define falcon_falcon_irqdest_host_wdtmr_f(v) (((v)&0x1U) << 1U) #define falcon_falcon_irqdest_host_wdtmr_f(v) ((U32(v) & 0x1U) << 1U)
#define falcon_falcon_irqdest_host_mthd_f(v) (((v)&0x1U) << 2U) #define falcon_falcon_irqdest_host_mthd_f(v) ((U32(v) & 0x1U) << 2U)
#define falcon_falcon_irqdest_host_ctxsw_f(v) (((v)&0x1U) << 3U) #define falcon_falcon_irqdest_host_ctxsw_f(v) ((U32(v) & 0x1U) << 3U)
#define falcon_falcon_irqdest_host_halt_f(v) (((v)&0x1U) << 4U) #define falcon_falcon_irqdest_host_halt_f(v) ((U32(v) & 0x1U) << 4U)
#define falcon_falcon_irqdest_host_exterr_f(v) (((v)&0x1U) << 5U) #define falcon_falcon_irqdest_host_exterr_f(v) ((U32(v) & 0x1U) << 5U)
#define falcon_falcon_irqdest_host_swgen0_f(v) (((v)&0x1U) << 6U) #define falcon_falcon_irqdest_host_swgen0_f(v) ((U32(v) & 0x1U) << 6U)
#define falcon_falcon_irqdest_host_swgen1_f(v) (((v)&0x1U) << 7U) #define falcon_falcon_irqdest_host_swgen1_f(v) ((U32(v) & 0x1U) << 7U)
#define falcon_falcon_irqdest_host_ext_f(v) (((v)&0xffU) << 8U) #define falcon_falcon_irqdest_host_ext_f(v) ((U32(v) & 0xffU) << 8U)
#define falcon_falcon_irqdest_target_gptmr_f(v) (((v)&0x1U) << 16U) #define falcon_falcon_irqdest_target_gptmr_f(v) ((U32(v) & 0x1U) << 16U)
#define falcon_falcon_irqdest_target_wdtmr_f(v) (((v)&0x1U) << 17U) #define falcon_falcon_irqdest_target_wdtmr_f(v) ((U32(v) & 0x1U) << 17U)
#define falcon_falcon_irqdest_target_mthd_f(v) (((v)&0x1U) << 18U) #define falcon_falcon_irqdest_target_mthd_f(v) ((U32(v) & 0x1U) << 18U)
#define falcon_falcon_irqdest_target_ctxsw_f(v) (((v)&0x1U) << 19U) #define falcon_falcon_irqdest_target_ctxsw_f(v) ((U32(v) & 0x1U) << 19U)
#define falcon_falcon_irqdest_target_halt_f(v) (((v)&0x1U) << 20U) #define falcon_falcon_irqdest_target_halt_f(v) ((U32(v) & 0x1U) << 20U)
#define falcon_falcon_irqdest_target_exterr_f(v) (((v)&0x1U) << 21U) #define falcon_falcon_irqdest_target_exterr_f(v) ((U32(v) & 0x1U) << 21U)
#define falcon_falcon_irqdest_target_swgen0_f(v) (((v)&0x1U) << 22U) #define falcon_falcon_irqdest_target_swgen0_f(v) ((U32(v) & 0x1U) << 22U)
#define falcon_falcon_irqdest_target_swgen1_f(v) (((v)&0x1U) << 23U) #define falcon_falcon_irqdest_target_swgen1_f(v) ((U32(v) & 0x1U) << 23U)
#define falcon_falcon_irqdest_target_ext_f(v) (((v)&0xffU) << 24U) #define falcon_falcon_irqdest_target_ext_f(v) ((U32(v) & 0xffU) << 24U)
#define falcon_falcon_curctx_r() (0x00000050U) #define falcon_falcon_curctx_r() (0x00000050U)
#define falcon_falcon_nxtctx_r() (0x00000054U) #define falcon_falcon_nxtctx_r() (0x00000054U)
#define falcon_falcon_mailbox0_r() (0x00000040U) #define falcon_falcon_mailbox0_r() (0x00000040U)
@@ -118,24 +118,24 @@
#define falcon_falcon_os_r() (0x00000080U) #define falcon_falcon_os_r() (0x00000080U)
#define falcon_falcon_engctl_r() (0x000000a4U) #define falcon_falcon_engctl_r() (0x000000a4U)
#define falcon_falcon_cpuctl_r() (0x00000100U) #define falcon_falcon_cpuctl_r() (0x00000100U)
#define falcon_falcon_cpuctl_startcpu_f(v) (((v)&0x1U) << 1U) #define falcon_falcon_cpuctl_startcpu_f(v) ((U32(v) & 0x1U) << 1U)
#define falcon_falcon_cpuctl_sreset_f(v) (((v)&0x1U) << 2U) #define falcon_falcon_cpuctl_sreset_f(v) ((U32(v) & 0x1U) << 2U)
#define falcon_falcon_cpuctl_hreset_f(v) (((v)&0x1U) << 3U) #define falcon_falcon_cpuctl_hreset_f(v) ((U32(v) & 0x1U) << 3U)
#define falcon_falcon_cpuctl_halt_intr_f(v) (((v)&0x1U) << 4U) #define falcon_falcon_cpuctl_halt_intr_f(v) ((U32(v) & 0x1U) << 4U)
#define falcon_falcon_cpuctl_halt_intr_m() (U32(0x1U) << 4U) #define falcon_falcon_cpuctl_halt_intr_m() (U32(0x1U) << 4U)
#define falcon_falcon_cpuctl_halt_intr_v(r) (((r) >> 4U) & 0x1U) #define falcon_falcon_cpuctl_halt_intr_v(r) (((r) >> 4U) & 0x1U)
#define falcon_falcon_cpuctl_stopped_m() (U32(0x1U) << 5U) #define falcon_falcon_cpuctl_stopped_m() (U32(0x1U) << 5U)
#define falcon_falcon_cpuctl_cpuctl_alias_en_f(v) (((v)&0x1U) << 6U) #define falcon_falcon_cpuctl_cpuctl_alias_en_f(v) ((U32(v) & 0x1U) << 6U)
#define falcon_falcon_cpuctl_cpuctl_alias_en_m() (U32(0x1U) << 6U) #define falcon_falcon_cpuctl_cpuctl_alias_en_m() (U32(0x1U) << 6U)
#define falcon_falcon_cpuctl_cpuctl_alias_en_v(r) (((r) >> 6U) & 0x1U) #define falcon_falcon_cpuctl_cpuctl_alias_en_v(r) (((r) >> 6U) & 0x1U)
#define falcon_falcon_cpuctl_alias_r() (0x00000130U) #define falcon_falcon_cpuctl_alias_r() (0x00000130U)
#define falcon_falcon_cpuctl_alias_startcpu_f(v) (((v)&0x1U) << 1U) #define falcon_falcon_cpuctl_alias_startcpu_f(v) ((U32(v) & 0x1U) << 1U)
#define falcon_falcon_imemc_r(i)\ #define falcon_falcon_imemc_r(i)\
(nvgpu_safe_add_u32(0x00000180U, nvgpu_safe_mult_u32((i), 16U))) (nvgpu_safe_add_u32(0x00000180U, nvgpu_safe_mult_u32((i), 16U)))
#define falcon_falcon_imemc_offs_f(v) (((v)&0x3fU) << 2U) #define falcon_falcon_imemc_offs_f(v) ((U32(v) & 0x3fU) << 2U)
#define falcon_falcon_imemc_blk_f(v) (((v)&0xffU) << 8U) #define falcon_falcon_imemc_blk_f(v) ((U32(v) & 0xffU) << 8U)
#define falcon_falcon_imemc_aincw_f(v) (((v)&0x1U) << 24U) #define falcon_falcon_imemc_aincw_f(v) ((U32(v) & 0x1U) << 24U)
#define falcon_falcon_imemc_secure_f(v) (((v)&0x1U) << 28U) #define falcon_falcon_imemc_secure_f(v) ((U32(v) & 0x1U) << 28U)
#define falcon_falcon_imemd_r(i)\ #define falcon_falcon_imemd_r(i)\
(nvgpu_safe_add_u32(0x00000184U, nvgpu_safe_mult_u32((i), 16U))) (nvgpu_safe_add_u32(0x00000184U, nvgpu_safe_mult_u32((i), 16U)))
#define falcon_falcon_imemt_r(i)\ #define falcon_falcon_imemt_r(i)\
@@ -143,11 +143,11 @@
#define falcon_falcon_sctl_r() (0x00000240U) #define falcon_falcon_sctl_r() (0x00000240U)
#define falcon_falcon_mmu_phys_sec_r() (0x00100ce4U) #define falcon_falcon_mmu_phys_sec_r() (0x00100ce4U)
#define falcon_falcon_bootvec_r() (0x00000104U) #define falcon_falcon_bootvec_r() (0x00000104U)
#define falcon_falcon_bootvec_vec_f(v) (((v)&0xffffffffU) << 0U) #define falcon_falcon_bootvec_vec_f(v) ((U32(v) & 0xffffffffU) << 0U)
#define falcon_falcon_dmactl_r() (0x0000010cU) #define falcon_falcon_dmactl_r() (0x0000010cU)
#define falcon_falcon_dmactl_dmem_scrubbing_m() (U32(0x1U) << 1U) #define falcon_falcon_dmactl_dmem_scrubbing_m() (U32(0x1U) << 1U)
#define falcon_falcon_dmactl_imem_scrubbing_m() (U32(0x1U) << 2U) #define falcon_falcon_dmactl_imem_scrubbing_m() (U32(0x1U) << 2U)
#define falcon_falcon_dmactl_require_ctx_f(v) (((v)&0x1U) << 0U) #define falcon_falcon_dmactl_require_ctx_f(v) ((U32(v) & 0x1U) << 0U)
#define falcon_falcon_hwcfg_r() (0x00000108U) #define falcon_falcon_hwcfg_r() (0x00000108U)
#define falcon_falcon_hwcfg_imem_size_v(r) (((r) >> 0U) & 0x1ffU) #define falcon_falcon_hwcfg_imem_size_v(r) (((r) >> 0U) & 0x1ffU)
#define falcon_falcon_hwcfg_dmem_size_v(r) (((r) >> 9U) & 0x1ffU) #define falcon_falcon_hwcfg_dmem_size_v(r) (((r) >> 9U) & 0x1ffU)
@@ -155,18 +155,18 @@
#define falcon_falcon_dmatrfbase1_r() (0x00000128U) #define falcon_falcon_dmatrfbase1_r() (0x00000128U)
#define falcon_falcon_dmatrfmoffs_r() (0x00000114U) #define falcon_falcon_dmatrfmoffs_r() (0x00000114U)
#define falcon_falcon_dmatrfcmd_r() (0x00000118U) #define falcon_falcon_dmatrfcmd_r() (0x00000118U)
#define falcon_falcon_dmatrfcmd_imem_f(v) (((v)&0x1U) << 4U) #define falcon_falcon_dmatrfcmd_imem_f(v) ((U32(v) & 0x1U) << 4U)
#define falcon_falcon_dmatrfcmd_write_f(v) (((v)&0x1U) << 5U) #define falcon_falcon_dmatrfcmd_write_f(v) ((U32(v) & 0x1U) << 5U)
#define falcon_falcon_dmatrfcmd_size_f(v) (((v)&0x7U) << 8U) #define falcon_falcon_dmatrfcmd_size_f(v) ((U32(v) & 0x7U) << 8U)
#define falcon_falcon_dmatrfcmd_ctxdma_f(v) (((v)&0x7U) << 12U) #define falcon_falcon_dmatrfcmd_ctxdma_f(v) ((U32(v) & 0x7U) << 12U)
#define falcon_falcon_dmatrffboffs_r() (0x0000011cU) #define falcon_falcon_dmatrffboffs_r() (0x0000011cU)
#define falcon_falcon_imctl_debug_r() (0x0000015cU) #define falcon_falcon_imctl_debug_r() (0x0000015cU)
#define falcon_falcon_imctl_debug_addr_blk_f(v) (((v)&0xffffffU) << 0U) #define falcon_falcon_imctl_debug_addr_blk_f(v) ((U32(v) & 0xffffffU) << 0U)
#define falcon_falcon_imctl_debug_cmd_f(v) (((v)&0x7U) << 24U) #define falcon_falcon_imctl_debug_cmd_f(v) ((U32(v) & 0x7U) << 24U)
#define falcon_falcon_imstat_r() (0x00000144U) #define falcon_falcon_imstat_r() (0x00000144U)
#define falcon_falcon_traceidx_r() (0x00000148U) #define falcon_falcon_traceidx_r() (0x00000148U)
#define falcon_falcon_traceidx_maxidx_v(r) (((r) >> 16U) & 0xffU) #define falcon_falcon_traceidx_maxidx_v(r) (((r) >> 16U) & 0xffU)
#define falcon_falcon_traceidx_idx_f(v) (((v)&0xffU) << 0U) #define falcon_falcon_traceidx_idx_f(v) ((U32(v) & 0xffU) << 0U)
#define falcon_falcon_tracepc_r() (0x0000014cU) #define falcon_falcon_tracepc_r() (0x0000014cU)
#define falcon_falcon_tracepc_pc_v(r) (((r) >> 0U) & 0xffffffU) #define falcon_falcon_tracepc_pc_v(r) (((r) >> 0U) & 0xffffffU)
#define falcon_falcon_exterraddr_r() (0x0010a168U) #define falcon_falcon_exterraddr_r() (0x0010a168U)
@@ -176,26 +176,26 @@
#define falcon_falcon_exterrstat_valid_true_v() (0x00000001U) #define falcon_falcon_exterrstat_valid_true_v() (0x00000001U)
#define falcon_falcon_icd_cmd_r() (0x00000200U) #define falcon_falcon_icd_cmd_r() (0x00000200U)
#define falcon_falcon_icd_cmd_opc_s() (4U) #define falcon_falcon_icd_cmd_opc_s() (4U)
#define falcon_falcon_icd_cmd_opc_f(v) (((v)&0xfU) << 0U) #define falcon_falcon_icd_cmd_opc_f(v) ((U32(v) & 0xfU) << 0U)
#define falcon_falcon_icd_cmd_opc_m() (U32(0xfU) << 0U) #define falcon_falcon_icd_cmd_opc_m() (U32(0xfU) << 0U)
#define falcon_falcon_icd_cmd_opc_v(r) (((r) >> 0U) & 0xfU) #define falcon_falcon_icd_cmd_opc_v(r) (((r) >> 0U) & 0xfU)
#define falcon_falcon_icd_cmd_opc_rreg_f() (0x8U) #define falcon_falcon_icd_cmd_opc_rreg_f() (0x8U)
#define falcon_falcon_icd_cmd_opc_rstat_f() (0xeU) #define falcon_falcon_icd_cmd_opc_rstat_f() (0xeU)
#define falcon_falcon_icd_cmd_idx_f(v) (((v)&0x1fU) << 8U) #define falcon_falcon_icd_cmd_idx_f(v) ((U32(v) & 0x1fU) << 8U)
#define falcon_falcon_icd_rdata_r() (0x0000020cU) #define falcon_falcon_icd_rdata_r() (0x0000020cU)
#define falcon_falcon_dmemc_r(i)\ #define falcon_falcon_dmemc_r(i)\
(nvgpu_safe_add_u32(0x000001c0U, nvgpu_safe_mult_u32((i), 8U))) (nvgpu_safe_add_u32(0x000001c0U, nvgpu_safe_mult_u32((i), 8U)))
#define falcon_falcon_dmemc_offs_f(v) (((v)&0x3fU) << 2U) #define falcon_falcon_dmemc_offs_f(v) ((U32(v) & 0x3fU) << 2U)
#define falcon_falcon_dmemc_offs_m() (U32(0x3fU) << 2U) #define falcon_falcon_dmemc_offs_m() (U32(0x3fU) << 2U)
#define falcon_falcon_dmemc_blk_f(v) (((v)&0xffU) << 8U) #define falcon_falcon_dmemc_blk_f(v) ((U32(v) & 0xffU) << 8U)
#define falcon_falcon_dmemc_blk_m() (U32(0xffU) << 8U) #define falcon_falcon_dmemc_blk_m() (U32(0xffU) << 8U)
#define falcon_falcon_dmemc_aincw_f(v) (((v)&0x1U) << 24U) #define falcon_falcon_dmemc_aincw_f(v) ((U32(v) & 0x1U) << 24U)
#define falcon_falcon_dmemc_aincr_f(v) (((v)&0x1U) << 25U) #define falcon_falcon_dmemc_aincr_f(v) ((U32(v) & 0x1U) << 25U)
#define falcon_falcon_dmemd_r(i)\ #define falcon_falcon_dmemd_r(i)\
(nvgpu_safe_add_u32(0x000001c4U, nvgpu_safe_mult_u32((i), 8U))) (nvgpu_safe_add_u32(0x000001c4U, nvgpu_safe_mult_u32((i), 8U)))
#define falcon_falcon_debug1_r() (0x00000090U) #define falcon_falcon_debug1_r() (0x00000090U)
#define falcon_falcon_debug1_ctxsw_mode_s() (1U) #define falcon_falcon_debug1_ctxsw_mode_s() (1U)
#define falcon_falcon_debug1_ctxsw_mode_f(v) (((v)&0x1U) << 16U) #define falcon_falcon_debug1_ctxsw_mode_f(v) ((U32(v) & 0x1U) << 16U)
#define falcon_falcon_debug1_ctxsw_mode_m() (U32(0x1U) << 16U) #define falcon_falcon_debug1_ctxsw_mode_m() (U32(0x1U) << 16U)
#define falcon_falcon_debug1_ctxsw_mode_v(r) (((r) >> 16U) & 0x1U) #define falcon_falcon_debug1_ctxsw_mode_v(r) (((r) >> 16U) & 0x1U)
#define falcon_falcon_debug1_ctxsw_mode_init_f() (0x0U) #define falcon_falcon_debug1_ctxsw_mode_init_f() (0x0U)

34
drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_fb_gp106.h
View File

@@ -68,17 +68,17 @@
#define fb_mmu_invalidate_pdb_r() (0x00100cb8U) #define fb_mmu_invalidate_pdb_r() (0x00100cb8U)
#define fb_mmu_invalidate_pdb_aperture_vid_mem_f() (0x0U) #define fb_mmu_invalidate_pdb_aperture_vid_mem_f() (0x0U)
#define fb_mmu_invalidate_pdb_aperture_sys_mem_f() (0x2U) #define fb_mmu_invalidate_pdb_aperture_sys_mem_f() (0x2U)
#define fb_mmu_invalidate_pdb_addr_f(v) (((v)&0xfffffffU) << 4U) #define fb_mmu_invalidate_pdb_addr_f(v) ((U32(v) & 0xfffffffU) << 4U)
#define fb_mmu_invalidate_r() (0x00100cbcU) #define fb_mmu_invalidate_r() (0x00100cbcU)
#define fb_mmu_invalidate_all_va_true_f() (0x1U) #define fb_mmu_invalidate_all_va_true_f() (0x1U)
#define fb_mmu_invalidate_all_pdb_true_f() (0x2U) #define fb_mmu_invalidate_all_pdb_true_f() (0x2U)
#define fb_mmu_invalidate_hubtlb_only_s() (1U) #define fb_mmu_invalidate_hubtlb_only_s() (1U)
#define fb_mmu_invalidate_hubtlb_only_f(v) (((v)&0x1U) << 2U) #define fb_mmu_invalidate_hubtlb_only_f(v) ((U32(v) & 0x1U) << 2U)
#define fb_mmu_invalidate_hubtlb_only_m() (U32(0x1U) << 2U) #define fb_mmu_invalidate_hubtlb_only_m() (U32(0x1U) << 2U)
#define fb_mmu_invalidate_hubtlb_only_v(r) (((r) >> 2U) & 0x1U) #define fb_mmu_invalidate_hubtlb_only_v(r) (((r) >> 2U) & 0x1U)
#define fb_mmu_invalidate_hubtlb_only_true_f() (0x4U) #define fb_mmu_invalidate_hubtlb_only_true_f() (0x4U)
#define fb_mmu_invalidate_replay_s() (3U) #define fb_mmu_invalidate_replay_s() (3U)
#define fb_mmu_invalidate_replay_f(v) (((v)&0x7U) << 3U) #define fb_mmu_invalidate_replay_f(v) ((U32(v) & 0x7U) << 3U)
#define fb_mmu_invalidate_replay_m() (U32(0x7U) << 3U) #define fb_mmu_invalidate_replay_m() (U32(0x7U) << 3U)
#define fb_mmu_invalidate_replay_v(r) (((r) >> 3U) & 0x7U) #define fb_mmu_invalidate_replay_v(r) (((r) >> 3U) & 0x7U)
#define fb_mmu_invalidate_replay_none_f() (0x0U) #define fb_mmu_invalidate_replay_none_f() (0x0U)
@@ -88,33 +88,33 @@
#define fb_mmu_invalidate_replay_cancel_global_f() (0x20U) #define fb_mmu_invalidate_replay_cancel_global_f() (0x20U)
#define fb_mmu_invalidate_replay_cancel_f() (0x20U) #define fb_mmu_invalidate_replay_cancel_f() (0x20U)
#define fb_mmu_invalidate_sys_membar_s() (1U) #define fb_mmu_invalidate_sys_membar_s() (1U)
#define fb_mmu_invalidate_sys_membar_f(v) (((v)&0x1U) << 6U) #define fb_mmu_invalidate_sys_membar_f(v) ((U32(v) & 0x1U) << 6U)
#define fb_mmu_invalidate_sys_membar_m() (U32(0x1U) << 6U) #define fb_mmu_invalidate_sys_membar_m() (U32(0x1U) << 6U)
#define fb_mmu_invalidate_sys_membar_v(r) (((r) >> 6U) & 0x1U) #define fb_mmu_invalidate_sys_membar_v(r) (((r) >> 6U) & 0x1U)
#define fb_mmu_invalidate_sys_membar_true_f() (0x40U) #define fb_mmu_invalidate_sys_membar_true_f() (0x40U)
#define fb_mmu_invalidate_ack_s() (2U) #define fb_mmu_invalidate_ack_s() (2U)
#define fb_mmu_invalidate_ack_f(v) (((v)&0x3U) << 7U) #define fb_mmu_invalidate_ack_f(v) ((U32(v) & 0x3U) << 7U)
#define fb_mmu_invalidate_ack_m() (U32(0x3U) << 7U) #define fb_mmu_invalidate_ack_m() (U32(0x3U) << 7U)
#define fb_mmu_invalidate_ack_v(r) (((r) >> 7U) & 0x3U) #define fb_mmu_invalidate_ack_v(r) (((r) >> 7U) & 0x3U)
#define fb_mmu_invalidate_ack_ack_none_required_f() (0x0U) #define fb_mmu_invalidate_ack_ack_none_required_f() (0x0U)
#define fb_mmu_invalidate_ack_ack_intranode_f() (0x100U) #define fb_mmu_invalidate_ack_ack_intranode_f() (0x100U)
#define fb_mmu_invalidate_ack_ack_globally_f() (0x80U) #define fb_mmu_invalidate_ack_ack_globally_f() (0x80U)
#define fb_mmu_invalidate_cancel_client_id_s() (6U) #define fb_mmu_invalidate_cancel_client_id_s() (6U)
#define fb_mmu_invalidate_cancel_client_id_f(v) (((v)&0x3fU) << 9U) #define fb_mmu_invalidate_cancel_client_id_f(v) ((U32(v) & 0x3fU) << 9U)
#define fb_mmu_invalidate_cancel_client_id_m() (U32(0x3fU) << 9U) #define fb_mmu_invalidate_cancel_client_id_m() (U32(0x3fU) << 9U)
#define fb_mmu_invalidate_cancel_client_id_v(r) (((r) >> 9U) & 0x3fU) #define fb_mmu_invalidate_cancel_client_id_v(r) (((r) >> 9U) & 0x3fU)
#define fb_mmu_invalidate_cancel_gpc_id_s() (5U) #define fb_mmu_invalidate_cancel_gpc_id_s() (5U)
#define fb_mmu_invalidate_cancel_gpc_id_f(v) (((v)&0x1fU) << 15U) #define fb_mmu_invalidate_cancel_gpc_id_f(v) ((U32(v) & 0x1fU) << 15U)
#define fb_mmu_invalidate_cancel_gpc_id_m() (U32(0x1fU) << 15U) #define fb_mmu_invalidate_cancel_gpc_id_m() (U32(0x1fU) << 15U)
#define fb_mmu_invalidate_cancel_gpc_id_v(r) (((r) >> 15U) & 0x1fU) #define fb_mmu_invalidate_cancel_gpc_id_v(r) (((r) >> 15U) & 0x1fU)
#define fb_mmu_invalidate_cancel_client_type_s() (1U) #define fb_mmu_invalidate_cancel_client_type_s() (1U)
#define fb_mmu_invalidate_cancel_client_type_f(v) (((v)&0x1U) << 20U) #define fb_mmu_invalidate_cancel_client_type_f(v) ((U32(v) & 0x1U) << 20U)
#define fb_mmu_invalidate_cancel_client_type_m() (U32(0x1U) << 20U) #define fb_mmu_invalidate_cancel_client_type_m() (U32(0x1U) << 20U)
#define fb_mmu_invalidate_cancel_client_type_v(r) (((r) >> 20U) & 0x1U) #define fb_mmu_invalidate_cancel_client_type_v(r) (((r) >> 20U) & 0x1U)
#define fb_mmu_invalidate_cancel_client_type_gpc_f() (0x0U) #define fb_mmu_invalidate_cancel_client_type_gpc_f() (0x0U)
#define fb_mmu_invalidate_cancel_client_type_hub_f() (0x100000U) #define fb_mmu_invalidate_cancel_client_type_hub_f() (0x100000U)
#define fb_mmu_invalidate_cancel_cache_level_s() (3U) #define fb_mmu_invalidate_cancel_cache_level_s() (3U)
#define fb_mmu_invalidate_cancel_cache_level_f(v) (((v)&0x7U) << 24U) #define fb_mmu_invalidate_cancel_cache_level_f(v) ((U32(v) & 0x7U) << 24U)
#define fb_mmu_invalidate_cancel_cache_level_m() (U32(0x7U) << 24U) #define fb_mmu_invalidate_cancel_cache_level_m() (U32(0x7U) << 24U)
#define fb_mmu_invalidate_cancel_cache_level_v(r) (((r) >> 24U) & 0x7U) #define fb_mmu_invalidate_cancel_cache_level_v(r) (((r) >> 24U) & 0x7U)
#define fb_mmu_invalidate_cancel_cache_level_all_f() (0x0U) #define fb_mmu_invalidate_cancel_cache_level_all_f() (0x0U)
@@ -126,13 +126,13 @@
#define fb_mmu_invalidate_cancel_cache_level_up_to_pde4_f() (0x6000000U) #define fb_mmu_invalidate_cancel_cache_level_up_to_pde4_f() (0x6000000U)
#define fb_mmu_invalidate_cancel_cache_level_up_to_pde5_f() (0x7000000U) #define fb_mmu_invalidate_cancel_cache_level_up_to_pde5_f() (0x7000000U)
#define fb_mmu_invalidate_trigger_s() (1U) #define fb_mmu_invalidate_trigger_s() (1U)
#define fb_mmu_invalidate_trigger_f(v) (((v)&0x1U) << 31U) #define fb_mmu_invalidate_trigger_f(v) ((U32(v) & 0x1U) << 31U)
#define fb_mmu_invalidate_trigger_m() (U32(0x1U) << 31U) #define fb_mmu_invalidate_trigger_m() (U32(0x1U) << 31U)
#define fb_mmu_invalidate_trigger_v(r) (((r) >> 31U) & 0x1U) #define fb_mmu_invalidate_trigger_v(r) (((r) >> 31U) & 0x1U)
#define fb_mmu_invalidate_trigger_true_f() (0x80000000U) #define fb_mmu_invalidate_trigger_true_f() (0x80000000U)
#define fb_mmu_debug_wr_r() (0x00100cc8U) #define fb_mmu_debug_wr_r() (0x00100cc8U)
#define fb_mmu_debug_wr_aperture_s() (2U) #define fb_mmu_debug_wr_aperture_s() (2U)
#define fb_mmu_debug_wr_aperture_f(v) (((v)&0x3U) << 0U) #define fb_mmu_debug_wr_aperture_f(v) ((U32(v) & 0x3U) << 0U)
#define fb_mmu_debug_wr_aperture_m() (U32(0x3U) << 0U) #define fb_mmu_debug_wr_aperture_m() (U32(0x3U) << 0U)
#define fb_mmu_debug_wr_aperture_v(r) (((r) >> 0U) & 0x3U) #define fb_mmu_debug_wr_aperture_v(r) (((r) >> 0U) & 0x3U)
#define fb_mmu_debug_wr_aperture_vid_mem_f() (0x0U) #define fb_mmu_debug_wr_aperture_vid_mem_f() (0x0U)
@@ -141,14 +141,14 @@
#define fb_mmu_debug_wr_vol_false_f() (0x0U) #define fb_mmu_debug_wr_vol_false_f() (0x0U)
#define fb_mmu_debug_wr_vol_true_v() (0x00000001U) #define fb_mmu_debug_wr_vol_true_v() (0x00000001U)
#define fb_mmu_debug_wr_vol_true_f() (0x4U) #define fb_mmu_debug_wr_vol_true_f() (0x4U)
#define fb_mmu_debug_wr_addr_f(v) (((v)&0xfffffffU) << 4U) #define fb_mmu_debug_wr_addr_f(v) ((U32(v) & 0xfffffffU) << 4U)
#define fb_mmu_debug_wr_addr_alignment_v() (0x0000000cU) #define fb_mmu_debug_wr_addr_alignment_v() (0x0000000cU)
#define fb_mmu_debug_rd_r() (0x00100cccU) #define fb_mmu_debug_rd_r() (0x00100cccU)
#define fb_mmu_debug_rd_aperture_vid_mem_f() (0x0U) #define fb_mmu_debug_rd_aperture_vid_mem_f() (0x0U)
#define fb_mmu_debug_rd_aperture_sys_mem_coh_f() (0x2U) #define fb_mmu_debug_rd_aperture_sys_mem_coh_f() (0x2U)
#define fb_mmu_debug_rd_aperture_sys_mem_ncoh_f() (0x3U) #define fb_mmu_debug_rd_aperture_sys_mem_ncoh_f() (0x3U)
#define fb_mmu_debug_rd_vol_false_f() (0x0U) #define fb_mmu_debug_rd_vol_false_f() (0x0U)
#define fb_mmu_debug_rd_addr_f(v) (((v)&0xfffffffU) << 4U) #define fb_mmu_debug_rd_addr_f(v) ((U32(v) & 0xfffffffU) << 4U)
#define fb_mmu_debug_rd_addr_alignment_v() (0x0000000cU) #define fb_mmu_debug_rd_addr_alignment_v() (0x0000000cU)
#define fb_mmu_debug_ctrl_r() (0x00100cc4U) #define fb_mmu_debug_ctrl_r() (0x00100cc4U)
#define fb_mmu_debug_ctrl_debug_v(r) (((r) >> 16U) & 0x1U) #define fb_mmu_debug_ctrl_debug_v(r) (((r) >> 16U) & 0x1U)
@@ -165,20 +165,20 @@
#define fb_mmu_local_memory_range_lower_mag_v(r) (((r) >> 4U) & 0x3fU) #define fb_mmu_local_memory_range_lower_mag_v(r) (((r) >> 4U) & 0x3fU)
#define fb_mmu_local_memory_range_ecc_mode_v(r) (((r) >> 30U) & 0x1U) #define fb_mmu_local_memory_range_ecc_mode_v(r) (((r) >> 30U) & 0x1U)
#define fb_fbpa_fbio_delay_r() (0x009a065cU) #define fb_fbpa_fbio_delay_r() (0x009a065cU)
#define fb_fbpa_fbio_delay_src_f(v) (((v)&0xfU) << 0U) #define fb_fbpa_fbio_delay_src_f(v) ((U32(v) & 0xfU) << 0U)
#define fb_fbpa_fbio_delay_src_m() (U32(0xfU) << 0U) #define fb_fbpa_fbio_delay_src_m() (U32(0xfU) << 0U)
#define fb_fbpa_fbio_delay_src_v(r) (((r) >> 0U) & 0xfU) #define fb_fbpa_fbio_delay_src_v(r) (((r) >> 0U) & 0xfU)
#define fb_fbpa_fbio_delay_src_max_v() (0x00000002U) #define fb_fbpa_fbio_delay_src_max_v() (0x00000002U)
#define fb_fbpa_fbio_delay_priv_f(v) (((v)&0xfU) << 4U) #define fb_fbpa_fbio_delay_priv_f(v) ((U32(v) & 0xfU) << 4U)
#define fb_fbpa_fbio_delay_priv_m() (U32(0xfU) << 4U) #define fb_fbpa_fbio_delay_priv_m() (U32(0xfU) << 4U)
#define fb_fbpa_fbio_delay_priv_v(r) (((r) >> 4U) & 0xfU) #define fb_fbpa_fbio_delay_priv_v(r) (((r) >> 4U) & 0xfU)
#define fb_fbpa_fbio_delay_priv_max_v() (0x00000002U) #define fb_fbpa_fbio_delay_priv_max_v() (0x00000002U)
#define fb_fbpa_fbio_cmd_delay_r() (0x009a08e0U) #define fb_fbpa_fbio_cmd_delay_r() (0x009a08e0U)
#define fb_fbpa_fbio_cmd_delay_cmd_src_f(v) (((v)&0xfU) << 0U) #define fb_fbpa_fbio_cmd_delay_cmd_src_f(v) ((U32(v) & 0xfU) << 0U)
#define fb_fbpa_fbio_cmd_delay_cmd_src_m() (U32(0xfU) << 0U) #define fb_fbpa_fbio_cmd_delay_cmd_src_m() (U32(0xfU) << 0U)
#define fb_fbpa_fbio_cmd_delay_cmd_src_v(r) (((r) >> 0U) & 0xfU) #define fb_fbpa_fbio_cmd_delay_cmd_src_v(r) (((r) >> 0U) & 0xfU)
#define fb_fbpa_fbio_cmd_delay_cmd_src_max_v() (0x00000001U) #define fb_fbpa_fbio_cmd_delay_cmd_src_max_v() (0x00000001U)
#define fb_fbpa_fbio_cmd_delay_cmd_priv_f(v) (((v)&0xfU) << 4U) #define fb_fbpa_fbio_cmd_delay_cmd_priv_f(v) ((U32(v) & 0xfU) << 4U)
#define fb_fbpa_fbio_cmd_delay_cmd_priv_m() (U32(0xfU) << 4U) #define fb_fbpa_fbio_cmd_delay_cmd_priv_m() (U32(0xfU) << 4U)
#define fb_fbpa_fbio_cmd_delay_cmd_priv_v(r) (((r) >> 4U) & 0xfU) #define fb_fbpa_fbio_cmd_delay_cmd_priv_v(r) (((r) >> 4U) & 0xfU)
#define fb_fbpa_fbio_cmd_delay_cmd_priv_max_v() (0x00000001U) #define fb_fbpa_fbio_cmd_delay_cmd_priv_max_v() (0x00000001U)

42
drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_fifo_gp106.h
View File

@@ -60,24 +60,24 @@
#include <nvgpu/safe_ops.h> #include <nvgpu/safe_ops.h>
#define fifo_bar1_base_r() (0x00002254U) #define fifo_bar1_base_r() (0x00002254U)
#define fifo_bar1_base_ptr_f(v) (((v)&0xfffffffU) << 0U) #define fifo_bar1_base_ptr_f(v) ((U32(v) & 0xfffffffU) << 0U)
#define fifo_bar1_base_ptr_align_shift_v() (0x0000000cU) #define fifo_bar1_base_ptr_align_shift_v() (0x0000000cU)
#define fifo_bar1_base_valid_false_f() (0x0U) #define fifo_bar1_base_valid_false_f() (0x0U)
#define fifo_bar1_base_valid_true_f() (0x10000000U) #define fifo_bar1_base_valid_true_f() (0x10000000U)
#define fifo_runlist_base_r() (0x00002270U) #define fifo_runlist_base_r() (0x00002270U)
#define fifo_runlist_base_ptr_f(v) (((v)&0xfffffffU) << 0U) #define fifo_runlist_base_ptr_f(v) ((U32(v) & 0xfffffffU) << 0U)
#define fifo_runlist_base_target_vid_mem_f() (0x0U) #define fifo_runlist_base_target_vid_mem_f() (0x0U)
#define fifo_runlist_base_target_sys_mem_coh_f() (0x20000000U) #define fifo_runlist_base_target_sys_mem_coh_f() (0x20000000U)
#define fifo_runlist_base_target_sys_mem_ncoh_f() (0x30000000U) #define fifo_runlist_base_target_sys_mem_ncoh_f() (0x30000000U)
#define fifo_runlist_r() (0x00002274U) #define fifo_runlist_r() (0x00002274U)
#define fifo_runlist_engine_f(v) (((v)&0xfU) << 20U) #define fifo_runlist_engine_f(v) ((U32(v) & 0xfU) << 20U)
#define fifo_eng_runlist_base_r(i)\ #define fifo_eng_runlist_base_r(i)\
(nvgpu_safe_add_u32(0x00002280U, nvgpu_safe_mult_u32((i), 8U))) (nvgpu_safe_add_u32(0x00002280U, nvgpu_safe_mult_u32((i), 8U)))
#define fifo_eng_runlist_base__size_1_v() (0x00000007U) #define fifo_eng_runlist_base__size_1_v() (0x00000007U)
#define fifo_eng_runlist_r(i)\ #define fifo_eng_runlist_r(i)\
(nvgpu_safe_add_u32(0x00002284U, nvgpu_safe_mult_u32((i), 8U))) (nvgpu_safe_add_u32(0x00002284U, nvgpu_safe_mult_u32((i), 8U)))
#define fifo_eng_runlist__size_1_v() (0x00000007U) #define fifo_eng_runlist__size_1_v() (0x00000007U)
#define fifo_eng_runlist_length_f(v) (((v)&0xffffU) << 0U) #define fifo_eng_runlist_length_f(v) ((U32(v) & 0xffffU) << 0U)
#define fifo_eng_runlist_length_max_v() (0x0000ffffU) #define fifo_eng_runlist_length_max_v() (0x0000ffffU)
#define fifo_eng_runlist_pending_true_f() (0x100000U) #define fifo_eng_runlist_pending_true_f() (0x100000U)
#define fifo_pb_timeslice_r(i)\ #define fifo_pb_timeslice_r(i)\
@@ -106,14 +106,14 @@
#define fifo_intr_0_runlist_event_pending_f() (0x40000000U) #define fifo_intr_0_runlist_event_pending_f() (0x40000000U)
#define fifo_intr_0_channel_intr_pending_f() (0x80000000U) #define fifo_intr_0_channel_intr_pending_f() (0x80000000U)
#define fifo_intr_en_0_r() (0x00002140U) #define fifo_intr_en_0_r() (0x00002140U)
#define fifo_intr_en_0_sched_error_f(v) (((v)&0x1U) << 8U) #define fifo_intr_en_0_sched_error_f(v) ((U32(v) & 0x1U) << 8U)
#define fifo_intr_en_0_sched_error_m() (U32(0x1U) << 8U) #define fifo_intr_en_0_sched_error_m() (U32(0x1U) << 8U)
#define fifo_intr_en_0_mmu_fault_f(v) (((v)&0x1U) << 28U) #define fifo_intr_en_0_mmu_fault_f(v) ((U32(v) & 0x1U) << 28U)
#define fifo_intr_en_0_mmu_fault_m() (U32(0x1U) << 28U) #define fifo_intr_en_0_mmu_fault_m() (U32(0x1U) << 28U)
#define fifo_intr_en_1_r() (0x00002528U) #define fifo_intr_en_1_r() (0x00002528U)
#define fifo_intr_bind_error_r() (0x0000252cU) #define fifo_intr_bind_error_r() (0x0000252cU)
#define fifo_intr_sched_error_r() (0x0000254cU) #define fifo_intr_sched_error_r() (0x0000254cU)
#define fifo_intr_sched_error_code_f(v) (((v)&0xffU) << 0U) #define fifo_intr_sched_error_code_f(v) ((U32(v) & 0xffU) << 0U)
#define fifo_intr_sched_error_code_ctxsw_timeout_v() (0x0000000aU) #define fifo_intr_sched_error_code_ctxsw_timeout_v() (0x0000000aU)
#define fifo_intr_chsw_error_r() (0x0000256cU) #define fifo_intr_chsw_error_r() (0x0000256cU)
#define fifo_intr_mmu_fault_id_r() (0x0000259cU) #define fifo_intr_mmu_fault_id_r() (0x0000259cU)
@@ -136,7 +136,7 @@
#define fifo_intr_mmu_fault_info_client_v(r) (((r) >> 8U) & 0x7fU) #define fifo_intr_mmu_fault_info_client_v(r) (((r) >> 8U) & 0x7fU)
#define fifo_intr_pbdma_id_r() (0x000025a0U) #define fifo_intr_pbdma_id_r() (0x000025a0U)
#define fifo_intr_pbdma_id_status_f(v, i)\ #define fifo_intr_pbdma_id_status_f(v, i)\
(((v) & 0x1) << (0U + i*1U)) ((U32(v) & 0x1U) << (0U + (i)*1U))
#define fifo_intr_pbdma_id_status_v(r, i)\ #define fifo_intr_pbdma_id_status_v(r, i)\
(((r) >> (0U + i*1U)) & 0x1U) (((r) >> (0U + i*1U)) & 0x1U)
#define fifo_intr_pbdma_id_status__size_1_v() (0x00000004U) #define fifo_intr_pbdma_id_status__size_1_v() (0x00000004U)
@@ -147,7 +147,7 @@
#define fifo_error_sched_disable_r() (0x0000262cU) #define fifo_error_sched_disable_r() (0x0000262cU)
#define fifo_sched_disable_r() (0x00002630U) #define fifo_sched_disable_r() (0x00002630U)
#define fifo_sched_disable_runlist_f(v, i)\ #define fifo_sched_disable_runlist_f(v, i)\
(((v) & 0x1) << (0U + i*1U)) ((U32(v) & 0x1U) << (0U + (i)*1U))
#define fifo_sched_disable_runlist_m(i)\ #define fifo_sched_disable_runlist_m(i)\
(U32(0x1U) << (0U + (i)*1U)) (U32(0x1U) << (0U + (i)*1U))
#define fifo_sched_disable_true_v() (0x00000001U) #define fifo_sched_disable_true_v() (0x00000001U)
@@ -155,12 +155,12 @@
#define fifo_preempt_pending_true_f() (0x100000U) #define fifo_preempt_pending_true_f() (0x100000U)
#define fifo_preempt_type_channel_f() (0x0U) #define fifo_preempt_type_channel_f() (0x0U)
#define fifo_preempt_type_tsg_f() (0x1000000U) #define fifo_preempt_type_tsg_f() (0x1000000U)
#define fifo_preempt_chid_f(v) (((v)&0xfffU) << 0U) #define fifo_preempt_chid_f(v) ((U32(v) & 0xfffU) << 0U)
#define fifo_preempt_id_f(v) (((v)&0xfffU) << 0U) #define fifo_preempt_id_f(v) ((U32(v) & 0xfffU) << 0U)
#define fifo_trigger_mmu_fault_r(i)\ #define fifo_trigger_mmu_fault_r(i)\
(nvgpu_safe_add_u32(0x00002a30U, nvgpu_safe_mult_u32((i), 4U))) (nvgpu_safe_add_u32(0x00002a30U, nvgpu_safe_mult_u32((i), 4U)))
#define fifo_trigger_mmu_fault_id_f(v) (((v)&0x1fU) << 0U) #define fifo_trigger_mmu_fault_id_f(v) ((U32(v) & 0x1fU) << 0U)
#define fifo_trigger_mmu_fault_enable_f(v) (((v)&0x1U) << 8U) #define fifo_trigger_mmu_fault_enable_f(v) ((U32(v) & 0x1U) << 8U)
#define fifo_engine_status_r(i)\ #define fifo_engine_status_r(i)\
(nvgpu_safe_add_u32(0x00002640U, nvgpu_safe_mult_u32((i), 8U))) (nvgpu_safe_add_u32(0x00002640U, nvgpu_safe_mult_u32((i), 8U)))
#define fifo_engine_status__size_1_v() (0x00000009U) #define fifo_engine_status__size_1_v() (0x00000009U)
@@ -208,31 +208,31 @@
#define fifo_replay_fault_buffer_lo_enable_v(r) (((r) >> 0U) & 0x1U) #define fifo_replay_fault_buffer_lo_enable_v(r) (((r) >> 0U) & 0x1U)
#define fifo_replay_fault_buffer_lo_enable_true_v() (0x00000001U) #define fifo_replay_fault_buffer_lo_enable_true_v() (0x00000001U)
#define fifo_replay_fault_buffer_lo_enable_false_v() (0x00000000U) #define fifo_replay_fault_buffer_lo_enable_false_v() (0x00000000U)
#define fifo_replay_fault_buffer_lo_base_f(v) (((v)&0xfffffU) << 12U) #define fifo_replay_fault_buffer_lo_base_f(v) ((U32(v) & 0xfffffU) << 12U)
#define fifo_replay_fault_buffer_lo_base_reset_v() (0x00000000U) #define fifo_replay_fault_buffer_lo_base_reset_v() (0x00000000U)
#define fifo_replay_fault_buffer_hi_r() (0x00002a74U) #define fifo_replay_fault_buffer_hi_r() (0x00002a74U)
#define fifo_replay_fault_buffer_hi_base_f(v) (((v)&0xffU) << 0U) #define fifo_replay_fault_buffer_hi_base_f(v) ((U32(v) & 0xffU) << 0U)
#define fifo_replay_fault_buffer_hi_base_reset_v() (0x00000000U) #define fifo_replay_fault_buffer_hi_base_reset_v() (0x00000000U)
#define fifo_replay_fault_buffer_size_r() (0x00002a78U) #define fifo_replay_fault_buffer_size_r() (0x00002a78U)
#define fifo_replay_fault_buffer_size_hw_f(v) (((v)&0x3fffU) << 0U) #define fifo_replay_fault_buffer_size_hw_f(v) ((U32(v) & 0x3fffU) << 0U)
#define fifo_replay_fault_buffer_size_hw_entries_v() (0x00001200U) #define fifo_replay_fault_buffer_size_hw_entries_v() (0x00001200U)
#define fifo_replay_fault_buffer_get_r() (0x00002a7cU) #define fifo_replay_fault_buffer_get_r() (0x00002a7cU)
#define fifo_replay_fault_buffer_get_offset_hw_f(v) (((v)&0x3fffU) << 0U) #define fifo_replay_fault_buffer_get_offset_hw_f(v) ((U32(v) & 0x3fffU) << 0U)
#define fifo_replay_fault_buffer_get_offset_hw_init_v() (0x00000000U) #define fifo_replay_fault_buffer_get_offset_hw_init_v() (0x00000000U)
#define fifo_replay_fault_buffer_put_r() (0x00002a80U) #define fifo_replay_fault_buffer_put_r() (0x00002a80U)
#define fifo_replay_fault_buffer_put_offset_hw_f(v) (((v)&0x3fffU) << 0U) #define fifo_replay_fault_buffer_put_offset_hw_f(v) ((U32(v) & 0x3fffU) << 0U)
#define fifo_replay_fault_buffer_put_offset_hw_init_v() (0x00000000U) #define fifo_replay_fault_buffer_put_offset_hw_init_v() (0x00000000U)
#define fifo_replay_fault_buffer_info_r() (0x00002a84U) #define fifo_replay_fault_buffer_info_r() (0x00002a84U)
#define fifo_replay_fault_buffer_info_overflow_f(v) (((v)&0x1U) << 0U) #define fifo_replay_fault_buffer_info_overflow_f(v) ((U32(v) & 0x1U) << 0U)
#define fifo_replay_fault_buffer_info_overflow_false_v() (0x00000000U) #define fifo_replay_fault_buffer_info_overflow_false_v() (0x00000000U)
#define fifo_replay_fault_buffer_info_overflow_true_v() (0x00000001U) #define fifo_replay_fault_buffer_info_overflow_true_v() (0x00000001U)
#define fifo_replay_fault_buffer_info_overflow_clear_v() (0x00000001U) #define fifo_replay_fault_buffer_info_overflow_clear_v() (0x00000001U)
#define fifo_replay_fault_buffer_info_write_nack_f(v) (((v)&0x1U) << 24U) #define fifo_replay_fault_buffer_info_write_nack_f(v) ((U32(v) & 0x1U) << 24U)
#define fifo_replay_fault_buffer_info_write_nack_false_v() (0x00000000U) #define fifo_replay_fault_buffer_info_write_nack_false_v() (0x00000000U)
#define fifo_replay_fault_buffer_info_write_nack_true_v() (0x00000001U) #define fifo_replay_fault_buffer_info_write_nack_true_v() (0x00000001U)
#define fifo_replay_fault_buffer_info_write_nack_clear_v() (0x00000001U) #define fifo_replay_fault_buffer_info_write_nack_clear_v() (0x00000001U)
#define fifo_replay_fault_buffer_info_fault_while_buffer_disabled_f(v)\ #define fifo_replay_fault_buffer_info_fault_while_buffer_disabled_f(v)\
(((v)&0x1U) << 28U) ((U32(v) & 0x1U) << 28U)
#define fifo_replay_fault_buffer_info_fault_while_buffer_disabled_false_v()\ #define fifo_replay_fault_buffer_info_fault_while_buffer_disabled_false_v()\
(0x00000000U) (0x00000000U)
#define fifo_replay_fault_buffer_info_fault_while_buffer_disabled_true_v()\ #define fifo_replay_fault_buffer_info_fault_while_buffer_disabled_true_v()\

6
drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_fuse_gp106.h
View File

@@ -65,17 +65,17 @@
#define fuse_ctrl_opt_tpc_gpc_r(i)\ #define fuse_ctrl_opt_tpc_gpc_r(i)\
(nvgpu_safe_add_u32(0x00021838U, nvgpu_safe_mult_u32((i), 4U))) (nvgpu_safe_add_u32(0x00021838U, nvgpu_safe_mult_u32((i), 4U)))
#define fuse_ctrl_opt_ram_svop_pdp_r() (0x00021944U) #define fuse_ctrl_opt_ram_svop_pdp_r() (0x00021944U)
#define fuse_ctrl_opt_ram_svop_pdp_data_f(v) (((v)&0x3U) << 0U) #define fuse_ctrl_opt_ram_svop_pdp_data_f(v) ((U32(v) & 0x3U) << 0U)
#define fuse_ctrl_opt_ram_svop_pdp_data_m() (U32(0x3U) << 0U) #define fuse_ctrl_opt_ram_svop_pdp_data_m() (U32(0x3U) << 0U)
#define fuse_ctrl_opt_ram_svop_pdp_data_v(r) (((r) >> 0U) & 0x3U) #define fuse_ctrl_opt_ram_svop_pdp_data_v(r) (((r) >> 0U) & 0x3U)
#define fuse_ctrl_opt_ram_svop_pdp_override_r() (0x00021948U) #define fuse_ctrl_opt_ram_svop_pdp_override_r() (0x00021948U)
#define fuse_ctrl_opt_ram_svop_pdp_override_data_f(v) (((v)&0x1U) << 0U) #define fuse_ctrl_opt_ram_svop_pdp_override_data_f(v) ((U32(v) & 0x1U) << 0U)
#define fuse_ctrl_opt_ram_svop_pdp_override_data_m() (U32(0x1U) << 0U) #define fuse_ctrl_opt_ram_svop_pdp_override_data_m() (U32(0x1U) << 0U)
#define fuse_ctrl_opt_ram_svop_pdp_override_data_v(r) (((r) >> 0U) & 0x1U) #define fuse_ctrl_opt_ram_svop_pdp_override_data_v(r) (((r) >> 0U) & 0x1U)
#define fuse_ctrl_opt_ram_svop_pdp_override_data_yes_f() (0x1U) #define fuse_ctrl_opt_ram_svop_pdp_override_data_yes_f() (0x1U)
#define fuse_ctrl_opt_ram_svop_pdp_override_data_no_f() (0x0U) #define fuse_ctrl_opt_ram_svop_pdp_override_data_no_f() (0x0U)
#define fuse_status_opt_fbio_r() (0x00021c14U) #define fuse_status_opt_fbio_r() (0x00021c14U)
#define fuse_status_opt_fbio_data_f(v) (((v)&0xffffU) << 0U) #define fuse_status_opt_fbio_data_f(v) ((U32(v) & 0xffffU) << 0U)
#define fuse_status_opt_fbio_data_m() (U32(0xffffU) << 0U) #define fuse_status_opt_fbio_data_m() (U32(0xffffU) << 0U)
#define fuse_status_opt_fbio_data_v(r) (((r) >> 0U) & 0xffffU) #define fuse_status_opt_fbio_data_v(r) (((r) >> 0U) & 0xffffU)
#define fuse_status_opt_rop_l2_fbp_r(i)\ #define fuse_status_opt_rop_l2_fbp_r(i)\

16
drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_gmmu_gp106.h
View File

@@ -66,7 +66,7 @@
#define gmmu_new_pde_aperture_video_memory_f() (0x2U) #define gmmu_new_pde_aperture_video_memory_f() (0x2U)
#define gmmu_new_pde_aperture_sys_mem_coh_f() (0x4U) #define gmmu_new_pde_aperture_sys_mem_coh_f() (0x4U)
#define gmmu_new_pde_aperture_sys_mem_ncoh_f() (0x6U) #define gmmu_new_pde_aperture_sys_mem_ncoh_f() (0x6U)
#define gmmu_new_pde_address_sys_f(v) (((v)&0xffffffU) << 8U) #define gmmu_new_pde_address_sys_f(v) ((U32(v) & 0xffffffU) << 8U)
#define gmmu_new_pde_address_sys_w() (0U) #define gmmu_new_pde_address_sys_w() (0U)
#define gmmu_new_pde_vol_w() (0U) #define gmmu_new_pde_vol_w() (0U)
#define gmmu_new_pde_vol_true_f() (0x8U) #define gmmu_new_pde_vol_true_f() (0x8U)
@@ -80,7 +80,7 @@
#define gmmu_new_dual_pde_aperture_big_video_memory_f() (0x2U) #define gmmu_new_dual_pde_aperture_big_video_memory_f() (0x2U)
#define gmmu_new_dual_pde_aperture_big_sys_mem_coh_f() (0x4U) #define gmmu_new_dual_pde_aperture_big_sys_mem_coh_f() (0x4U)
#define gmmu_new_dual_pde_aperture_big_sys_mem_ncoh_f() (0x6U) #define gmmu_new_dual_pde_aperture_big_sys_mem_ncoh_f() (0x6U)
#define gmmu_new_dual_pde_address_big_sys_f(v) (((v)&0xfffffffU) << 4U) #define gmmu_new_dual_pde_address_big_sys_f(v) ((U32(v) & 0xfffffffU) << 4U)
#define gmmu_new_dual_pde_address_big_sys_w() (0U) #define gmmu_new_dual_pde_address_big_sys_w() (0U)
#define gmmu_new_dual_pde_aperture_small_w() (2U) #define gmmu_new_dual_pde_aperture_small_w() (2U)
#define gmmu_new_dual_pde_aperture_small_invalid_f() (0x0U) #define gmmu_new_dual_pde_aperture_small_invalid_f() (0x0U)
@@ -93,7 +93,7 @@
#define gmmu_new_dual_pde_vol_big_w() (0U) #define gmmu_new_dual_pde_vol_big_w() (0U)
#define gmmu_new_dual_pde_vol_big_true_f() (0x8U) #define gmmu_new_dual_pde_vol_big_true_f() (0x8U)
#define gmmu_new_dual_pde_vol_big_false_f() (0x0U) #define gmmu_new_dual_pde_vol_big_false_f() (0x0U)
#define gmmu_new_dual_pde_address_small_sys_f(v) (((v)&0xffffffU) << 8U) #define gmmu_new_dual_pde_address_small_sys_f(v) ((U32(v) & 0xffffffU) << 8U)
#define gmmu_new_dual_pde_address_small_sys_w() (2U) #define gmmu_new_dual_pde_address_small_sys_w() (2U)
#define gmmu_new_dual_pde_address_shift_v() (0x0000000cU) #define gmmu_new_dual_pde_address_shift_v() (0x0000000cU)
#define gmmu_new_dual_pde_address_big_shift_v() (0x00000008U) #define gmmu_new_dual_pde_address_big_shift_v() (0x00000008U)
@@ -105,9 +105,9 @@
#define gmmu_new_pte_privilege_w() (0U) #define gmmu_new_pte_privilege_w() (0U)
#define gmmu_new_pte_privilege_true_f() (0x20U) #define gmmu_new_pte_privilege_true_f() (0x20U)
#define gmmu_new_pte_privilege_false_f() (0x0U) #define gmmu_new_pte_privilege_false_f() (0x0U)
#define gmmu_new_pte_address_sys_f(v) (((v)&0xffffffU) << 8U) #define gmmu_new_pte_address_sys_f(v) ((U32(v) & 0xffffffU) << 8U)
#define gmmu_new_pte_address_sys_w() (0U) #define gmmu_new_pte_address_sys_w() (0U)
#define gmmu_new_pte_address_vid_f(v) (((v)&0xffffffU) << 8U) #define gmmu_new_pte_address_vid_f(v) ((U32(v) & 0xffffffU) << 8U)
#define gmmu_new_pte_address_vid_w() (0U) #define gmmu_new_pte_address_vid_w() (0U)
#define gmmu_new_pte_vol_w() (0U) #define gmmu_new_pte_vol_w() (0U)
#define gmmu_new_pte_vol_true_f() (0x8U) #define gmmu_new_pte_vol_true_f() (0x8U)
@@ -118,12 +118,12 @@
#define gmmu_new_pte_aperture_sys_mem_ncoh_f() (0x6U) #define gmmu_new_pte_aperture_sys_mem_ncoh_f() (0x6U)
#define gmmu_new_pte_read_only_w() (0U) #define gmmu_new_pte_read_only_w() (0U)
#define gmmu_new_pte_read_only_true_f() (0x40U) #define gmmu_new_pte_read_only_true_f() (0x40U)
#define gmmu_new_pte_comptagline_f(v) (((v)&0x3ffffU) << 4U) #define gmmu_new_pte_comptagline_f(v) ((U32(v) & 0x3ffffU) << 4U)
#define gmmu_new_pte_comptagline_w() (1U) #define gmmu_new_pte_comptagline_w() (1U)
#define gmmu_new_pte_kind_f(v) (((v)&0xffU) << 24U) #define gmmu_new_pte_kind_f(v) ((U32(v) & 0xffU) << 24U)
#define gmmu_new_pte_kind_w() (1U) #define gmmu_new_pte_kind_w() (1U)
#define gmmu_new_pte_address_shift_v() (0x0000000cU) #define gmmu_new_pte_address_shift_v() (0x0000000cU)
#define gmmu_pte_kind_f(v) (((v)&0xffU) << 4U) #define gmmu_pte_kind_f(v) ((U32(v) & 0xffU) << 4U)
#define gmmu_pte_kind_w() (1U) #define gmmu_pte_kind_w() (1U)
#define gmmu_pte_kind_invalid_v() (0x000000ffU) #define gmmu_pte_kind_invalid_v() (0x000000ffU)
#define gmmu_pte_kind_pitch_v() (0x00000000U) #define gmmu_pte_kind_pitch_v() (0x00000000U)

488
drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_gr_gp106.h
View File

@@ -68,7 +68,7 @@
#define gr_intr_illegal_method_reset_f() (0x10U) #define gr_intr_illegal_method_reset_f() (0x10U)
#define gr_intr_illegal_notify_pending_f() (0x40U) #define gr_intr_illegal_notify_pending_f() (0x40U)
#define gr_intr_illegal_notify_reset_f() (0x40U) #define gr_intr_illegal_notify_reset_f() (0x40U)
#define gr_intr_firmware_method_f(v) (((v)&0x1U) << 8U) #define gr_intr_firmware_method_f(v) ((U32(v) & 0x1U) << 8U)
#define gr_intr_firmware_method_pending_f() (0x100U) #define gr_intr_firmware_method_pending_f() (0x100U)
#define gr_intr_firmware_method_reset_f() (0x100U) #define gr_intr_firmware_method_reset_f() (0x100U)
#define gr_intr_illegal_class_pending_f() (0x20U) #define gr_intr_illegal_class_pending_f() (0x20U)
@@ -103,10 +103,10 @@
#define gr_exception1_en_r() (0x00400130U) #define gr_exception1_en_r() (0x00400130U)
#define gr_exception2_en_r() (0x00400134U) #define gr_exception2_en_r() (0x00400134U)
#define gr_gpfifo_ctl_r() (0x00400500U) #define gr_gpfifo_ctl_r() (0x00400500U)
#define gr_gpfifo_ctl_access_f(v) (((v)&0x1U) << 0U) #define gr_gpfifo_ctl_access_f(v) ((U32(v) & 0x1U) << 0U)
#define gr_gpfifo_ctl_access_disabled_f() (0x0U) #define gr_gpfifo_ctl_access_disabled_f() (0x0U)
#define gr_gpfifo_ctl_access_enabled_f() (0x1U) #define gr_gpfifo_ctl_access_enabled_f() (0x1U)
#define gr_gpfifo_ctl_semaphore_access_f(v) (((v)&0x1U) << 16U) #define gr_gpfifo_ctl_semaphore_access_f(v) ((U32(v) & 0x1U) << 16U)
#define gr_gpfifo_ctl_semaphore_access_enabled_v() (0x00000001U) #define gr_gpfifo_ctl_semaphore_access_enabled_v() (0x00000001U)
#define gr_gpfifo_ctl_semaphore_access_enabled_f() (0x10000U) #define gr_gpfifo_ctl_semaphore_access_enabled_f() (0x10000U)
#define gr_gpfifo_status_r() (0x00400504U) #define gr_gpfifo_status_r() (0x00400504U)
@@ -142,7 +142,7 @@
#define gr_activity_2_r() (0x00400388U) #define gr_activity_2_r() (0x00400388U)
#define gr_activity_4_r() (0x00400390U) #define gr_activity_4_r() (0x00400390U)
#define gr_activity_4_gpc0_s() (3U) #define gr_activity_4_gpc0_s() (3U)
#define gr_activity_4_gpc0_f(v) (((v)&0x7U) << 0U) #define gr_activity_4_gpc0_f(v) ((U32(v) & 0x7U) << 0U)
#define gr_activity_4_gpc0_m() (U32(0x7U) << 0U) #define gr_activity_4_gpc0_m() (U32(0x7U) << 0U)
#define gr_activity_4_gpc0_v(r) (((r) >> 0U) & 0x7U) #define gr_activity_4_gpc0_v(r) (((r) >> 0U) & 0x7U)
#define gr_activity_4_gpc0_empty_v() (0x00000000U) #define gr_activity_4_gpc0_empty_v() (0x00000000U)
@@ -240,7 +240,7 @@
#define gr_fe_hww_esr_en_enable_f() (0x80000000U) #define gr_fe_hww_esr_en_enable_f() (0x80000000U)
#define gr_fe_hww_esr_info_r() (0x004041b0U) #define gr_fe_hww_esr_info_r() (0x004041b0U)
#define gr_fe_go_idle_timeout_r() (0x00404154U) #define gr_fe_go_idle_timeout_r() (0x00404154U)
#define gr_fe_go_idle_timeout_count_f(v) (((v)&0xffffffffU) << 0U) #define gr_fe_go_idle_timeout_count_f(v) ((U32(v) & 0xffffffffU) << 0U)
#define gr_fe_go_idle_timeout_count_disabled_f() (0x0U) #define gr_fe_go_idle_timeout_count_disabled_f() (0x0U)
#define gr_fe_go_idle_timeout_count_prod_f() (0x1800U) #define gr_fe_go_idle_timeout_count_prod_f() (0x1800U)
#define gr_fe_object_table_r(i)\ #define gr_fe_object_table_r(i)\
@@ -258,11 +258,11 @@
#define gr_memfmt_hww_esr_reset_active_f() (0x40000000U) #define gr_memfmt_hww_esr_reset_active_f() (0x40000000U)
#define gr_memfmt_hww_esr_en_enable_f() (0x80000000U) #define gr_memfmt_hww_esr_en_enable_f() (0x80000000U)
#define gr_fecs_cpuctl_r() (0x00409100U) #define gr_fecs_cpuctl_r() (0x00409100U)
#define gr_fecs_cpuctl_startcpu_f(v) (((v)&0x1U) << 1U) #define gr_fecs_cpuctl_startcpu_f(v) ((U32(v) & 0x1U) << 1U)
#define gr_fecs_cpuctl_alias_r() (0x00409130U) #define gr_fecs_cpuctl_alias_r() (0x00409130U)
#define gr_fecs_cpuctl_alias_startcpu_f(v) (((v)&0x1U) << 1U) #define gr_fecs_cpuctl_alias_startcpu_f(v) ((U32(v) & 0x1U) << 1U)
#define gr_fecs_dmactl_r() (0x0040910cU) #define gr_fecs_dmactl_r() (0x0040910cU)
#define gr_fecs_dmactl_require_ctx_f(v) (((v)&0x1U) << 0U) #define gr_fecs_dmactl_require_ctx_f(v) ((U32(v) & 0x1U) << 0U)
#define gr_fecs_dmactl_dmem_scrubbing_m() (U32(0x1U) << 1U) #define gr_fecs_dmactl_dmem_scrubbing_m() (U32(0x1U) << 1U)
#define gr_fecs_dmactl_imem_scrubbing_m() (U32(0x1U) << 2U) #define gr_fecs_dmactl_imem_scrubbing_m() (U32(0x1U) << 2U)
#define gr_fecs_os_r() (0x00409080U) #define gr_fecs_os_r() (0x00409080U)
@@ -280,43 +280,43 @@
#define gr_fecs_debuginfo_r() (0x00409094U) #define gr_fecs_debuginfo_r() (0x00409094U)
#define gr_fecs_icd_cmd_r() (0x00409200U) #define gr_fecs_icd_cmd_r() (0x00409200U)
#define gr_fecs_icd_cmd_opc_s() (4U) #define gr_fecs_icd_cmd_opc_s() (4U)
#define gr_fecs_icd_cmd_opc_f(v) (((v)&0xfU) << 0U) #define gr_fecs_icd_cmd_opc_f(v) ((U32(v) & 0xfU) << 0U)
#define gr_fecs_icd_cmd_opc_m() (U32(0xfU) << 0U) #define gr_fecs_icd_cmd_opc_m() (U32(0xfU) << 0U)
#define gr_fecs_icd_cmd_opc_v(r) (((r) >> 0U) & 0xfU) #define gr_fecs_icd_cmd_opc_v(r) (((r) >> 0U) & 0xfU)
#define gr_fecs_icd_cmd_opc_rreg_f() (0x8U) #define gr_fecs_icd_cmd_opc_rreg_f() (0x8U)
#define gr_fecs_icd_cmd_opc_rstat_f() (0xeU) #define gr_fecs_icd_cmd_opc_rstat_f() (0xeU)
#define gr_fecs_icd_cmd_idx_f(v) (((v)&0x1fU) << 8U) #define gr_fecs_icd_cmd_idx_f(v) ((U32(v) & 0x1fU) << 8U)
#define gr_fecs_icd_rdata_r() (0x0040920cU) #define gr_fecs_icd_rdata_r() (0x0040920cU)
#define gr_fecs_imemc_r(i)\ #define gr_fecs_imemc_r(i)\
(nvgpu_safe_add_u32(0x00409180U, nvgpu_safe_mult_u32((i), 16U))) (nvgpu_safe_add_u32(0x00409180U, nvgpu_safe_mult_u32((i), 16U)))
#define gr_fecs_imemc_offs_f(v) (((v)&0x3fU) << 2U) #define gr_fecs_imemc_offs_f(v) ((U32(v) & 0x3fU) << 2U)
#define gr_fecs_imemc_blk_f(v) (((v)&0xffU) << 8U) #define gr_fecs_imemc_blk_f(v) ((U32(v) & 0xffU) << 8U)
#define gr_fecs_imemc_aincw_f(v) (((v)&0x1U) << 24U) #define gr_fecs_imemc_aincw_f(v) ((U32(v) & 0x1U) << 24U)
#define gr_fecs_imemd_r(i)\ #define gr_fecs_imemd_r(i)\
(nvgpu_safe_add_u32(0x00409184U, nvgpu_safe_mult_u32((i), 16U))) (nvgpu_safe_add_u32(0x00409184U, nvgpu_safe_mult_u32((i), 16U)))
#define gr_fecs_imemt_r(i)\ #define gr_fecs_imemt_r(i)\
(nvgpu_safe_add_u32(0x00409188U, nvgpu_safe_mult_u32((i), 16U))) (nvgpu_safe_add_u32(0x00409188U, nvgpu_safe_mult_u32((i), 16U)))
#define gr_fecs_imemt_tag_f(v) (((v)&0xffffU) << 0U) #define gr_fecs_imemt_tag_f(v) ((U32(v) & 0xffffU) << 0U)
#define gr_fecs_dmemc_r(i)\ #define gr_fecs_dmemc_r(i)\
(nvgpu_safe_add_u32(0x004091c0U, nvgpu_safe_mult_u32((i), 8U))) (nvgpu_safe_add_u32(0x004091c0U, nvgpu_safe_mult_u32((i), 8U)))
#define gr_fecs_dmemc_offs_s() (6U) #define gr_fecs_dmemc_offs_s() (6U)
#define gr_fecs_dmemc_offs_f(v) (((v)&0x3fU) << 2U) #define gr_fecs_dmemc_offs_f(v) ((U32(v) & 0x3fU) << 2U)
#define gr_fecs_dmemc_offs_m() (U32(0x3fU) << 2U) #define gr_fecs_dmemc_offs_m() (U32(0x3fU) << 2U)
#define gr_fecs_dmemc_offs_v(r) (((r) >> 2U) & 0x3fU) #define gr_fecs_dmemc_offs_v(r) (((r) >> 2U) & 0x3fU)
#define gr_fecs_dmemc_blk_f(v) (((v)&0xffU) << 8U) #define gr_fecs_dmemc_blk_f(v) ((U32(v) & 0xffU) << 8U)
#define gr_fecs_dmemc_aincw_f(v) (((v)&0x1U) << 24U) #define gr_fecs_dmemc_aincw_f(v) ((U32(v) & 0x1U) << 24U)
#define gr_fecs_dmemd_r(i)\ #define gr_fecs_dmemd_r(i)\
(nvgpu_safe_add_u32(0x004091c4U, nvgpu_safe_mult_u32((i), 8U))) (nvgpu_safe_add_u32(0x004091c4U, nvgpu_safe_mult_u32((i), 8U)))
#define gr_fecs_dmatrfbase_r() (0x00409110U) #define gr_fecs_dmatrfbase_r() (0x00409110U)
#define gr_fecs_dmatrfmoffs_r() (0x00409114U) #define gr_fecs_dmatrfmoffs_r() (0x00409114U)
#define gr_fecs_dmatrffboffs_r() (0x0040911cU) #define gr_fecs_dmatrffboffs_r() (0x0040911cU)
#define gr_fecs_dmatrfcmd_r() (0x00409118U) #define gr_fecs_dmatrfcmd_r() (0x00409118U)
#define gr_fecs_dmatrfcmd_imem_f(v) (((v)&0x1U) << 4U) #define gr_fecs_dmatrfcmd_imem_f(v) ((U32(v) & 0x1U) << 4U)
#define gr_fecs_dmatrfcmd_write_f(v) (((v)&0x1U) << 5U) #define gr_fecs_dmatrfcmd_write_f(v) ((U32(v) & 0x1U) << 5U)
#define gr_fecs_dmatrfcmd_size_f(v) (((v)&0x7U) << 8U) #define gr_fecs_dmatrfcmd_size_f(v) ((U32(v) & 0x7U) << 8U)
#define gr_fecs_dmatrfcmd_ctxdma_f(v) (((v)&0x7U) << 12U) #define gr_fecs_dmatrfcmd_ctxdma_f(v) ((U32(v) & 0x7U) << 12U)
#define gr_fecs_bootvec_r() (0x00409104U) #define gr_fecs_bootvec_r() (0x00409104U)
#define gr_fecs_bootvec_vec_f(v) (((v)&0xffffffffU) << 0U) #define gr_fecs_bootvec_vec_f(v) ((U32(v) & 0xffffffffU) << 0U)
#define gr_fecs_irqsset_r() (0x00409000U) #define gr_fecs_irqsset_r() (0x00409000U)
#define gr_fecs_irqsclr_r() (0x00409004U) #define gr_fecs_irqsclr_r() (0x00409004U)
#define gr_fecs_falcon_hwcfg_r() (0x00409108U) #define gr_fecs_falcon_hwcfg_r() (0x00409108U)
@@ -325,23 +325,23 @@
#define gr_gpcs_gpccs_falcon_hwcfg_r() (0x0041a108U) #define gr_gpcs_gpccs_falcon_hwcfg_r() (0x0041a108U)
#define gr_fecs_falcon_rm_r() (0x00409084U) #define gr_fecs_falcon_rm_r() (0x00409084U)
#define gr_fecs_current_ctx_r() (0x00409b00U) #define gr_fecs_current_ctx_r() (0x00409b00U)
#define gr_fecs_current_ctx_ptr_f(v) (((v)&0xfffffffU) << 0U) #define gr_fecs_current_ctx_ptr_f(v) ((U32(v) & 0xfffffffU) << 0U)
#define gr_fecs_current_ctx_ptr_v(r) (((r) >> 0U) & 0xfffffffU) #define gr_fecs_current_ctx_ptr_v(r) (((r) >> 0U) & 0xfffffffU)
#define gr_fecs_current_ctx_target_s() (2U) #define gr_fecs_current_ctx_target_s() (2U)
#define gr_fecs_current_ctx_target_f(v) (((v)&0x3U) << 28U) #define gr_fecs_current_ctx_target_f(v) ((U32(v) & 0x3U) << 28U)
#define gr_fecs_current_ctx_target_m() (U32(0x3U) << 28U) #define gr_fecs_current_ctx_target_m() (U32(0x3U) << 28U)
#define gr_fecs_current_ctx_target_v(r) (((r) >> 28U) & 0x3U) #define gr_fecs_current_ctx_target_v(r) (((r) >> 28U) & 0x3U)
#define gr_fecs_current_ctx_target_vid_mem_f() (0x0U) #define gr_fecs_current_ctx_target_vid_mem_f() (0x0U)
#define gr_fecs_current_ctx_target_sys_mem_coh_f() (0x20000000U) #define gr_fecs_current_ctx_target_sys_mem_coh_f() (0x20000000U)
#define gr_fecs_current_ctx_target_sys_mem_ncoh_f() (0x30000000U) #define gr_fecs_current_ctx_target_sys_mem_ncoh_f() (0x30000000U)
#define gr_fecs_current_ctx_valid_s() (1U) #define gr_fecs_current_ctx_valid_s() (1U)
#define gr_fecs_current_ctx_valid_f(v) (((v)&0x1U) << 31U) #define gr_fecs_current_ctx_valid_f(v) ((U32(v) & 0x1U) << 31U)
#define gr_fecs_current_ctx_valid_m() (U32(0x1U) << 31U) #define gr_fecs_current_ctx_valid_m() (U32(0x1U) << 31U)
#define gr_fecs_current_ctx_valid_v(r) (((r) >> 31U) & 0x1U) #define gr_fecs_current_ctx_valid_v(r) (((r) >> 31U) & 0x1U)
#define gr_fecs_current_ctx_valid_false_f() (0x0U) #define gr_fecs_current_ctx_valid_false_f() (0x0U)
#define gr_fecs_method_data_r() (0x00409500U) #define gr_fecs_method_data_r() (0x00409500U)
#define gr_fecs_method_push_r() (0x00409504U) #define gr_fecs_method_push_r() (0x00409504U)
#define gr_fecs_method_push_adr_f(v) (((v)&0xfffU) << 0U) #define gr_fecs_method_push_adr_f(v) ((U32(v) & 0xfffU) << 0U)
#define gr_fecs_method_push_adr_bind_pointer_v() (0x00000003U) #define gr_fecs_method_push_adr_bind_pointer_v() (0x00000003U)
#define gr_fecs_method_push_adr_bind_pointer_f() (0x3U) #define gr_fecs_method_push_adr_bind_pointer_f() (0x3U)
#define gr_fecs_method_push_adr_discover_image_size_v() (0x00000010U) #define gr_fecs_method_push_adr_discover_image_size_v() (0x00000010U)
@@ -358,9 +358,11 @@
#define gr_fecs_method_push_adr_discover_preemption_image_size_v() (0x0000001aU) #define gr_fecs_method_push_adr_discover_preemption_image_size_v() (0x0000001aU)
#define gr_fecs_method_push_adr_halt_pipeline_v() (0x00000004U) #define gr_fecs_method_push_adr_halt_pipeline_v() (0x00000004U)
#define gr_fecs_host_int_status_r() (0x00409c18U) #define gr_fecs_host_int_status_r() (0x00409c18U)
#define gr_fecs_host_int_status_fault_during_ctxsw_f(v) (((v)&0x1U) << 16U) #define gr_fecs_host_int_status_fault_during_ctxsw_f(v) ((U32(v) & 0x1U) << 16U)
#define gr_fecs_host_int_status_umimp_firmware_method_f(v) (((v)&0x1U) << 17U) #define gr_fecs_host_int_status_umimp_firmware_method_f(v)\
#define gr_fecs_host_int_status_umimp_illegal_method_f(v) (((v)&0x1U) << 18U) ((U32(v) & 0x1U) << 17U)
#define gr_fecs_host_int_status_umimp_illegal_method_f(v)\
((U32(v) & 0x1U) << 18U)
#define gr_fecs_host_int_clear_r() (0x00409c20U) #define gr_fecs_host_int_clear_r() (0x00409c20U)
#define gr_fecs_host_int_enable_r() (0x00409c24U) #define gr_fecs_host_int_enable_r() (0x00409c24U)
#define gr_fecs_host_int_enable_fault_during_ctxsw_enable_f() (0x10000U) #define gr_fecs_host_int_enable_fault_during_ctxsw_enable_f() (0x10000U)
@@ -379,7 +381,7 @@
#define gr_fecs_ctxsw_reset_ctl_gpc_context_reset_enabled_f() (0x0U) #define gr_fecs_ctxsw_reset_ctl_gpc_context_reset_enabled_f() (0x0U)
#define gr_fecs_ctxsw_reset_ctl_gpc_context_reset_disabled_f() (0x200U) #define gr_fecs_ctxsw_reset_ctl_gpc_context_reset_disabled_f() (0x200U)
#define gr_fecs_ctxsw_reset_ctl_be_context_reset_s() (1U) #define gr_fecs_ctxsw_reset_ctl_be_context_reset_s() (1U)
#define gr_fecs_ctxsw_reset_ctl_be_context_reset_f(v) (((v)&0x1U) << 10U) #define gr_fecs_ctxsw_reset_ctl_be_context_reset_f(v) ((U32(v) & 0x1U) << 10U)
#define gr_fecs_ctxsw_reset_ctl_be_context_reset_m() (U32(0x1U) << 10U) #define gr_fecs_ctxsw_reset_ctl_be_context_reset_m() (U32(0x1U) << 10U)
#define gr_fecs_ctxsw_reset_ctl_be_context_reset_v(r) (((r) >> 10U) & 0x1U) #define gr_fecs_ctxsw_reset_ctl_be_context_reset_v(r) (((r) >> 10U) & 0x1U)
#define gr_fecs_ctxsw_reset_ctl_be_context_reset_enabled_f() (0x0U) #define gr_fecs_ctxsw_reset_ctl_be_context_reset_enabled_f() (0x0U)
@@ -388,60 +390,60 @@
#define gr_fecs_ctxsw_mailbox_r(i)\ #define gr_fecs_ctxsw_mailbox_r(i)\
(nvgpu_safe_add_u32(0x00409800U, nvgpu_safe_mult_u32((i), 4U))) (nvgpu_safe_add_u32(0x00409800U, nvgpu_safe_mult_u32((i), 4U)))
#define gr_fecs_ctxsw_mailbox__size_1_v() (0x00000010U) #define gr_fecs_ctxsw_mailbox__size_1_v() (0x00000010U)
#define gr_fecs_ctxsw_mailbox_value_f(v) (((v)&0xffffffffU) << 0U) #define gr_fecs_ctxsw_mailbox_value_f(v) ((U32(v) & 0xffffffffU) << 0U)
#define gr_fecs_ctxsw_mailbox_value_pass_v() (0x00000001U) #define gr_fecs_ctxsw_mailbox_value_pass_v() (0x00000001U)
#define gr_fecs_ctxsw_mailbox_value_fail_v() (0x00000002U) #define gr_fecs_ctxsw_mailbox_value_fail_v() (0x00000002U)
#define gr_fecs_ctxsw_mailbox_set_r(i)\ #define gr_fecs_ctxsw_mailbox_set_r(i)\
(nvgpu_safe_add_u32(0x004098c0U, nvgpu_safe_mult_u32((i), 4U))) (nvgpu_safe_add_u32(0x004098c0U, nvgpu_safe_mult_u32((i), 4U)))
#define gr_fecs_ctxsw_mailbox_set_value_f(v) (((v)&0xffffffffU) << 0U) #define gr_fecs_ctxsw_mailbox_set_value_f(v) ((U32(v) & 0xffffffffU) << 0U)
#define gr_fecs_ctxsw_mailbox_clear_r(i)\ #define gr_fecs_ctxsw_mailbox_clear_r(i)\
(nvgpu_safe_add_u32(0x00409840U, nvgpu_safe_mult_u32((i), 4U))) (nvgpu_safe_add_u32(0x00409840U, nvgpu_safe_mult_u32((i), 4U)))
#define gr_fecs_ctxsw_mailbox_clear_value_f(v) (((v)&0xffffffffU) << 0U) #define gr_fecs_ctxsw_mailbox_clear_value_f(v) ((U32(v) & 0xffffffffU) << 0U)
#define gr_fecs_fs_r() (0x00409604U) #define gr_fecs_fs_r() (0x00409604U)
#define gr_fecs_fs_num_available_gpcs_s() (5U) #define gr_fecs_fs_num_available_gpcs_s() (5U)
#define gr_fecs_fs_num_available_gpcs_f(v) (((v)&0x1fU) << 0U) #define gr_fecs_fs_num_available_gpcs_f(v) ((U32(v) & 0x1fU) << 0U)
#define gr_fecs_fs_num_available_gpcs_m() (U32(0x1fU) << 0U) #define gr_fecs_fs_num_available_gpcs_m() (U32(0x1fU) << 0U)
#define gr_fecs_fs_num_available_gpcs_v(r) (((r) >> 0U) & 0x1fU) #define gr_fecs_fs_num_available_gpcs_v(r) (((r) >> 0U) & 0x1fU)
#define gr_fecs_fs_num_available_fbps_s() (5U) #define gr_fecs_fs_num_available_fbps_s() (5U)
#define gr_fecs_fs_num_available_fbps_f(v) (((v)&0x1fU) << 16U) #define gr_fecs_fs_num_available_fbps_f(v) ((U32(v) & 0x1fU) << 16U)
#define gr_fecs_fs_num_available_fbps_m() (U32(0x1fU) << 16U) #define gr_fecs_fs_num_available_fbps_m() (U32(0x1fU) << 16U)
#define gr_fecs_fs_num_available_fbps_v(r) (((r) >> 16U) & 0x1fU) #define gr_fecs_fs_num_available_fbps_v(r) (((r) >> 16U) & 0x1fU)
#define gr_fecs_cfg_r() (0x00409620U) #define gr_fecs_cfg_r() (0x00409620U)
#define gr_fecs_cfg_imem_sz_v(r) (((r) >> 0U) & 0xffU) #define gr_fecs_cfg_imem_sz_v(r) (((r) >> 0U) & 0xffU)
#define gr_fecs_rc_lanes_r() (0x00409880U) #define gr_fecs_rc_lanes_r() (0x00409880U)
#define gr_fecs_rc_lanes_num_chains_s() (6U) #define gr_fecs_rc_lanes_num_chains_s() (6U)
#define gr_fecs_rc_lanes_num_chains_f(v) (((v)&0x3fU) << 0U) #define gr_fecs_rc_lanes_num_chains_f(v) ((U32(v) & 0x3fU) << 0U)
#define gr_fecs_rc_lanes_num_chains_m() (U32(0x3fU) << 0U) #define gr_fecs_rc_lanes_num_chains_m() (U32(0x3fU) << 0U)
#define gr_fecs_rc_lanes_num_chains_v(r) (((r) >> 0U) & 0x3fU) #define gr_fecs_rc_lanes_num_chains_v(r) (((r) >> 0U) & 0x3fU)
#define gr_fecs_ctxsw_status_1_r() (0x00409400U) #define gr_fecs_ctxsw_status_1_r() (0x00409400U)
#define gr_fecs_ctxsw_status_1_arb_busy_s() (1U) #define gr_fecs_ctxsw_status_1_arb_busy_s() (1U)
#define gr_fecs_ctxsw_status_1_arb_busy_f(v) (((v)&0x1U) << 12U) #define gr_fecs_ctxsw_status_1_arb_busy_f(v) ((U32(v) & 0x1U) << 12U)
#define gr_fecs_ctxsw_status_1_arb_busy_m() (U32(0x1U) << 12U) #define gr_fecs_ctxsw_status_1_arb_busy_m() (U32(0x1U) << 12U)
#define gr_fecs_ctxsw_status_1_arb_busy_v(r) (((r) >> 12U) & 0x1U) #define gr_fecs_ctxsw_status_1_arb_busy_v(r) (((r) >> 12U) & 0x1U)
#define gr_fecs_arb_ctx_adr_r() (0x00409a24U) #define gr_fecs_arb_ctx_adr_r() (0x00409a24U)
#define gr_fecs_new_ctx_r() (0x00409b04U) #define gr_fecs_new_ctx_r() (0x00409b04U)
#define gr_fecs_new_ctx_ptr_s() (28U) #define gr_fecs_new_ctx_ptr_s() (28U)
#define gr_fecs_new_ctx_ptr_f(v) (((v)&0xfffffffU) << 0U) #define gr_fecs_new_ctx_ptr_f(v) ((U32(v) & 0xfffffffU) << 0U)
#define gr_fecs_new_ctx_ptr_m() (U32(0xfffffffU) << 0U) #define gr_fecs_new_ctx_ptr_m() (U32(0xfffffffU) << 0U)
#define gr_fecs_new_ctx_ptr_v(r) (((r) >> 0U) & 0xfffffffU) #define gr_fecs_new_ctx_ptr_v(r) (((r) >> 0U) & 0xfffffffU)
#define gr_fecs_new_ctx_target_s() (2U) #define gr_fecs_new_ctx_target_s() (2U)
#define gr_fecs_new_ctx_target_f(v) (((v)&0x3U) << 28U) #define gr_fecs_new_ctx_target_f(v) ((U32(v) & 0x3U) << 28U)
#define gr_fecs_new_ctx_target_m() (U32(0x3U) << 28U) #define gr_fecs_new_ctx_target_m() (U32(0x3U) << 28U)
#define gr_fecs_new_ctx_target_v(r) (((r) >> 28U) & 0x3U) #define gr_fecs_new_ctx_target_v(r) (((r) >> 28U) & 0x3U)
#define gr_fecs_new_ctx_target_vid_mem_f() (0x0U) #define gr_fecs_new_ctx_target_vid_mem_f() (0x0U)
#define gr_fecs_new_ctx_target_sys_mem_ncoh_f() (0x30000000U) #define gr_fecs_new_ctx_target_sys_mem_ncoh_f() (0x30000000U)
#define gr_fecs_new_ctx_target_sys_mem_coh_f() (0x20000000U) #define gr_fecs_new_ctx_target_sys_mem_coh_f() (0x20000000U)
#define gr_fecs_new_ctx_valid_s() (1U) #define gr_fecs_new_ctx_valid_s() (1U)
#define gr_fecs_new_ctx_valid_f(v) (((v)&0x1U) << 31U) #define gr_fecs_new_ctx_valid_f(v) ((U32(v) & 0x1U) << 31U)
#define gr_fecs_new_ctx_valid_m() (U32(0x1U) << 31U) #define gr_fecs_new_ctx_valid_m() (U32(0x1U) << 31U)
#define gr_fecs_new_ctx_valid_v(r) (((r) >> 31U) & 0x1U) #define gr_fecs_new_ctx_valid_v(r) (((r) >> 31U) & 0x1U)
#define gr_fecs_arb_ctx_ptr_r() (0x00409a0cU) #define gr_fecs_arb_ctx_ptr_r() (0x00409a0cU)
#define gr_fecs_arb_ctx_ptr_ptr_s() (28U) #define gr_fecs_arb_ctx_ptr_ptr_s() (28U)
#define gr_fecs_arb_ctx_ptr_ptr_f(v) (((v)&0xfffffffU) << 0U) #define gr_fecs_arb_ctx_ptr_ptr_f(v) ((U32(v) & 0xfffffffU) << 0U)
#define gr_fecs_arb_ctx_ptr_ptr_m() (U32(0xfffffffU) << 0U) #define gr_fecs_arb_ctx_ptr_ptr_m() (U32(0xfffffffU) << 0U)
#define gr_fecs_arb_ctx_ptr_ptr_v(r) (((r) >> 0U) & 0xfffffffU) #define gr_fecs_arb_ctx_ptr_ptr_v(r) (((r) >> 0U) & 0xfffffffU)
#define gr_fecs_arb_ctx_ptr_target_s() (2U) #define gr_fecs_arb_ctx_ptr_target_s() (2U)
#define gr_fecs_arb_ctx_ptr_target_f(v) (((v)&0x3U) << 28U) #define gr_fecs_arb_ctx_ptr_target_f(v) ((U32(v) & 0x3U) << 28U)
#define gr_fecs_arb_ctx_ptr_target_m() (U32(0x3U) << 28U) #define gr_fecs_arb_ctx_ptr_target_m() (U32(0x3U) << 28U)
#define gr_fecs_arb_ctx_ptr_target_v(r) (((r) >> 28U) & 0x3U) #define gr_fecs_arb_ctx_ptr_target_v(r) (((r) >> 28U) & 0x3U)
#define gr_fecs_arb_ctx_ptr_target_vid_mem_f() (0x0U) #define gr_fecs_arb_ctx_ptr_target_vid_mem_f() (0x0U)
@@ -449,7 +451,7 @@
#define gr_fecs_arb_ctx_ptr_target_sys_mem_coh_f() (0x20000000U) #define gr_fecs_arb_ctx_ptr_target_sys_mem_coh_f() (0x20000000U)
#define gr_fecs_arb_ctx_cmd_r() (0x00409a10U) #define gr_fecs_arb_ctx_cmd_r() (0x00409a10U)
#define gr_fecs_arb_ctx_cmd_cmd_s() (5U) #define gr_fecs_arb_ctx_cmd_cmd_s() (5U)
#define gr_fecs_arb_ctx_cmd_cmd_f(v) (((v)&0x1fU) << 0U) #define gr_fecs_arb_ctx_cmd_cmd_f(v) ((U32(v) & 0x1fU) << 0U)
#define gr_fecs_arb_ctx_cmd_cmd_m() (U32(0x1fU) << 0U) #define gr_fecs_arb_ctx_cmd_cmd_m() (U32(0x1fU) << 0U)
#define gr_fecs_arb_ctx_cmd_cmd_v(r) (((r) >> 0U) & 0x1fU) #define gr_fecs_arb_ctx_cmd_cmd_v(r) (((r) >> 0U) & 0x1fU)
#define gr_fecs_ctxsw_status_fe_0_r() (0x00409c00U) #define gr_fecs_ctxsw_status_fe_0_r() (0x00409c00U)
@@ -465,55 +467,55 @@
#define gr_rstr2d_gpc_map4_r() (0x0040781cU) #define gr_rstr2d_gpc_map4_r() (0x0040781cU)
#define gr_rstr2d_gpc_map5_r() (0x00407820U) #define gr_rstr2d_gpc_map5_r() (0x00407820U)
#define gr_rstr2d_map_table_cfg_r() (0x004078bcU) #define gr_rstr2d_map_table_cfg_r() (0x004078bcU)
#define gr_rstr2d_map_table_cfg_row_offset_f(v) (((v)&0xffU) << 0U) #define gr_rstr2d_map_table_cfg_row_offset_f(v) ((U32(v) & 0xffU) << 0U)
#define gr_rstr2d_map_table_cfg_num_entries_f(v) (((v)&0xffU) << 8U) #define gr_rstr2d_map_table_cfg_num_entries_f(v) ((U32(v) & 0xffU) << 8U)
#define gr_pd_hww_esr_r() (0x00406018U) #define gr_pd_hww_esr_r() (0x00406018U)
#define gr_pd_hww_esr_reset_active_f() (0x40000000U) #define gr_pd_hww_esr_reset_active_f() (0x40000000U)
#define gr_pd_hww_esr_en_enable_f() (0x80000000U) #define gr_pd_hww_esr_en_enable_f() (0x80000000U)
#define gr_pd_num_tpc_per_gpc_r(i)\ #define gr_pd_num_tpc_per_gpc_r(i)\
(nvgpu_safe_add_u32(0x00406028U, nvgpu_safe_mult_u32((i), 4U))) (nvgpu_safe_add_u32(0x00406028U, nvgpu_safe_mult_u32((i), 4U)))
#define gr_pd_num_tpc_per_gpc__size_1_v() (0x00000004U) #define gr_pd_num_tpc_per_gpc__size_1_v() (0x00000004U)
#define gr_pd_num_tpc_per_gpc_count0_f(v) (((v)&0xfU) << 0U) #define gr_pd_num_tpc_per_gpc_count0_f(v) ((U32(v) & 0xfU) << 0U)
#define gr_pd_num_tpc_per_gpc_count1_f(v) (((v)&0xfU) << 4U) #define gr_pd_num_tpc_per_gpc_count1_f(v) ((U32(v) & 0xfU) << 4U)
#define gr_pd_num_tpc_per_gpc_count2_f(v) (((v)&0xfU) << 8U) #define gr_pd_num_tpc_per_gpc_count2_f(v) ((U32(v) & 0xfU) << 8U)
#define gr_pd_num_tpc_per_gpc_count3_f(v) (((v)&0xfU) << 12U) #define gr_pd_num_tpc_per_gpc_count3_f(v) ((U32(v) & 0xfU) << 12U)
#define gr_pd_num_tpc_per_gpc_count4_f(v) (((v)&0xfU) << 16U) #define gr_pd_num_tpc_per_gpc_count4_f(v) ((U32(v) & 0xfU) << 16U)
#define gr_pd_num_tpc_per_gpc_count5_f(v) (((v)&0xfU) << 20U) #define gr_pd_num_tpc_per_gpc_count5_f(v) ((U32(v) & 0xfU) << 20U)
#define gr_pd_num_tpc_per_gpc_count6_f(v) (((v)&0xfU) << 24U) #define gr_pd_num_tpc_per_gpc_count6_f(v) ((U32(v) & 0xfU) << 24U)
#define gr_pd_num_tpc_per_gpc_count7_f(v) (((v)&0xfU) << 28U) #define gr_pd_num_tpc_per_gpc_count7_f(v) ((U32(v) & 0xfU) << 28U)
#define gr_pd_ab_dist_cfg0_r() (0x004064c0U) #define gr_pd_ab_dist_cfg0_r() (0x004064c0U)
#define gr_pd_ab_dist_cfg0_timeslice_enable_en_f() (0x80000000U) #define gr_pd_ab_dist_cfg0_timeslice_enable_en_f() (0x80000000U)
#define gr_pd_ab_dist_cfg0_timeslice_enable_dis_f() (0x0U) #define gr_pd_ab_dist_cfg0_timeslice_enable_dis_f() (0x0U)
#define gr_pd_ab_dist_cfg1_r() (0x004064c4U) #define gr_pd_ab_dist_cfg1_r() (0x004064c4U)
#define gr_pd_ab_dist_cfg1_max_batches_init_f() (0xffffU) #define gr_pd_ab_dist_cfg1_max_batches_init_f() (0xffffU)
#define gr_pd_ab_dist_cfg1_max_output_f(v) (((v)&0xffffU) << 16U) #define gr_pd_ab_dist_cfg1_max_output_f(v) ((U32(v) & 0xffffU) << 16U)
#define gr_pd_ab_dist_cfg1_max_output_granularity_v() (0x00000080U) #define gr_pd_ab_dist_cfg1_max_output_granularity_v() (0x00000080U)
#define gr_pd_ab_dist_cfg2_r() (0x004064c8U) #define gr_pd_ab_dist_cfg2_r() (0x004064c8U)
#define gr_pd_ab_dist_cfg2_token_limit_f(v) (((v)&0x1fffU) << 0U) #define gr_pd_ab_dist_cfg2_token_limit_f(v) ((U32(v) & 0x1fffU) << 0U)
#define gr_pd_ab_dist_cfg2_token_limit_init_v() (0x00000900U) #define gr_pd_ab_dist_cfg2_token_limit_init_v() (0x00000900U)
#define gr_pd_ab_dist_cfg2_state_limit_f(v) (((v)&0x1fffU) << 16U) #define gr_pd_ab_dist_cfg2_state_limit_f(v) ((U32(v) & 0x1fffU) << 16U)
#define gr_pd_ab_dist_cfg2_state_limit_scc_bundle_granularity_v() (0x00000020U) #define gr_pd_ab_dist_cfg2_state_limit_scc_bundle_granularity_v() (0x00000020U)
#define gr_pd_ab_dist_cfg2_state_limit_min_gpm_fifo_depths_v() (0x00000900U) #define gr_pd_ab_dist_cfg2_state_limit_min_gpm_fifo_depths_v() (0x00000900U)
#define gr_pd_dist_skip_table_r(i)\ #define gr_pd_dist_skip_table_r(i)\
(nvgpu_safe_add_u32(0x004064d0U, nvgpu_safe_mult_u32((i), 4U))) (nvgpu_safe_add_u32(0x004064d0U, nvgpu_safe_mult_u32((i), 4U)))
#define gr_pd_dist_skip_table__size_1_v() (0x00000008U) #define gr_pd_dist_skip_table__size_1_v() (0x00000008U)
#define gr_pd_dist_skip_table_gpc_4n0_mask_f(v) (((v)&0xffU) << 0U) #define gr_pd_dist_skip_table_gpc_4n0_mask_f(v) ((U32(v) & 0xffU) << 0U)
#define gr_pd_dist_skip_table_gpc_4n1_mask_f(v) (((v)&0xffU) << 8U) #define gr_pd_dist_skip_table_gpc_4n1_mask_f(v) ((U32(v) & 0xffU) << 8U)
#define gr_pd_dist_skip_table_gpc_4n2_mask_f(v) (((v)&0xffU) << 16U) #define gr_pd_dist_skip_table_gpc_4n2_mask_f(v) ((U32(v) & 0xffU) << 16U)
#define gr_pd_dist_skip_table_gpc_4n3_mask_f(v) (((v)&0xffU) << 24U) #define gr_pd_dist_skip_table_gpc_4n3_mask_f(v) ((U32(v) & 0xffU) << 24U)
#define gr_ds_debug_r() (0x00405800U) #define gr_ds_debug_r() (0x00405800U)
#define gr_ds_debug_timeslice_mode_disable_f() (0x0U) #define gr_ds_debug_timeslice_mode_disable_f() (0x0U)
#define gr_ds_debug_timeslice_mode_enable_f() (0x8000000U) #define gr_ds_debug_timeslice_mode_enable_f() (0x8000000U)
#define gr_ds_zbc_color_r_r() (0x00405804U) #define gr_ds_zbc_color_r_r() (0x00405804U)
#define gr_ds_zbc_color_r_val_f(v) (((v)&0xffffffffU) << 0U) #define gr_ds_zbc_color_r_val_f(v) ((U32(v) & 0xffffffffU) << 0U)
#define gr_ds_zbc_color_g_r() (0x00405808U) #define gr_ds_zbc_color_g_r() (0x00405808U)
#define gr_ds_zbc_color_g_val_f(v) (((v)&0xffffffffU) << 0U) #define gr_ds_zbc_color_g_val_f(v) ((U32(v) & 0xffffffffU) << 0U)
#define gr_ds_zbc_color_b_r() (0x0040580cU) #define gr_ds_zbc_color_b_r() (0x0040580cU)
#define gr_ds_zbc_color_b_val_f(v) (((v)&0xffffffffU) << 0U) #define gr_ds_zbc_color_b_val_f(v) ((U32(v) & 0xffffffffU) << 0U)
#define gr_ds_zbc_color_a_r() (0x00405810U) #define gr_ds_zbc_color_a_r() (0x00405810U)
#define gr_ds_zbc_color_a_val_f(v) (((v)&0xffffffffU) << 0U) #define gr_ds_zbc_color_a_val_f(v) ((U32(v) & 0xffffffffU) << 0U)
#define gr_ds_zbc_color_fmt_r() (0x00405814U) #define gr_ds_zbc_color_fmt_r() (0x00405814U)
#define gr_ds_zbc_color_fmt_val_f(v) (((v)&0x7fU) << 0U) #define gr_ds_zbc_color_fmt_val_f(v) ((U32(v) & 0x7fU) << 0U)
#define gr_ds_zbc_color_fmt_val_invalid_f() (0x0U) #define gr_ds_zbc_color_fmt_val_invalid_f() (0x0U)
#define gr_ds_zbc_color_fmt_val_zero_v() (0x00000001U) #define gr_ds_zbc_color_fmt_val_zero_v() (0x00000001U)
#define gr_ds_zbc_color_fmt_val_unorm_one_v() (0x00000002U) #define gr_ds_zbc_color_fmt_val_unorm_one_v() (0x00000002U)
@@ -521,29 +523,29 @@
#define gr_ds_zbc_color_fmt_val_a8_b8_g8_r8_v() (0x00000028U) #define gr_ds_zbc_color_fmt_val_a8_b8_g8_r8_v() (0x00000028U)
#define gr_ds_zbc_z_r() (0x00405818U) #define gr_ds_zbc_z_r() (0x00405818U)
#define gr_ds_zbc_z_val_s() (32U) #define gr_ds_zbc_z_val_s() (32U)
#define gr_ds_zbc_z_val_f(v) (((v)&0xffffffffU) << 0U) #define gr_ds_zbc_z_val_f(v) ((U32(v) & 0xffffffffU) << 0U)
#define gr_ds_zbc_z_val_m() (U32(0xffffffffU) << 0U) #define gr_ds_zbc_z_val_m() (U32(0xffffffffU) << 0U)
#define gr_ds_zbc_z_val_v(r) (((r) >> 0U) & 0xffffffffU) #define gr_ds_zbc_z_val_v(r) (((r) >> 0U) & 0xffffffffU)
#define gr_ds_zbc_z_val__init_v() (0x00000000U) #define gr_ds_zbc_z_val__init_v() (0x00000000U)
#define gr_ds_zbc_z_val__init_f() (0x0U) #define gr_ds_zbc_z_val__init_f() (0x0U)
#define gr_ds_zbc_z_fmt_r() (0x0040581cU) #define gr_ds_zbc_z_fmt_r() (0x0040581cU)
#define gr_ds_zbc_z_fmt_val_f(v) (((v)&0x1U) << 0U) #define gr_ds_zbc_z_fmt_val_f(v) ((U32(v) & 0x1U) << 0U)
#define gr_ds_zbc_z_fmt_val_invalid_f() (0x0U) #define gr_ds_zbc_z_fmt_val_invalid_f() (0x0U)
#define gr_ds_zbc_z_fmt_val_fp32_v() (0x00000001U) #define gr_ds_zbc_z_fmt_val_fp32_v() (0x00000001U)
#define gr_ds_zbc_tbl_index_r() (0x00405820U) #define gr_ds_zbc_tbl_index_r() (0x00405820U)
#define gr_ds_zbc_tbl_index_val_f(v) (((v)&0xfU) << 0U) #define gr_ds_zbc_tbl_index_val_f(v) ((U32(v) & 0xfU) << 0U)
#define gr_ds_zbc_tbl_ld_r() (0x00405824U) #define gr_ds_zbc_tbl_ld_r() (0x00405824U)
#define gr_ds_zbc_tbl_ld_select_c_f() (0x0U) #define gr_ds_zbc_tbl_ld_select_c_f() (0x0U)
#define gr_ds_zbc_tbl_ld_select_z_f() (0x1U) #define gr_ds_zbc_tbl_ld_select_z_f() (0x1U)
#define gr_ds_zbc_tbl_ld_action_write_f() (0x0U) #define gr_ds_zbc_tbl_ld_action_write_f() (0x0U)
#define gr_ds_zbc_tbl_ld_trigger_active_f() (0x4U) #define gr_ds_zbc_tbl_ld_trigger_active_f() (0x4U)
#define gr_ds_tga_constraintlogic_beta_r() (0x00405830U) #define gr_ds_tga_constraintlogic_beta_r() (0x00405830U)
#define gr_ds_tga_constraintlogic_beta_cbsize_f(v) (((v)&0x3fffffU) << 0U) #define gr_ds_tga_constraintlogic_beta_cbsize_f(v) ((U32(v) & 0x3fffffU) << 0U)
#define gr_ds_tga_constraintlogic_alpha_r() (0x0040585cU) #define gr_ds_tga_constraintlogic_alpha_r() (0x0040585cU)
#define gr_ds_tga_constraintlogic_alpha_cbsize_f(v) (((v)&0xffffU) << 0U) #define gr_ds_tga_constraintlogic_alpha_cbsize_f(v) ((U32(v) & 0xffffU) << 0U)
#define gr_ds_hww_esr_r() (0x00405840U) #define gr_ds_hww_esr_r() (0x00405840U)
#define gr_ds_hww_esr_reset_s() (1U) #define gr_ds_hww_esr_reset_s() (1U)
#define gr_ds_hww_esr_reset_f(v) (((v)&0x1U) << 30U) #define gr_ds_hww_esr_reset_f(v) ((U32(v) & 0x1U) << 30U)
#define gr_ds_hww_esr_reset_m() (U32(0x1U) << 30U) #define gr_ds_hww_esr_reset_m() (U32(0x1U) << 30U)
#define gr_ds_hww_esr_reset_v(r) (((r) >> 30U) & 0x1U) #define gr_ds_hww_esr_reset_v(r) (((r) >> 30U) & 0x1U)
#define gr_ds_hww_esr_reset_task_v() (0x00000001U) #define gr_ds_hww_esr_reset_task_v() (0x00000001U)
@@ -551,7 +553,7 @@
#define gr_ds_hww_esr_en_enabled_f() (0x80000000U) #define gr_ds_hww_esr_en_enabled_f() (0x80000000U)
#define gr_ds_hww_esr_2_r() (0x00405848U) #define gr_ds_hww_esr_2_r() (0x00405848U)
#define gr_ds_hww_esr_2_reset_s() (1U) #define gr_ds_hww_esr_2_reset_s() (1U)
#define gr_ds_hww_esr_2_reset_f(v) (((v)&0x1U) << 30U) #define gr_ds_hww_esr_2_reset_f(v) ((U32(v) & 0x1U) << 30U)
#define gr_ds_hww_esr_2_reset_m() (U32(0x1U) << 30U) #define gr_ds_hww_esr_2_reset_m() (U32(0x1U) << 30U)
#define gr_ds_hww_esr_2_reset_v(r) (((r) >> 30U) & 0x1U) #define gr_ds_hww_esr_2_reset_v(r) (((r) >> 30U) & 0x1U)
#define gr_ds_hww_esr_2_reset_task_v() (0x00000001U) #define gr_ds_hww_esr_2_reset_task_v() (0x00000001U)
@@ -587,25 +589,25 @@
#define gr_ds_num_tpc_per_gpc_r(i)\ #define gr_ds_num_tpc_per_gpc_r(i)\
(nvgpu_safe_add_u32(0x00405870U, nvgpu_safe_mult_u32((i), 4U))) (nvgpu_safe_add_u32(0x00405870U, nvgpu_safe_mult_u32((i), 4U)))
#define gr_scc_bundle_cb_base_r() (0x00408004U) #define gr_scc_bundle_cb_base_r() (0x00408004U)
#define gr_scc_bundle_cb_base_addr_39_8_f(v) (((v)&0xffffffffU) << 0U) #define gr_scc_bundle_cb_base_addr_39_8_f(v) ((U32(v) & 0xffffffffU) << 0U)
#define gr_scc_bundle_cb_base_addr_39_8_align_bits_v() (0x00000008U) #define gr_scc_bundle_cb_base_addr_39_8_align_bits_v() (0x00000008U)
#define gr_scc_bundle_cb_size_r() (0x00408008U) #define gr_scc_bundle_cb_size_r() (0x00408008U)
#define gr_scc_bundle_cb_size_div_256b_f(v) (((v)&0x7ffU) << 0U) #define gr_scc_bundle_cb_size_div_256b_f(v) ((U32(v) & 0x7ffU) << 0U)
#define gr_scc_bundle_cb_size_div_256b__prod_v() (0x00000030U) #define gr_scc_bundle_cb_size_div_256b__prod_v() (0x00000030U)
#define gr_scc_bundle_cb_size_div_256b_byte_granularity_v() (0x00000100U) #define gr_scc_bundle_cb_size_div_256b_byte_granularity_v() (0x00000100U)
#define gr_scc_bundle_cb_size_valid_false_v() (0x00000000U) #define gr_scc_bundle_cb_size_valid_false_v() (0x00000000U)
#define gr_scc_bundle_cb_size_valid_false_f() (0x0U) #define gr_scc_bundle_cb_size_valid_false_f() (0x0U)
#define gr_scc_bundle_cb_size_valid_true_f() (0x80000000U) #define gr_scc_bundle_cb_size_valid_true_f() (0x80000000U)
#define gr_scc_pagepool_base_r() (0x0040800cU) #define gr_scc_pagepool_base_r() (0x0040800cU)
#define gr_scc_pagepool_base_addr_39_8_f(v) (((v)&0xffffffffU) << 0U) #define gr_scc_pagepool_base_addr_39_8_f(v) ((U32(v) & 0xffffffffU) << 0U)
#define gr_scc_pagepool_base_addr_39_8_align_bits_v() (0x00000008U) #define gr_scc_pagepool_base_addr_39_8_align_bits_v() (0x00000008U)
#define gr_scc_pagepool_r() (0x00408010U) #define gr_scc_pagepool_r() (0x00408010U)
#define gr_scc_pagepool_total_pages_f(v) (((v)&0x3ffU) << 0U) #define gr_scc_pagepool_total_pages_f(v) ((U32(v) & 0x3ffU) << 0U)
#define gr_scc_pagepool_total_pages_hwmax_v() (0x00000000U) #define gr_scc_pagepool_total_pages_hwmax_v() (0x00000000U)
#define gr_scc_pagepool_total_pages_hwmax_value_v() (0x00000200U) #define gr_scc_pagepool_total_pages_hwmax_value_v() (0x00000200U)
#define gr_scc_pagepool_total_pages_byte_granularity_v() (0x00000100U) #define gr_scc_pagepool_total_pages_byte_granularity_v() (0x00000100U)
#define gr_scc_pagepool_max_valid_pages_s() (10U) #define gr_scc_pagepool_max_valid_pages_s() (10U)
#define gr_scc_pagepool_max_valid_pages_f(v) (((v)&0x3ffU) << 10U) #define gr_scc_pagepool_max_valid_pages_f(v) ((U32(v) & 0x3ffU) << 10U)
#define gr_scc_pagepool_max_valid_pages_m() (U32(0x3ffU) << 10U) #define gr_scc_pagepool_max_valid_pages_m() (U32(0x3ffU) << 10U)
#define gr_scc_pagepool_max_valid_pages_v(r) (((r) >> 10U) & 0x3ffU) #define gr_scc_pagepool_max_valid_pages_v(r) (((r) >> 10U) & 0x3ffU)
#define gr_scc_pagepool_valid_true_f() (0x80000000U) #define gr_scc_pagepool_valid_true_f() (0x80000000U)
@@ -615,20 +617,20 @@
#define gr_sked_hww_esr_r() (0x00407020U) #define gr_sked_hww_esr_r() (0x00407020U)
#define gr_sked_hww_esr_reset_active_f() (0x40000000U) #define gr_sked_hww_esr_reset_active_f() (0x40000000U)
#define gr_cwd_fs_r() (0x00405b00U) #define gr_cwd_fs_r() (0x00405b00U)
#define gr_cwd_fs_num_gpcs_f(v) (((v)&0xffU) << 0U) #define gr_cwd_fs_num_gpcs_f(v) ((U32(v) & 0xffU) << 0U)
#define gr_cwd_fs_num_tpcs_f(v) (((v)&0xffU) << 8U) #define gr_cwd_fs_num_tpcs_f(v) ((U32(v) & 0xffU) << 8U)
#define gr_cwd_gpc_tpc_id_r(i)\ #define gr_cwd_gpc_tpc_id_r(i)\
(nvgpu_safe_add_u32(0x00405b60U, nvgpu_safe_mult_u32((i), 4U))) (nvgpu_safe_add_u32(0x00405b60U, nvgpu_safe_mult_u32((i), 4U)))
#define gr_cwd_gpc_tpc_id_tpc0_s() (4U) #define gr_cwd_gpc_tpc_id_tpc0_s() (4U)
#define gr_cwd_gpc_tpc_id_tpc0_f(v) (((v)&0xfU) << 0U) #define gr_cwd_gpc_tpc_id_tpc0_f(v) ((U32(v) & 0xfU) << 0U)
#define gr_cwd_gpc_tpc_id_gpc0_s() (4U) #define gr_cwd_gpc_tpc_id_gpc0_s() (4U)
#define gr_cwd_gpc_tpc_id_gpc0_f(v) (((v)&0xfU) << 4U) #define gr_cwd_gpc_tpc_id_gpc0_f(v) ((U32(v) & 0xfU) << 4U)
#define gr_cwd_gpc_tpc_id_tpc1_f(v) (((v)&0xfU) << 8U) #define gr_cwd_gpc_tpc_id_tpc1_f(v) ((U32(v) & 0xfU) << 8U)
#define gr_cwd_sm_id_r(i)\ #define gr_cwd_sm_id_r(i)\
(nvgpu_safe_add_u32(0x00405ba0U, nvgpu_safe_mult_u32((i), 4U))) (nvgpu_safe_add_u32(0x00405ba0U, nvgpu_safe_mult_u32((i), 4U)))
#define gr_cwd_sm_id__size_1_v() (0x00000010U) #define gr_cwd_sm_id__size_1_v() (0x00000010U)
#define gr_cwd_sm_id_tpc0_f(v) (((v)&0xffU) << 0U) #define gr_cwd_sm_id_tpc0_f(v) ((U32(v) & 0xffU) << 0U)
#define gr_cwd_sm_id_tpc1_f(v) (((v)&0xffU) << 8U) #define gr_cwd_sm_id_tpc1_f(v) ((U32(v) & 0xffU) << 8U)
#define gr_gpc0_fs_gpc_r() (0x00502608U) #define gr_gpc0_fs_gpc_r() (0x00502608U)
#define gr_gpc0_fs_gpc_num_available_tpcs_v(r) (((r) >> 0U) & 0x1fU) #define gr_gpc0_fs_gpc_num_available_tpcs_v(r) (((r) >> 0U) & 0x1fU)
#define gr_gpc0_fs_gpc_num_available_zculls_v(r) (((r) >> 16U) & 0x1fU) #define gr_gpc0_fs_gpc_num_available_zculls_v(r) (((r) >> 16U) & 0x1fU)
@@ -636,42 +638,43 @@
#define gr_gpc0_cfg_imem_sz_v(r) (((r) >> 0U) & 0xffU) #define gr_gpc0_cfg_imem_sz_v(r) (((r) >> 0U) & 0xffU)
#define gr_gpccs_rc_lanes_r() (0x00502880U) #define gr_gpccs_rc_lanes_r() (0x00502880U)
#define gr_gpccs_rc_lanes_num_chains_s() (6U) #define gr_gpccs_rc_lanes_num_chains_s() (6U)
#define gr_gpccs_rc_lanes_num_chains_f(v) (((v)&0x3fU) << 0U) #define gr_gpccs_rc_lanes_num_chains_f(v) ((U32(v) & 0x3fU) << 0U)
#define gr_gpccs_rc_lanes_num_chains_m() (U32(0x3fU) << 0U) #define gr_gpccs_rc_lanes_num_chains_m() (U32(0x3fU) << 0U)
#define gr_gpccs_rc_lanes_num_chains_v(r) (((r) >> 0U) & 0x3fU) #define gr_gpccs_rc_lanes_num_chains_v(r) (((r) >> 0U) & 0x3fU)
#define gr_gpccs_rc_lane_size_r() (0x00502910U) #define gr_gpccs_rc_lane_size_r() (0x00502910U)
#define gr_gpccs_rc_lane_size_v_s() (24U) #define gr_gpccs_rc_lane_size_v_s() (24U)
#define gr_gpccs_rc_lane_size_v_f(v) (((v)&0xffffffU) << 0U) #define gr_gpccs_rc_lane_size_v_f(v) ((U32(v) & 0xffffffU) << 0U)
#define gr_gpccs_rc_lane_size_v_m() (U32(0xffffffU) << 0U) #define gr_gpccs_rc_lane_size_v_m() (U32(0xffffffU) << 0U)
#define gr_gpccs_rc_lane_size_v_v(r) (((r) >> 0U) & 0xffffffU) #define gr_gpccs_rc_lane_size_v_v(r) (((r) >> 0U) & 0xffffffU)
#define gr_gpccs_rc_lane_size_v_0_v() (0x00000000U) #define gr_gpccs_rc_lane_size_v_0_v() (0x00000000U)
#define gr_gpccs_rc_lane_size_v_0_f() (0x0U) #define gr_gpccs_rc_lane_size_v_0_f() (0x0U)
#define gr_gpc0_zcull_fs_r() (0x00500910U) #define gr_gpc0_zcull_fs_r() (0x00500910U)
#define gr_gpc0_zcull_fs_num_sms_f(v) (((v)&0x1ffU) << 0U) #define gr_gpc0_zcull_fs_num_sms_f(v) ((U32(v) & 0x1ffU) << 0U)
#define gr_gpc0_zcull_fs_num_active_banks_f(v) (((v)&0xfU) << 16U) #define gr_gpc0_zcull_fs_num_active_banks_f(v) ((U32(v) & 0xfU) << 16U)
#define gr_gpc0_zcull_ram_addr_r() (0x00500914U) #define gr_gpc0_zcull_ram_addr_r() (0x00500914U)
#define gr_gpc0_zcull_ram_addr_tiles_per_hypertile_row_per_gpc_f(v)\ #define gr_gpc0_zcull_ram_addr_tiles_per_hypertile_row_per_gpc_f(v)\
(((v)&0xfU) << 0U) ((U32(v) & 0xfU) << 0U)
#define gr_gpc0_zcull_ram_addr_row_offset_f(v) (((v)&0xfU) << 8U) #define gr_gpc0_zcull_ram_addr_row_offset_f(v) ((U32(v) & 0xfU) << 8U)
#define gr_gpc0_zcull_sm_num_rcp_r() (0x00500918U) #define gr_gpc0_zcull_sm_num_rcp_r() (0x00500918U)
#define gr_gpc0_zcull_sm_num_rcp_conservative_f(v) (((v)&0xffffffU) << 0U) #define gr_gpc0_zcull_sm_num_rcp_conservative_f(v) ((U32(v) & 0xffffffU) << 0U)
#define gr_gpc0_zcull_sm_num_rcp_conservative__max_v() (0x00800000U) #define gr_gpc0_zcull_sm_num_rcp_conservative__max_v() (0x00800000U)
#define gr_gpc0_zcull_total_ram_size_r() (0x00500920U) #define gr_gpc0_zcull_total_ram_size_r() (0x00500920U)
#define gr_gpc0_zcull_total_ram_size_num_aliquots_f(v) (((v)&0xffffU) << 0U) #define gr_gpc0_zcull_total_ram_size_num_aliquots_f(v)\
((U32(v) & 0xffffU) << 0U)
#define gr_gpc0_zcull_zcsize_r(i)\ #define gr_gpc0_zcull_zcsize_r(i)\
(nvgpu_safe_add_u32(0x00500a04U, nvgpu_safe_mult_u32((i), 32U))) (nvgpu_safe_add_u32(0x00500a04U, nvgpu_safe_mult_u32((i), 32U)))
#define gr_gpc0_zcull_zcsize_height_subregion__multiple_v() (0x00000040U) #define gr_gpc0_zcull_zcsize_height_subregion__multiple_v() (0x00000040U)
#define gr_gpc0_zcull_zcsize_width_subregion__multiple_v() (0x00000010U) #define gr_gpc0_zcull_zcsize_width_subregion__multiple_v() (0x00000010U)
#define gr_gpc0_gpm_pd_sm_id_r(i)\ #define gr_gpc0_gpm_pd_sm_id_r(i)\
(nvgpu_safe_add_u32(0x00500c10U, nvgpu_safe_mult_u32((i), 4U))) (nvgpu_safe_add_u32(0x00500c10U, nvgpu_safe_mult_u32((i), 4U)))
#define gr_gpc0_gpm_pd_sm_id_id_f(v) (((v)&0xffU) << 0U) #define gr_gpc0_gpm_pd_sm_id_id_f(v) ((U32(v) & 0xffU) << 0U)
#define gr_gpc0_gpm_pd_pes_tpc_id_mask_r(i)\ #define gr_gpc0_gpm_pd_pes_tpc_id_mask_r(i)\
(nvgpu_safe_add_u32(0x00500c30U, nvgpu_safe_mult_u32((i), 4U))) (nvgpu_safe_add_u32(0x00500c30U, nvgpu_safe_mult_u32((i), 4U)))
#define gr_gpc0_gpm_pd_pes_tpc_id_mask_mask_v(r) (((r) >> 0U) & 0xffU) #define gr_gpc0_gpm_pd_pes_tpc_id_mask_mask_v(r) (((r) >> 0U) & 0xffU)
#define gr_gpc0_tpc0_pe_cfg_smid_r() (0x00504088U) #define gr_gpc0_tpc0_pe_cfg_smid_r() (0x00504088U)
#define gr_gpc0_tpc0_pe_cfg_smid_value_f(v) (((v)&0xffffU) << 0U) #define gr_gpc0_tpc0_pe_cfg_smid_value_f(v) ((U32(v) & 0xffffU) << 0U)
#define gr_gpc0_tpc0_sm_cfg_r() (0x00504698U) #define gr_gpc0_tpc0_sm_cfg_r() (0x00504698U)
#define gr_gpc0_tpc0_sm_cfg_sm_id_f(v) (((v)&0xffffU) << 0U) #define gr_gpc0_tpc0_sm_cfg_sm_id_f(v) ((U32(v) & 0xffffU) << 0U)
#define gr_gpc0_tpc0_sm_arch_r() (0x0050469cU) #define gr_gpc0_tpc0_sm_arch_r() (0x0050469cU)
#define gr_gpc0_tpc0_sm_arch_warp_count_v(r) (((r) >> 0U) & 0xffU) #define gr_gpc0_tpc0_sm_arch_warp_count_v(r) (((r) >> 0U) & 0xffU)
#define gr_gpc0_tpc0_sm_arch_spa_version_v(r) (((r) >> 8U) & 0xfffU) #define gr_gpc0_tpc0_sm_arch_spa_version_v(r) (((r) >> 8U) & 0xfffU)
@@ -680,95 +683,97 @@
#define gr_gpc0_ppc0_pes_vsc_strem_master_pe_m() (U32(0x1U) << 0U) #define gr_gpc0_ppc0_pes_vsc_strem_master_pe_m() (U32(0x1U) << 0U)
#define gr_gpc0_ppc0_pes_vsc_strem_master_pe_true_f() (0x1U) #define gr_gpc0_ppc0_pes_vsc_strem_master_pe_true_f() (0x1U)
#define gr_gpc0_ppc0_cbm_beta_cb_size_r() (0x005030c0U) #define gr_gpc0_ppc0_cbm_beta_cb_size_r() (0x005030c0U)
#define gr_gpc0_ppc0_cbm_beta_cb_size_v_f(v) (((v)&0x3fffffU) << 0U) #define gr_gpc0_ppc0_cbm_beta_cb_size_v_f(v) ((U32(v) & 0x3fffffU) << 0U)
#define gr_gpc0_ppc0_cbm_beta_cb_size_v_m() (U32(0x3fffffU) << 0U) #define gr_gpc0_ppc0_cbm_beta_cb_size_v_m() (U32(0x3fffffU) << 0U)
#define gr_gpc0_ppc0_cbm_beta_cb_size_v_default_v() (0x00000320U) #define gr_gpc0_ppc0_cbm_beta_cb_size_v_default_v() (0x00000320U)
#define gr_gpc0_ppc0_cbm_beta_cb_size_v_gfxp_v() (0x00000ba8U) #define gr_gpc0_ppc0_cbm_beta_cb_size_v_gfxp_v() (0x00000ba8U)
#define gr_gpc0_ppc0_cbm_beta_cb_size_v_granularity_v() (0x00000020U) #define gr_gpc0_ppc0_cbm_beta_cb_size_v_granularity_v() (0x00000020U)
#define gr_gpc0_ppc0_cbm_beta_cb_offset_r() (0x005030f4U) #define gr_gpc0_ppc0_cbm_beta_cb_offset_r() (0x005030f4U)
#define gr_gpc0_ppc0_cbm_alpha_cb_size_r() (0x005030e4U) #define gr_gpc0_ppc0_cbm_alpha_cb_size_r() (0x005030e4U)
#define gr_gpc0_ppc0_cbm_alpha_cb_size_v_f(v) (((v)&0xffffU) << 0U) #define gr_gpc0_ppc0_cbm_alpha_cb_size_v_f(v) ((U32(v) & 0xffffU) << 0U)
#define gr_gpc0_ppc0_cbm_alpha_cb_size_v_m() (U32(0xffffU) << 0U) #define gr_gpc0_ppc0_cbm_alpha_cb_size_v_m() (U32(0xffffU) << 0U)
#define gr_gpc0_ppc0_cbm_alpha_cb_size_v_default_v() (0x00000800U) #define gr_gpc0_ppc0_cbm_alpha_cb_size_v_default_v() (0x00000800U)
#define gr_gpc0_ppc0_cbm_alpha_cb_size_v_granularity_v() (0x00000020U) #define gr_gpc0_ppc0_cbm_alpha_cb_size_v_granularity_v() (0x00000020U)
#define gr_gpc0_ppc0_cbm_alpha_cb_offset_r() (0x005030f8U) #define gr_gpc0_ppc0_cbm_alpha_cb_offset_r() (0x005030f8U)
#define gr_gpc0_ppc0_cbm_beta_steady_state_cb_size_r() (0x005030f0U) #define gr_gpc0_ppc0_cbm_beta_steady_state_cb_size_r() (0x005030f0U)
#define gr_gpc0_ppc0_cbm_beta_steady_state_cb_size_v_f(v)\ #define gr_gpc0_ppc0_cbm_beta_steady_state_cb_size_v_f(v)\
(((v)&0x3fffffU) << 0U) ((U32(v) & 0x3fffffU) << 0U)
#define gr_gpc0_ppc0_cbm_beta_steady_state_cb_size_v_default_v() (0x00000320U) #define gr_gpc0_ppc0_cbm_beta_steady_state_cb_size_v_default_v() (0x00000320U)
#define gr_gpcs_tpcs_tex_rm_cb_0_r() (0x00419b00U) #define gr_gpcs_tpcs_tex_rm_cb_0_r() (0x00419b00U)
#define gr_gpcs_tpcs_tex_rm_cb_0_base_addr_43_12_f(v) (((v)&0xffffffffU) << 0U) #define gr_gpcs_tpcs_tex_rm_cb_0_base_addr_43_12_f(v)\
((U32(v) & 0xffffffffU) << 0U)
#define gr_gpcs_tpcs_tex_rm_cb_1_r() (0x00419b04U) #define gr_gpcs_tpcs_tex_rm_cb_1_r() (0x00419b04U)
#define gr_gpcs_tpcs_tex_rm_cb_1_size_div_128b_s() (21U) #define gr_gpcs_tpcs_tex_rm_cb_1_size_div_128b_s() (21U)
#define gr_gpcs_tpcs_tex_rm_cb_1_size_div_128b_f(v) (((v)&0x1fffffU) << 0U) #define gr_gpcs_tpcs_tex_rm_cb_1_size_div_128b_f(v) ((U32(v) & 0x1fffffU) << 0U)
#define gr_gpcs_tpcs_tex_rm_cb_1_size_div_128b_m() (U32(0x1fffffU) << 0U) #define gr_gpcs_tpcs_tex_rm_cb_1_size_div_128b_m() (U32(0x1fffffU) << 0U)
#define gr_gpcs_tpcs_tex_rm_cb_1_size_div_128b_v(r) (((r) >> 0U) & 0x1fffffU) #define gr_gpcs_tpcs_tex_rm_cb_1_size_div_128b_v(r) (((r) >> 0U) & 0x1fffffU)
#define gr_gpcs_tpcs_tex_rm_cb_1_size_div_128b_granularity_f() (0x80U) #define gr_gpcs_tpcs_tex_rm_cb_1_size_div_128b_granularity_f() (0x80U)
#define gr_gpcs_tpcs_tex_rm_cb_1_valid_s() (1U) #define gr_gpcs_tpcs_tex_rm_cb_1_valid_s() (1U)
#define gr_gpcs_tpcs_tex_rm_cb_1_valid_f(v) (((v)&0x1U) << 31U) #define gr_gpcs_tpcs_tex_rm_cb_1_valid_f(v) ((U32(v) & 0x1U) << 31U)
#define gr_gpcs_tpcs_tex_rm_cb_1_valid_m() (U32(0x1U) << 31U) #define gr_gpcs_tpcs_tex_rm_cb_1_valid_m() (U32(0x1U) << 31U)
#define gr_gpcs_tpcs_tex_rm_cb_1_valid_v(r) (((r) >> 31U) & 0x1U) #define gr_gpcs_tpcs_tex_rm_cb_1_valid_v(r) (((r) >> 31U) & 0x1U)
#define gr_gpcs_tpcs_tex_rm_cb_1_valid_true_f() (0x80000000U) #define gr_gpcs_tpcs_tex_rm_cb_1_valid_true_f() (0x80000000U)
#define gr_gpccs_falcon_addr_r() (0x0041a0acU) #define gr_gpccs_falcon_addr_r() (0x0041a0acU)
#define gr_gpccs_falcon_addr_lsb_s() (6U) #define gr_gpccs_falcon_addr_lsb_s() (6U)
#define gr_gpccs_falcon_addr_lsb_f(v) (((v)&0x3fU) << 0U) #define gr_gpccs_falcon_addr_lsb_f(v) ((U32(v) & 0x3fU) << 0U)
#define gr_gpccs_falcon_addr_lsb_m() (U32(0x3fU) << 0U) #define gr_gpccs_falcon_addr_lsb_m() (U32(0x3fU) << 0U)
#define gr_gpccs_falcon_addr_lsb_v(r) (((r) >> 0U) & 0x3fU) #define gr_gpccs_falcon_addr_lsb_v(r) (((r) >> 0U) & 0x3fU)
#define gr_gpccs_falcon_addr_lsb_init_v() (0x00000000U) #define gr_gpccs_falcon_addr_lsb_init_v() (0x00000000U)
#define gr_gpccs_falcon_addr_lsb_init_f() (0x0U) #define gr_gpccs_falcon_addr_lsb_init_f() (0x0U)
#define gr_gpccs_falcon_addr_msb_s() (6U) #define gr_gpccs_falcon_addr_msb_s() (6U)
#define gr_gpccs_falcon_addr_msb_f(v) (((v)&0x3fU) << 6U) #define gr_gpccs_falcon_addr_msb_f(v) ((U32(v) & 0x3fU) << 6U)
#define gr_gpccs_falcon_addr_msb_m() (U32(0x3fU) << 6U) #define gr_gpccs_falcon_addr_msb_m() (U32(0x3fU) << 6U)
#define gr_gpccs_falcon_addr_msb_v(r) (((r) >> 6U) & 0x3fU) #define gr_gpccs_falcon_addr_msb_v(r) (((r) >> 6U) & 0x3fU)
#define gr_gpccs_falcon_addr_msb_init_v() (0x00000000U) #define gr_gpccs_falcon_addr_msb_init_v() (0x00000000U)
#define gr_gpccs_falcon_addr_msb_init_f() (0x0U) #define gr_gpccs_falcon_addr_msb_init_f() (0x0U)
#define gr_gpccs_falcon_addr_ext_s() (12U) #define gr_gpccs_falcon_addr_ext_s() (12U)
#define gr_gpccs_falcon_addr_ext_f(v) (((v)&0xfffU) << 0U) #define gr_gpccs_falcon_addr_ext_f(v) ((U32(v) & 0xfffU) << 0U)
#define gr_gpccs_falcon_addr_ext_m() (U32(0xfffU) << 0U) #define gr_gpccs_falcon_addr_ext_m() (U32(0xfffU) << 0U)
#define gr_gpccs_falcon_addr_ext_v(r) (((r) >> 0U) & 0xfffU) #define gr_gpccs_falcon_addr_ext_v(r) (((r) >> 0U) & 0xfffU)
#define gr_gpccs_cpuctl_r() (0x0041a100U) #define gr_gpccs_cpuctl_r() (0x0041a100U)
#define gr_gpccs_cpuctl_startcpu_f(v) (((v)&0x1U) << 1U) #define gr_gpccs_cpuctl_startcpu_f(v) ((U32(v) & 0x1U) << 1U)
#define gr_gpccs_dmactl_r() (0x0041a10cU) #define gr_gpccs_dmactl_r() (0x0041a10cU)
#define gr_gpccs_dmactl_require_ctx_f(v) (((v)&0x1U) << 0U) #define gr_gpccs_dmactl_require_ctx_f(v) ((U32(v) & 0x1U) << 0U)
#define gr_gpccs_dmactl_dmem_scrubbing_m() (U32(0x1U) << 1U) #define gr_gpccs_dmactl_dmem_scrubbing_m() (U32(0x1U) << 1U)
#define gr_gpccs_dmactl_imem_scrubbing_m() (U32(0x1U) << 2U) #define gr_gpccs_dmactl_imem_scrubbing_m() (U32(0x1U) << 2U)
#define gr_gpccs_imemc_r(i)\ #define gr_gpccs_imemc_r(i)\
(nvgpu_safe_add_u32(0x0041a180U, nvgpu_safe_mult_u32((i), 16U))) (nvgpu_safe_add_u32(0x0041a180U, nvgpu_safe_mult_u32((i), 16U)))
#define gr_gpccs_imemc_offs_f(v) (((v)&0x3fU) << 2U) #define gr_gpccs_imemc_offs_f(v) ((U32(v) & 0x3fU) << 2U)
#define gr_gpccs_imemc_blk_f(v) (((v)&0xffU) << 8U) #define gr_gpccs_imemc_blk_f(v) ((U32(v) & 0xffU) << 8U)
#define gr_gpccs_imemc_aincw_f(v) (((v)&0x1U) << 24U) #define gr_gpccs_imemc_aincw_f(v) ((U32(v) & 0x1U) << 24U)
#define gr_gpccs_imemd_r(i)\ #define gr_gpccs_imemd_r(i)\
(nvgpu_safe_add_u32(0x0041a184U, nvgpu_safe_mult_u32((i), 16U))) (nvgpu_safe_add_u32(0x0041a184U, nvgpu_safe_mult_u32((i), 16U)))
#define gr_gpccs_imemt_r(i)\ #define gr_gpccs_imemt_r(i)\
(nvgpu_safe_add_u32(0x0041a188U, nvgpu_safe_mult_u32((i), 16U))) (nvgpu_safe_add_u32(0x0041a188U, nvgpu_safe_mult_u32((i), 16U)))
#define gr_gpccs_imemt__size_1_v() (0x00000004U) #define gr_gpccs_imemt__size_1_v() (0x00000004U)
#define gr_gpccs_imemt_tag_f(v) (((v)&0xffffU) << 0U) #define gr_gpccs_imemt_tag_f(v) ((U32(v) & 0xffffU) << 0U)
#define gr_gpccs_dmemc_r(i)\ #define gr_gpccs_dmemc_r(i)\
(nvgpu_safe_add_u32(0x0041a1c0U, nvgpu_safe_mult_u32((i), 8U))) (nvgpu_safe_add_u32(0x0041a1c0U, nvgpu_safe_mult_u32((i), 8U)))
#define gr_gpccs_dmemc_offs_f(v) (((v)&0x3fU) << 2U) #define gr_gpccs_dmemc_offs_f(v) ((U32(v) & 0x3fU) << 2U)
#define gr_gpccs_dmemc_blk_f(v) (((v)&0xffU) << 8U) #define gr_gpccs_dmemc_blk_f(v) ((U32(v) & 0xffU) << 8U)
#define gr_gpccs_dmemc_aincw_f(v) (((v)&0x1U) << 24U) #define gr_gpccs_dmemc_aincw_f(v) ((U32(v) & 0x1U) << 24U)
#define gr_gpccs_dmemd_r(i)\ #define gr_gpccs_dmemd_r(i)\
(nvgpu_safe_add_u32(0x0041a1c4U, nvgpu_safe_mult_u32((i), 8U))) (nvgpu_safe_add_u32(0x0041a1c4U, nvgpu_safe_mult_u32((i), 8U)))
#define gr_gpccs_ctxsw_mailbox_r(i)\ #define gr_gpccs_ctxsw_mailbox_r(i)\
(nvgpu_safe_add_u32(0x0041a800U, nvgpu_safe_mult_u32((i), 4U))) (nvgpu_safe_add_u32(0x0041a800U, nvgpu_safe_mult_u32((i), 4U)))
#define gr_gpccs_ctxsw_mailbox_value_f(v) (((v)&0xffffffffU) << 0U) #define gr_gpccs_ctxsw_mailbox_value_f(v) ((U32(v) & 0xffffffffU) << 0U)
#define gr_gpcs_swdx_bundle_cb_base_r() (0x00418e24U) #define gr_gpcs_swdx_bundle_cb_base_r() (0x00418e24U)
#define gr_gpcs_swdx_bundle_cb_base_addr_39_8_s() (32U) #define gr_gpcs_swdx_bundle_cb_base_addr_39_8_s() (32U)
#define gr_gpcs_swdx_bundle_cb_base_addr_39_8_f(v) (((v)&0xffffffffU) << 0U) #define gr_gpcs_swdx_bundle_cb_base_addr_39_8_f(v)\
((U32(v) & 0xffffffffU) << 0U)
#define gr_gpcs_swdx_bundle_cb_base_addr_39_8_m() (U32(0xffffffffU) << 0U) #define gr_gpcs_swdx_bundle_cb_base_addr_39_8_m() (U32(0xffffffffU) << 0U)
#define gr_gpcs_swdx_bundle_cb_base_addr_39_8_v(r) (((r) >> 0U) & 0xffffffffU) #define gr_gpcs_swdx_bundle_cb_base_addr_39_8_v(r) (((r) >> 0U) & 0xffffffffU)
#define gr_gpcs_swdx_bundle_cb_base_addr_39_8_init_v() (0x00000000U) #define gr_gpcs_swdx_bundle_cb_base_addr_39_8_init_v() (0x00000000U)
#define gr_gpcs_swdx_bundle_cb_base_addr_39_8_init_f() (0x0U) #define gr_gpcs_swdx_bundle_cb_base_addr_39_8_init_f() (0x0U)
#define gr_gpcs_swdx_bundle_cb_size_r() (0x00418e28U) #define gr_gpcs_swdx_bundle_cb_size_r() (0x00418e28U)
#define gr_gpcs_swdx_bundle_cb_size_div_256b_s() (11U) #define gr_gpcs_swdx_bundle_cb_size_div_256b_s() (11U)
#define gr_gpcs_swdx_bundle_cb_size_div_256b_f(v) (((v)&0x7ffU) << 0U) #define gr_gpcs_swdx_bundle_cb_size_div_256b_f(v) ((U32(v) & 0x7ffU) << 0U)
#define gr_gpcs_swdx_bundle_cb_size_div_256b_m() (U32(0x7ffU) << 0U) #define gr_gpcs_swdx_bundle_cb_size_div_256b_m() (U32(0x7ffU) << 0U)
#define gr_gpcs_swdx_bundle_cb_size_div_256b_v(r) (((r) >> 0U) & 0x7ffU) #define gr_gpcs_swdx_bundle_cb_size_div_256b_v(r) (((r) >> 0U) & 0x7ffU)
#define gr_gpcs_swdx_bundle_cb_size_div_256b_init_v() (0x00000030U) #define gr_gpcs_swdx_bundle_cb_size_div_256b_init_v() (0x00000030U)
#define gr_gpcs_swdx_bundle_cb_size_div_256b_init_f() (0x30U) #define gr_gpcs_swdx_bundle_cb_size_div_256b_init_f() (0x30U)
#define gr_gpcs_swdx_bundle_cb_size_valid_s() (1U) #define gr_gpcs_swdx_bundle_cb_size_valid_s() (1U)
#define gr_gpcs_swdx_bundle_cb_size_valid_f(v) (((v)&0x1U) << 31U) #define gr_gpcs_swdx_bundle_cb_size_valid_f(v) ((U32(v) & 0x1U) << 31U)
#define gr_gpcs_swdx_bundle_cb_size_valid_m() (U32(0x1U) << 31U) #define gr_gpcs_swdx_bundle_cb_size_valid_m() (U32(0x1U) << 31U)
#define gr_gpcs_swdx_bundle_cb_size_valid_v(r) (((r) >> 31U) & 0x1U) #define gr_gpcs_swdx_bundle_cb_size_valid_v(r) (((r) >> 31U) & 0x1U)
#define gr_gpcs_swdx_bundle_cb_size_valid_false_v() (0x00000000U) #define gr_gpcs_swdx_bundle_cb_size_valid_false_v() (0x00000000U)
@@ -776,146 +781,168 @@
#define gr_gpcs_swdx_bundle_cb_size_valid_true_v() (0x00000001U) #define gr_gpcs_swdx_bundle_cb_size_valid_true_v() (0x00000001U)
#define gr_gpcs_swdx_bundle_cb_size_valid_true_f() (0x80000000U) #define gr_gpcs_swdx_bundle_cb_size_valid_true_f() (0x80000000U)
#define gr_gpc0_swdx_rm_spill_buffer_size_r() (0x005001dcU) #define gr_gpc0_swdx_rm_spill_buffer_size_r() (0x005001dcU)
#define gr_gpc0_swdx_rm_spill_buffer_size_256b_f(v) (((v)&0xffffU) << 0U) #define gr_gpc0_swdx_rm_spill_buffer_size_256b_f(v) ((U32(v) & 0xffffU) << 0U)
#define gr_gpc0_swdx_rm_spill_buffer_size_256b_default_v() (0x00000de0U) #define gr_gpc0_swdx_rm_spill_buffer_size_256b_default_v() (0x00000de0U)
#define gr_gpc0_swdx_rm_spill_buffer_size_256b_byte_granularity_v()\ #define gr_gpc0_swdx_rm_spill_buffer_size_256b_byte_granularity_v()\
(0x00000100U) (0x00000100U)
#define gr_gpc0_swdx_rm_spill_buffer_addr_r() (0x005001d8U) #define gr_gpc0_swdx_rm_spill_buffer_addr_r() (0x005001d8U)
#define gr_gpc0_swdx_rm_spill_buffer_addr_39_8_f(v) (((v)&0xffffffffU) << 0U) #define gr_gpc0_swdx_rm_spill_buffer_addr_39_8_f(v)\
((U32(v) & 0xffffffffU) << 0U)
#define gr_gpc0_swdx_rm_spill_buffer_addr_39_8_align_bits_v() (0x00000008U) #define gr_gpc0_swdx_rm_spill_buffer_addr_39_8_align_bits_v() (0x00000008U)
#define gr_gpcs_swdx_beta_cb_ctrl_r() (0x004181e4U) #define gr_gpcs_swdx_beta_cb_ctrl_r() (0x004181e4U)
#define gr_gpcs_swdx_beta_cb_ctrl_cbes_reserve_f(v) (((v)&0xfffU) << 0U) #define gr_gpcs_swdx_beta_cb_ctrl_cbes_reserve_f(v) ((U32(v) & 0xfffU) << 0U)
#define gr_gpcs_swdx_beta_cb_ctrl_cbes_reserve_gfxp_v() (0x00000100U) #define gr_gpcs_swdx_beta_cb_ctrl_cbes_reserve_gfxp_v() (0x00000100U)
#define gr_gpcs_ppcs_cbm_beta_cb_ctrl_r() (0x0041befcU) #define gr_gpcs_ppcs_cbm_beta_cb_ctrl_r() (0x0041befcU)
#define gr_gpcs_ppcs_cbm_beta_cb_ctrl_cbes_reserve_f(v) (((v)&0xfffU) << 0U) #define gr_gpcs_ppcs_cbm_beta_cb_ctrl_cbes_reserve_f(v)\
((U32(v) & 0xfffU) << 0U)
#define gr_gpcs_swdx_tc_beta_cb_size_r(i)\ #define gr_gpcs_swdx_tc_beta_cb_size_r(i)\
(nvgpu_safe_add_u32(0x00418ea0U, nvgpu_safe_mult_u32((i), 4U))) (nvgpu_safe_add_u32(0x00418ea0U, nvgpu_safe_mult_u32((i), 4U)))
#define gr_gpcs_swdx_tc_beta_cb_size_v_f(v) (((v)&0x3fffffU) << 0U) #define gr_gpcs_swdx_tc_beta_cb_size_v_f(v) ((U32(v) & 0x3fffffU) << 0U)
#define gr_gpcs_swdx_tc_beta_cb_size_v_m() (U32(0x3fffffU) << 0U) #define gr_gpcs_swdx_tc_beta_cb_size_v_m() (U32(0x3fffffU) << 0U)
#define gr_gpcs_swdx_dss_zbc_color_r_r(i)\ #define gr_gpcs_swdx_dss_zbc_color_r_r(i)\
(nvgpu_safe_add_u32(0x00418010U, nvgpu_safe_mult_u32((i), 4U))) (nvgpu_safe_add_u32(0x00418010U, nvgpu_safe_mult_u32((i), 4U)))
#define gr_gpcs_swdx_dss_zbc_color_r_val_f(v) (((v)&0xffffffffU) << 0U) #define gr_gpcs_swdx_dss_zbc_color_r_val_f(v) ((U32(v) & 0xffffffffU) << 0U)
#define gr_gpcs_swdx_dss_zbc_color_g_r(i)\ #define gr_gpcs_swdx_dss_zbc_color_g_r(i)\
(nvgpu_safe_add_u32(0x0041804cU, nvgpu_safe_mult_u32((i), 4U))) (nvgpu_safe_add_u32(0x0041804cU, nvgpu_safe_mult_u32((i), 4U)))
#define gr_gpcs_swdx_dss_zbc_color_g_val_f(v) (((v)&0xffffffffU) << 0U) #define gr_gpcs_swdx_dss_zbc_color_g_val_f(v) ((U32(v) & 0xffffffffU) << 0U)
#define gr_gpcs_swdx_dss_zbc_color_b_r(i)\ #define gr_gpcs_swdx_dss_zbc_color_b_r(i)\
(nvgpu_safe_add_u32(0x00418088U, nvgpu_safe_mult_u32((i), 4U))) (nvgpu_safe_add_u32(0x00418088U, nvgpu_safe_mult_u32((i), 4U)))
#define gr_gpcs_swdx_dss_zbc_color_b_val_f(v) (((v)&0xffffffffU) << 0U) #define gr_gpcs_swdx_dss_zbc_color_b_val_f(v) ((U32(v) & 0xffffffffU) << 0U)
#define gr_gpcs_swdx_dss_zbc_color_a_r(i)\ #define gr_gpcs_swdx_dss_zbc_color_a_r(i)\
(nvgpu_safe_add_u32(0x004180c4U, nvgpu_safe_mult_u32((i), 4U))) (nvgpu_safe_add_u32(0x004180c4U, nvgpu_safe_mult_u32((i), 4U)))
#define gr_gpcs_swdx_dss_zbc_color_a_val_f(v) (((v)&0xffffffffU) << 0U) #define gr_gpcs_swdx_dss_zbc_color_a_val_f(v) ((U32(v) & 0xffffffffU) << 0U)
#define gr_gpcs_swdx_dss_zbc_c_01_to_04_format_r() (0x00500100U) #define gr_gpcs_swdx_dss_zbc_c_01_to_04_format_r() (0x00500100U)
#define gr_gpcs_swdx_dss_zbc_z_r(i)\ #define gr_gpcs_swdx_dss_zbc_z_r(i)\
(nvgpu_safe_add_u32(0x00418110U, nvgpu_safe_mult_u32((i), 4U))) (nvgpu_safe_add_u32(0x00418110U, nvgpu_safe_mult_u32((i), 4U)))
#define gr_gpcs_swdx_dss_zbc_z_val_f(v) (((v)&0xffffffffU) << 0U) #define gr_gpcs_swdx_dss_zbc_z_val_f(v) ((U32(v) & 0xffffffffU) << 0U)
#define gr_gpcs_swdx_dss_zbc_z_01_to_04_format_r() (0x0050014cU) #define gr_gpcs_swdx_dss_zbc_z_01_to_04_format_r() (0x0050014cU)
#define gr_gpcs_setup_attrib_cb_base_r() (0x00418810U) #define gr_gpcs_setup_attrib_cb_base_r() (0x00418810U)
#define gr_gpcs_setup_attrib_cb_base_addr_39_12_f(v) (((v)&0xfffffffU) << 0U) #define gr_gpcs_setup_attrib_cb_base_addr_39_12_f(v)\
((U32(v) & 0xfffffffU) << 0U)
#define gr_gpcs_setup_attrib_cb_base_addr_39_12_align_bits_v() (0x0000000cU) #define gr_gpcs_setup_attrib_cb_base_addr_39_12_align_bits_v() (0x0000000cU)
#define gr_gpcs_setup_attrib_cb_base_valid_true_f() (0x80000000U) #define gr_gpcs_setup_attrib_cb_base_valid_true_f() (0x80000000U)
#define gr_crstr_gpc_map0_r() (0x00418b08U) #define gr_crstr_gpc_map0_r() (0x00418b08U)
#define gr_crstr_gpc_map0_tile0_f(v) (((v)&0x7U) << 0U) #define gr_crstr_gpc_map0_tile0_f(v) ((U32(v) & 0x7U) << 0U)
#define gr_crstr_gpc_map0_tile1_f(v) (((v)&0x7U) << 5U) #define gr_crstr_gpc_map0_tile1_f(v) ((U32(v) & 0x7U) << 5U)
#define gr_crstr_gpc_map0_tile2_f(v) (((v)&0x7U) << 10U) #define gr_crstr_gpc_map0_tile2_f(v) ((U32(v) & 0x7U) << 10U)
#define gr_crstr_gpc_map0_tile3_f(v) (((v)&0x7U) << 15U) #define gr_crstr_gpc_map0_tile3_f(v) ((U32(v) & 0x7U) << 15U)
#define gr_crstr_gpc_map0_tile4_f(v) (((v)&0x7U) << 20U) #define gr_crstr_gpc_map0_tile4_f(v) ((U32(v) & 0x7U) << 20U)
#define gr_crstr_gpc_map0_tile5_f(v) (((v)&0x7U) << 25U) #define gr_crstr_gpc_map0_tile5_f(v) ((U32(v) & 0x7U) << 25U)
#define gr_crstr_gpc_map1_r() (0x00418b0cU) #define gr_crstr_gpc_map1_r() (0x00418b0cU)
#define gr_crstr_gpc_map1_tile6_f(v) (((v)&0x7U) << 0U) #define gr_crstr_gpc_map1_tile6_f(v) ((U32(v) & 0x7U) << 0U)
#define gr_crstr_gpc_map1_tile7_f(v) (((v)&0x7U) << 5U) #define gr_crstr_gpc_map1_tile7_f(v) ((U32(v) & 0x7U) << 5U)
#define gr_crstr_gpc_map1_tile8_f(v) (((v)&0x7U) << 10U) #define gr_crstr_gpc_map1_tile8_f(v) ((U32(v) & 0x7U) << 10U)
#define gr_crstr_gpc_map1_tile9_f(v) (((v)&0x7U) << 15U) #define gr_crstr_gpc_map1_tile9_f(v) ((U32(v) & 0x7U) << 15U)
#define gr_crstr_gpc_map1_tile10_f(v) (((v)&0x7U) << 20U) #define gr_crstr_gpc_map1_tile10_f(v) ((U32(v) & 0x7U) << 20U)
#define gr_crstr_gpc_map1_tile11_f(v) (((v)&0x7U) << 25U) #define gr_crstr_gpc_map1_tile11_f(v) ((U32(v) & 0x7U) << 25U)
#define gr_crstr_gpc_map2_r() (0x00418b10U) #define gr_crstr_gpc_map2_r() (0x00418b10U)
#define gr_crstr_gpc_map2_tile12_f(v) (((v)&0x7U) << 0U) #define gr_crstr_gpc_map2_tile12_f(v) ((U32(v) & 0x7U) << 0U)
#define gr_crstr_gpc_map2_tile13_f(v) (((v)&0x7U) << 5U) #define gr_crstr_gpc_map2_tile13_f(v) ((U32(v) & 0x7U) << 5U)
#define gr_crstr_gpc_map2_tile14_f(v) (((v)&0x7U) << 10U) #define gr_crstr_gpc_map2_tile14_f(v) ((U32(v) & 0x7U) << 10U)
#define gr_crstr_gpc_map2_tile15_f(v) (((v)&0x7U) << 15U) #define gr_crstr_gpc_map2_tile15_f(v) ((U32(v) & 0x7U) << 15U)
#define gr_crstr_gpc_map2_tile16_f(v) (((v)&0x7U) << 20U) #define gr_crstr_gpc_map2_tile16_f(v) ((U32(v) & 0x7U) << 20U)
#define gr_crstr_gpc_map2_tile17_f(v) (((v)&0x7U) << 25U) #define gr_crstr_gpc_map2_tile17_f(v) ((U32(v) & 0x7U) << 25U)
#define gr_crstr_gpc_map3_r() (0x00418b14U) #define gr_crstr_gpc_map3_r() (0x00418b14U)
#define gr_crstr_gpc_map3_tile18_f(v) (((v)&0x7U) << 0U) #define gr_crstr_gpc_map3_tile18_f(v) ((U32(v) & 0x7U) << 0U)
#define gr_crstr_gpc_map3_tile19_f(v) (((v)&0x7U) << 5U) #define gr_crstr_gpc_map3_tile19_f(v) ((U32(v) & 0x7U) << 5U)
#define gr_crstr_gpc_map3_tile20_f(v) (((v)&0x7U) << 10U) #define gr_crstr_gpc_map3_tile20_f(v) ((U32(v) & 0x7U) << 10U)
#define gr_crstr_gpc_map3_tile21_f(v) (((v)&0x7U) << 15U) #define gr_crstr_gpc_map3_tile21_f(v) ((U32(v) & 0x7U) << 15U)
#define gr_crstr_gpc_map3_tile22_f(v) (((v)&0x7U) << 20U) #define gr_crstr_gpc_map3_tile22_f(v) ((U32(v) & 0x7U) << 20U)
#define gr_crstr_gpc_map3_tile23_f(v) (((v)&0x7U) << 25U) #define gr_crstr_gpc_map3_tile23_f(v) ((U32(v) & 0x7U) << 25U)
#define gr_crstr_gpc_map4_r() (0x00418b18U) #define gr_crstr_gpc_map4_r() (0x00418b18U)
#define gr_crstr_gpc_map4_tile24_f(v) (((v)&0x7U) << 0U) #define gr_crstr_gpc_map4_tile24_f(v) ((U32(v) & 0x7U) << 0U)
#define gr_crstr_gpc_map4_tile25_f(v) (((v)&0x7U) << 5U) #define gr_crstr_gpc_map4_tile25_f(v) ((U32(v) & 0x7U) << 5U)
#define gr_crstr_gpc_map4_tile26_f(v) (((v)&0x7U) << 10U) #define gr_crstr_gpc_map4_tile26_f(v) ((U32(v) & 0x7U) << 10U)
#define gr_crstr_gpc_map4_tile27_f(v) (((v)&0x7U) << 15U) #define gr_crstr_gpc_map4_tile27_f(v) ((U32(v) & 0x7U) << 15U)
#define gr_crstr_gpc_map4_tile28_f(v) (((v)&0x7U) << 20U) #define gr_crstr_gpc_map4_tile28_f(v) ((U32(v) & 0x7U) << 20U)
#define gr_crstr_gpc_map4_tile29_f(v) (((v)&0x7U) << 25U) #define gr_crstr_gpc_map4_tile29_f(v) ((U32(v) & 0x7U) << 25U)
#define gr_crstr_gpc_map5_r() (0x00418b1cU) #define gr_crstr_gpc_map5_r() (0x00418b1cU)
#define gr_crstr_gpc_map5_tile30_f(v) (((v)&0x7U) << 0U) #define gr_crstr_gpc_map5_tile30_f(v) ((U32(v) & 0x7U) << 0U)
#define gr_crstr_gpc_map5_tile31_f(v) (((v)&0x7U) << 5U) #define gr_crstr_gpc_map5_tile31_f(v) ((U32(v) & 0x7U) << 5U)
#define gr_crstr_gpc_map5_tile32_f(v) (((v)&0x7U) << 10U) #define gr_crstr_gpc_map5_tile32_f(v) ((U32(v) & 0x7U) << 10U)
#define gr_crstr_gpc_map5_tile33_f(v) (((v)&0x7U) << 15U) #define gr_crstr_gpc_map5_tile33_f(v) ((U32(v) & 0x7U) << 15U)
#define gr_crstr_gpc_map5_tile34_f(v) (((v)&0x7U) << 20U) #define gr_crstr_gpc_map5_tile34_f(v) ((U32(v) & 0x7U) << 20U)
#define gr_crstr_gpc_map5_tile35_f(v) (((v)&0x7U) << 25U) #define gr_crstr_gpc_map5_tile35_f(v) ((U32(v) & 0x7U) << 25U)
#define gr_crstr_map_table_cfg_r() (0x00418bb8U) #define gr_crstr_map_table_cfg_r() (0x00418bb8U)
#define gr_crstr_map_table_cfg_row_offset_f(v) (((v)&0xffU) << 0U) #define gr_crstr_map_table_cfg_row_offset_f(v) ((U32(v) & 0xffU) << 0U)
#define gr_crstr_map_table_cfg_num_entries_f(v) (((v)&0xffU) << 8U) #define gr_crstr_map_table_cfg_num_entries_f(v) ((U32(v) & 0xffU) << 8U)
#define gr_gpcs_zcull_sm_in_gpc_number_map0_r() (0x00418980U) #define gr_gpcs_zcull_sm_in_gpc_number_map0_r() (0x00418980U)
#define gr_gpcs_zcull_sm_in_gpc_number_map0_tile_0_f(v) (((v)&0x7U) << 0U) #define gr_gpcs_zcull_sm_in_gpc_number_map0_tile_0_f(v) ((U32(v) & 0x7U) << 0U)
#define gr_gpcs_zcull_sm_in_gpc_number_map0_tile_1_f(v) (((v)&0x7U) << 4U) #define gr_gpcs_zcull_sm_in_gpc_number_map0_tile_1_f(v) ((U32(v) & 0x7U) << 4U)
#define gr_gpcs_zcull_sm_in_gpc_number_map0_tile_2_f(v) (((v)&0x7U) << 8U) #define gr_gpcs_zcull_sm_in_gpc_number_map0_tile_2_f(v) ((U32(v) & 0x7U) << 8U)
#define gr_gpcs_zcull_sm_in_gpc_number_map0_tile_3_f(v) (((v)&0x7U) << 12U) #define gr_gpcs_zcull_sm_in_gpc_number_map0_tile_3_f(v) ((U32(v) & 0x7U) << 12U)
#define gr_gpcs_zcull_sm_in_gpc_number_map0_tile_4_f(v) (((v)&0x7U) << 16U) #define gr_gpcs_zcull_sm_in_gpc_number_map0_tile_4_f(v) ((U32(v) & 0x7U) << 16U)
#define gr_gpcs_zcull_sm_in_gpc_number_map0_tile_5_f(v) (((v)&0x7U) << 20U) #define gr_gpcs_zcull_sm_in_gpc_number_map0_tile_5_f(v) ((U32(v) & 0x7U) << 20U)
#define gr_gpcs_zcull_sm_in_gpc_number_map0_tile_6_f(v) (((v)&0x7U) << 24U) #define gr_gpcs_zcull_sm_in_gpc_number_map0_tile_6_f(v) ((U32(v) & 0x7U) << 24U)
#define gr_gpcs_zcull_sm_in_gpc_number_map0_tile_7_f(v) (((v)&0x7U) << 28U) #define gr_gpcs_zcull_sm_in_gpc_number_map0_tile_7_f(v) ((U32(v) & 0x7U) << 28U)
#define gr_gpcs_zcull_sm_in_gpc_number_map1_r() (0x00418984U) #define gr_gpcs_zcull_sm_in_gpc_number_map1_r() (0x00418984U)
#define gr_gpcs_zcull_sm_in_gpc_number_map1_tile_8_f(v) (((v)&0x7U) << 0U) #define gr_gpcs_zcull_sm_in_gpc_number_map1_tile_8_f(v) ((U32(v) & 0x7U) << 0U)
#define gr_gpcs_zcull_sm_in_gpc_number_map1_tile_9_f(v) (((v)&0x7U) << 4U) #define gr_gpcs_zcull_sm_in_gpc_number_map1_tile_9_f(v) ((U32(v) & 0x7U) << 4U)
#define gr_gpcs_zcull_sm_in_gpc_number_map1_tile_10_f(v) (((v)&0x7U) << 8U) #define gr_gpcs_zcull_sm_in_gpc_number_map1_tile_10_f(v) ((U32(v) & 0x7U) << 8U)
#define gr_gpcs_zcull_sm_in_gpc_number_map1_tile_11_f(v) (((v)&0x7U) << 12U) #define gr_gpcs_zcull_sm_in_gpc_number_map1_tile_11_f(v)\
#define gr_gpcs_zcull_sm_in_gpc_number_map1_tile_12_f(v) (((v)&0x7U) << 16U) ((U32(v) & 0x7U) << 12U)
#define gr_gpcs_zcull_sm_in_gpc_number_map1_tile_13_f(v) (((v)&0x7U) << 20U) #define gr_gpcs_zcull_sm_in_gpc_number_map1_tile_12_f(v)\
#define gr_gpcs_zcull_sm_in_gpc_number_map1_tile_14_f(v) (((v)&0x7U) << 24U) ((U32(v) & 0x7U) << 16U)
#define gr_gpcs_zcull_sm_in_gpc_number_map1_tile_15_f(v) (((v)&0x7U) << 28U) #define gr_gpcs_zcull_sm_in_gpc_number_map1_tile_13_f(v)\
((U32(v) & 0x7U) << 20U)
#define gr_gpcs_zcull_sm_in_gpc_number_map1_tile_14_f(v)\
((U32(v) & 0x7U) << 24U)
#define gr_gpcs_zcull_sm_in_gpc_number_map1_tile_15_f(v)\
((U32(v) & 0x7U) << 28U)
#define gr_gpcs_zcull_sm_in_gpc_number_map2_r() (0x00418988U) #define gr_gpcs_zcull_sm_in_gpc_number_map2_r() (0x00418988U)
#define gr_gpcs_zcull_sm_in_gpc_number_map2_tile_16_f(v) (((v)&0x7U) << 0U) #define gr_gpcs_zcull_sm_in_gpc_number_map2_tile_16_f(v) ((U32(v) & 0x7U) << 0U)
#define gr_gpcs_zcull_sm_in_gpc_number_map2_tile_17_f(v) (((v)&0x7U) << 4U) #define gr_gpcs_zcull_sm_in_gpc_number_map2_tile_17_f(v) ((U32(v) & 0x7U) << 4U)
#define gr_gpcs_zcull_sm_in_gpc_number_map2_tile_18_f(v) (((v)&0x7U) << 8U) #define gr_gpcs_zcull_sm_in_gpc_number_map2_tile_18_f(v) ((U32(v) & 0x7U) << 8U)
#define gr_gpcs_zcull_sm_in_gpc_number_map2_tile_19_f(v) (((v)&0x7U) << 12U) #define gr_gpcs_zcull_sm_in_gpc_number_map2_tile_19_f(v)\
#define gr_gpcs_zcull_sm_in_gpc_number_map2_tile_20_f(v) (((v)&0x7U) << 16U) ((U32(v) & 0x7U) << 12U)
#define gr_gpcs_zcull_sm_in_gpc_number_map2_tile_21_f(v) (((v)&0x7U) << 20U) #define gr_gpcs_zcull_sm_in_gpc_number_map2_tile_20_f(v)\
#define gr_gpcs_zcull_sm_in_gpc_number_map2_tile_22_f(v) (((v)&0x7U) << 24U) ((U32(v) & 0x7U) << 16U)
#define gr_gpcs_zcull_sm_in_gpc_number_map2_tile_21_f(v)\
((U32(v) & 0x7U) << 20U)
#define gr_gpcs_zcull_sm_in_gpc_number_map2_tile_22_f(v)\
((U32(v) & 0x7U) << 24U)
#define gr_gpcs_zcull_sm_in_gpc_number_map2_tile_23_s() (3U) #define gr_gpcs_zcull_sm_in_gpc_number_map2_tile_23_s() (3U)
#define gr_gpcs_zcull_sm_in_gpc_number_map2_tile_23_f(v) (((v)&0x7U) << 28U) #define gr_gpcs_zcull_sm_in_gpc_number_map2_tile_23_f(v)\
((U32(v) & 0x7U) << 28U)
#define gr_gpcs_zcull_sm_in_gpc_number_map2_tile_23_m() (U32(0x7U) << 28U) #define gr_gpcs_zcull_sm_in_gpc_number_map2_tile_23_m() (U32(0x7U) << 28U)
#define gr_gpcs_zcull_sm_in_gpc_number_map2_tile_23_v(r) (((r) >> 28U) & 0x7U) #define gr_gpcs_zcull_sm_in_gpc_number_map2_tile_23_v(r) (((r) >> 28U) & 0x7U)
#define gr_gpcs_zcull_sm_in_gpc_number_map3_r() (0x0041898cU) #define gr_gpcs_zcull_sm_in_gpc_number_map3_r() (0x0041898cU)
#define gr_gpcs_zcull_sm_in_gpc_number_map3_tile_24_f(v) (((v)&0x7U) << 0U) #define gr_gpcs_zcull_sm_in_gpc_number_map3_tile_24_f(v) ((U32(v) & 0x7U) << 0U)
#define gr_gpcs_zcull_sm_in_gpc_number_map3_tile_25_f(v) (((v)&0x7U) << 4U) #define gr_gpcs_zcull_sm_in_gpc_number_map3_tile_25_f(v) ((U32(v) & 0x7U) << 4U)
#define gr_gpcs_zcull_sm_in_gpc_number_map3_tile_26_f(v) (((v)&0x7U) << 8U) #define gr_gpcs_zcull_sm_in_gpc_number_map3_tile_26_f(v) ((U32(v) & 0x7U) << 8U)
#define gr_gpcs_zcull_sm_in_gpc_number_map3_tile_27_f(v) (((v)&0x7U) << 12U) #define gr_gpcs_zcull_sm_in_gpc_number_map3_tile_27_f(v)\
#define gr_gpcs_zcull_sm_in_gpc_number_map3_tile_28_f(v) (((v)&0x7U) << 16U) ((U32(v) & 0x7U) << 12U)
#define gr_gpcs_zcull_sm_in_gpc_number_map3_tile_29_f(v) (((v)&0x7U) << 20U) #define gr_gpcs_zcull_sm_in_gpc_number_map3_tile_28_f(v)\
#define gr_gpcs_zcull_sm_in_gpc_number_map3_tile_30_f(v) (((v)&0x7U) << 24U) ((U32(v) & 0x7U) << 16U)
#define gr_gpcs_zcull_sm_in_gpc_number_map3_tile_31_f(v) (((v)&0x7U) << 28U) #define gr_gpcs_zcull_sm_in_gpc_number_map3_tile_29_f(v)\
((U32(v) & 0x7U) << 20U)
#define gr_gpcs_zcull_sm_in_gpc_number_map3_tile_30_f(v)\
((U32(v) & 0x7U) << 24U)
#define gr_gpcs_zcull_sm_in_gpc_number_map3_tile_31_f(v)\
((U32(v) & 0x7U) << 28U)
#define gr_gpcs_gpm_pd_cfg_r() (0x00418c6cU) #define gr_gpcs_gpm_pd_cfg_r() (0x00418c6cU)
#define gr_gpcs_gpm_pd_cfg_timeslice_mode_disable_f() (0x0U) #define gr_gpcs_gpm_pd_cfg_timeslice_mode_disable_f() (0x0U)
#define gr_gpcs_gpm_pd_cfg_timeslice_mode_enable_f() (0x1U) #define gr_gpcs_gpm_pd_cfg_timeslice_mode_enable_f() (0x1U)
#define gr_gpcs_gcc_pagepool_base_r() (0x00419004U) #define gr_gpcs_gcc_pagepool_base_r() (0x00419004U)
#define gr_gpcs_gcc_pagepool_base_addr_39_8_f(v) (((v)&0xffffffffU) << 0U) #define gr_gpcs_gcc_pagepool_base_addr_39_8_f(v) ((U32(v) & 0xffffffffU) << 0U)
#define gr_gpcs_gcc_pagepool_r() (0x00419008U) #define gr_gpcs_gcc_pagepool_r() (0x00419008U)
#define gr_gpcs_gcc_pagepool_total_pages_f(v) (((v)&0x3ffU) << 0U) #define gr_gpcs_gcc_pagepool_total_pages_f(v) ((U32(v) & 0x3ffU) << 0U)
#define gr_gpcs_tpcs_pe_vaf_r() (0x0041980cU) #define gr_gpcs_tpcs_pe_vaf_r() (0x0041980cU)
#define gr_gpcs_tpcs_pe_vaf_fast_mode_switch_true_f() (0x10U) #define gr_gpcs_tpcs_pe_vaf_fast_mode_switch_true_f() (0x10U)
#define gr_gpcs_tpcs_pe_pin_cb_global_base_addr_r() (0x00419848U) #define gr_gpcs_tpcs_pe_pin_cb_global_base_addr_r() (0x00419848U)
#define gr_gpcs_tpcs_pe_pin_cb_global_base_addr_v_f(v) (((v)&0xfffffffU) << 0U) #define gr_gpcs_tpcs_pe_pin_cb_global_base_addr_v_f(v)\
#define gr_gpcs_tpcs_pe_pin_cb_global_base_addr_valid_f(v) (((v)&0x1U) << 28U) ((U32(v) & 0xfffffffU) << 0U)
#define gr_gpcs_tpcs_pe_pin_cb_global_base_addr_valid_f(v)\
((U32(v) & 0x1U) << 28U)
#define gr_gpcs_tpcs_pe_pin_cb_global_base_addr_valid_true_f() (0x10000000U) #define gr_gpcs_tpcs_pe_pin_cb_global_base_addr_valid_true_f() (0x10000000U)
#define gr_gpcs_tpcs_mpc_vtg_debug_r() (0x00419c00U) #define gr_gpcs_tpcs_mpc_vtg_debug_r() (0x00419c00U)
#define gr_gpcs_tpcs_mpc_vtg_debug_timeslice_mode_disabled_f() (0x0U) #define gr_gpcs_tpcs_mpc_vtg_debug_timeslice_mode_disabled_f() (0x0U)
#define gr_gpcs_tpcs_mpc_vtg_debug_timeslice_mode_enabled_f() (0x8U) #define gr_gpcs_tpcs_mpc_vtg_debug_timeslice_mode_enabled_f() (0x8U)
#define gr_gpcs_tpcs_mpc_vtg_cb_global_base_addr_r() (0x00419c2cU) #define gr_gpcs_tpcs_mpc_vtg_cb_global_base_addr_r() (0x00419c2cU)
#define gr_gpcs_tpcs_mpc_vtg_cb_global_base_addr_v_f(v) (((v)&0xfffffffU) << 0U) #define gr_gpcs_tpcs_mpc_vtg_cb_global_base_addr_v_f(v)\
#define gr_gpcs_tpcs_mpc_vtg_cb_global_base_addr_valid_f(v) (((v)&0x1U) << 28U) ((U32(v) & 0xfffffffU) << 0U)
#define gr_gpcs_tpcs_mpc_vtg_cb_global_base_addr_valid_f(v)\
((U32(v) & 0x1U) << 28U)
#define gr_gpcs_tpcs_mpc_vtg_cb_global_base_addr_valid_true_f() (0x10000000U) #define gr_gpcs_tpcs_mpc_vtg_cb_global_base_addr_valid_true_f() (0x10000000U)
#define gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_r() (0x00419e44U) #define gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_r() (0x00419e44U)
#define gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_stack_error_report_f() (0x2U) #define gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_stack_error_report_f() (0x2U)
@@ -982,7 +1009,7 @@
#define gr_gpc0_tpc0_tpccs_tpc_exception_en_sm_v(r) (((r) >> 1U) & 0x1U) #define gr_gpc0_tpc0_tpccs_tpc_exception_en_sm_v(r) (((r) >> 1U) & 0x1U)
#define gr_gpc0_tpc0_tpccs_tpc_exception_en_sm_enabled_f() (0x2U) #define gr_gpc0_tpc0_tpccs_tpc_exception_en_sm_enabled_f() (0x2U)
#define gr_gpcs_gpccs_gpc_exception_en_r() (0x0041ac94U) #define gr_gpcs_gpccs_gpc_exception_en_r() (0x0041ac94U)
#define gr_gpcs_gpccs_gpc_exception_en_tpc_f(v) (((v)&0xffU) << 16U) #define gr_gpcs_gpccs_gpc_exception_en_tpc_f(v) ((U32(v) & 0xffU) << 16U)
#define gr_gpc0_gpccs_gpc_exception_r() (0x00502c90U) #define gr_gpc0_gpccs_gpc_exception_r() (0x00502c90U)
#define gr_gpc0_gpccs_gpc_exception_gcc_v(r) (((r) >> 2U) & 0x1U) #define gr_gpc0_gpccs_gpc_exception_gcc_v(r) (((r) >> 2U) & 0x1U)
#define gr_gpc0_gpccs_gpc_exception_tpc_v(r) (((r) >> 16U) & 0xffU) #define gr_gpc0_gpccs_gpc_exception_tpc_v(r) (((r) >> 16U) & 0xffU)
@@ -1042,11 +1069,13 @@
#define gr_gpc0_tpc0_sm_halfctl_ctrl_r() (0x00504770U) #define gr_gpc0_tpc0_sm_halfctl_ctrl_r() (0x00504770U)
#define gr_gpcs_tpcs_sm_halfctl_ctrl_r() (0x00419f70U) #define gr_gpcs_tpcs_sm_halfctl_ctrl_r() (0x00419f70U)
#define gr_gpcs_tpcs_sm_halfctl_ctrl_sctl_read_quad_ctl_m() (U32(0x1U) << 4U) #define gr_gpcs_tpcs_sm_halfctl_ctrl_sctl_read_quad_ctl_m() (U32(0x1U) << 4U)
#define gr_gpcs_tpcs_sm_halfctl_ctrl_sctl_read_quad_ctl_f(v) (((v)&0x1U) << 4U) #define gr_gpcs_tpcs_sm_halfctl_ctrl_sctl_read_quad_ctl_f(v)\
((U32(v) & 0x1U) << 4U)
#define gr_gpc0_tpc0_sm_debug_sfe_control_r() (0x0050477cU) #define gr_gpc0_tpc0_sm_debug_sfe_control_r() (0x0050477cU)
#define gr_gpcs_tpcs_sm_debug_sfe_control_r() (0x00419f7cU) #define gr_gpcs_tpcs_sm_debug_sfe_control_r() (0x00419f7cU)
#define gr_gpcs_tpcs_sm_debug_sfe_control_read_half_ctl_m() (U32(0x1U) << 0U) #define gr_gpcs_tpcs_sm_debug_sfe_control_read_half_ctl_m() (U32(0x1U) << 0U)
#define gr_gpcs_tpcs_sm_debug_sfe_control_read_half_ctl_f(v) (((v)&0x1U) << 0U) #define gr_gpcs_tpcs_sm_debug_sfe_control_read_half_ctl_f(v)\
((U32(v) & 0x1U) << 0U)
#define gr_gpcs_tpcs_pes_vsc_vpc_r() (0x0041be08U) #define gr_gpcs_tpcs_pes_vsc_vpc_r() (0x0041be08U)
#define gr_gpcs_tpcs_pes_vsc_vpc_fast_mode_switch_true_f() (0x4U) #define gr_gpcs_tpcs_pes_vsc_vpc_fast_mode_switch_true_f() (0x4U)
#define gr_ppcs_wwdx_map_gpc_map0_r() (0x0041bf00U) #define gr_ppcs_wwdx_map_gpc_map0_r() (0x0041bf00U)
@@ -1056,24 +1085,32 @@
#define gr_ppcs_wwdx_map_gpc_map4_r() (0x0041bf10U) #define gr_ppcs_wwdx_map_gpc_map4_r() (0x0041bf10U)
#define gr_ppcs_wwdx_map_gpc_map5_r() (0x0041bf14U) #define gr_ppcs_wwdx_map_gpc_map5_r() (0x0041bf14U)
#define gr_ppcs_wwdx_map_table_cfg_r() (0x0041bfd0U) #define gr_ppcs_wwdx_map_table_cfg_r() (0x0041bfd0U)
#define gr_ppcs_wwdx_map_table_cfg_row_offset_f(v) (((v)&0xffU) << 0U) #define gr_ppcs_wwdx_map_table_cfg_row_offset_f(v) ((U32(v) & 0xffU) << 0U)
#define gr_ppcs_wwdx_map_table_cfg_num_entries_f(v) (((v)&0xffU) << 8U) #define gr_ppcs_wwdx_map_table_cfg_num_entries_f(v) ((U32(v) & 0xffU) << 8U)
#define gr_ppcs_wwdx_map_table_cfg_normalized_num_entries_f(v)\ #define gr_ppcs_wwdx_map_table_cfg_normalized_num_entries_f(v)\
(((v)&0x1fU) << 16U) ((U32(v) & 0x1fU) << 16U)
#define gr_ppcs_wwdx_map_table_cfg_normalized_shift_value_f(v)\ #define gr_ppcs_wwdx_map_table_cfg_normalized_shift_value_f(v)\
(((v)&0x7U) << 21U) ((U32(v) & 0x7U) << 21U)
#define gr_ppcs_wwdx_map_table_cfg_coeff5_mod_value_f(v) (((v)&0x1fU) << 24U) #define gr_ppcs_wwdx_map_table_cfg_coeff5_mod_value_f(v)\
((U32(v) & 0x1fU) << 24U)
#define gr_gpcs_ppcs_wwdx_sm_num_rcp_r() (0x0041bfd4U) #define gr_gpcs_ppcs_wwdx_sm_num_rcp_r() (0x0041bfd4U)
#define gr_gpcs_ppcs_wwdx_sm_num_rcp_conservative_f(v) (((v)&0xffffffU) << 0U) #define gr_gpcs_ppcs_wwdx_sm_num_rcp_conservative_f(v)\
((U32(v) & 0xffffffU) << 0U)
#define gr_ppcs_wwdx_map_table_cfg2_r() (0x0041bfe4U) #define gr_ppcs_wwdx_map_table_cfg2_r() (0x0041bfe4U)
#define gr_ppcs_wwdx_map_table_cfg2_coeff6_mod_value_f(v) (((v)&0x1fU) << 0U) #define gr_ppcs_wwdx_map_table_cfg2_coeff6_mod_value_f(v)\
#define gr_ppcs_wwdx_map_table_cfg2_coeff7_mod_value_f(v) (((v)&0x1fU) << 5U) ((U32(v) & 0x1fU) << 0U)
#define gr_ppcs_wwdx_map_table_cfg2_coeff8_mod_value_f(v) (((v)&0x1fU) << 10U) #define gr_ppcs_wwdx_map_table_cfg2_coeff7_mod_value_f(v)\
#define gr_ppcs_wwdx_map_table_cfg2_coeff9_mod_value_f(v) (((v)&0x1fU) << 15U) ((U32(v) & 0x1fU) << 5U)
#define gr_ppcs_wwdx_map_table_cfg2_coeff10_mod_value_f(v) (((v)&0x1fU) << 20U) #define gr_ppcs_wwdx_map_table_cfg2_coeff8_mod_value_f(v)\
#define gr_ppcs_wwdx_map_table_cfg2_coeff11_mod_value_f(v) (((v)&0x1fU) << 25U) ((U32(v) & 0x1fU) << 10U)
#define gr_ppcs_wwdx_map_table_cfg2_coeff9_mod_value_f(v)\
((U32(v) & 0x1fU) << 15U)
#define gr_ppcs_wwdx_map_table_cfg2_coeff10_mod_value_f(v)\
((U32(v) & 0x1fU) << 20U)
#define gr_ppcs_wwdx_map_table_cfg2_coeff11_mod_value_f(v)\
((U32(v) & 0x1fU) << 25U)
#define gr_bes_zrop_settings_r() (0x00408850U) #define gr_bes_zrop_settings_r() (0x00408850U)
#define gr_bes_zrop_settings_num_active_ltcs_f(v) (((v)&0xfU) << 0U) #define gr_bes_zrop_settings_num_active_ltcs_f(v) ((U32(v) & 0xfU) << 0U)
#define gr_be0_crop_debug3_r() (0x00410108U) #define gr_be0_crop_debug3_r() (0x00410108U)
#define gr_bes_crop_debug3_r() (0x00408908U) #define gr_bes_crop_debug3_r() (0x00408908U)
#define gr_bes_crop_debug3_comp_vdc_4to2_disable_m() (U32(0x1U) << 31U) #define gr_bes_crop_debug3_comp_vdc_4to2_disable_m() (U32(0x1U) << 31U)
@@ -1088,7 +1125,7 @@
#define gr_bes_crop_debug4_clamp_fp_blend_to_inf_f() (0x0U) #define gr_bes_crop_debug4_clamp_fp_blend_to_inf_f() (0x0U)
#define gr_bes_crop_debug4_clamp_fp_blend_to_maxval_f() (0x40000U) #define gr_bes_crop_debug4_clamp_fp_blend_to_maxval_f() (0x40000U)
#define gr_bes_crop_settings_r() (0x00408958U) #define gr_bes_crop_settings_r() (0x00408958U)
#define gr_bes_crop_settings_num_active_ltcs_f(v) (((v)&0xfU) << 0U) #define gr_bes_crop_settings_num_active_ltcs_f(v) ((U32(v) & 0xfU) << 0U)
#define gr_zcull_bytes_per_aliquot_per_gpu_v() (0x00000020U) #define gr_zcull_bytes_per_aliquot_per_gpu_v() (0x00000020U)
#define gr_zcull_save_restore_header_bytes_per_gpc_v() (0x00000020U) #define gr_zcull_save_restore_header_bytes_per_gpc_v() (0x00000020U)
#define gr_zcull_save_restore_subregion_header_bytes_per_gpc_v() (0x000000c0U) #define gr_zcull_save_restore_subregion_header_bytes_per_gpc_v() (0x000000c0U)
@@ -1144,7 +1181,7 @@
#define gr_gpcs_pri_mmu_debug_rd_r() (0x004188b8U) #define gr_gpcs_pri_mmu_debug_rd_r() (0x004188b8U)
#define gr_gpcs_mmu_num_active_ltcs_r() (0x004188acU) #define gr_gpcs_mmu_num_active_ltcs_r() (0x004188acU)
#define gr_gpcs_tpcs_sm_dbgr_control0_r() (0x00419e10U) #define gr_gpcs_tpcs_sm_dbgr_control0_r() (0x00419e10U)
#define gr_gpcs_tpcs_sm_dbgr_control0_debugger_mode_f(v) (((v)&0x1U) << 0U) #define gr_gpcs_tpcs_sm_dbgr_control0_debugger_mode_f(v) ((U32(v) & 0x1U) << 0U)
#define gr_gpcs_tpcs_sm_dbgr_control0_debugger_mode_on_v() (0x00000001U) #define gr_gpcs_tpcs_sm_dbgr_control0_debugger_mode_on_v() (0x00000001U)
#define gr_gpcs_tpcs_sm_dbgr_control0_stop_trigger_m() (U32(0x1U) << 31U) #define gr_gpcs_tpcs_sm_dbgr_control0_stop_trigger_m() (U32(0x1U) << 31U)
#define gr_gpcs_tpcs_sm_dbgr_control0_stop_trigger_v(r) (((r) >> 31U) & 0x1U) #define gr_gpcs_tpcs_sm_dbgr_control0_stop_trigger_v(r) (((r) >> 31U) & 0x1U)
@@ -1154,11 +1191,11 @@
#define gr_gpcs_tpcs_sm_dbgr_control0_run_trigger_v(r) (((r) >> 30U) & 0x1U) #define gr_gpcs_tpcs_sm_dbgr_control0_run_trigger_v(r) (((r) >> 30U) & 0x1U)
#define gr_gpcs_tpcs_sm_dbgr_control0_run_trigger_task_f() (0x40000000U) #define gr_gpcs_tpcs_sm_dbgr_control0_run_trigger_task_f() (0x40000000U)
#define gr_fe_gfxp_wfi_timeout_r() (0x004041c0U) #define gr_fe_gfxp_wfi_timeout_r() (0x004041c0U)
#define gr_fe_gfxp_wfi_timeout_count_f(v) (((v)&0xffffffffU) << 0U) #define gr_fe_gfxp_wfi_timeout_count_f(v) ((U32(v) & 0xffffffffU) << 0U)
#define gr_fe_gfxp_wfi_timeout_count_disabled_f() (0x0U) #define gr_fe_gfxp_wfi_timeout_count_disabled_f() (0x0U)
#define gr_gpcs_tpcs_sm_texio_control_r() (0x00419c84U) #define gr_gpcs_tpcs_sm_texio_control_r() (0x00419c84U)
#define gr_gpcs_tpcs_sm_texio_control_oor_addr_check_mode_f(v)\ #define gr_gpcs_tpcs_sm_texio_control_oor_addr_check_mode_f(v)\
(((v)&0x7U) << 8U) ((U32(v) & 0x7U) << 8U)
#define gr_gpcs_tpcs_sm_texio_control_oor_addr_check_mode_m() (U32(0x7U) << 8U) #define gr_gpcs_tpcs_sm_texio_control_oor_addr_check_mode_m() (U32(0x7U) << 8U)
#define gr_gpcs_tpcs_sm_texio_control_oor_addr_check_mode_arm_63_48_match_f()\ #define gr_gpcs_tpcs_sm_texio_control_oor_addr_check_mode_arm_63_48_match_f()\
(0x100U) (0x100U)
@@ -1166,6 +1203,7 @@
#define gr_gpcs_tpcs_sm_disp_ctrl_re_suppress_m() (U32(0x3U) << 11U) #define gr_gpcs_tpcs_sm_disp_ctrl_re_suppress_m() (U32(0x3U) << 11U)
#define gr_gpcs_tpcs_sm_disp_ctrl_re_suppress_disable_f() (0x1000U) #define gr_gpcs_tpcs_sm_disp_ctrl_re_suppress_disable_f() (0x1000U)
#define gr_gpcs_tc_debug0_r() (0x00418708U) #define gr_gpcs_tc_debug0_r() (0x00418708U)
#define gr_gpcs_tc_debug0_limit_coalesce_buffer_size_f(v) (((v)&0x1ffU) << 0U) #define gr_gpcs_tc_debug0_limit_coalesce_buffer_size_f(v)\
((U32(v) & 0x1ffU) << 0U)
#define gr_gpcs_tc_debug0_limit_coalesce_buffer_size_m() (U32(0x1ffU) << 0U) #define gr_gpcs_tc_debug0_limit_coalesce_buffer_size_m() (U32(0x1ffU) << 0U)
#endif #endif

12
drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_ltc_gp106.h
View File

@@ -77,9 +77,11 @@
#define ltc_ltcs_ltss_cbc_ctrl1_clear_active_f() (0x4U) #define ltc_ltcs_ltss_cbc_ctrl1_clear_active_f() (0x4U)
#define ltc_ltc0_lts0_cbc_ctrl1_r() (0x0014046cU) #define ltc_ltc0_lts0_cbc_ctrl1_r() (0x0014046cU)
#define ltc_ltcs_ltss_cbc_ctrl2_r() (0x0017e270U) #define ltc_ltcs_ltss_cbc_ctrl2_r() (0x0017e270U)
#define ltc_ltcs_ltss_cbc_ctrl2_clear_lower_bound_f(v) (((v)&0x3ffffU) << 0U) #define ltc_ltcs_ltss_cbc_ctrl2_clear_lower_bound_f(v)\
((U32(v) & 0x3ffffU) << 0U)
#define ltc_ltcs_ltss_cbc_ctrl3_r() (0x0017e274U) #define ltc_ltcs_ltss_cbc_ctrl3_r() (0x0017e274U)
#define ltc_ltcs_ltss_cbc_ctrl3_clear_upper_bound_f(v) (((v)&0x3ffffU) << 0U) #define ltc_ltcs_ltss_cbc_ctrl3_clear_upper_bound_f(v)\
((U32(v) & 0x3ffffU) << 0U)
#define ltc_ltcs_ltss_cbc_ctrl3_clear_upper_bound_init_v() (0x0003ffffU) #define ltc_ltcs_ltss_cbc_ctrl3_clear_upper_bound_init_v() (0x0003ffffU)
#define ltc_ltcs_ltss_cbc_base_r() (0x0017e278U) #define ltc_ltcs_ltss_cbc_base_r() (0x0017e278U)
#define ltc_ltcs_ltss_cbc_base_alignment_shift_v() (0x0000000bU) #define ltc_ltcs_ltss_cbc_base_alignment_shift_v() (0x0000000bU)
@@ -96,16 +98,16 @@
(((r) >> 0U) & 0xffffU) (((r) >> 0U) & 0xffffU)
#define ltc_ltcs_ltss_tstg_set_mgmt_r() (0x0017e2acU) #define ltc_ltcs_ltss_tstg_set_mgmt_r() (0x0017e2acU)
#define ltc_ltcs_ltss_tstg_set_mgmt_max_ways_evict_last_f(v)\ #define ltc_ltcs_ltss_tstg_set_mgmt_max_ways_evict_last_f(v)\
(((v)&0x1fU) << 16U) ((U32(v) & 0x1fU) << 16U)
#define ltc_ltcs_ltss_dstg_zbc_index_r() (0x0017e338U) #define ltc_ltcs_ltss_dstg_zbc_index_r() (0x0017e338U)
#define ltc_ltcs_ltss_dstg_zbc_index_address_f(v) (((v)&0xfU) << 0U) #define ltc_ltcs_ltss_dstg_zbc_index_address_f(v) ((U32(v) & 0xfU) << 0U)
#define ltc_ltcs_ltss_dstg_zbc_color_clear_value_r(i)\ #define ltc_ltcs_ltss_dstg_zbc_color_clear_value_r(i)\
(nvgpu_safe_add_u32(0x0017e33cU, nvgpu_safe_mult_u32((i), 4U))) (nvgpu_safe_add_u32(0x0017e33cU, nvgpu_safe_mult_u32((i), 4U)))
#define ltc_ltcs_ltss_dstg_zbc_color_clear_value__size_1_v() (0x00000004U) #define ltc_ltcs_ltss_dstg_zbc_color_clear_value__size_1_v() (0x00000004U)
#define ltc_ltcs_ltss_dstg_zbc_depth_clear_value_r() (0x0017e34cU) #define ltc_ltcs_ltss_dstg_zbc_depth_clear_value_r() (0x0017e34cU)
#define ltc_ltcs_ltss_dstg_zbc_depth_clear_value_field_s() (32U) #define ltc_ltcs_ltss_dstg_zbc_depth_clear_value_field_s() (32U)
#define ltc_ltcs_ltss_dstg_zbc_depth_clear_value_field_f(v)\ #define ltc_ltcs_ltss_dstg_zbc_depth_clear_value_field_f(v)\
(((v)&0xffffffffU) << 0U) ((U32(v) & 0xffffffffU) << 0U)
#define ltc_ltcs_ltss_dstg_zbc_depth_clear_value_field_m()\ #define ltc_ltcs_ltss_dstg_zbc_depth_clear_value_field_m()\
(U32(0xffffffffU) << 0U) (U32(0xffffffffU) << 0U)
#define ltc_ltcs_ltss_dstg_zbc_depth_clear_value_field_v(r)\ #define ltc_ltcs_ltss_dstg_zbc_depth_clear_value_field_v(r)\

6
drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_mc_gp106.h
View File

@@ -83,7 +83,7 @@
#define mc_enable_xbar_enabled_f() (0x4U) #define mc_enable_xbar_enabled_f() (0x4U)
#define mc_enable_l2_enabled_f() (0x8U) #define mc_enable_l2_enabled_f() (0x8U)
#define mc_enable_pmedia_s() (1U) #define mc_enable_pmedia_s() (1U)
#define mc_enable_pmedia_f(v) (((v)&0x1U) << 4U) #define mc_enable_pmedia_f(v) ((U32(v) & 0x1U) << 4U)
#define mc_enable_pmedia_m() (U32(0x1U) << 4U) #define mc_enable_pmedia_m() (U32(0x1U) << 4U)
#define mc_enable_pmedia_v(r) (((r) >> 4U) & 0x1U) #define mc_enable_pmedia_v(r) (((r) >> 4U) & 0x1U)
#define mc_enable_priv_ring_enabled_f() (0x20U) #define mc_enable_priv_ring_enabled_f() (0x20U)
@@ -102,12 +102,12 @@
#define mc_intr_ltc_r() (0x000001c0U) #define mc_intr_ltc_r() (0x000001c0U)
#define mc_enable_pb_r() (0x00000204U) #define mc_enable_pb_r() (0x00000204U)
#define mc_enable_pb_0_s() (1U) #define mc_enable_pb_0_s() (1U)
#define mc_enable_pb_0_f(v) (((v)&0x1U) << 0U) #define mc_enable_pb_0_f(v) ((U32(v) & 0x1U) << 0U)
#define mc_enable_pb_0_m() (U32(0x1U) << 0U) #define mc_enable_pb_0_m() (U32(0x1U) << 0U)
#define mc_enable_pb_0_v(r) (((r) >> 0U) & 0x1U) #define mc_enable_pb_0_v(r) (((r) >> 0U) & 0x1U)
#define mc_enable_pb_0_enabled_v() (0x00000001U) #define mc_enable_pb_0_enabled_v() (0x00000001U)
#define mc_enable_pb_sel_f(v, i)\ #define mc_enable_pb_sel_f(v, i)\
(((v) & 0x1) << (0U + i*1U)) ((U32(v) & 0x1U) << (0U + (i)*1U))
#define mc_elpg_enable_r() (0x0000020cU) #define mc_elpg_enable_r() (0x0000020cU)
#define mc_elpg_enable_xbar_enabled_f() (0x4U) #define mc_elpg_enable_xbar_enabled_f() (0x4U)
#define mc_elpg_enable_pfb_enabled_f() (0x100000U) #define mc_elpg_enable_pfb_enabled_f() (0x100000U)

16
drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_pbdma_gp106.h
View File

@@ -61,17 +61,17 @@
#define pbdma_gp_entry1_r() (0x10000004U) #define pbdma_gp_entry1_r() (0x10000004U)
#define pbdma_gp_entry1_get_hi_v(r) (((r) >> 0U) & 0xffU) #define pbdma_gp_entry1_get_hi_v(r) (((r) >> 0U) & 0xffU)
#define pbdma_gp_entry1_length_f(v) (((v)&0x1fffffU) << 10U) #define pbdma_gp_entry1_length_f(v) ((U32(v) & 0x1fffffU) << 10U)
#define pbdma_gp_entry1_length_v(r) (((r) >> 10U) & 0x1fffffU) #define pbdma_gp_entry1_length_v(r) (((r) >> 10U) & 0x1fffffU)
#define pbdma_gp_base_r(i)\ #define pbdma_gp_base_r(i)\
(nvgpu_safe_add_u32(0x00040048U, nvgpu_safe_mult_u32((i), 8192U))) (nvgpu_safe_add_u32(0x00040048U, nvgpu_safe_mult_u32((i), 8192U)))
#define pbdma_gp_base__size_1_v() (0x00000004U) #define pbdma_gp_base__size_1_v() (0x00000004U)
#define pbdma_gp_base_offset_f(v) (((v)&0x1fffffffU) << 3U) #define pbdma_gp_base_offset_f(v) ((U32(v) & 0x1fffffffU) << 3U)
#define pbdma_gp_base_rsvd_s() (3U) #define pbdma_gp_base_rsvd_s() (3U)
#define pbdma_gp_base_hi_r(i)\ #define pbdma_gp_base_hi_r(i)\
(nvgpu_safe_add_u32(0x0004004cU, nvgpu_safe_mult_u32((i), 8192U))) (nvgpu_safe_add_u32(0x0004004cU, nvgpu_safe_mult_u32((i), 8192U)))
#define pbdma_gp_base_hi_offset_f(v) (((v)&0xffU) << 0U) #define pbdma_gp_base_hi_offset_f(v) ((U32(v) & 0xffU) << 0U)
#define pbdma_gp_base_hi_limit2_f(v) (((v)&0x1fU) << 16U) #define pbdma_gp_base_hi_limit2_f(v) ((U32(v) & 0x1fU) << 16U)
#define pbdma_gp_fetch_r(i)\ #define pbdma_gp_fetch_r(i)\
(nvgpu_safe_add_u32(0x00040050U, nvgpu_safe_mult_u32((i), 8192U))) (nvgpu_safe_add_u32(0x00040050U, nvgpu_safe_mult_u32((i), 8192U)))
#define pbdma_gp_get_r(i)\ #define pbdma_gp_get_r(i)\
@@ -112,13 +112,13 @@
(nvgpu_safe_add_u32(0x00040114U, nvgpu_safe_mult_u32((i), 8192U))) (nvgpu_safe_add_u32(0x00040114U, nvgpu_safe_mult_u32((i), 8192U)))
#define pbdma_subdevice_r(i)\ #define pbdma_subdevice_r(i)\
(nvgpu_safe_add_u32(0x00040094U, nvgpu_safe_mult_u32((i), 8192U))) (nvgpu_safe_add_u32(0x00040094U, nvgpu_safe_mult_u32((i), 8192U)))
#define pbdma_subdevice_id_f(v) (((v)&0xfffU) << 0U) #define pbdma_subdevice_id_f(v) ((U32(v) & 0xfffU) << 0U)
#define pbdma_subdevice_status_active_f() (0x10000000U) #define pbdma_subdevice_status_active_f() (0x10000000U)
#define pbdma_subdevice_channel_dma_enable_f() (0x20000000U) #define pbdma_subdevice_channel_dma_enable_f() (0x20000000U)
#define pbdma_method0_r(i)\ #define pbdma_method0_r(i)\
(nvgpu_safe_add_u32(0x000400c0U, nvgpu_safe_mult_u32((i), 8192U))) (nvgpu_safe_add_u32(0x000400c0U, nvgpu_safe_mult_u32((i), 8192U)))
#define pbdma_method0_fifo_size_v() (0x00000004U) #define pbdma_method0_fifo_size_v() (0x00000004U)
#define pbdma_method0_addr_f(v) (((v)&0xfffU) << 2U) #define pbdma_method0_addr_f(v) ((U32(v) & 0xfffU) << 2U)
#define pbdma_method0_addr_v(r) (((r) >> 2U) & 0xfffU) #define pbdma_method0_addr_v(r) (((r) >> 2U) & 0xfffU)
#define pbdma_method0_subch_v(r) (((r) >> 16U) & 0x7U) #define pbdma_method0_subch_v(r) (((r) >> 16U) & 0x7U)
#define pbdma_method0_first_true_f() (0x400000U) #define pbdma_method0_first_true_f() (0x400000U)
@@ -154,10 +154,10 @@
#define pbdma_userd_target_vid_mem_f() (0x0U) #define pbdma_userd_target_vid_mem_f() (0x0U)
#define pbdma_userd_target_sys_mem_coh_f() (0x2U) #define pbdma_userd_target_sys_mem_coh_f() (0x2U)
#define pbdma_userd_target_sys_mem_ncoh_f() (0x3U) #define pbdma_userd_target_sys_mem_ncoh_f() (0x3U)
#define pbdma_userd_addr_f(v) (((v)&0x7fffffU) << 9U) #define pbdma_userd_addr_f(v) ((U32(v) & 0x7fffffU) << 9U)
#define pbdma_userd_hi_r(i)\ #define pbdma_userd_hi_r(i)\
(nvgpu_safe_add_u32(0x0004000cU, nvgpu_safe_mult_u32((i), 8192U))) (nvgpu_safe_add_u32(0x0004000cU, nvgpu_safe_mult_u32((i), 8192U)))
#define pbdma_userd_hi_addr_f(v) (((v)&0xffU) << 0U) #define pbdma_userd_hi_addr_f(v) ((U32(v) & 0xffU) << 0U)
#define pbdma_config_r(i)\ #define pbdma_config_r(i)\
(nvgpu_safe_add_u32(0x000400f4U, nvgpu_safe_mult_u32((i), 8192U))) (nvgpu_safe_add_u32(0x000400f4U, nvgpu_safe_mult_u32((i), 8192U)))
#define pbdma_config_auth_level_privileged_f() (0x100U) #define pbdma_config_auth_level_privileged_f() (0x100U)

20
drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_perf_gp106.h
View File

@@ -65,13 +65,13 @@
#define perf_pmasys_control_membuf_status_v(r) (((r) >> 4U) & 0x1U) #define perf_pmasys_control_membuf_status_v(r) (((r) >> 4U) & 0x1U)
#define perf_pmasys_control_membuf_status_overflowed_v() (0x00000001U) #define perf_pmasys_control_membuf_status_overflowed_v() (0x00000001U)
#define perf_pmasys_control_membuf_status_overflowed_f() (0x10U) #define perf_pmasys_control_membuf_status_overflowed_f() (0x10U)
#define perf_pmasys_control_membuf_clear_status_f(v) (((v)&0x1U) << 5U) #define perf_pmasys_control_membuf_clear_status_f(v) ((U32(v) & 0x1U) << 5U)
#define perf_pmasys_control_membuf_clear_status_v(r) (((r) >> 5U) & 0x1U) #define perf_pmasys_control_membuf_clear_status_v(r) (((r) >> 5U) & 0x1U)
#define perf_pmasys_control_membuf_clear_status_doit_v() (0x00000001U) #define perf_pmasys_control_membuf_clear_status_doit_v() (0x00000001U)
#define perf_pmasys_control_membuf_clear_status_doit_f() (0x20U) #define perf_pmasys_control_membuf_clear_status_doit_f() (0x20U)
#define perf_pmasys_mem_block_r() (0x001b4070U) #define perf_pmasys_mem_block_r() (0x001b4070U)
#define perf_pmasys_mem_block_base_f(v) (((v)&0xfffffffU) << 0U) #define perf_pmasys_mem_block_base_f(v) ((U32(v) & 0xfffffffU) << 0U)
#define perf_pmasys_mem_block_target_f(v) (((v)&0x3U) << 28U) #define perf_pmasys_mem_block_target_f(v) ((U32(v) & 0x3U) << 28U)
#define perf_pmasys_mem_block_target_v(r) (((r) >> 28U) & 0x3U) #define perf_pmasys_mem_block_target_v(r) (((r) >> 28U) & 0x3U)
#define perf_pmasys_mem_block_target_lfb_v() (0x00000000U) #define perf_pmasys_mem_block_target_lfb_v() (0x00000000U)
#define perf_pmasys_mem_block_target_lfb_f() (0x0U) #define perf_pmasys_mem_block_target_lfb_f() (0x0U)
@@ -79,24 +79,24 @@
#define perf_pmasys_mem_block_target_sys_coh_f() (0x20000000U) #define perf_pmasys_mem_block_target_sys_coh_f() (0x20000000U)
#define perf_pmasys_mem_block_target_sys_ncoh_v() (0x00000003U) #define perf_pmasys_mem_block_target_sys_ncoh_v() (0x00000003U)
#define perf_pmasys_mem_block_target_sys_ncoh_f() (0x30000000U) #define perf_pmasys_mem_block_target_sys_ncoh_f() (0x30000000U)
#define perf_pmasys_mem_block_valid_f(v) (((v)&0x1U) << 31U) #define perf_pmasys_mem_block_valid_f(v) ((U32(v) & 0x1U) << 31U)
#define perf_pmasys_mem_block_valid_v(r) (((r) >> 31U) & 0x1U) #define perf_pmasys_mem_block_valid_v(r) (((r) >> 31U) & 0x1U)
#define perf_pmasys_mem_block_valid_true_v() (0x00000001U) #define perf_pmasys_mem_block_valid_true_v() (0x00000001U)
#define perf_pmasys_mem_block_valid_true_f() (0x80000000U) #define perf_pmasys_mem_block_valid_true_f() (0x80000000U)
#define perf_pmasys_mem_block_valid_false_v() (0x00000000U) #define perf_pmasys_mem_block_valid_false_v() (0x00000000U)
#define perf_pmasys_mem_block_valid_false_f() (0x0U) #define perf_pmasys_mem_block_valid_false_f() (0x0U)
#define perf_pmasys_outbase_r() (0x001b4074U) #define perf_pmasys_outbase_r() (0x001b4074U)
#define perf_pmasys_outbase_ptr_f(v) (((v)&0x7ffffffU) << 5U) #define perf_pmasys_outbase_ptr_f(v) ((U32(v) & 0x7ffffffU) << 5U)
#define perf_pmasys_outbaseupper_r() (0x001b4078U) #define perf_pmasys_outbaseupper_r() (0x001b4078U)
#define perf_pmasys_outbaseupper_ptr_f(v) (((v)&0xffU) << 0U) #define perf_pmasys_outbaseupper_ptr_f(v) ((U32(v) & 0xffU) << 0U)
#define perf_pmasys_outsize_r() (0x001b407cU) #define perf_pmasys_outsize_r() (0x001b407cU)
#define perf_pmasys_outsize_numbytes_f(v) (((v)&0x7ffffffU) << 5U) #define perf_pmasys_outsize_numbytes_f(v) ((U32(v) & 0x7ffffffU) << 5U)
#define perf_pmasys_mem_bytes_r() (0x001b4084U) #define perf_pmasys_mem_bytes_r() (0x001b4084U)
#define perf_pmasys_mem_bytes_numbytes_f(v) (((v)&0xfffffffU) << 4U) #define perf_pmasys_mem_bytes_numbytes_f(v) ((U32(v) & 0xfffffffU) << 4U)
#define perf_pmasys_mem_bump_r() (0x001b4088U) #define perf_pmasys_mem_bump_r() (0x001b4088U)
#define perf_pmasys_mem_bump_numbytes_f(v) (((v)&0xfffffffU) << 4U) #define perf_pmasys_mem_bump_numbytes_f(v) ((U32(v) & 0xfffffffU) << 4U)
#define perf_pmasys_enginestatus_r() (0x001b40a4U) #define perf_pmasys_enginestatus_r() (0x001b40a4U)
#define perf_pmasys_enginestatus_rbufempty_f(v) (((v)&0x1U) << 4U) #define perf_pmasys_enginestatus_rbufempty_f(v) ((U32(v) & 0x1U) << 4U)
#define perf_pmasys_enginestatus_rbufempty_empty_v() (0x00000001U) #define perf_pmasys_enginestatus_rbufempty_empty_v() (0x00000001U)
#define perf_pmasys_enginestatus_rbufempty_empty_f() (0x10U) #define perf_pmasys_enginestatus_rbufempty_empty_f() (0x10U)
#endif #endif

112
drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_psec_gp106.h
View File

@@ -68,44 +68,44 @@
#define psec_falcon_irqstat_swgen0_true_f() (0x40U) #define psec_falcon_irqstat_swgen0_true_f() (0x40U)
#define psec_falcon_irqmode_r() (0x0008700cU) #define psec_falcon_irqmode_r() (0x0008700cU)
#define psec_falcon_irqmset_r() (0x00087010U) #define psec_falcon_irqmset_r() (0x00087010U)
#define psec_falcon_irqmset_gptmr_f(v) (((v)&0x1U) << 0U) #define psec_falcon_irqmset_gptmr_f(v) ((U32(v) & 0x1U) << 0U)
#define psec_falcon_irqmset_wdtmr_f(v) (((v)&0x1U) << 1U) #define psec_falcon_irqmset_wdtmr_f(v) ((U32(v) & 0x1U) << 1U)
#define psec_falcon_irqmset_mthd_f(v) (((v)&0x1U) << 2U) #define psec_falcon_irqmset_mthd_f(v) ((U32(v) & 0x1U) << 2U)
#define psec_falcon_irqmset_ctxsw_f(v) (((v)&0x1U) << 3U) #define psec_falcon_irqmset_ctxsw_f(v) ((U32(v) & 0x1U) << 3U)
#define psec_falcon_irqmset_halt_f(v) (((v)&0x1U) << 4U) #define psec_falcon_irqmset_halt_f(v) ((U32(v) & 0x1U) << 4U)
#define psec_falcon_irqmset_exterr_f(v) (((v)&0x1U) << 5U) #define psec_falcon_irqmset_exterr_f(v) ((U32(v) & 0x1U) << 5U)
#define psec_falcon_irqmset_swgen0_f(v) (((v)&0x1U) << 6U) #define psec_falcon_irqmset_swgen0_f(v) ((U32(v) & 0x1U) << 6U)
#define psec_falcon_irqmset_swgen1_f(v) (((v)&0x1U) << 7U) #define psec_falcon_irqmset_swgen1_f(v) ((U32(v) & 0x1U) << 7U)
#define psec_falcon_irqmclr_r() (0x00087014U) #define psec_falcon_irqmclr_r() (0x00087014U)
#define psec_falcon_irqmclr_gptmr_f(v) (((v)&0x1U) << 0U) #define psec_falcon_irqmclr_gptmr_f(v) ((U32(v) & 0x1U) << 0U)
#define psec_falcon_irqmclr_wdtmr_f(v) (((v)&0x1U) << 1U) #define psec_falcon_irqmclr_wdtmr_f(v) ((U32(v) & 0x1U) << 1U)
#define psec_falcon_irqmclr_mthd_f(v) (((v)&0x1U) << 2U) #define psec_falcon_irqmclr_mthd_f(v) ((U32(v) & 0x1U) << 2U)
#define psec_falcon_irqmclr_ctxsw_f(v) (((v)&0x1U) << 3U) #define psec_falcon_irqmclr_ctxsw_f(v) ((U32(v) & 0x1U) << 3U)
#define psec_falcon_irqmclr_halt_f(v) (((v)&0x1U) << 4U) #define psec_falcon_irqmclr_halt_f(v) ((U32(v) & 0x1U) << 4U)
#define psec_falcon_irqmclr_exterr_f(v) (((v)&0x1U) << 5U) #define psec_falcon_irqmclr_exterr_f(v) ((U32(v) & 0x1U) << 5U)
#define psec_falcon_irqmclr_swgen0_f(v) (((v)&0x1U) << 6U) #define psec_falcon_irqmclr_swgen0_f(v) ((U32(v) & 0x1U) << 6U)
#define psec_falcon_irqmclr_swgen1_f(v) (((v)&0x1U) << 7U) #define psec_falcon_irqmclr_swgen1_f(v) ((U32(v) & 0x1U) << 7U)
#define psec_falcon_irqmclr_ext_f(v) (((v)&0xffU) << 8U) #define psec_falcon_irqmclr_ext_f(v) ((U32(v) & 0xffU) << 8U)
#define psec_falcon_irqmask_r() (0x00087018U) #define psec_falcon_irqmask_r() (0x00087018U)
#define psec_falcon_irqdest_r() (0x0008701cU) #define psec_falcon_irqdest_r() (0x0008701cU)
#define psec_falcon_irqdest_host_gptmr_f(v) (((v)&0x1U) << 0U) #define psec_falcon_irqdest_host_gptmr_f(v) ((U32(v) & 0x1U) << 0U)
#define psec_falcon_irqdest_host_wdtmr_f(v) (((v)&0x1U) << 1U) #define psec_falcon_irqdest_host_wdtmr_f(v) ((U32(v) & 0x1U) << 1U)
#define psec_falcon_irqdest_host_mthd_f(v) (((v)&0x1U) << 2U) #define psec_falcon_irqdest_host_mthd_f(v) ((U32(v) & 0x1U) << 2U)
#define psec_falcon_irqdest_host_ctxsw_f(v) (((v)&0x1U) << 3U) #define psec_falcon_irqdest_host_ctxsw_f(v) ((U32(v) & 0x1U) << 3U)
#define psec_falcon_irqdest_host_halt_f(v) (((v)&0x1U) << 4U) #define psec_falcon_irqdest_host_halt_f(v) ((U32(v) & 0x1U) << 4U)
#define psec_falcon_irqdest_host_exterr_f(v) (((v)&0x1U) << 5U) #define psec_falcon_irqdest_host_exterr_f(v) ((U32(v) & 0x1U) << 5U)
#define psec_falcon_irqdest_host_swgen0_f(v) (((v)&0x1U) << 6U) #define psec_falcon_irqdest_host_swgen0_f(v) ((U32(v) & 0x1U) << 6U)
#define psec_falcon_irqdest_host_swgen1_f(v) (((v)&0x1U) << 7U) #define psec_falcon_irqdest_host_swgen1_f(v) ((U32(v) & 0x1U) << 7U)
#define psec_falcon_irqdest_host_ext_f(v) (((v)&0xffU) << 8U) #define psec_falcon_irqdest_host_ext_f(v) ((U32(v) & 0xffU) << 8U)
#define psec_falcon_irqdest_target_gptmr_f(v) (((v)&0x1U) << 16U) #define psec_falcon_irqdest_target_gptmr_f(v) ((U32(v) & 0x1U) << 16U)
#define psec_falcon_irqdest_target_wdtmr_f(v) (((v)&0x1U) << 17U) #define psec_falcon_irqdest_target_wdtmr_f(v) ((U32(v) & 0x1U) << 17U)
#define psec_falcon_irqdest_target_mthd_f(v) (((v)&0x1U) << 18U) #define psec_falcon_irqdest_target_mthd_f(v) ((U32(v) & 0x1U) << 18U)
#define psec_falcon_irqdest_target_ctxsw_f(v) (((v)&0x1U) << 19U) #define psec_falcon_irqdest_target_ctxsw_f(v) ((U32(v) & 0x1U) << 19U)
#define psec_falcon_irqdest_target_halt_f(v) (((v)&0x1U) << 20U) #define psec_falcon_irqdest_target_halt_f(v) ((U32(v) & 0x1U) << 20U)
#define psec_falcon_irqdest_target_exterr_f(v) (((v)&0x1U) << 21U) #define psec_falcon_irqdest_target_exterr_f(v) ((U32(v) & 0x1U) << 21U)
#define psec_falcon_irqdest_target_swgen0_f(v) (((v)&0x1U) << 22U) #define psec_falcon_irqdest_target_swgen0_f(v) ((U32(v) & 0x1U) << 22U)
#define psec_falcon_irqdest_target_swgen1_f(v) (((v)&0x1U) << 23U) #define psec_falcon_irqdest_target_swgen1_f(v) ((U32(v) & 0x1U) << 23U)
#define psec_falcon_irqdest_target_ext_f(v) (((v)&0xffU) << 24U) #define psec_falcon_irqdest_target_ext_f(v) ((U32(v) & 0xffU) << 24U)
#define psec_falcon_curctx_r() (0x00087050U) #define psec_falcon_curctx_r() (0x00087050U)
#define psec_falcon_nxtctx_r() (0x00087054U) #define psec_falcon_nxtctx_r() (0x00087054U)
#define psec_falcon_mailbox0_r() (0x00087040U) #define psec_falcon_mailbox0_r() (0x00087040U)
@@ -118,20 +118,20 @@
#define psec_falcon_os_r() (0x00087080U) #define psec_falcon_os_r() (0x00087080U)
#define psec_falcon_engctl_r() (0x000870a4U) #define psec_falcon_engctl_r() (0x000870a4U)
#define psec_falcon_cpuctl_r() (0x00087100U) #define psec_falcon_cpuctl_r() (0x00087100U)
#define psec_falcon_cpuctl_startcpu_f(v) (((v)&0x1U) << 1U) #define psec_falcon_cpuctl_startcpu_f(v) ((U32(v) & 0x1U) << 1U)
#define psec_falcon_cpuctl_halt_intr_f(v) (((v)&0x1U) << 4U) #define psec_falcon_cpuctl_halt_intr_f(v) ((U32(v) & 0x1U) << 4U)
#define psec_falcon_cpuctl_halt_intr_m() (U32(0x1U) << 4U) #define psec_falcon_cpuctl_halt_intr_m() (U32(0x1U) << 4U)
#define psec_falcon_cpuctl_halt_intr_v(r) (((r) >> 4U) & 0x1U) #define psec_falcon_cpuctl_halt_intr_v(r) (((r) >> 4U) & 0x1U)
#define psec_falcon_cpuctl_cpuctl_alias_en_f(v) (((v)&0x1U) << 6U) #define psec_falcon_cpuctl_cpuctl_alias_en_f(v) ((U32(v) & 0x1U) << 6U)
#define psec_falcon_cpuctl_cpuctl_alias_en_m() (U32(0x1U) << 6U) #define psec_falcon_cpuctl_cpuctl_alias_en_m() (U32(0x1U) << 6U)
#define psec_falcon_cpuctl_cpuctl_alias_en_v(r) (((r) >> 6U) & 0x1U) #define psec_falcon_cpuctl_cpuctl_alias_en_v(r) (((r) >> 6U) & 0x1U)
#define psec_falcon_cpuctl_alias_r() (0x00087130U) #define psec_falcon_cpuctl_alias_r() (0x00087130U)
#define psec_falcon_cpuctl_alias_startcpu_f(v) (((v)&0x1U) << 1U) #define psec_falcon_cpuctl_alias_startcpu_f(v) ((U32(v) & 0x1U) << 1U)
#define psec_falcon_imemc_r(i)\ #define psec_falcon_imemc_r(i)\
(nvgpu_safe_add_u32(0x00087180U, nvgpu_safe_mult_u32((i), 16U))) (nvgpu_safe_add_u32(0x00087180U, nvgpu_safe_mult_u32((i), 16U)))
#define psec_falcon_imemc_offs_f(v) (((v)&0x3fU) << 2U) #define psec_falcon_imemc_offs_f(v) ((U32(v) & 0x3fU) << 2U)
#define psec_falcon_imemc_blk_f(v) (((v)&0xffU) << 8U) #define psec_falcon_imemc_blk_f(v) ((U32(v) & 0xffU) << 8U)
#define psec_falcon_imemc_aincw_f(v) (((v)&0x1U) << 24U) #define psec_falcon_imemc_aincw_f(v) ((U32(v) & 0x1U) << 24U)
#define psec_falcon_imemd_r(i)\ #define psec_falcon_imemd_r(i)\
(nvgpu_safe_add_u32(0x00087184U, nvgpu_safe_mult_u32((i), 16U))) (nvgpu_safe_add_u32(0x00087184U, nvgpu_safe_mult_u32((i), 16U)))
#define psec_falcon_imemt_r(i)\ #define psec_falcon_imemt_r(i)\
@@ -139,11 +139,11 @@
#define psec_falcon_sctl_r() (0x00087240U) #define psec_falcon_sctl_r() (0x00087240U)
#define psec_falcon_mmu_phys_sec_r() (0x00100ce4U) #define psec_falcon_mmu_phys_sec_r() (0x00100ce4U)
#define psec_falcon_bootvec_r() (0x00087104U) #define psec_falcon_bootvec_r() (0x00087104U)
#define psec_falcon_bootvec_vec_f(v) (((v)&0xffffffffU) << 0U) #define psec_falcon_bootvec_vec_f(v) ((U32(v) & 0xffffffffU) << 0U)
#define psec_falcon_dmactl_r() (0x0008710cU) #define psec_falcon_dmactl_r() (0x0008710cU)
#define psec_falcon_dmactl_dmem_scrubbing_m() (U32(0x1U) << 1U) #define psec_falcon_dmactl_dmem_scrubbing_m() (U32(0x1U) << 1U)
#define psec_falcon_dmactl_imem_scrubbing_m() (U32(0x1U) << 2U) #define psec_falcon_dmactl_imem_scrubbing_m() (U32(0x1U) << 2U)
#define psec_falcon_dmactl_require_ctx_f(v) (((v)&0x1U) << 0U) #define psec_falcon_dmactl_require_ctx_f(v) ((U32(v) & 0x1U) << 0U)
#define psec_falcon_hwcfg_r() (0x00087108U) #define psec_falcon_hwcfg_r() (0x00087108U)
#define psec_falcon_hwcfg_imem_size_v(r) (((r) >> 0U) & 0x1ffU) #define psec_falcon_hwcfg_imem_size_v(r) (((r) >> 0U) & 0x1ffU)
#define psec_falcon_hwcfg_dmem_size_v(r) (((r) >> 9U) & 0x1ffU) #define psec_falcon_hwcfg_dmem_size_v(r) (((r) >> 9U) & 0x1ffU)
@@ -151,10 +151,10 @@
#define psec_falcon_dmatrfbase1_r() (0x00087128U) #define psec_falcon_dmatrfbase1_r() (0x00087128U)
#define psec_falcon_dmatrfmoffs_r() (0x00087114U) #define psec_falcon_dmatrfmoffs_r() (0x00087114U)
#define psec_falcon_dmatrfcmd_r() (0x00087118U) #define psec_falcon_dmatrfcmd_r() (0x00087118U)
#define psec_falcon_dmatrfcmd_imem_f(v) (((v)&0x1U) << 4U) #define psec_falcon_dmatrfcmd_imem_f(v) ((U32(v) & 0x1U) << 4U)
#define psec_falcon_dmatrfcmd_write_f(v) (((v)&0x1U) << 5U) #define psec_falcon_dmatrfcmd_write_f(v) ((U32(v) & 0x1U) << 5U)
#define psec_falcon_dmatrfcmd_size_f(v) (((v)&0x7U) << 8U) #define psec_falcon_dmatrfcmd_size_f(v) ((U32(v) & 0x7U) << 8U)
#define psec_falcon_dmatrfcmd_ctxdma_f(v) (((v)&0x7U) << 12U) #define psec_falcon_dmatrfcmd_ctxdma_f(v) ((U32(v) & 0x7U) << 12U)
#define psec_falcon_dmatrffboffs_r() (0x0008711cU) #define psec_falcon_dmatrffboffs_r() (0x0008711cU)
#define psec_falcon_exterraddr_r() (0x00087168U) #define psec_falcon_exterraddr_r() (0x00087168U)
#define psec_falcon_exterrstat_r() (0x0008716cU) #define psec_falcon_exterrstat_r() (0x0008716cU)
@@ -163,26 +163,26 @@
#define psec_falcon_exterrstat_valid_true_v() (0x00000001U) #define psec_falcon_exterrstat_valid_true_v() (0x00000001U)
#define psec_sec2_falcon_icd_cmd_r() (0x00087200U) #define psec_sec2_falcon_icd_cmd_r() (0x00087200U)
#define psec_sec2_falcon_icd_cmd_opc_s() (4U) #define psec_sec2_falcon_icd_cmd_opc_s() (4U)
#define psec_sec2_falcon_icd_cmd_opc_f(v) (((v)&0xfU) << 0U) #define psec_sec2_falcon_icd_cmd_opc_f(v) ((U32(v) & 0xfU) << 0U)
#define psec_sec2_falcon_icd_cmd_opc_m() (U32(0xfU) << 0U) #define psec_sec2_falcon_icd_cmd_opc_m() (U32(0xfU) << 0U)
#define psec_sec2_falcon_icd_cmd_opc_v(r) (((r) >> 0U) & 0xfU) #define psec_sec2_falcon_icd_cmd_opc_v(r) (((r) >> 0U) & 0xfU)
#define psec_sec2_falcon_icd_cmd_opc_rreg_f() (0x8U) #define psec_sec2_falcon_icd_cmd_opc_rreg_f() (0x8U)
#define psec_sec2_falcon_icd_cmd_opc_rstat_f() (0xeU) #define psec_sec2_falcon_icd_cmd_opc_rstat_f() (0xeU)
#define psec_sec2_falcon_icd_cmd_idx_f(v) (((v)&0x1fU) << 8U) #define psec_sec2_falcon_icd_cmd_idx_f(v) ((U32(v) & 0x1fU) << 8U)
#define psec_sec2_falcon_icd_rdata_r() (0x0008720cU) #define psec_sec2_falcon_icd_rdata_r() (0x0008720cU)
#define psec_falcon_dmemc_r(i)\ #define psec_falcon_dmemc_r(i)\
(nvgpu_safe_add_u32(0x000871c0U, nvgpu_safe_mult_u32((i), 8U))) (nvgpu_safe_add_u32(0x000871c0U, nvgpu_safe_mult_u32((i), 8U)))
#define psec_falcon_dmemc_offs_f(v) (((v)&0x3fU) << 2U) #define psec_falcon_dmemc_offs_f(v) ((U32(v) & 0x3fU) << 2U)
#define psec_falcon_dmemc_offs_m() (U32(0x3fU) << 2U) #define psec_falcon_dmemc_offs_m() (U32(0x3fU) << 2U)
#define psec_falcon_dmemc_blk_f(v) (((v)&0xffU) << 8U) #define psec_falcon_dmemc_blk_f(v) ((U32(v) & 0xffU) << 8U)
#define psec_falcon_dmemc_blk_m() (U32(0xffU) << 8U) #define psec_falcon_dmemc_blk_m() (U32(0xffU) << 8U)
#define psec_falcon_dmemc_aincw_f(v) (((v)&0x1U) << 24U) #define psec_falcon_dmemc_aincw_f(v) ((U32(v) & 0x1U) << 24U)
#define psec_falcon_dmemc_aincr_f(v) (((v)&0x1U) << 25U) #define psec_falcon_dmemc_aincr_f(v) ((U32(v) & 0x1U) << 25U)
#define psec_falcon_dmemd_r(i)\ #define psec_falcon_dmemd_r(i)\
(nvgpu_safe_add_u32(0x000871c4U, nvgpu_safe_mult_u32((i), 8U))) (nvgpu_safe_add_u32(0x000871c4U, nvgpu_safe_mult_u32((i), 8U)))
#define psec_falcon_debug1_r() (0x00087090U) #define psec_falcon_debug1_r() (0x00087090U)
#define psec_falcon_debug1_ctxsw_mode_s() (1U) #define psec_falcon_debug1_ctxsw_mode_s() (1U)
#define psec_falcon_debug1_ctxsw_mode_f(v) (((v)&0x1U) << 16U) #define psec_falcon_debug1_ctxsw_mode_f(v) ((U32(v) & 0x1U) << 16U)
#define psec_falcon_debug1_ctxsw_mode_m() (U32(0x1U) << 16U) #define psec_falcon_debug1_ctxsw_mode_m() (U32(0x1U) << 16U)
#define psec_falcon_debug1_ctxsw_mode_v(r) (((r) >> 16U) & 0x1U) #define psec_falcon_debug1_ctxsw_mode_v(r) (((r) >> 16U) & 0x1U)
#define psec_falcon_debug1_ctxsw_mode_init_f() (0x0U) #define psec_falcon_debug1_ctxsw_mode_init_f() (0x0U)
@@ -192,7 +192,7 @@
#define psec_fbif_transcfg_target_coherent_sysmem_f() (0x1U) #define psec_fbif_transcfg_target_coherent_sysmem_f() (0x1U)
#define psec_fbif_transcfg_target_noncoherent_sysmem_f() (0x2U) #define psec_fbif_transcfg_target_noncoherent_sysmem_f() (0x2U)
#define psec_fbif_transcfg_mem_type_s() (1U) #define psec_fbif_transcfg_mem_type_s() (1U)
#define psec_fbif_transcfg_mem_type_f(v) (((v)&0x1U) << 2U) #define psec_fbif_transcfg_mem_type_f(v) ((U32(v) & 0x1U) << 2U)
#define psec_fbif_transcfg_mem_type_m() (U32(0x1U) << 2U) #define psec_fbif_transcfg_mem_type_m() (U32(0x1U) << 2U)
#define psec_fbif_transcfg_mem_type_v(r) (((r) >> 2U) & 0x1U) #define psec_fbif_transcfg_mem_type_v(r) (((r) >> 2U) & 0x1U)
#define psec_fbif_transcfg_mem_type_virtual_f() (0x0U) #define psec_fbif_transcfg_mem_type_virtual_f() (0x0U)

138
drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_pwr_gp106.h
View File

@@ -68,44 +68,44 @@
#define pwr_falcon_irqstat_swgen0_true_f() (0x40U) #define pwr_falcon_irqstat_swgen0_true_f() (0x40U)
#define pwr_falcon_irqmode_r() (0x0010a00cU) #define pwr_falcon_irqmode_r() (0x0010a00cU)
#define pwr_falcon_irqmset_r() (0x0010a010U) #define pwr_falcon_irqmset_r() (0x0010a010U)
#define pwr_falcon_irqmset_gptmr_f(v) (((v)&0x1U) << 0U) #define pwr_falcon_irqmset_gptmr_f(v) ((U32(v) & 0x1U) << 0U)
#define pwr_falcon_irqmset_wdtmr_f(v) (((v)&0x1U) << 1U) #define pwr_falcon_irqmset_wdtmr_f(v) ((U32(v) & 0x1U) << 1U)
#define pwr_falcon_irqmset_mthd_f(v) (((v)&0x1U) << 2U) #define pwr_falcon_irqmset_mthd_f(v) ((U32(v) & 0x1U) << 2U)
#define pwr_falcon_irqmset_ctxsw_f(v) (((v)&0x1U) << 3U) #define pwr_falcon_irqmset_ctxsw_f(v) ((U32(v) & 0x1U) << 3U)
#define pwr_falcon_irqmset_halt_f(v) (((v)&0x1U) << 4U) #define pwr_falcon_irqmset_halt_f(v) ((U32(v) & 0x1U) << 4U)
#define pwr_falcon_irqmset_exterr_f(v) (((v)&0x1U) << 5U) #define pwr_falcon_irqmset_exterr_f(v) ((U32(v) & 0x1U) << 5U)
#define pwr_falcon_irqmset_swgen0_f(v) (((v)&0x1U) << 6U) #define pwr_falcon_irqmset_swgen0_f(v) ((U32(v) & 0x1U) << 6U)
#define pwr_falcon_irqmset_swgen1_f(v) (((v)&0x1U) << 7U) #define pwr_falcon_irqmset_swgen1_f(v) ((U32(v) & 0x1U) << 7U)
#define pwr_falcon_irqmclr_r() (0x0010a014U) #define pwr_falcon_irqmclr_r() (0x0010a014U)
#define pwr_falcon_irqmclr_gptmr_f(v) (((v)&0x1U) << 0U) #define pwr_falcon_irqmclr_gptmr_f(v) ((U32(v) & 0x1U) << 0U)
#define pwr_falcon_irqmclr_wdtmr_f(v) (((v)&0x1U) << 1U) #define pwr_falcon_irqmclr_wdtmr_f(v) ((U32(v) & 0x1U) << 1U)
#define pwr_falcon_irqmclr_mthd_f(v) (((v)&0x1U) << 2U) #define pwr_falcon_irqmclr_mthd_f(v) ((U32(v) & 0x1U) << 2U)
#define pwr_falcon_irqmclr_ctxsw_f(v) (((v)&0x1U) << 3U) #define pwr_falcon_irqmclr_ctxsw_f(v) ((U32(v) & 0x1U) << 3U)
#define pwr_falcon_irqmclr_halt_f(v) (((v)&0x1U) << 4U) #define pwr_falcon_irqmclr_halt_f(v) ((U32(v) & 0x1U) << 4U)
#define pwr_falcon_irqmclr_exterr_f(v) (((v)&0x1U) << 5U) #define pwr_falcon_irqmclr_exterr_f(v) ((U32(v) & 0x1U) << 5U)
#define pwr_falcon_irqmclr_swgen0_f(v) (((v)&0x1U) << 6U) #define pwr_falcon_irqmclr_swgen0_f(v) ((U32(v) & 0x1U) << 6U)
#define pwr_falcon_irqmclr_swgen1_f(v) (((v)&0x1U) << 7U) #define pwr_falcon_irqmclr_swgen1_f(v) ((U32(v) & 0x1U) << 7U)
#define pwr_falcon_irqmclr_ext_f(v) (((v)&0xffU) << 8U) #define pwr_falcon_irqmclr_ext_f(v) ((U32(v) & 0xffU) << 8U)
#define pwr_falcon_irqmask_r() (0x0010a018U) #define pwr_falcon_irqmask_r() (0x0010a018U)
#define pwr_falcon_irqdest_r() (0x0010a01cU) #define pwr_falcon_irqdest_r() (0x0010a01cU)
#define pwr_falcon_irqdest_host_gptmr_f(v) (((v)&0x1U) << 0U) #define pwr_falcon_irqdest_host_gptmr_f(v) ((U32(v) & 0x1U) << 0U)
#define pwr_falcon_irqdest_host_wdtmr_f(v) (((v)&0x1U) << 1U) #define pwr_falcon_irqdest_host_wdtmr_f(v) ((U32(v) & 0x1U) << 1U)
#define pwr_falcon_irqdest_host_mthd_f(v) (((v)&0x1U) << 2U) #define pwr_falcon_irqdest_host_mthd_f(v) ((U32(v) & 0x1U) << 2U)
#define pwr_falcon_irqdest_host_ctxsw_f(v) (((v)&0x1U) << 3U) #define pwr_falcon_irqdest_host_ctxsw_f(v) ((U32(v) & 0x1U) << 3U)
#define pwr_falcon_irqdest_host_halt_f(v) (((v)&0x1U) << 4U) #define pwr_falcon_irqdest_host_halt_f(v) ((U32(v) & 0x1U) << 4U)
#define pwr_falcon_irqdest_host_exterr_f(v) (((v)&0x1U) << 5U) #define pwr_falcon_irqdest_host_exterr_f(v) ((U32(v) & 0x1U) << 5U)
#define pwr_falcon_irqdest_host_swgen0_f(v) (((v)&0x1U) << 6U) #define pwr_falcon_irqdest_host_swgen0_f(v) ((U32(v) & 0x1U) << 6U)
#define pwr_falcon_irqdest_host_swgen1_f(v) (((v)&0x1U) << 7U) #define pwr_falcon_irqdest_host_swgen1_f(v) ((U32(v) & 0x1U) << 7U)
#define pwr_falcon_irqdest_host_ext_f(v) (((v)&0xffU) << 8U) #define pwr_falcon_irqdest_host_ext_f(v) ((U32(v) & 0xffU) << 8U)
#define pwr_falcon_irqdest_target_gptmr_f(v) (((v)&0x1U) << 16U) #define pwr_falcon_irqdest_target_gptmr_f(v) ((U32(v) & 0x1U) << 16U)
#define pwr_falcon_irqdest_target_wdtmr_f(v) (((v)&0x1U) << 17U) #define pwr_falcon_irqdest_target_wdtmr_f(v) ((U32(v) & 0x1U) << 17U)
#define pwr_falcon_irqdest_target_mthd_f(v) (((v)&0x1U) << 18U) #define pwr_falcon_irqdest_target_mthd_f(v) ((U32(v) & 0x1U) << 18U)
#define pwr_falcon_irqdest_target_ctxsw_f(v) (((v)&0x1U) << 19U) #define pwr_falcon_irqdest_target_ctxsw_f(v) ((U32(v) & 0x1U) << 19U)
#define pwr_falcon_irqdest_target_halt_f(v) (((v)&0x1U) << 20U) #define pwr_falcon_irqdest_target_halt_f(v) ((U32(v) & 0x1U) << 20U)
#define pwr_falcon_irqdest_target_exterr_f(v) (((v)&0x1U) << 21U) #define pwr_falcon_irqdest_target_exterr_f(v) ((U32(v) & 0x1U) << 21U)
#define pwr_falcon_irqdest_target_swgen0_f(v) (((v)&0x1U) << 22U) #define pwr_falcon_irqdest_target_swgen0_f(v) ((U32(v) & 0x1U) << 22U)
#define pwr_falcon_irqdest_target_swgen1_f(v) (((v)&0x1U) << 23U) #define pwr_falcon_irqdest_target_swgen1_f(v) ((U32(v) & 0x1U) << 23U)
#define pwr_falcon_irqdest_target_ext_f(v) (((v)&0xffU) << 24U) #define pwr_falcon_irqdest_target_ext_f(v) ((U32(v) & 0xffU) << 24U)
#define pwr_falcon_curctx_r() (0x0010a050U) #define pwr_falcon_curctx_r() (0x0010a050U)
#define pwr_falcon_nxtctx_r() (0x0010a054U) #define pwr_falcon_nxtctx_r() (0x0010a054U)
#define pwr_falcon_mailbox0_r() (0x0010a040U) #define pwr_falcon_mailbox0_r() (0x0010a040U)
@@ -118,24 +118,24 @@
#define pwr_falcon_os_r() (0x0010a080U) #define pwr_falcon_os_r() (0x0010a080U)
#define pwr_falcon_engctl_r() (0x0010a0a4U) #define pwr_falcon_engctl_r() (0x0010a0a4U)
#define pwr_falcon_cpuctl_r() (0x0010a100U) #define pwr_falcon_cpuctl_r() (0x0010a100U)
#define pwr_falcon_cpuctl_startcpu_f(v) (((v)&0x1U) << 1U) #define pwr_falcon_cpuctl_startcpu_f(v) ((U32(v) & 0x1U) << 1U)
#define pwr_falcon_cpuctl_halt_intr_f(v) (((v)&0x1U) << 4U) #define pwr_falcon_cpuctl_halt_intr_f(v) ((U32(v) & 0x1U) << 4U)
#define pwr_falcon_cpuctl_halt_intr_m() (U32(0x1U) << 4U) #define pwr_falcon_cpuctl_halt_intr_m() (U32(0x1U) << 4U)
#define pwr_falcon_cpuctl_halt_intr_v(r) (((r) >> 4U) & 0x1U) #define pwr_falcon_cpuctl_halt_intr_v(r) (((r) >> 4U) & 0x1U)
#define pwr_falcon_cpuctl_cpuctl_alias_en_f(v) (((v)&0x1U) << 6U) #define pwr_falcon_cpuctl_cpuctl_alias_en_f(v) ((U32(v) & 0x1U) << 6U)
#define pwr_falcon_cpuctl_cpuctl_alias_en_m() (U32(0x1U) << 6U) #define pwr_falcon_cpuctl_cpuctl_alias_en_m() (U32(0x1U) << 6U)
#define pwr_falcon_cpuctl_cpuctl_alias_en_v(r) (((r) >> 6U) & 0x1U) #define pwr_falcon_cpuctl_cpuctl_alias_en_v(r) (((r) >> 6U) & 0x1U)
#define pwr_falcon_cpuctl_alias_r() (0x0010a130U) #define pwr_falcon_cpuctl_alias_r() (0x0010a130U)
#define pwr_falcon_cpuctl_alias_startcpu_f(v) (((v)&0x1U) << 1U) #define pwr_falcon_cpuctl_alias_startcpu_f(v) ((U32(v) & 0x1U) << 1U)
#define pwr_pmu_scpctl_stat_r() (0x0010ac08U) #define pwr_pmu_scpctl_stat_r() (0x0010ac08U)
#define pwr_pmu_scpctl_stat_debug_mode_f(v) (((v)&0x1U) << 20U) #define pwr_pmu_scpctl_stat_debug_mode_f(v) ((U32(v) & 0x1U) << 20U)
#define pwr_pmu_scpctl_stat_debug_mode_m() (U32(0x1U) << 20U) #define pwr_pmu_scpctl_stat_debug_mode_m() (U32(0x1U) << 20U)
#define pwr_pmu_scpctl_stat_debug_mode_v(r) (((r) >> 20U) & 0x1U) #define pwr_pmu_scpctl_stat_debug_mode_v(r) (((r) >> 20U) & 0x1U)
#define pwr_falcon_imemc_r(i)\ #define pwr_falcon_imemc_r(i)\
(nvgpu_safe_add_u32(0x0010a180U, nvgpu_safe_mult_u32((i), 16U))) (nvgpu_safe_add_u32(0x0010a180U, nvgpu_safe_mult_u32((i), 16U)))
#define pwr_falcon_imemc_offs_f(v) (((v)&0x3fU) << 2U) #define pwr_falcon_imemc_offs_f(v) ((U32(v) & 0x3fU) << 2U)
#define pwr_falcon_imemc_blk_f(v) (((v)&0xffU) << 8U) #define pwr_falcon_imemc_blk_f(v) ((U32(v) & 0xffU) << 8U)
#define pwr_falcon_imemc_aincw_f(v) (((v)&0x1U) << 24U) #define pwr_falcon_imemc_aincw_f(v) ((U32(v) & 0x1U) << 24U)
#define pwr_falcon_imemd_r(i)\ #define pwr_falcon_imemd_r(i)\
(nvgpu_safe_add_u32(0x0010a184U, nvgpu_safe_mult_u32((i), 16U))) (nvgpu_safe_add_u32(0x0010a184U, nvgpu_safe_mult_u32((i), 16U)))
#define pwr_falcon_imemt_r(i)\ #define pwr_falcon_imemt_r(i)\
@@ -143,11 +143,11 @@
#define pwr_falcon_sctl_r() (0x0010a240U) #define pwr_falcon_sctl_r() (0x0010a240U)
#define pwr_falcon_mmu_phys_sec_r() (0x00100ce4U) #define pwr_falcon_mmu_phys_sec_r() (0x00100ce4U)
#define pwr_falcon_bootvec_r() (0x0010a104U) #define pwr_falcon_bootvec_r() (0x0010a104U)
#define pwr_falcon_bootvec_vec_f(v) (((v)&0xffffffffU) << 0U) #define pwr_falcon_bootvec_vec_f(v) ((U32(v) & 0xffffffffU) << 0U)
#define pwr_falcon_dmactl_r() (0x0010a10cU) #define pwr_falcon_dmactl_r() (0x0010a10cU)
#define pwr_falcon_dmactl_dmem_scrubbing_m() (U32(0x1U) << 1U) #define pwr_falcon_dmactl_dmem_scrubbing_m() (U32(0x1U) << 1U)
#define pwr_falcon_dmactl_imem_scrubbing_m() (U32(0x1U) << 2U) #define pwr_falcon_dmactl_imem_scrubbing_m() (U32(0x1U) << 2U)
#define pwr_falcon_dmactl_require_ctx_f(v) (((v)&0x1U) << 0U) #define pwr_falcon_dmactl_require_ctx_f(v) ((U32(v) & 0x1U) << 0U)
#define pwr_falcon_hwcfg_r() (0x0010a108U) #define pwr_falcon_hwcfg_r() (0x0010a108U)
#define pwr_falcon_hwcfg_imem_size_v(r) (((r) >> 0U) & 0x1ffU) #define pwr_falcon_hwcfg_imem_size_v(r) (((r) >> 0U) & 0x1ffU)
#define pwr_falcon_hwcfg_dmem_size_v(r) (((r) >> 9U) & 0x1ffU) #define pwr_falcon_hwcfg_dmem_size_v(r) (((r) >> 9U) & 0x1ffU)
@@ -155,10 +155,10 @@
#define pwr_falcon_dmatrfbase1_r() (0x0010a128U) #define pwr_falcon_dmatrfbase1_r() (0x0010a128U)
#define pwr_falcon_dmatrfmoffs_r() (0x0010a114U) #define pwr_falcon_dmatrfmoffs_r() (0x0010a114U)
#define pwr_falcon_dmatrfcmd_r() (0x0010a118U) #define pwr_falcon_dmatrfcmd_r() (0x0010a118U)
#define pwr_falcon_dmatrfcmd_imem_f(v) (((v)&0x1U) << 4U) #define pwr_falcon_dmatrfcmd_imem_f(v) ((U32(v) & 0x1U) << 4U)
#define pwr_falcon_dmatrfcmd_write_f(v) (((v)&0x1U) << 5U) #define pwr_falcon_dmatrfcmd_write_f(v) ((U32(v) & 0x1U) << 5U)
#define pwr_falcon_dmatrfcmd_size_f(v) (((v)&0x7U) << 8U) #define pwr_falcon_dmatrfcmd_size_f(v) ((U32(v) & 0x7U) << 8U)
#define pwr_falcon_dmatrfcmd_ctxdma_f(v) (((v)&0x7U) << 12U) #define pwr_falcon_dmatrfcmd_ctxdma_f(v) ((U32(v) & 0x7U) << 12U)
#define pwr_falcon_dmatrffboffs_r() (0x0010a11cU) #define pwr_falcon_dmatrffboffs_r() (0x0010a11cU)
#define pwr_falcon_exterraddr_r() (0x0010a168U) #define pwr_falcon_exterraddr_r() (0x0010a168U)
#define pwr_falcon_exterrstat_r() (0x0010a16cU) #define pwr_falcon_exterrstat_r() (0x0010a16cU)
@@ -167,59 +167,59 @@
#define pwr_falcon_exterrstat_valid_true_v() (0x00000001U) #define pwr_falcon_exterrstat_valid_true_v() (0x00000001U)
#define pwr_pmu_falcon_icd_cmd_r() (0x0010a200U) #define pwr_pmu_falcon_icd_cmd_r() (0x0010a200U)
#define pwr_pmu_falcon_icd_cmd_opc_s() (4U) #define pwr_pmu_falcon_icd_cmd_opc_s() (4U)
#define pwr_pmu_falcon_icd_cmd_opc_f(v) (((v)&0xfU) << 0U) #define pwr_pmu_falcon_icd_cmd_opc_f(v) ((U32(v) & 0xfU) << 0U)
#define pwr_pmu_falcon_icd_cmd_opc_m() (U32(0xfU) << 0U) #define pwr_pmu_falcon_icd_cmd_opc_m() (U32(0xfU) << 0U)
#define pwr_pmu_falcon_icd_cmd_opc_v(r) (((r) >> 0U) & 0xfU) #define pwr_pmu_falcon_icd_cmd_opc_v(r) (((r) >> 0U) & 0xfU)
#define pwr_pmu_falcon_icd_cmd_opc_rreg_f() (0x8U) #define pwr_pmu_falcon_icd_cmd_opc_rreg_f() (0x8U)
#define pwr_pmu_falcon_icd_cmd_opc_rstat_f() (0xeU) #define pwr_pmu_falcon_icd_cmd_opc_rstat_f() (0xeU)
#define pwr_pmu_falcon_icd_cmd_idx_f(v) (((v)&0x1fU) << 8U) #define pwr_pmu_falcon_icd_cmd_idx_f(v) ((U32(v) & 0x1fU) << 8U)
#define pwr_pmu_falcon_icd_rdata_r() (0x0010a20cU) #define pwr_pmu_falcon_icd_rdata_r() (0x0010a20cU)
#define pwr_falcon_dmemc_r(i)\ #define pwr_falcon_dmemc_r(i)\
(nvgpu_safe_add_u32(0x0010a1c0U, nvgpu_safe_mult_u32((i), 8U))) (nvgpu_safe_add_u32(0x0010a1c0U, nvgpu_safe_mult_u32((i), 8U)))
#define pwr_falcon_dmemc_offs_f(v) (((v)&0x3fU) << 2U) #define pwr_falcon_dmemc_offs_f(v) ((U32(v) & 0x3fU) << 2U)
#define pwr_falcon_dmemc_offs_m() (U32(0x3fU) << 2U) #define pwr_falcon_dmemc_offs_m() (U32(0x3fU) << 2U)
#define pwr_falcon_dmemc_blk_f(v) (((v)&0xffU) << 8U) #define pwr_falcon_dmemc_blk_f(v) ((U32(v) & 0xffU) << 8U)
#define pwr_falcon_dmemc_blk_m() (U32(0xffU) << 8U) #define pwr_falcon_dmemc_blk_m() (U32(0xffU) << 8U)
#define pwr_falcon_dmemc_aincw_f(v) (((v)&0x1U) << 24U) #define pwr_falcon_dmemc_aincw_f(v) ((U32(v) & 0x1U) << 24U)
#define pwr_falcon_dmemc_aincr_f(v) (((v)&0x1U) << 25U) #define pwr_falcon_dmemc_aincr_f(v) ((U32(v) & 0x1U) << 25U)
#define pwr_falcon_dmemd_r(i)\ #define pwr_falcon_dmemd_r(i)\
(nvgpu_safe_add_u32(0x0010a1c4U, nvgpu_safe_mult_u32((i), 8U))) (nvgpu_safe_add_u32(0x0010a1c4U, nvgpu_safe_mult_u32((i), 8U)))
#define pwr_pmu_new_instblk_r() (0x0010a480U) #define pwr_pmu_new_instblk_r() (0x0010a480U)
#define pwr_pmu_new_instblk_ptr_f(v) (((v)&0xfffffffU) << 0U) #define pwr_pmu_new_instblk_ptr_f(v) ((U32(v) & 0xfffffffU) << 0U)
#define pwr_pmu_new_instblk_target_fb_f() (0x0U) #define pwr_pmu_new_instblk_target_fb_f() (0x0U)
#define pwr_pmu_new_instblk_target_sys_coh_f() (0x20000000U) #define pwr_pmu_new_instblk_target_sys_coh_f() (0x20000000U)
#define pwr_pmu_new_instblk_target_sys_ncoh_f() (0x30000000U) #define pwr_pmu_new_instblk_target_sys_ncoh_f() (0x30000000U)
#define pwr_pmu_new_instblk_valid_f(v) (((v)&0x1U) << 30U) #define pwr_pmu_new_instblk_valid_f(v) ((U32(v) & 0x1U) << 30U)
#define pwr_pmu_mutex_id_r() (0x0010a488U) #define pwr_pmu_mutex_id_r() (0x0010a488U)
#define pwr_pmu_mutex_id_value_v(r) (((r) >> 0U) & 0xffU) #define pwr_pmu_mutex_id_value_v(r) (((r) >> 0U) & 0xffU)
#define pwr_pmu_mutex_id_value_init_v() (0x00000000U) #define pwr_pmu_mutex_id_value_init_v() (0x00000000U)
#define pwr_pmu_mutex_id_value_not_avail_v() (0x000000ffU) #define pwr_pmu_mutex_id_value_not_avail_v() (0x000000ffU)
#define pwr_pmu_mutex_id_release_r() (0x0010a48cU) #define pwr_pmu_mutex_id_release_r() (0x0010a48cU)
#define pwr_pmu_mutex_id_release_value_f(v) (((v)&0xffU) << 0U) #define pwr_pmu_mutex_id_release_value_f(v) ((U32(v) & 0xffU) << 0U)
#define pwr_pmu_mutex_id_release_value_m() (U32(0xffU) << 0U) #define pwr_pmu_mutex_id_release_value_m() (U32(0xffU) << 0U)
#define pwr_pmu_mutex_id_release_value_init_v() (0x00000000U) #define pwr_pmu_mutex_id_release_value_init_v() (0x00000000U)
#define pwr_pmu_mutex_id_release_value_init_f() (0x0U) #define pwr_pmu_mutex_id_release_value_init_f() (0x0U)
#define pwr_pmu_mutex_r(i)\ #define pwr_pmu_mutex_r(i)\
(nvgpu_safe_add_u32(0x0010a580U, nvgpu_safe_mult_u32((i), 4U))) (nvgpu_safe_add_u32(0x0010a580U, nvgpu_safe_mult_u32((i), 4U)))
#define pwr_pmu_mutex__size_1_v() (0x00000010U) #define pwr_pmu_mutex__size_1_v() (0x00000010U)
#define pwr_pmu_mutex_value_f(v) (((v)&0xffU) << 0U) #define pwr_pmu_mutex_value_f(v) ((U32(v) & 0xffU) << 0U)
#define pwr_pmu_mutex_value_v(r) (((r) >> 0U) & 0xffU) #define pwr_pmu_mutex_value_v(r) (((r) >> 0U) & 0xffU)
#define pwr_pmu_mutex_value_initial_lock_f() (0x0U) #define pwr_pmu_mutex_value_initial_lock_f() (0x0U)
#define pwr_pmu_queue_head_r(i)\ #define pwr_pmu_queue_head_r(i)\
(nvgpu_safe_add_u32(0x0010a4a0U, nvgpu_safe_mult_u32((i), 4U))) (nvgpu_safe_add_u32(0x0010a4a0U, nvgpu_safe_mult_u32((i), 4U)))
#define pwr_pmu_queue_head__size_1_v() (0x00000004U) #define pwr_pmu_queue_head__size_1_v() (0x00000004U)
#define pwr_pmu_queue_head_address_f(v) (((v)&0xffffffffU) << 0U) #define pwr_pmu_queue_head_address_f(v) ((U32(v) & 0xffffffffU) << 0U)
#define pwr_pmu_queue_head_address_v(r) (((r) >> 0U) & 0xffffffffU) #define pwr_pmu_queue_head_address_v(r) (((r) >> 0U) & 0xffffffffU)
#define pwr_pmu_queue_tail_r(i)\ #define pwr_pmu_queue_tail_r(i)\
(nvgpu_safe_add_u32(0x0010a4b0U, nvgpu_safe_mult_u32((i), 4U))) (nvgpu_safe_add_u32(0x0010a4b0U, nvgpu_safe_mult_u32((i), 4U)))
#define pwr_pmu_queue_tail__size_1_v() (0x00000004U) #define pwr_pmu_queue_tail__size_1_v() (0x00000004U)
#define pwr_pmu_queue_tail_address_f(v) (((v)&0xffffffffU) << 0U) #define pwr_pmu_queue_tail_address_f(v) ((U32(v) & 0xffffffffU) << 0U)
#define pwr_pmu_queue_tail_address_v(r) (((r) >> 0U) & 0xffffffffU) #define pwr_pmu_queue_tail_address_v(r) (((r) >> 0U) & 0xffffffffU)
#define pwr_pmu_msgq_head_r() (0x0010a4c8U) #define pwr_pmu_msgq_head_r() (0x0010a4c8U)
#define pwr_pmu_msgq_head_val_f(v) (((v)&0xffffffffU) << 0U) #define pwr_pmu_msgq_head_val_f(v) ((U32(v) & 0xffffffffU) << 0U)
#define pwr_pmu_msgq_head_val_v(r) (((r) >> 0U) & 0xffffffffU) #define pwr_pmu_msgq_head_val_v(r) (((r) >> 0U) & 0xffffffffU)
#define pwr_pmu_msgq_tail_r() (0x0010a4ccU) #define pwr_pmu_msgq_tail_r() (0x0010a4ccU)
#define pwr_pmu_msgq_tail_val_f(v) (((v)&0xffffffffU) << 0U) #define pwr_pmu_msgq_tail_val_f(v) ((U32(v) & 0xffffffffU) << 0U)
#define pwr_pmu_msgq_tail_val_v(r) (((r) >> 0U) & 0xffffffffU) #define pwr_pmu_msgq_tail_val_v(r) (((r) >> 0U) & 0xffffffffU)
#define pwr_pmu_idle_mask_r(i)\ #define pwr_pmu_idle_mask_r(i)\
(nvgpu_safe_add_u32(0x0010a504U, nvgpu_safe_mult_u32((i), 16U))) (nvgpu_safe_add_u32(0x0010a504U, nvgpu_safe_mult_u32((i), 16U)))
@@ -227,9 +227,9 @@
#define pwr_pmu_idle_mask_ce_2_enabled_f() (0x200000U) #define pwr_pmu_idle_mask_ce_2_enabled_f() (0x200000U)
#define pwr_pmu_idle_count_r(i)\ #define pwr_pmu_idle_count_r(i)\
(nvgpu_safe_add_u32(0x0010a508U, nvgpu_safe_mult_u32((i), 16U))) (nvgpu_safe_add_u32(0x0010a508U, nvgpu_safe_mult_u32((i), 16U)))
#define pwr_pmu_idle_count_value_f(v) (((v)&0x7fffffffU) << 0U) #define pwr_pmu_idle_count_value_f(v) ((U32(v) & 0x7fffffffU) << 0U)
#define pwr_pmu_idle_count_value_v(r) (((r) >> 0U) & 0x7fffffffU) #define pwr_pmu_idle_count_value_v(r) (((r) >> 0U) & 0x7fffffffU)
#define pwr_pmu_idle_count_reset_f(v) (((v)&0x1U) << 31U) #define pwr_pmu_idle_count_reset_f(v) ((U32(v) & 0x1U) << 31U)
#define pwr_pmu_idle_ctrl_r(i)\ #define pwr_pmu_idle_ctrl_r(i)\
(nvgpu_safe_add_u32(0x0010a50cU, nvgpu_safe_mult_u32((i), 16U))) (nvgpu_safe_add_u32(0x0010a50cU, nvgpu_safe_mult_u32((i), 16U)))
#define pwr_pmu_idle_ctrl_value_m() (U32(0x3U) << 0U) #define pwr_pmu_idle_ctrl_value_m() (U32(0x3U) << 0U)
@@ -239,13 +239,13 @@
#define pwr_pmu_idle_ctrl_filter_disabled_f() (0x0U) #define pwr_pmu_idle_ctrl_filter_disabled_f() (0x0U)
#define pwr_pmu_idle_threshold_r(i)\ #define pwr_pmu_idle_threshold_r(i)\
(nvgpu_safe_add_u32(0x0010a8a0U, nvgpu_safe_mult_u32((i), 4U))) (nvgpu_safe_add_u32(0x0010a8a0U, nvgpu_safe_mult_u32((i), 4U)))
#define pwr_pmu_idle_threshold_value_f(v) (((v)&0x7fffffffU) << 0U) #define pwr_pmu_idle_threshold_value_f(v) ((U32(v) & 0x7fffffffU) << 0U)
#define pwr_pmu_idle_intr_r() (0x0010a9e8U) #define pwr_pmu_idle_intr_r() (0x0010a9e8U)
#define pwr_pmu_idle_intr_en_f(v) (((v)&0x1U) << 0U) #define pwr_pmu_idle_intr_en_f(v) ((U32(v) & 0x1U) << 0U)
#define pwr_pmu_idle_intr_en_disabled_v() (0x00000000U) #define pwr_pmu_idle_intr_en_disabled_v() (0x00000000U)
#define pwr_pmu_idle_intr_en_enabled_v() (0x00000001U) #define pwr_pmu_idle_intr_en_enabled_v() (0x00000001U)
#define pwr_pmu_idle_intr_status_r() (0x0010a9ecU) #define pwr_pmu_idle_intr_status_r() (0x0010a9ecU)
#define pwr_pmu_idle_intr_status_intr_f(v) (((v)&0x1U) << 0U) #define pwr_pmu_idle_intr_status_intr_f(v) ((U32(v) & 0x1U) << 0U)
#define pwr_pmu_idle_intr_status_intr_m() (U32(0x1U) << 0U) #define pwr_pmu_idle_intr_status_intr_m() (U32(0x1U) << 0U)
#define pwr_pmu_idle_intr_status_intr_v(r) (((r) >> 0U) & 0x1U) #define pwr_pmu_idle_intr_status_intr_v(r) (((r) >> 0U) & 0x1U)
#define pwr_pmu_idle_intr_status_intr_pending_v() (0x00000001U) #define pwr_pmu_idle_intr_status_intr_pending_v() (0x00000001U)
@@ -289,7 +289,7 @@
#define pwr_fbif_transcfg_target_coherent_sysmem_f() (0x1U) #define pwr_fbif_transcfg_target_coherent_sysmem_f() (0x1U)
#define pwr_fbif_transcfg_target_noncoherent_sysmem_f() (0x2U) #define pwr_fbif_transcfg_target_noncoherent_sysmem_f() (0x2U)
#define pwr_fbif_transcfg_mem_type_s() (1U) #define pwr_fbif_transcfg_mem_type_s() (1U)
#define pwr_fbif_transcfg_mem_type_f(v) (((v)&0x1U) << 2U) #define pwr_fbif_transcfg_mem_type_f(v) ((U32(v) & 0x1U) << 2U)
#define pwr_fbif_transcfg_mem_type_m() (U32(0x1U) << 2U) #define pwr_fbif_transcfg_mem_type_m() (U32(0x1U) << 2U)
#define pwr_fbif_transcfg_mem_type_v(r) (((r) >> 2U) & 0x1U) #define pwr_fbif_transcfg_mem_type_v(r) (((r) >> 2U) & 0x1U)
#define pwr_fbif_transcfg_mem_type_virtual_f() (0x0U) #define pwr_fbif_transcfg_mem_type_virtual_f() (0x0U)

36
drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_ram_gp106.h
View File

@@ -61,38 +61,38 @@
#define ram_in_ramfc_s() (4096U) #define ram_in_ramfc_s() (4096U)
#define ram_in_ramfc_w() (0U) #define ram_in_ramfc_w() (0U)
#define ram_in_page_dir_base_target_f(v) (((v)&0x3U) << 0U) #define ram_in_page_dir_base_target_f(v) ((U32(v) & 0x3U) << 0U)
#define ram_in_page_dir_base_target_w() (128U) #define ram_in_page_dir_base_target_w() (128U)
#define ram_in_page_dir_base_target_vid_mem_f() (0x0U) #define ram_in_page_dir_base_target_vid_mem_f() (0x0U)
#define ram_in_page_dir_base_target_sys_mem_coh_f() (0x2U) #define ram_in_page_dir_base_target_sys_mem_coh_f() (0x2U)
#define ram_in_page_dir_base_target_sys_mem_ncoh_f() (0x3U) #define ram_in_page_dir_base_target_sys_mem_ncoh_f() (0x3U)
#define ram_in_page_dir_base_vol_w() (128U) #define ram_in_page_dir_base_vol_w() (128U)
#define ram_in_page_dir_base_vol_true_f() (0x4U) #define ram_in_page_dir_base_vol_true_f() (0x4U)
#define ram_in_page_dir_base_fault_replay_tex_f(v) (((v)&0x1U) << 4U) #define ram_in_page_dir_base_fault_replay_tex_f(v) ((U32(v) & 0x1U) << 4U)
#define ram_in_page_dir_base_fault_replay_tex_m() (U32(0x1U) << 4U) #define ram_in_page_dir_base_fault_replay_tex_m() (U32(0x1U) << 4U)
#define ram_in_page_dir_base_fault_replay_tex_w() (128U) #define ram_in_page_dir_base_fault_replay_tex_w() (128U)
#define ram_in_page_dir_base_fault_replay_tex_true_f() (0x10U) #define ram_in_page_dir_base_fault_replay_tex_true_f() (0x10U)
#define ram_in_page_dir_base_fault_replay_gcc_f(v) (((v)&0x1U) << 5U) #define ram_in_page_dir_base_fault_replay_gcc_f(v) ((U32(v) & 0x1U) << 5U)
#define ram_in_page_dir_base_fault_replay_gcc_m() (U32(0x1U) << 5U) #define ram_in_page_dir_base_fault_replay_gcc_m() (U32(0x1U) << 5U)
#define ram_in_page_dir_base_fault_replay_gcc_w() (128U) #define ram_in_page_dir_base_fault_replay_gcc_w() (128U)
#define ram_in_page_dir_base_fault_replay_gcc_true_f() (0x20U) #define ram_in_page_dir_base_fault_replay_gcc_true_f() (0x20U)
#define ram_in_use_ver2_pt_format_f(v) (((v)&0x1U) << 10U) #define ram_in_use_ver2_pt_format_f(v) ((U32(v) & 0x1U) << 10U)
#define ram_in_use_ver2_pt_format_m() (U32(0x1U) << 10U) #define ram_in_use_ver2_pt_format_m() (U32(0x1U) << 10U)
#define ram_in_use_ver2_pt_format_w() (128U) #define ram_in_use_ver2_pt_format_w() (128U)
#define ram_in_use_ver2_pt_format_true_f() (0x400U) #define ram_in_use_ver2_pt_format_true_f() (0x400U)
#define ram_in_use_ver2_pt_format_false_f() (0x0U) #define ram_in_use_ver2_pt_format_false_f() (0x0U)
#define ram_in_big_page_size_f(v) (((v)&0x1U) << 11U) #define ram_in_big_page_size_f(v) ((U32(v) & 0x1U) << 11U)
#define ram_in_big_page_size_m() (U32(0x1U) << 11U) #define ram_in_big_page_size_m() (U32(0x1U) << 11U)
#define ram_in_big_page_size_w() (128U) #define ram_in_big_page_size_w() (128U)
#define ram_in_big_page_size_128kb_f() (0x0U) #define ram_in_big_page_size_128kb_f() (0x0U)
#define ram_in_big_page_size_64kb_f() (0x800U) #define ram_in_big_page_size_64kb_f() (0x800U)
#define ram_in_page_dir_base_lo_f(v) (((v)&0xfffffU) << 12U) #define ram_in_page_dir_base_lo_f(v) ((U32(v) & 0xfffffU) << 12U)
#define ram_in_page_dir_base_lo_w() (128U) #define ram_in_page_dir_base_lo_w() (128U)
#define ram_in_page_dir_base_hi_f(v) (((v)&0xffffffffU) << 0U) #define ram_in_page_dir_base_hi_f(v) ((U32(v) & 0xffffffffU) << 0U)
#define ram_in_page_dir_base_hi_w() (129U) #define ram_in_page_dir_base_hi_w() (129U)
#define ram_in_adr_limit_lo_f(v) (((v)&0xfffffU) << 12U) #define ram_in_adr_limit_lo_f(v) ((U32(v) & 0xfffffU) << 12U)
#define ram_in_adr_limit_lo_w() (130U) #define ram_in_adr_limit_lo_w() (130U)
#define ram_in_adr_limit_hi_f(v) (((v)&0xffffffffU) << 0U) #define ram_in_adr_limit_hi_f(v) ((U32(v) & 0xffffffffU) << 0U)
#define ram_in_adr_limit_hi_w() (131U) #define ram_in_adr_limit_hi_w() (131U)
#define ram_in_engine_cs_w() (132U) #define ram_in_engine_cs_w() (132U)
#define ram_in_engine_cs_wfi_v() (0x00000000U) #define ram_in_engine_cs_wfi_v() (0x00000000U)
@@ -107,9 +107,9 @@
#define ram_in_gr_wfi_mode_physical_f() (0x0U) #define ram_in_gr_wfi_mode_physical_f() (0x0U)
#define ram_in_gr_wfi_mode_virtual_v() (0x00000001U) #define ram_in_gr_wfi_mode_virtual_v() (0x00000001U)
#define ram_in_gr_wfi_mode_virtual_f() (0x4U) #define ram_in_gr_wfi_mode_virtual_f() (0x4U)
#define ram_in_gr_wfi_ptr_lo_f(v) (((v)&0xfffffU) << 12U) #define ram_in_gr_wfi_ptr_lo_f(v) ((U32(v) & 0xfffffU) << 12U)
#define ram_in_gr_wfi_ptr_lo_w() (132U) #define ram_in_gr_wfi_ptr_lo_w() (132U)
#define ram_in_gr_wfi_ptr_hi_f(v) (((v)&0xffU) << 0U) #define ram_in_gr_wfi_ptr_hi_f(v) ((U32(v) & 0xffU) << 0U)
#define ram_in_gr_wfi_ptr_hi_w() (133U) #define ram_in_gr_wfi_ptr_hi_w() (133U)
#define ram_in_base_shift_v() (0x0000000cU) #define ram_in_base_shift_v() (0x0000000cU)
#define ram_in_alloc_size_v() (0x00001000U) #define ram_in_alloc_size_v() (0x00001000U)
@@ -142,7 +142,7 @@
#define ram_fc_target_w() (43U) #define ram_fc_target_w() (43U)
#define ram_fc_hce_ctrl_w() (57U) #define ram_fc_hce_ctrl_w() (57U)
#define ram_fc_chid_w() (58U) #define ram_fc_chid_w() (58U)
#define ram_fc_chid_id_f(v) (((v)&0xfffU) << 0U) #define ram_fc_chid_id_f(v) ((U32(v) & 0xfffU) << 0U)
#define ram_fc_chid_id_w() (0U) #define ram_fc_chid_id_w() (0U)
#define ram_fc_config_w() (61U) #define ram_fc_config_w() (61U)
#define ram_fc_runlist_timeslice_w() (62U) #define ram_fc_runlist_timeslice_w() (62U)
@@ -160,16 +160,16 @@
#define ram_userd_gp_top_level_get_w() (22U) #define ram_userd_gp_top_level_get_w() (22U)
#define ram_userd_gp_top_level_get_hi_w() (23U) #define ram_userd_gp_top_level_get_hi_w() (23U)
#define ram_rl_entry_size_v() (0x00000008U) #define ram_rl_entry_size_v() (0x00000008U)
#define ram_rl_entry_chid_f(v) (((v)&0xfffU) << 0U) #define ram_rl_entry_chid_f(v) ((U32(v) & 0xfffU) << 0U)
#define ram_rl_entry_id_f(v) (((v)&0xfffU) << 0U) #define ram_rl_entry_id_f(v) ((U32(v) & 0xfffU) << 0U)
#define ram_rl_entry_type_f(v) (((v)&0x1U) << 13U) #define ram_rl_entry_type_f(v) ((U32(v) & 0x1U) << 13U)
#define ram_rl_entry_type_chid_f() (0x0U) #define ram_rl_entry_type_chid_f() (0x0U)
#define ram_rl_entry_type_tsg_f() (0x2000U) #define ram_rl_entry_type_tsg_f() (0x2000U)
#define ram_rl_entry_timeslice_scale_f(v) (((v)&0xfU) << 14U) #define ram_rl_entry_timeslice_scale_f(v) ((U32(v) & 0xfU) << 14U)
#define ram_rl_entry_timeslice_scale_v(r) (((r) >> 14U) & 0xfU) #define ram_rl_entry_timeslice_scale_v(r) (((r) >> 14U) & 0xfU)
#define ram_rl_entry_timeslice_scale_3_f() (0xc000U) #define ram_rl_entry_timeslice_scale_3_f() (0xc000U)
#define ram_rl_entry_timeslice_timeout_f(v) (((v)&0xffU) << 18U) #define ram_rl_entry_timeslice_timeout_f(v) ((U32(v) & 0xffU) << 18U)
#define ram_rl_entry_timeslice_timeout_v(r) (((r) >> 18U) & 0xffU) #define ram_rl_entry_timeslice_timeout_v(r) (((r) >> 18U) & 0xffU)
#define ram_rl_entry_timeslice_timeout_128_f() (0x2000000U) #define ram_rl_entry_timeslice_timeout_128_f() (0x2000000U)
#define ram_rl_entry_tsg_length_f(v) (((v)&0x3fU) << 26U) #define ram_rl_entry_tsg_length_f(v) ((U32(v) & 0x3fU) << 26U)
#endif #endif

8
drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_therm_gp106.h
View File

@@ -68,13 +68,13 @@
#define therm_gate_ctrl_blk_clk_m() (U32(0x3U) << 2U) #define therm_gate_ctrl_blk_clk_m() (U32(0x3U) << 2U)
#define therm_gate_ctrl_blk_clk_run_f() (0x0U) #define therm_gate_ctrl_blk_clk_run_f() (0x0U)
#define therm_gate_ctrl_blk_clk_auto_f() (0x4U) #define therm_gate_ctrl_blk_clk_auto_f() (0x4U)
#define therm_gate_ctrl_eng_idle_filt_exp_f(v) (((v)&0x1fU) << 8U) #define therm_gate_ctrl_eng_idle_filt_exp_f(v) ((U32(v) & 0x1fU) << 8U)
#define therm_gate_ctrl_eng_idle_filt_exp_m() (U32(0x1fU) << 8U) #define therm_gate_ctrl_eng_idle_filt_exp_m() (U32(0x1fU) << 8U)
#define therm_gate_ctrl_eng_idle_filt_mant_f(v) (((v)&0x7U) << 13U) #define therm_gate_ctrl_eng_idle_filt_mant_f(v) ((U32(v) & 0x7U) << 13U)
#define therm_gate_ctrl_eng_idle_filt_mant_m() (U32(0x7U) << 13U) #define therm_gate_ctrl_eng_idle_filt_mant_m() (U32(0x7U) << 13U)
#define therm_gate_ctrl_eng_delay_before_f(v) (((v)&0xfU) << 16U) #define therm_gate_ctrl_eng_delay_before_f(v) ((U32(v) & 0xfU) << 16U)
#define therm_gate_ctrl_eng_delay_before_m() (U32(0xfU) << 16U) #define therm_gate_ctrl_eng_delay_before_m() (U32(0xfU) << 16U)
#define therm_gate_ctrl_eng_delay_after_f(v) (((v)&0xfU) << 20U) #define therm_gate_ctrl_eng_delay_after_f(v) ((U32(v) & 0xfU) << 20U)
#define therm_gate_ctrl_eng_delay_after_m() (U32(0xfU) << 20U) #define therm_gate_ctrl_eng_delay_after_m() (U32(0xfU) << 20U)
#define therm_fecs_idle_filter_r() (0x00020288U) #define therm_fecs_idle_filter_r() (0x00020288U)
#define therm_fecs_idle_filter_value_m() (U32(0xffffffffU) << 0U) #define therm_fecs_idle_filter_value_m() (U32(0xffffffffU) << 0U)

4
drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_timer_gp106.h
View File

@@ -60,10 +60,10 @@
#include <nvgpu/safe_ops.h> #include <nvgpu/safe_ops.h>
#define timer_pri_timeout_r() (0x00009080U) #define timer_pri_timeout_r() (0x00009080U)
#define timer_pri_timeout_period_f(v) (((v)&0xffffffU) << 0U) #define timer_pri_timeout_period_f(v) ((U32(v) & 0xffffffU) << 0U)
#define timer_pri_timeout_period_m() (U32(0xffffffU) << 0U) #define timer_pri_timeout_period_m() (U32(0xffffffU) << 0U)
#define timer_pri_timeout_period_v(r) (((r) >> 0U) & 0xffffffU) #define timer_pri_timeout_period_v(r) (((r) >> 0U) & 0xffffffU)
#define timer_pri_timeout_en_f(v) (((v)&0x1U) << 31U) #define timer_pri_timeout_en_f(v) ((U32(v) & 0x1U) << 31U)
#define timer_pri_timeout_en_m() (U32(0x1U) << 31U) #define timer_pri_timeout_en_m() (U32(0x1U) << 31U)
#define timer_pri_timeout_en_v(r) (((r) >> 31U) & 0x1U) #define timer_pri_timeout_en_v(r) (((r) >> 31U) & 0x1U)
#define timer_pri_timeout_en_en_enabled_f() (0x80000000U) #define timer_pri_timeout_en_en_enabled_f() (0x80000000U)

10
drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_trim_gp106.h
View File

@@ -62,24 +62,26 @@
#define trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_r() (0x00132924U) #define trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_r() (0x00132924U)
#define trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_noofipclks_s() (16U) #define trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_noofipclks_s() (16U)
#define trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_noofipclks_f(v)\ #define trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_noofipclks_f(v)\
(((v)&0xffffU) << 0U) ((U32(v) & 0xffffU) << 0U)
#define trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_noofipclks_m() (U32(0xffffU) << 0U) #define trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_noofipclks_m() (U32(0xffffU) << 0U)
#define trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_noofipclks_v(r)\ #define trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_noofipclks_v(r)\
(((r) >> 0U) & 0xffffU) (((r) >> 0U) & 0xffffU)
#define trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_write_en_s() (1U) #define trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_write_en_s() (1U)
#define trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_write_en_f(v) (((v)&0x1U) << 16U) #define trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_write_en_f(v)\
((U32(v) & 0x1U) << 16U)
#define trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_write_en_m() (U32(0x1U) << 16U) #define trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_write_en_m() (U32(0x1U) << 16U)
#define trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_write_en_v(r) (((r) >> 16U) & 0x1U) #define trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_write_en_v(r) (((r) >> 16U) & 0x1U)
#define trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_write_en_deasserted_f() (0x0U) #define trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_write_en_deasserted_f() (0x0U)
#define trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_write_en_asserted_f() (0x10000U) #define trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_write_en_asserted_f() (0x10000U)
#define trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_enable_s() (1U) #define trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_enable_s() (1U)
#define trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_enable_f(v) (((v)&0x1U) << 20U) #define trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_enable_f(v)\
((U32(v) & 0x1U) << 20U)
#define trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_enable_m() (U32(0x1U) << 20U) #define trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_enable_m() (U32(0x1U) << 20U)
#define trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_enable_v(r) (((r) >> 20U) & 0x1U) #define trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_enable_v(r) (((r) >> 20U) & 0x1U)
#define trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_enable_deasserted_f() (0x0U) #define trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_enable_deasserted_f() (0x0U)
#define trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_enable_asserted_f() (0x100000U) #define trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_enable_asserted_f() (0x100000U)
#define trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_reset_s() (1U) #define trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_reset_s() (1U)
#define trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_reset_f(v) (((v)&0x1U) << 24U) #define trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_reset_f(v) ((U32(v) & 0x1U) << 24U)
#define trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_reset_m() (U32(0x1U) << 24U) #define trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_reset_m() (U32(0x1U) << 24U)
#define trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_reset_v(r) (((r) >> 24U) & 0x1U) #define trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_reset_v(r) (((r) >> 24U) & 0x1U)
#define trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_reset_deasserted_f() (0x0U) #define trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_reset_deasserted_f() (0x0U)

10
drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_xp_gp106.h
View File

@@ -61,21 +61,21 @@
#define xp_dl_mgr_r(i)\ #define xp_dl_mgr_r(i)\
(nvgpu_safe_add_u32(0x0008b8c0U, nvgpu_safe_mult_u32((i), 4U))) (nvgpu_safe_add_u32(0x0008b8c0U, nvgpu_safe_mult_u32((i), 4U)))
#define xp_dl_mgr_safe_timing_f(v) (((v)&0x1U) << 2U) #define xp_dl_mgr_safe_timing_f(v) ((U32(v) & 0x1U) << 2U)
#define xp_pl_link_config_r(i)\ #define xp_pl_link_config_r(i)\
(nvgpu_safe_add_u32(0x0008c040U, nvgpu_safe_mult_u32((i), 4U))) (nvgpu_safe_add_u32(0x0008c040U, nvgpu_safe_mult_u32((i), 4U)))
#define xp_pl_link_config_ltssm_status_f(v) (((v)&0x1U) << 4U) #define xp_pl_link_config_ltssm_status_f(v) ((U32(v) & 0x1U) << 4U)
#define xp_pl_link_config_ltssm_status_idle_v() (0x00000000U) #define xp_pl_link_config_ltssm_status_idle_v() (0x00000000U)
#define xp_pl_link_config_ltssm_directive_f(v) (((v)&0xfU) << 0U) #define xp_pl_link_config_ltssm_directive_f(v) ((U32(v) & 0xfU) << 0U)
#define xp_pl_link_config_ltssm_directive_m() (U32(0xfU) << 0U) #define xp_pl_link_config_ltssm_directive_m() (U32(0xfU) << 0U)
#define xp_pl_link_config_ltssm_directive_normal_operations_v() (0x00000000U) #define xp_pl_link_config_ltssm_directive_normal_operations_v() (0x00000000U)
#define xp_pl_link_config_ltssm_directive_change_speed_v() (0x00000001U) #define xp_pl_link_config_ltssm_directive_change_speed_v() (0x00000001U)
#define xp_pl_link_config_max_link_rate_f(v) (((v)&0x3U) << 18U) #define xp_pl_link_config_max_link_rate_f(v) ((U32(v) & 0x3U) << 18U)
#define xp_pl_link_config_max_link_rate_m() (U32(0x3U) << 18U) #define xp_pl_link_config_max_link_rate_m() (U32(0x3U) << 18U)
#define xp_pl_link_config_max_link_rate_2500_mtps_v() (0x00000002U) #define xp_pl_link_config_max_link_rate_2500_mtps_v() (0x00000002U)
#define xp_pl_link_config_max_link_rate_5000_mtps_v() (0x00000001U) #define xp_pl_link_config_max_link_rate_5000_mtps_v() (0x00000001U)
#define xp_pl_link_config_max_link_rate_8000_mtps_v() (0x00000000U) #define xp_pl_link_config_max_link_rate_8000_mtps_v() (0x00000000U)
#define xp_pl_link_config_target_tx_width_f(v) (((v)&0x7U) << 20U) #define xp_pl_link_config_target_tx_width_f(v) ((U32(v) & 0x7U) << 20U)
#define xp_pl_link_config_target_tx_width_m() (U32(0x7U) << 20U) #define xp_pl_link_config_target_tx_width_m() (U32(0x7U) << 20U)
#define xp_pl_link_config_target_tx_width_x1_v() (0x00000007U) #define xp_pl_link_config_target_tx_width_x1_v() (0x00000007U)
#define xp_pl_link_config_target_tx_width_x2_v() (0x00000006U) #define xp_pl_link_config_target_tx_width_x2_v() (0x00000006U)

10
drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_xve_gp106.h
View File

@@ -60,7 +60,7 @@
#include <nvgpu/safe_ops.h> #include <nvgpu/safe_ops.h>
#define xve_rom_ctrl_r() (0x00000050U) #define xve_rom_ctrl_r() (0x00000050U)
#define xve_rom_ctrl_rom_shadow_f(v) (((v)&0x1U) << 0U) #define xve_rom_ctrl_rom_shadow_f(v) ((U32(v) & 0x1U) << 0U)
#define xve_rom_ctrl_rom_shadow_disabled_f() (0x0U) #define xve_rom_ctrl_rom_shadow_disabled_f() (0x0U)
#define xve_rom_ctrl_rom_shadow_enabled_f() (0x1U) #define xve_rom_ctrl_rom_shadow_enabled_f() (0x1U)
#define xve_link_control_status_r() (0x00000088U) #define xve_link_control_status_r() (0x00000088U)
@@ -77,10 +77,10 @@
#define xve_link_control_status_link_width_x8_v() (0x00000008U) #define xve_link_control_status_link_width_x8_v() (0x00000008U)
#define xve_link_control_status_link_width_x16_v() (0x00000010U) #define xve_link_control_status_link_width_x16_v() (0x00000010U)
#define xve_priv_xv_r() (0x00000150U) #define xve_priv_xv_r() (0x00000150U)
#define xve_priv_xv_cya_l0s_enable_f(v) (((v)&0x1U) << 7U) #define xve_priv_xv_cya_l0s_enable_f(v) ((U32(v) & 0x1U) << 7U)
#define xve_priv_xv_cya_l0s_enable_m() (U32(0x1U) << 7U) #define xve_priv_xv_cya_l0s_enable_m() (U32(0x1U) << 7U)
#define xve_priv_xv_cya_l0s_enable_v(r) (((r) >> 7U) & 0x1U) #define xve_priv_xv_cya_l0s_enable_v(r) (((r) >> 7U) & 0x1U)
#define xve_priv_xv_cya_l1_enable_f(v) (((v)&0x1U) << 8U) #define xve_priv_xv_cya_l1_enable_f(v) ((U32(v) & 0x1U) << 8U)
#define xve_priv_xv_cya_l1_enable_m() (U32(0x1U) << 8U) #define xve_priv_xv_cya_l1_enable_m() (U32(0x1U) << 8U)
#define xve_priv_xv_cya_l1_enable_v(r) (((r) >> 8U) & 0x1U) #define xve_priv_xv_cya_l1_enable_v(r) (((r) >> 8U) & 0x1U)
#define xve_cya_2_r() (0x00000704U) #define xve_cya_2_r() (0x00000704U)
@@ -88,12 +88,12 @@
#define xve_reset_reset_m() (U32(0x1U) << 0U) #define xve_reset_reset_m() (U32(0x1U) << 0U)
#define xve_reset_gpu_on_sw_reset_m() (U32(0x1U) << 1U) #define xve_reset_gpu_on_sw_reset_m() (U32(0x1U) << 1U)
#define xve_reset_counter_en_m() (U32(0x1U) << 2U) #define xve_reset_counter_en_m() (U32(0x1U) << 2U)
#define xve_reset_counter_val_f(v) (((v)&0x7ffU) << 4U) #define xve_reset_counter_val_f(v) ((U32(v) & 0x7ffU) << 4U)
#define xve_reset_counter_val_m() (U32(0x7ffU) << 4U) #define xve_reset_counter_val_m() (U32(0x7ffU) << 4U)
#define xve_reset_counter_val_v(r) (((r) >> 4U) & 0x7ffU) #define xve_reset_counter_val_v(r) (((r) >> 4U) & 0x7ffU)
#define xve_reset_clock_on_sw_reset_m() (U32(0x1U) << 15U) #define xve_reset_clock_on_sw_reset_m() (U32(0x1U) << 15U)
#define xve_reset_clock_counter_en_m() (U32(0x1U) << 16U) #define xve_reset_clock_counter_en_m() (U32(0x1U) << 16U)
#define xve_reset_clock_counter_val_f(v) (((v)&0x7ffU) << 17U) #define xve_reset_clock_counter_val_f(v) ((U32(v) & 0x7ffU) << 17U)
#define xve_reset_clock_counter_val_m() (U32(0x7ffU) << 17U) #define xve_reset_clock_counter_val_m() (U32(0x7ffU) << 17U)
#define xve_reset_clock_counter_val_v(r) (((r) >> 17U) & 0x7ffU) #define xve_reset_clock_counter_val_v(r) (((r) >> 17U) & 0x7ffU)
#endif #endif

6
drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_bus_gp10b.h
View File

@@ -60,19 +60,19 @@
#include <nvgpu/safe_ops.h> #include <nvgpu/safe_ops.h>
#define bus_bar0_window_r() (0x00001700U) #define bus_bar0_window_r() (0x00001700U)
#define bus_bar0_window_base_f(v) (((v)&0xffffffU) << 0U) #define bus_bar0_window_base_f(v) ((U32(v) & 0xffffffU) << 0U)
#define bus_bar0_window_target_vid_mem_f() (0x0U) #define bus_bar0_window_target_vid_mem_f() (0x0U)
#define bus_bar0_window_target_sys_mem_coherent_f() (0x2000000U) #define bus_bar0_window_target_sys_mem_coherent_f() (0x2000000U)
#define bus_bar0_window_target_sys_mem_noncoherent_f() (0x3000000U) #define bus_bar0_window_target_sys_mem_noncoherent_f() (0x3000000U)
#define bus_bar0_window_target_bar0_window_base_shift_v() (0x00000010U) #define bus_bar0_window_target_bar0_window_base_shift_v() (0x00000010U)
#define bus_bar1_block_r() (0x00001704U) #define bus_bar1_block_r() (0x00001704U)
#define bus_bar1_block_ptr_f(v) (((v)&0xfffffffU) << 0U) #define bus_bar1_block_ptr_f(v) ((U32(v) & 0xfffffffU) << 0U)
#define bus_bar1_block_target_vid_mem_f() (0x0U) #define bus_bar1_block_target_vid_mem_f() (0x0U)
#define bus_bar1_block_target_sys_mem_coh_f() (0x20000000U) #define bus_bar1_block_target_sys_mem_coh_f() (0x20000000U)
#define bus_bar1_block_target_sys_mem_ncoh_f() (0x30000000U) #define bus_bar1_block_target_sys_mem_ncoh_f() (0x30000000U)
#define bus_bar1_block_mode_virtual_f() (0x80000000U) #define bus_bar1_block_mode_virtual_f() (0x80000000U)
#define bus_bar2_block_r() (0x00001714U) #define bus_bar2_block_r() (0x00001714U)
#define bus_bar2_block_ptr_f(v) (((v)&0xfffffffU) << 0U) #define bus_bar2_block_ptr_f(v) ((U32(v) & 0xfffffffU) << 0U)
#define bus_bar2_block_target_vid_mem_f() (0x0U) #define bus_bar2_block_target_vid_mem_f() (0x0U)
#define bus_bar2_block_target_sys_mem_coh_f() (0x20000000U) #define bus_bar2_block_target_sys_mem_coh_f() (0x20000000U)
#define bus_bar2_block_target_sys_mem_ncoh_f() (0x30000000U) #define bus_bar2_block_target_sys_mem_ncoh_f() (0x30000000U)

4
drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_ccsr_gp10b.h
View File

@@ -62,7 +62,7 @@
#define ccsr_channel_inst_r(i)\ #define ccsr_channel_inst_r(i)\
(nvgpu_safe_add_u32(0x00800000U, nvgpu_safe_mult_u32((i), 8U))) (nvgpu_safe_add_u32(0x00800000U, nvgpu_safe_mult_u32((i), 8U)))
#define ccsr_channel_inst__size_1_v() (0x00000200U) #define ccsr_channel_inst__size_1_v() (0x00000200U)
#define ccsr_channel_inst_ptr_f(v) (((v)&0xfffffffU) << 0U) #define ccsr_channel_inst_ptr_f(v) ((U32(v) & 0xfffffffU) << 0U)
#define ccsr_channel_inst_target_vid_mem_f() (0x0U) #define ccsr_channel_inst_target_vid_mem_f() (0x0U)
#define ccsr_channel_inst_target_sys_mem_coh_f() (0x20000000U) #define ccsr_channel_inst_target_sys_mem_coh_f() (0x20000000U)
#define ccsr_channel_inst_target_sys_mem_ncoh_f() (0x30000000U) #define ccsr_channel_inst_target_sys_mem_ncoh_f() (0x30000000U)
@@ -73,7 +73,7 @@
#define ccsr_channel__size_1_v() (0x00000200U) #define ccsr_channel__size_1_v() (0x00000200U)
#define ccsr_channel_enable_v(r) (((r) >> 0U) & 0x1U) #define ccsr_channel_enable_v(r) (((r) >> 0U) & 0x1U)
#define ccsr_channel_enable_in_use_v() (0x00000001U) #define ccsr_channel_enable_in_use_v() (0x00000001U)
#define ccsr_channel_enable_set_f(v) (((v)&0x1U) << 10U) #define ccsr_channel_enable_set_f(v) ((U32(v) & 0x1U) << 10U)
#define ccsr_channel_enable_set_true_f() (0x400U) #define ccsr_channel_enable_set_true_f() (0x400U)
#define ccsr_channel_enable_clr_true_f() (0x800U) #define ccsr_channel_enable_clr_true_f() (0x800U)
#define ccsr_channel_status_v(r) (((r) >> 24U) & 0xfU) #define ccsr_channel_status_v(r) (((r) >> 24U) & 0xfU)

18
drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_ctxsw_prog_gp10b.h
View File

@@ -106,7 +106,7 @@
#define ctxsw_prog_main_image_priv_access_map_config_o() (0x000000a0U) #define ctxsw_prog_main_image_priv_access_map_config_o() (0x000000a0U)
#define ctxsw_prog_main_image_priv_access_map_config_mode_s() (2U) #define ctxsw_prog_main_image_priv_access_map_config_mode_s() (2U)
#define ctxsw_prog_main_image_priv_access_map_config_mode_f(v)\ #define ctxsw_prog_main_image_priv_access_map_config_mode_f(v)\
(((v)&0x3U) << 0U) ((U32(v) & 0x3U) << 0U)
#define ctxsw_prog_main_image_priv_access_map_config_mode_m() (U32(0x3U) << 0U) #define ctxsw_prog_main_image_priv_access_map_config_mode_m() (U32(0x3U) << 0U)
#define ctxsw_prog_main_image_priv_access_map_config_mode_v(r)\ #define ctxsw_prog_main_image_priv_access_map_config_mode_v(r)\
(((r) >> 0U) & 0x3U) (((r) >> 0U) & 0x3U)
@@ -119,21 +119,21 @@
#define ctxsw_prog_main_image_misc_options_verif_features_disabled_f() (0x0U) #define ctxsw_prog_main_image_misc_options_verif_features_disabled_f() (0x0U)
#define ctxsw_prog_main_image_pmu_options_o() (0x00000070U) #define ctxsw_prog_main_image_pmu_options_o() (0x00000070U)
#define ctxsw_prog_main_image_pmu_options_boost_clock_frequencies_f(v)\ #define ctxsw_prog_main_image_pmu_options_boost_clock_frequencies_f(v)\
(((v)&0x1U) << 0U) ((U32(v) & 0x1U) << 0U)
#define ctxsw_prog_main_image_graphics_preemption_options_o() (0x00000080U) #define ctxsw_prog_main_image_graphics_preemption_options_o() (0x00000080U)
#define ctxsw_prog_main_image_graphics_preemption_options_control_f(v)\ #define ctxsw_prog_main_image_graphics_preemption_options_control_f(v)\
(((v)&0x3U) << 0U) ((U32(v) & 0x3U) << 0U)
#define ctxsw_prog_main_image_graphics_preemption_options_control_gfxp_f()\ #define ctxsw_prog_main_image_graphics_preemption_options_control_gfxp_f()\
(0x1U) (0x1U)
#define ctxsw_prog_main_image_full_preemption_ptr_o() (0x00000068U) #define ctxsw_prog_main_image_full_preemption_ptr_o() (0x00000068U)
#define ctxsw_prog_main_image_compute_preemption_options_o() (0x00000084U) #define ctxsw_prog_main_image_compute_preemption_options_o() (0x00000084U)
#define ctxsw_prog_main_image_compute_preemption_options_control_f(v)\ #define ctxsw_prog_main_image_compute_preemption_options_control_f(v)\
(((v)&0x3U) << 0U) ((U32(v) & 0x3U) << 0U)
#define ctxsw_prog_main_image_compute_preemption_options_control_cta_f() (0x1U) #define ctxsw_prog_main_image_compute_preemption_options_control_cta_f() (0x1U)
#define ctxsw_prog_main_image_compute_preemption_options_control_cilp_f() (0x2U) #define ctxsw_prog_main_image_compute_preemption_options_control_cilp_f() (0x2U)
#define ctxsw_prog_main_image_context_timestamp_buffer_control_o() (0x000000acU) #define ctxsw_prog_main_image_context_timestamp_buffer_control_o() (0x000000acU)
#define ctxsw_prog_main_image_context_timestamp_buffer_control_num_records_f(v)\ #define ctxsw_prog_main_image_context_timestamp_buffer_control_num_records_f(v)\
(((v)&0xffffU) << 0U) ((U32(v) & 0xffffU) << 0U)
#define ctxsw_prog_main_image_context_timestamp_buffer_ptr_hi_o() (0x000000b0U) #define ctxsw_prog_main_image_context_timestamp_buffer_ptr_hi_o() (0x000000b0U)
#define ctxsw_prog_main_image_context_timestamp_buffer_ptr_hi_v_m()\ #define ctxsw_prog_main_image_context_timestamp_buffer_ptr_hi_v_m()\
(U32(0xfffffffU) << 0U) (U32(0xfffffffU) << 0U)
@@ -147,7 +147,7 @@
(0x30000000U) (0x30000000U)
#define ctxsw_prog_main_image_context_timestamp_buffer_ptr_o() (0x000000b4U) #define ctxsw_prog_main_image_context_timestamp_buffer_ptr_o() (0x000000b4U)
#define ctxsw_prog_main_image_context_timestamp_buffer_ptr_v_f(v)\ #define ctxsw_prog_main_image_context_timestamp_buffer_ptr_v_f(v)\
(((v)&0xffffffffU) << 0U) ((U32(v) & 0xffffffffU) << 0U)
#define ctxsw_prog_record_timestamp_record_size_in_bytes_v() (0x00000080U) #define ctxsw_prog_record_timestamp_record_size_in_bytes_v() (0x00000080U)
#define ctxsw_prog_record_timestamp_record_size_in_words_v() (0x00000020U) #define ctxsw_prog_record_timestamp_record_size_in_words_v() (0x00000020U)
#define ctxsw_prog_record_timestamp_magic_value_lo_o() (0x00000000U) #define ctxsw_prog_record_timestamp_magic_value_lo_o() (0x00000000U)
@@ -158,10 +158,12 @@
#define ctxsw_prog_record_timestamp_context_ptr_o() (0x0000000cU) #define ctxsw_prog_record_timestamp_context_ptr_o() (0x0000000cU)
#define ctxsw_prog_record_timestamp_timestamp_lo_o() (0x00000018U) #define ctxsw_prog_record_timestamp_timestamp_lo_o() (0x00000018U)
#define ctxsw_prog_record_timestamp_timestamp_hi_o() (0x0000001cU) #define ctxsw_prog_record_timestamp_timestamp_hi_o() (0x0000001cU)
#define ctxsw_prog_record_timestamp_timestamp_hi_v_f(v) (((v)&0xffffffU) << 0U) #define ctxsw_prog_record_timestamp_timestamp_hi_v_f(v)\
((U32(v) & 0xffffffU) << 0U)
#define ctxsw_prog_record_timestamp_timestamp_hi_v_v(r)\ #define ctxsw_prog_record_timestamp_timestamp_hi_v_v(r)\
(((r) >> 0U) & 0xffffffU) (((r) >> 0U) & 0xffffffU)
#define ctxsw_prog_record_timestamp_timestamp_hi_tag_f(v) (((v)&0xffU) << 24U) #define ctxsw_prog_record_timestamp_timestamp_hi_tag_f(v)\
((U32(v) & 0xffU) << 24U)
#define ctxsw_prog_record_timestamp_timestamp_hi_tag_m() (U32(0xffU) << 24U) #define ctxsw_prog_record_timestamp_timestamp_hi_tag_m() (U32(0xffU) << 24U)
#define ctxsw_prog_record_timestamp_timestamp_hi_tag_v(r) (((r) >> 24U) & 0xffU) #define ctxsw_prog_record_timestamp_timestamp_hi_tag_v(r) (((r) >> 24U) & 0xffU)
#define ctxsw_prog_record_timestamp_timestamp_hi_tag_ctxsw_req_by_host_v()\ #define ctxsw_prog_record_timestamp_timestamp_hi_tag_ctxsw_req_by_host_v()\

122
drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_falcon_gp10b.h
View File

@@ -68,44 +68,44 @@
#define falcon_falcon_irqstat_swgen0_true_f() (0x40U) #define falcon_falcon_irqstat_swgen0_true_f() (0x40U)
#define falcon_falcon_irqmode_r() (0x0000000cU) #define falcon_falcon_irqmode_r() (0x0000000cU)
#define falcon_falcon_irqmset_r() (0x00000010U) #define falcon_falcon_irqmset_r() (0x00000010U)
#define falcon_falcon_irqmset_gptmr_f(v) (((v)&0x1U) << 0U) #define falcon_falcon_irqmset_gptmr_f(v) ((U32(v) & 0x1U) << 0U)
#define falcon_falcon_irqmset_wdtmr_f(v) (((v)&0x1U) << 1U) #define falcon_falcon_irqmset_wdtmr_f(v) ((U32(v) & 0x1U) << 1U)
#define falcon_falcon_irqmset_mthd_f(v) (((v)&0x1U) << 2U) #define falcon_falcon_irqmset_mthd_f(v) ((U32(v) & 0x1U) << 2U)
#define falcon_falcon_irqmset_ctxsw_f(v) (((v)&0x1U) << 3U) #define falcon_falcon_irqmset_ctxsw_f(v) ((U32(v) & 0x1U) << 3U)
#define falcon_falcon_irqmset_halt_f(v) (((v)&0x1U) << 4U) #define falcon_falcon_irqmset_halt_f(v) ((U32(v) & 0x1U) << 4U)
#define falcon_falcon_irqmset_exterr_f(v) (((v)&0x1U) << 5U) #define falcon_falcon_irqmset_exterr_f(v) ((U32(v) & 0x1U) << 5U)
#define falcon_falcon_irqmset_swgen0_f(v) (((v)&0x1U) << 6U) #define falcon_falcon_irqmset_swgen0_f(v) ((U32(v) & 0x1U) << 6U)
#define falcon_falcon_irqmset_swgen1_f(v) (((v)&0x1U) << 7U) #define falcon_falcon_irqmset_swgen1_f(v) ((U32(v) & 0x1U) << 7U)
#define falcon_falcon_irqmclr_r() (0x00000014U) #define falcon_falcon_irqmclr_r() (0x00000014U)
#define falcon_falcon_irqmclr_gptmr_f(v) (((v)&0x1U) << 0U) #define falcon_falcon_irqmclr_gptmr_f(v) ((U32(v) & 0x1U) << 0U)
#define falcon_falcon_irqmclr_wdtmr_f(v) (((v)&0x1U) << 1U) #define falcon_falcon_irqmclr_wdtmr_f(v) ((U32(v) & 0x1U) << 1U)
#define falcon_falcon_irqmclr_mthd_f(v) (((v)&0x1U) << 2U) #define falcon_falcon_irqmclr_mthd_f(v) ((U32(v) & 0x1U) << 2U)
#define falcon_falcon_irqmclr_ctxsw_f(v) (((v)&0x1U) << 3U) #define falcon_falcon_irqmclr_ctxsw_f(v) ((U32(v) & 0x1U) << 3U)
#define falcon_falcon_irqmclr_halt_f(v) (((v)&0x1U) << 4U) #define falcon_falcon_irqmclr_halt_f(v) ((U32(v) & 0x1U) << 4U)
#define falcon_falcon_irqmclr_exterr_f(v) (((v)&0x1U) << 5U) #define falcon_falcon_irqmclr_exterr_f(v) ((U32(v) & 0x1U) << 5U)
#define falcon_falcon_irqmclr_swgen0_f(v) (((v)&0x1U) << 6U) #define falcon_falcon_irqmclr_swgen0_f(v) ((U32(v) & 0x1U) << 6U)
#define falcon_falcon_irqmclr_swgen1_f(v) (((v)&0x1U) << 7U) #define falcon_falcon_irqmclr_swgen1_f(v) ((U32(v) & 0x1U) << 7U)
#define falcon_falcon_irqmclr_ext_f(v) (((v)&0xffU) << 8U) #define falcon_falcon_irqmclr_ext_f(v) ((U32(v) & 0xffU) << 8U)
#define falcon_falcon_irqmask_r() (0x00000018U) #define falcon_falcon_irqmask_r() (0x00000018U)
#define falcon_falcon_irqdest_r() (0x0000001cU) #define falcon_falcon_irqdest_r() (0x0000001cU)
#define falcon_falcon_irqdest_host_gptmr_f(v) (((v)&0x1U) << 0U) #define falcon_falcon_irqdest_host_gptmr_f(v) ((U32(v) & 0x1U) << 0U)
#define falcon_falcon_irqdest_host_wdtmr_f(v) (((v)&0x1U) << 1U) #define falcon_falcon_irqdest_host_wdtmr_f(v) ((U32(v) & 0x1U) << 1U)
#define falcon_falcon_irqdest_host_mthd_f(v) (((v)&0x1U) << 2U) #define falcon_falcon_irqdest_host_mthd_f(v) ((U32(v) & 0x1U) << 2U)
#define falcon_falcon_irqdest_host_ctxsw_f(v) (((v)&0x1U) << 3U) #define falcon_falcon_irqdest_host_ctxsw_f(v) ((U32(v) & 0x1U) << 3U)
#define falcon_falcon_irqdest_host_halt_f(v) (((v)&0x1U) << 4U) #define falcon_falcon_irqdest_host_halt_f(v) ((U32(v) & 0x1U) << 4U)
#define falcon_falcon_irqdest_host_exterr_f(v) (((v)&0x1U) << 5U) #define falcon_falcon_irqdest_host_exterr_f(v) ((U32(v) & 0x1U) << 5U)
#define falcon_falcon_irqdest_host_swgen0_f(v) (((v)&0x1U) << 6U) #define falcon_falcon_irqdest_host_swgen0_f(v) ((U32(v) & 0x1U) << 6U)
#define falcon_falcon_irqdest_host_swgen1_f(v) (((v)&0x1U) << 7U) #define falcon_falcon_irqdest_host_swgen1_f(v) ((U32(v) & 0x1U) << 7U)
#define falcon_falcon_irqdest_host_ext_f(v) (((v)&0xffU) << 8U) #define falcon_falcon_irqdest_host_ext_f(v) ((U32(v) & 0xffU) << 8U)
#define falcon_falcon_irqdest_target_gptmr_f(v) (((v)&0x1U) << 16U) #define falcon_falcon_irqdest_target_gptmr_f(v) ((U32(v) & 0x1U) << 16U)
#define falcon_falcon_irqdest_target_wdtmr_f(v) (((v)&0x1U) << 17U) #define falcon_falcon_irqdest_target_wdtmr_f(v) ((U32(v) & 0x1U) << 17U)
#define falcon_falcon_irqdest_target_mthd_f(v) (((v)&0x1U) << 18U) #define falcon_falcon_irqdest_target_mthd_f(v) ((U32(v) & 0x1U) << 18U)
#define falcon_falcon_irqdest_target_ctxsw_f(v) (((v)&0x1U) << 19U) #define falcon_falcon_irqdest_target_ctxsw_f(v) ((U32(v) & 0x1U) << 19U)
#define falcon_falcon_irqdest_target_halt_f(v) (((v)&0x1U) << 20U) #define falcon_falcon_irqdest_target_halt_f(v) ((U32(v) & 0x1U) << 20U)
#define falcon_falcon_irqdest_target_exterr_f(v) (((v)&0x1U) << 21U) #define falcon_falcon_irqdest_target_exterr_f(v) ((U32(v) & 0x1U) << 21U)
#define falcon_falcon_irqdest_target_swgen0_f(v) (((v)&0x1U) << 22U) #define falcon_falcon_irqdest_target_swgen0_f(v) ((U32(v) & 0x1U) << 22U)
#define falcon_falcon_irqdest_target_swgen1_f(v) (((v)&0x1U) << 23U) #define falcon_falcon_irqdest_target_swgen1_f(v) ((U32(v) & 0x1U) << 23U)
#define falcon_falcon_irqdest_target_ext_f(v) (((v)&0xffU) << 24U) #define falcon_falcon_irqdest_target_ext_f(v) ((U32(v) & 0xffU) << 24U)
#define falcon_falcon_curctx_r() (0x00000050U) #define falcon_falcon_curctx_r() (0x00000050U)
#define falcon_falcon_nxtctx_r() (0x00000054U) #define falcon_falcon_nxtctx_r() (0x00000054U)
#define falcon_falcon_mailbox0_r() (0x00000040U) #define falcon_falcon_mailbox0_r() (0x00000040U)
@@ -118,24 +118,24 @@
#define falcon_falcon_os_r() (0x00000080U) #define falcon_falcon_os_r() (0x00000080U)
#define falcon_falcon_engctl_r() (0x000000a4U) #define falcon_falcon_engctl_r() (0x000000a4U)
#define falcon_falcon_cpuctl_r() (0x00000100U) #define falcon_falcon_cpuctl_r() (0x00000100U)
#define falcon_falcon_cpuctl_startcpu_f(v) (((v)&0x1U) << 1U) #define falcon_falcon_cpuctl_startcpu_f(v) ((U32(v) & 0x1U) << 1U)
#define falcon_falcon_cpuctl_sreset_f(v) (((v)&0x1U) << 2U) #define falcon_falcon_cpuctl_sreset_f(v) ((U32(v) & 0x1U) << 2U)
#define falcon_falcon_cpuctl_hreset_f(v) (((v)&0x1U) << 3U) #define falcon_falcon_cpuctl_hreset_f(v) ((U32(v) & 0x1U) << 3U)
#define falcon_falcon_cpuctl_halt_intr_f(v) (((v)&0x1U) << 4U) #define falcon_falcon_cpuctl_halt_intr_f(v) ((U32(v) & 0x1U) << 4U)
#define falcon_falcon_cpuctl_halt_intr_m() (U32(0x1U) << 4U) #define falcon_falcon_cpuctl_halt_intr_m() (U32(0x1U) << 4U)
#define falcon_falcon_cpuctl_halt_intr_v(r) (((r) >> 4U) & 0x1U) #define falcon_falcon_cpuctl_halt_intr_v(r) (((r) >> 4U) & 0x1U)
#define falcon_falcon_cpuctl_stopped_m() (U32(0x1U) << 5U) #define falcon_falcon_cpuctl_stopped_m() (U32(0x1U) << 5U)
#define falcon_falcon_cpuctl_cpuctl_alias_en_f(v) (((v)&0x1U) << 6U) #define falcon_falcon_cpuctl_cpuctl_alias_en_f(v) ((U32(v) & 0x1U) << 6U)
#define falcon_falcon_cpuctl_cpuctl_alias_en_m() (U32(0x1U) << 6U) #define falcon_falcon_cpuctl_cpuctl_alias_en_m() (U32(0x1U) << 6U)
#define falcon_falcon_cpuctl_cpuctl_alias_en_v(r) (((r) >> 6U) & 0x1U) #define falcon_falcon_cpuctl_cpuctl_alias_en_v(r) (((r) >> 6U) & 0x1U)
#define falcon_falcon_cpuctl_alias_r() (0x00000130U) #define falcon_falcon_cpuctl_alias_r() (0x00000130U)
#define falcon_falcon_cpuctl_alias_startcpu_f(v) (((v)&0x1U) << 1U) #define falcon_falcon_cpuctl_alias_startcpu_f(v) ((U32(v) & 0x1U) << 1U)
#define falcon_falcon_imemc_r(i)\ #define falcon_falcon_imemc_r(i)\
(nvgpu_safe_add_u32(0x00000180U, nvgpu_safe_mult_u32((i), 16U))) (nvgpu_safe_add_u32(0x00000180U, nvgpu_safe_mult_u32((i), 16U)))
#define falcon_falcon_imemc_offs_f(v) (((v)&0x3fU) << 2U) #define falcon_falcon_imemc_offs_f(v) ((U32(v) & 0x3fU) << 2U)
#define falcon_falcon_imemc_blk_f(v) (((v)&0xffU) << 8U) #define falcon_falcon_imemc_blk_f(v) ((U32(v) & 0xffU) << 8U)
#define falcon_falcon_imemc_aincw_f(v) (((v)&0x1U) << 24U) #define falcon_falcon_imemc_aincw_f(v) ((U32(v) & 0x1U) << 24U)
#define falcon_falcon_imemc_secure_f(v) (((v)&0x1U) << 28U) #define falcon_falcon_imemc_secure_f(v) ((U32(v) & 0x1U) << 28U)
#define falcon_falcon_imemd_r(i)\ #define falcon_falcon_imemd_r(i)\
(nvgpu_safe_add_u32(0x00000184U, nvgpu_safe_mult_u32((i), 16U))) (nvgpu_safe_add_u32(0x00000184U, nvgpu_safe_mult_u32((i), 16U)))
#define falcon_falcon_imemt_r(i)\ #define falcon_falcon_imemt_r(i)\
@@ -143,11 +143,11 @@
#define falcon_falcon_sctl_r() (0x00000240U) #define falcon_falcon_sctl_r() (0x00000240U)
#define falcon_falcon_mmu_phys_sec_r() (0x00100ce4U) #define falcon_falcon_mmu_phys_sec_r() (0x00100ce4U)
#define falcon_falcon_bootvec_r() (0x00000104U) #define falcon_falcon_bootvec_r() (0x00000104U)
#define falcon_falcon_bootvec_vec_f(v) (((v)&0xffffffffU) << 0U) #define falcon_falcon_bootvec_vec_f(v) ((U32(v) & 0xffffffffU) << 0U)
#define falcon_falcon_dmactl_r() (0x0000010cU) #define falcon_falcon_dmactl_r() (0x0000010cU)
#define falcon_falcon_dmactl_dmem_scrubbing_m() (U32(0x1U) << 1U) #define falcon_falcon_dmactl_dmem_scrubbing_m() (U32(0x1U) << 1U)
#define falcon_falcon_dmactl_imem_scrubbing_m() (U32(0x1U) << 2U) #define falcon_falcon_dmactl_imem_scrubbing_m() (U32(0x1U) << 2U)
#define falcon_falcon_dmactl_require_ctx_f(v) (((v)&0x1U) << 0U) #define falcon_falcon_dmactl_require_ctx_f(v) ((U32(v) & 0x1U) << 0U)
#define falcon_falcon_hwcfg_r() (0x00000108U) #define falcon_falcon_hwcfg_r() (0x00000108U)
#define falcon_falcon_hwcfg_imem_size_v(r) (((r) >> 0U) & 0x1ffU) #define falcon_falcon_hwcfg_imem_size_v(r) (((r) >> 0U) & 0x1ffU)
#define falcon_falcon_hwcfg_dmem_size_v(r) (((r) >> 9U) & 0x1ffU) #define falcon_falcon_hwcfg_dmem_size_v(r) (((r) >> 9U) & 0x1ffU)
@@ -155,19 +155,19 @@
#define falcon_falcon_dmatrfbase1_r() (0x00000128U) #define falcon_falcon_dmatrfbase1_r() (0x00000128U)
#define falcon_falcon_dmatrfmoffs_r() (0x00000114U) #define falcon_falcon_dmatrfmoffs_r() (0x00000114U)
#define falcon_falcon_imctl_debug_r() (0x0000015cU) #define falcon_falcon_imctl_debug_r() (0x0000015cU)
#define falcon_falcon_imctl_debug_addr_blk_f(v) (((v)&0xffffffU) << 0U) #define falcon_falcon_imctl_debug_addr_blk_f(v) ((U32(v) & 0xffffffU) << 0U)
#define falcon_falcon_imctl_debug_cmd_f(v) (((v)&0x7U) << 24U) #define falcon_falcon_imctl_debug_cmd_f(v) ((U32(v) & 0x7U) << 24U)
#define falcon_falcon_imstat_r() (0x00000144U) #define falcon_falcon_imstat_r() (0x00000144U)
#define falcon_falcon_traceidx_r() (0x00000148U) #define falcon_falcon_traceidx_r() (0x00000148U)
#define falcon_falcon_traceidx_maxidx_v(r) (((r) >> 16U) & 0xffU) #define falcon_falcon_traceidx_maxidx_v(r) (((r) >> 16U) & 0xffU)
#define falcon_falcon_traceidx_idx_f(v) (((v)&0xffU) << 0U) #define falcon_falcon_traceidx_idx_f(v) ((U32(v) & 0xffU) << 0U)
#define falcon_falcon_tracepc_r() (0x0000014cU) #define falcon_falcon_tracepc_r() (0x0000014cU)
#define falcon_falcon_tracepc_pc_v(r) (((r) >> 0U) & 0xffffffU) #define falcon_falcon_tracepc_pc_v(r) (((r) >> 0U) & 0xffffffU)
#define falcon_falcon_dmatrfcmd_r() (0x00000118U) #define falcon_falcon_dmatrfcmd_r() (0x00000118U)
#define falcon_falcon_dmatrfcmd_imem_f(v) (((v)&0x1U) << 4U) #define falcon_falcon_dmatrfcmd_imem_f(v) ((U32(v) & 0x1U) << 4U)
#define falcon_falcon_dmatrfcmd_write_f(v) (((v)&0x1U) << 5U) #define falcon_falcon_dmatrfcmd_write_f(v) ((U32(v) & 0x1U) << 5U)
#define falcon_falcon_dmatrfcmd_size_f(v) (((v)&0x7U) << 8U) #define falcon_falcon_dmatrfcmd_size_f(v) ((U32(v) & 0x7U) << 8U)
#define falcon_falcon_dmatrfcmd_ctxdma_f(v) (((v)&0x7U) << 12U) #define falcon_falcon_dmatrfcmd_ctxdma_f(v) ((U32(v) & 0x7U) << 12U)
#define falcon_falcon_dmatrffboffs_r() (0x0000011cU) #define falcon_falcon_dmatrffboffs_r() (0x0000011cU)
#define falcon_falcon_exterraddr_r() (0x0010a168U) #define falcon_falcon_exterraddr_r() (0x0010a168U)
#define falcon_falcon_exterrstat_r() (0x0010a16cU) #define falcon_falcon_exterrstat_r() (0x0010a16cU)
@@ -176,26 +176,26 @@
#define falcon_falcon_exterrstat_valid_true_v() (0x00000001U) #define falcon_falcon_exterrstat_valid_true_v() (0x00000001U)
#define falcon_falcon_icd_cmd_r() (0x00000200U) #define falcon_falcon_icd_cmd_r() (0x00000200U)
#define falcon_falcon_icd_cmd_opc_s() (4U) #define falcon_falcon_icd_cmd_opc_s() (4U)
#define falcon_falcon_icd_cmd_opc_f(v) (((v)&0xfU) << 0U) #define falcon_falcon_icd_cmd_opc_f(v) ((U32(v) & 0xfU) << 0U)
#define falcon_falcon_icd_cmd_opc_m() (U32(0xfU) << 0U) #define falcon_falcon_icd_cmd_opc_m() (U32(0xfU) << 0U)
#define falcon_falcon_icd_cmd_opc_v(r) (((r) >> 0U) & 0xfU) #define falcon_falcon_icd_cmd_opc_v(r) (((r) >> 0U) & 0xfU)
#define falcon_falcon_icd_cmd_opc_rreg_f() (0x8U) #define falcon_falcon_icd_cmd_opc_rreg_f() (0x8U)
#define falcon_falcon_icd_cmd_opc_rstat_f() (0xeU) #define falcon_falcon_icd_cmd_opc_rstat_f() (0xeU)
#define falcon_falcon_icd_cmd_idx_f(v) (((v)&0x1fU) << 8U) #define falcon_falcon_icd_cmd_idx_f(v) ((U32(v) & 0x1fU) << 8U)
#define falcon_falcon_icd_rdata_r() (0x0000020cU) #define falcon_falcon_icd_rdata_r() (0x0000020cU)
#define falcon_falcon_dmemc_r(i)\ #define falcon_falcon_dmemc_r(i)\
(nvgpu_safe_add_u32(0x000001c0U, nvgpu_safe_mult_u32((i), 8U))) (nvgpu_safe_add_u32(0x000001c0U, nvgpu_safe_mult_u32((i), 8U)))
#define falcon_falcon_dmemc_offs_f(v) (((v)&0x3fU) << 2U) #define falcon_falcon_dmemc_offs_f(v) ((U32(v) & 0x3fU) << 2U)
#define falcon_falcon_dmemc_offs_m() (U32(0x3fU) << 2U) #define falcon_falcon_dmemc_offs_m() (U32(0x3fU) << 2U)
#define falcon_falcon_dmemc_blk_f(v) (((v)&0xffU) << 8U) #define falcon_falcon_dmemc_blk_f(v) ((U32(v) & 0xffU) << 8U)
#define falcon_falcon_dmemc_blk_m() (U32(0xffU) << 8U) #define falcon_falcon_dmemc_blk_m() (U32(0xffU) << 8U)
#define falcon_falcon_dmemc_aincw_f(v) (((v)&0x1U) << 24U) #define falcon_falcon_dmemc_aincw_f(v) ((U32(v) & 0x1U) << 24U)
#define falcon_falcon_dmemc_aincr_f(v) (((v)&0x1U) << 25U) #define falcon_falcon_dmemc_aincr_f(v) ((U32(v) & 0x1U) << 25U)
#define falcon_falcon_dmemd_r(i)\ #define falcon_falcon_dmemd_r(i)\
(nvgpu_safe_add_u32(0x000001c4U, nvgpu_safe_mult_u32((i), 8U))) (nvgpu_safe_add_u32(0x000001c4U, nvgpu_safe_mult_u32((i), 8U)))
#define falcon_falcon_debug1_r() (0x00000090U) #define falcon_falcon_debug1_r() (0x00000090U)
#define falcon_falcon_debug1_ctxsw_mode_s() (1U) #define falcon_falcon_debug1_ctxsw_mode_s() (1U)
#define falcon_falcon_debug1_ctxsw_mode_f(v) (((v)&0x1U) << 16U) #define falcon_falcon_debug1_ctxsw_mode_f(v) ((U32(v) & 0x1U) << 16U)
#define falcon_falcon_debug1_ctxsw_mode_m() (U32(0x1U) << 16U) #define falcon_falcon_debug1_ctxsw_mode_m() (U32(0x1U) << 16U)
#define falcon_falcon_debug1_ctxsw_mode_v(r) (((r) >> 16U) & 0x1U) #define falcon_falcon_debug1_ctxsw_mode_v(r) (((r) >> 16U) & 0x1U)
#define falcon_falcon_debug1_ctxsw_mode_init_f() (0x0U) #define falcon_falcon_debug1_ctxsw_mode_init_f() (0x0U)

26
drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_fb_gp10b.h
View File

@@ -68,17 +68,17 @@
#define fb_mmu_invalidate_pdb_r() (0x00100cb8U) #define fb_mmu_invalidate_pdb_r() (0x00100cb8U)
#define fb_mmu_invalidate_pdb_aperture_vid_mem_f() (0x0U) #define fb_mmu_invalidate_pdb_aperture_vid_mem_f() (0x0U)
#define fb_mmu_invalidate_pdb_aperture_sys_mem_f() (0x2U) #define fb_mmu_invalidate_pdb_aperture_sys_mem_f() (0x2U)
#define fb_mmu_invalidate_pdb_addr_f(v) (((v)&0xfffffffU) << 4U) #define fb_mmu_invalidate_pdb_addr_f(v) ((U32(v) & 0xfffffffU) << 4U)
#define fb_mmu_invalidate_r() (0x00100cbcU) #define fb_mmu_invalidate_r() (0x00100cbcU)
#define fb_mmu_invalidate_all_va_true_f() (0x1U) #define fb_mmu_invalidate_all_va_true_f() (0x1U)
#define fb_mmu_invalidate_all_pdb_true_f() (0x2U) #define fb_mmu_invalidate_all_pdb_true_f() (0x2U)
#define fb_mmu_invalidate_hubtlb_only_s() (1U) #define fb_mmu_invalidate_hubtlb_only_s() (1U)
#define fb_mmu_invalidate_hubtlb_only_f(v) (((v)&0x1U) << 2U) #define fb_mmu_invalidate_hubtlb_only_f(v) ((U32(v) & 0x1U) << 2U)
#define fb_mmu_invalidate_hubtlb_only_m() (U32(0x1U) << 2U) #define fb_mmu_invalidate_hubtlb_only_m() (U32(0x1U) << 2U)
#define fb_mmu_invalidate_hubtlb_only_v(r) (((r) >> 2U) & 0x1U) #define fb_mmu_invalidate_hubtlb_only_v(r) (((r) >> 2U) & 0x1U)
#define fb_mmu_invalidate_hubtlb_only_true_f() (0x4U) #define fb_mmu_invalidate_hubtlb_only_true_f() (0x4U)
#define fb_mmu_invalidate_replay_s() (3U) #define fb_mmu_invalidate_replay_s() (3U)
#define fb_mmu_invalidate_replay_f(v) (((v)&0x7U) << 3U) #define fb_mmu_invalidate_replay_f(v) ((U32(v) & 0x7U) << 3U)
#define fb_mmu_invalidate_replay_m() (U32(0x7U) << 3U) #define fb_mmu_invalidate_replay_m() (U32(0x7U) << 3U)
#define fb_mmu_invalidate_replay_v(r) (((r) >> 3U) & 0x7U) #define fb_mmu_invalidate_replay_v(r) (((r) >> 3U) & 0x7U)
#define fb_mmu_invalidate_replay_none_f() (0x0U) #define fb_mmu_invalidate_replay_none_f() (0x0U)
@@ -88,33 +88,33 @@
#define fb_mmu_invalidate_replay_cancel_global_f() (0x20U) #define fb_mmu_invalidate_replay_cancel_global_f() (0x20U)
#define fb_mmu_invalidate_replay_cancel_f() (0x20U) #define fb_mmu_invalidate_replay_cancel_f() (0x20U)
#define fb_mmu_invalidate_sys_membar_s() (1U) #define fb_mmu_invalidate_sys_membar_s() (1U)
#define fb_mmu_invalidate_sys_membar_f(v) (((v)&0x1U) << 6U) #define fb_mmu_invalidate_sys_membar_f(v) ((U32(v) & 0x1U) << 6U)
#define fb_mmu_invalidate_sys_membar_m() (U32(0x1U) << 6U) #define fb_mmu_invalidate_sys_membar_m() (U32(0x1U) << 6U)
#define fb_mmu_invalidate_sys_membar_v(r) (((r) >> 6U) & 0x1U) #define fb_mmu_invalidate_sys_membar_v(r) (((r) >> 6U) & 0x1U)
#define fb_mmu_invalidate_sys_membar_true_f() (0x40U) #define fb_mmu_invalidate_sys_membar_true_f() (0x40U)
#define fb_mmu_invalidate_ack_s() (2U) #define fb_mmu_invalidate_ack_s() (2U)
#define fb_mmu_invalidate_ack_f(v) (((v)&0x3U) << 7U) #define fb_mmu_invalidate_ack_f(v) ((U32(v) & 0x3U) << 7U)
#define fb_mmu_invalidate_ack_m() (U32(0x3U) << 7U) #define fb_mmu_invalidate_ack_m() (U32(0x3U) << 7U)
#define fb_mmu_invalidate_ack_v(r) (((r) >> 7U) & 0x3U) #define fb_mmu_invalidate_ack_v(r) (((r) >> 7U) & 0x3U)
#define fb_mmu_invalidate_ack_ack_none_required_f() (0x0U) #define fb_mmu_invalidate_ack_ack_none_required_f() (0x0U)
#define fb_mmu_invalidate_ack_ack_intranode_f() (0x100U) #define fb_mmu_invalidate_ack_ack_intranode_f() (0x100U)
#define fb_mmu_invalidate_ack_ack_globally_f() (0x80U) #define fb_mmu_invalidate_ack_ack_globally_f() (0x80U)
#define fb_mmu_invalidate_cancel_client_id_s() (6U) #define fb_mmu_invalidate_cancel_client_id_s() (6U)
#define fb_mmu_invalidate_cancel_client_id_f(v) (((v)&0x3fU) << 9U) #define fb_mmu_invalidate_cancel_client_id_f(v) ((U32(v) & 0x3fU) << 9U)
#define fb_mmu_invalidate_cancel_client_id_m() (U32(0x3fU) << 9U) #define fb_mmu_invalidate_cancel_client_id_m() (U32(0x3fU) << 9U)
#define fb_mmu_invalidate_cancel_client_id_v(r) (((r) >> 9U) & 0x3fU) #define fb_mmu_invalidate_cancel_client_id_v(r) (((r) >> 9U) & 0x3fU)
#define fb_mmu_invalidate_cancel_gpc_id_s() (5U) #define fb_mmu_invalidate_cancel_gpc_id_s() (5U)
#define fb_mmu_invalidate_cancel_gpc_id_f(v) (((v)&0x1fU) << 15U) #define fb_mmu_invalidate_cancel_gpc_id_f(v) ((U32(v) & 0x1fU) << 15U)
#define fb_mmu_invalidate_cancel_gpc_id_m() (U32(0x1fU) << 15U) #define fb_mmu_invalidate_cancel_gpc_id_m() (U32(0x1fU) << 15U)
#define fb_mmu_invalidate_cancel_gpc_id_v(r) (((r) >> 15U) & 0x1fU) #define fb_mmu_invalidate_cancel_gpc_id_v(r) (((r) >> 15U) & 0x1fU)
#define fb_mmu_invalidate_cancel_client_type_s() (1U) #define fb_mmu_invalidate_cancel_client_type_s() (1U)
#define fb_mmu_invalidate_cancel_client_type_f(v) (((v)&0x1U) << 20U) #define fb_mmu_invalidate_cancel_client_type_f(v) ((U32(v) & 0x1U) << 20U)
#define fb_mmu_invalidate_cancel_client_type_m() (U32(0x1U) << 20U) #define fb_mmu_invalidate_cancel_client_type_m() (U32(0x1U) << 20U)
#define fb_mmu_invalidate_cancel_client_type_v(r) (((r) >> 20U) & 0x1U) #define fb_mmu_invalidate_cancel_client_type_v(r) (((r) >> 20U) & 0x1U)
#define fb_mmu_invalidate_cancel_client_type_gpc_f() (0x0U) #define fb_mmu_invalidate_cancel_client_type_gpc_f() (0x0U)
#define fb_mmu_invalidate_cancel_client_type_hub_f() (0x100000U) #define fb_mmu_invalidate_cancel_client_type_hub_f() (0x100000U)
#define fb_mmu_invalidate_cancel_cache_level_s() (3U) #define fb_mmu_invalidate_cancel_cache_level_s() (3U)
#define fb_mmu_invalidate_cancel_cache_level_f(v) (((v)&0x7U) << 24U) #define fb_mmu_invalidate_cancel_cache_level_f(v) ((U32(v) & 0x7U) << 24U)
#define fb_mmu_invalidate_cancel_cache_level_m() (U32(0x7U) << 24U) #define fb_mmu_invalidate_cancel_cache_level_m() (U32(0x7U) << 24U)
#define fb_mmu_invalidate_cancel_cache_level_v(r) (((r) >> 24U) & 0x7U) #define fb_mmu_invalidate_cancel_cache_level_v(r) (((r) >> 24U) & 0x7U)
#define fb_mmu_invalidate_cancel_cache_level_all_f() (0x0U) #define fb_mmu_invalidate_cancel_cache_level_all_f() (0x0U)
@@ -126,13 +126,13 @@
#define fb_mmu_invalidate_cancel_cache_level_up_to_pde4_f() (0x6000000U) #define fb_mmu_invalidate_cancel_cache_level_up_to_pde4_f() (0x6000000U)
#define fb_mmu_invalidate_cancel_cache_level_up_to_pde5_f() (0x7000000U) #define fb_mmu_invalidate_cancel_cache_level_up_to_pde5_f() (0x7000000U)
#define fb_mmu_invalidate_trigger_s() (1U) #define fb_mmu_invalidate_trigger_s() (1U)
#define fb_mmu_invalidate_trigger_f(v) (((v)&0x1U) << 31U) #define fb_mmu_invalidate_trigger_f(v) ((U32(v) & 0x1U) << 31U)
#define fb_mmu_invalidate_trigger_m() (U32(0x1U) << 31U) #define fb_mmu_invalidate_trigger_m() (U32(0x1U) << 31U)
#define fb_mmu_invalidate_trigger_v(r) (((r) >> 31U) & 0x1U) #define fb_mmu_invalidate_trigger_v(r) (((r) >> 31U) & 0x1U)
#define fb_mmu_invalidate_trigger_true_f() (0x80000000U) #define fb_mmu_invalidate_trigger_true_f() (0x80000000U)
#define fb_mmu_debug_wr_r() (0x00100cc8U) #define fb_mmu_debug_wr_r() (0x00100cc8U)
#define fb_mmu_debug_wr_aperture_s() (2U) #define fb_mmu_debug_wr_aperture_s() (2U)
#define fb_mmu_debug_wr_aperture_f(v) (((v)&0x3U) << 0U) #define fb_mmu_debug_wr_aperture_f(v) ((U32(v) & 0x3U) << 0U)
#define fb_mmu_debug_wr_aperture_m() (U32(0x3U) << 0U) #define fb_mmu_debug_wr_aperture_m() (U32(0x3U) << 0U)
#define fb_mmu_debug_wr_aperture_v(r) (((r) >> 0U) & 0x3U) #define fb_mmu_debug_wr_aperture_v(r) (((r) >> 0U) & 0x3U)
#define fb_mmu_debug_wr_aperture_vid_mem_f() (0x0U) #define fb_mmu_debug_wr_aperture_vid_mem_f() (0x0U)
@@ -141,14 +141,14 @@
#define fb_mmu_debug_wr_vol_false_f() (0x0U) #define fb_mmu_debug_wr_vol_false_f() (0x0U)
#define fb_mmu_debug_wr_vol_true_v() (0x00000001U) #define fb_mmu_debug_wr_vol_true_v() (0x00000001U)
#define fb_mmu_debug_wr_vol_true_f() (0x4U) #define fb_mmu_debug_wr_vol_true_f() (0x4U)
#define fb_mmu_debug_wr_addr_f(v) (((v)&0xfffffffU) << 4U) #define fb_mmu_debug_wr_addr_f(v) ((U32(v) & 0xfffffffU) << 4U)
#define fb_mmu_debug_wr_addr_alignment_v() (0x0000000cU) #define fb_mmu_debug_wr_addr_alignment_v() (0x0000000cU)
#define fb_mmu_debug_rd_r() (0x00100cccU) #define fb_mmu_debug_rd_r() (0x00100cccU)
#define fb_mmu_debug_rd_aperture_vid_mem_f() (0x0U) #define fb_mmu_debug_rd_aperture_vid_mem_f() (0x0U)
#define fb_mmu_debug_rd_aperture_sys_mem_coh_f() (0x2U) #define fb_mmu_debug_rd_aperture_sys_mem_coh_f() (0x2U)
#define fb_mmu_debug_rd_aperture_sys_mem_ncoh_f() (0x3U) #define fb_mmu_debug_rd_aperture_sys_mem_ncoh_f() (0x3U)
#define fb_mmu_debug_rd_vol_false_f() (0x0U) #define fb_mmu_debug_rd_vol_false_f() (0x0U)
#define fb_mmu_debug_rd_addr_f(v) (((v)&0xfffffffU) << 4U) #define fb_mmu_debug_rd_addr_f(v) ((U32(v) & 0xfffffffU) << 4U)
#define fb_mmu_debug_rd_addr_alignment_v() (0x0000000cU) #define fb_mmu_debug_rd_addr_alignment_v() (0x0000000cU)
#define fb_mmu_debug_ctrl_r() (0x00100cc4U) #define fb_mmu_debug_ctrl_r() (0x00100cc4U)
#define fb_mmu_debug_ctrl_debug_v(r) (((r) >> 16U) & 0x1U) #define fb_mmu_debug_ctrl_debug_v(r) (((r) >> 16U) & 0x1U)

42
drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_fifo_gp10b.h
View File

@@ -60,24 +60,24 @@
#include <nvgpu/safe_ops.h> #include <nvgpu/safe_ops.h>
#define fifo_bar1_base_r() (0x00002254U) #define fifo_bar1_base_r() (0x00002254U)
#define fifo_bar1_base_ptr_f(v) (((v)&0xfffffffU) << 0U) #define fifo_bar1_base_ptr_f(v) ((U32(v) & 0xfffffffU) << 0U)
#define fifo_bar1_base_ptr_align_shift_v() (0x0000000cU) #define fifo_bar1_base_ptr_align_shift_v() (0x0000000cU)
#define fifo_bar1_base_valid_false_f() (0x0U) #define fifo_bar1_base_valid_false_f() (0x0U)
#define fifo_bar1_base_valid_true_f() (0x10000000U) #define fifo_bar1_base_valid_true_f() (0x10000000U)
#define fifo_runlist_base_r() (0x00002270U) #define fifo_runlist_base_r() (0x00002270U)
#define fifo_runlist_base_ptr_f(v) (((v)&0xfffffffU) << 0U) #define fifo_runlist_base_ptr_f(v) ((U32(v) & 0xfffffffU) << 0U)
#define fifo_runlist_base_target_vid_mem_f() (0x0U) #define fifo_runlist_base_target_vid_mem_f() (0x0U)
#define fifo_runlist_base_target_sys_mem_coh_f() (0x20000000U) #define fifo_runlist_base_target_sys_mem_coh_f() (0x20000000U)
#define fifo_runlist_base_target_sys_mem_ncoh_f() (0x30000000U) #define fifo_runlist_base_target_sys_mem_ncoh_f() (0x30000000U)
#define fifo_runlist_r() (0x00002274U) #define fifo_runlist_r() (0x00002274U)
#define fifo_runlist_engine_f(v) (((v)&0xfU) << 20U) #define fifo_runlist_engine_f(v) ((U32(v) & 0xfU) << 20U)
#define fifo_eng_runlist_base_r(i)\ #define fifo_eng_runlist_base_r(i)\
(nvgpu_safe_add_u32(0x00002280U, nvgpu_safe_mult_u32((i), 8U))) (nvgpu_safe_add_u32(0x00002280U, nvgpu_safe_mult_u32((i), 8U)))
#define fifo_eng_runlist_base__size_1_v() (0x00000001U) #define fifo_eng_runlist_base__size_1_v() (0x00000001U)
#define fifo_eng_runlist_r(i)\ #define fifo_eng_runlist_r(i)\
(nvgpu_safe_add_u32(0x00002284U, nvgpu_safe_mult_u32((i), 8U))) (nvgpu_safe_add_u32(0x00002284U, nvgpu_safe_mult_u32((i), 8U)))
#define fifo_eng_runlist__size_1_v() (0x00000001U) #define fifo_eng_runlist__size_1_v() (0x00000001U)
#define fifo_eng_runlist_length_f(v) (((v)&0xffffU) << 0U) #define fifo_eng_runlist_length_f(v) ((U32(v) & 0xffffU) << 0U)
#define fifo_eng_runlist_length_max_v() (0x0000ffffU) #define fifo_eng_runlist_length_max_v() (0x0000ffffU)
#define fifo_eng_runlist_pending_true_f() (0x100000U) #define fifo_eng_runlist_pending_true_f() (0x100000U)
#define fifo_pb_timeslice_r(i)\ #define fifo_pb_timeslice_r(i)\
@@ -106,14 +106,14 @@
#define fifo_intr_0_runlist_event_pending_f() (0x40000000U) #define fifo_intr_0_runlist_event_pending_f() (0x40000000U)
#define fifo_intr_0_channel_intr_pending_f() (0x80000000U) #define fifo_intr_0_channel_intr_pending_f() (0x80000000U)
#define fifo_intr_en_0_r() (0x00002140U) #define fifo_intr_en_0_r() (0x00002140U)
#define fifo_intr_en_0_sched_error_f(v) (((v)&0x1U) << 8U) #define fifo_intr_en_0_sched_error_f(v) ((U32(v) & 0x1U) << 8U)
#define fifo_intr_en_0_sched_error_m() (U32(0x1U) << 8U) #define fifo_intr_en_0_sched_error_m() (U32(0x1U) << 8U)
#define fifo_intr_en_0_mmu_fault_f(v) (((v)&0x1U) << 28U) #define fifo_intr_en_0_mmu_fault_f(v) ((U32(v) & 0x1U) << 28U)
#define fifo_intr_en_0_mmu_fault_m() (U32(0x1U) << 28U) #define fifo_intr_en_0_mmu_fault_m() (U32(0x1U) << 28U)
#define fifo_intr_en_1_r() (0x00002528U) #define fifo_intr_en_1_r() (0x00002528U)
#define fifo_intr_bind_error_r() (0x0000252cU) #define fifo_intr_bind_error_r() (0x0000252cU)
#define fifo_intr_sched_error_r() (0x0000254cU) #define fifo_intr_sched_error_r() (0x0000254cU)
#define fifo_intr_sched_error_code_f(v) (((v)&0xffU) << 0U) #define fifo_intr_sched_error_code_f(v) ((U32(v) & 0xffU) << 0U)
#define fifo_intr_sched_error_code_ctxsw_timeout_v() (0x0000000aU) #define fifo_intr_sched_error_code_ctxsw_timeout_v() (0x0000000aU)
#define fifo_intr_chsw_error_r() (0x0000256cU) #define fifo_intr_chsw_error_r() (0x0000256cU)
#define fifo_intr_mmu_fault_id_r() (0x0000259cU) #define fifo_intr_mmu_fault_id_r() (0x0000259cU)
@@ -137,7 +137,7 @@
#define fifo_intr_mmu_fault_info_client_v(r) (((r) >> 8U) & 0x7fU) #define fifo_intr_mmu_fault_info_client_v(r) (((r) >> 8U) & 0x7fU)
#define fifo_intr_pbdma_id_r() (0x000025a0U) #define fifo_intr_pbdma_id_r() (0x000025a0U)
#define fifo_intr_pbdma_id_status_f(v, i)\ #define fifo_intr_pbdma_id_status_f(v, i)\
(((v) & 0x1) << (0U + i*1U)) ((U32(v) & 0x1U) << (0U + (i)*1U))
#define fifo_intr_pbdma_id_status_v(r, i)\ #define fifo_intr_pbdma_id_status_v(r, i)\
(((r) >> (0U + i*1U)) & 0x1U) (((r) >> (0U + i*1U)) & 0x1U)
#define fifo_intr_pbdma_id_status__size_1_v() (0x00000001U) #define fifo_intr_pbdma_id_status__size_1_v() (0x00000001U)
@@ -148,7 +148,7 @@
#define fifo_error_sched_disable_r() (0x0000262cU) #define fifo_error_sched_disable_r() (0x0000262cU)
#define fifo_sched_disable_r() (0x00002630U) #define fifo_sched_disable_r() (0x00002630U)
#define fifo_sched_disable_runlist_f(v, i)\ #define fifo_sched_disable_runlist_f(v, i)\
(((v) & 0x1) << (0U + i*1U)) ((U32(v) & 0x1U) << (0U + (i)*1U))
#define fifo_sched_disable_runlist_m(i)\ #define fifo_sched_disable_runlist_m(i)\
(U32(0x1U) << (0U + (i)*1U)) (U32(0x1U) << (0U + (i)*1U))
#define fifo_sched_disable_true_v() (0x00000001U) #define fifo_sched_disable_true_v() (0x00000001U)
@@ -156,12 +156,12 @@
#define fifo_preempt_pending_true_f() (0x100000U) #define fifo_preempt_pending_true_f() (0x100000U)
#define fifo_preempt_type_channel_f() (0x0U) #define fifo_preempt_type_channel_f() (0x0U)
#define fifo_preempt_type_tsg_f() (0x1000000U) #define fifo_preempt_type_tsg_f() (0x1000000U)
#define fifo_preempt_chid_f(v) (((v)&0xfffU) << 0U) #define fifo_preempt_chid_f(v) ((U32(v) & 0xfffU) << 0U)
#define fifo_preempt_id_f(v) (((v)&0xfffU) << 0U) #define fifo_preempt_id_f(v) ((U32(v) & 0xfffU) << 0U)
#define fifo_trigger_mmu_fault_r(i)\ #define fifo_trigger_mmu_fault_r(i)\
(nvgpu_safe_add_u32(0x00002a30U, nvgpu_safe_mult_u32((i), 4U))) (nvgpu_safe_add_u32(0x00002a30U, nvgpu_safe_mult_u32((i), 4U)))
#define fifo_trigger_mmu_fault_id_f(v) (((v)&0x1fU) << 0U) #define fifo_trigger_mmu_fault_id_f(v) ((U32(v) & 0x1fU) << 0U)
#define fifo_trigger_mmu_fault_enable_f(v) (((v)&0x1U) << 8U) #define fifo_trigger_mmu_fault_enable_f(v) ((U32(v) & 0x1U) << 8U)
#define fifo_engine_status_r(i)\ #define fifo_engine_status_r(i)\
(nvgpu_safe_add_u32(0x00002640U, nvgpu_safe_mult_u32((i), 8U))) (nvgpu_safe_add_u32(0x00002640U, nvgpu_safe_mult_u32((i), 8U)))
#define fifo_engine_status__size_1_v() (0x00000002U) #define fifo_engine_status__size_1_v() (0x00000002U)
@@ -209,31 +209,31 @@
#define fifo_replay_fault_buffer_lo_enable_v(r) (((r) >> 0U) & 0x1U) #define fifo_replay_fault_buffer_lo_enable_v(r) (((r) >> 0U) & 0x1U)
#define fifo_replay_fault_buffer_lo_enable_true_v() (0x00000001U) #define fifo_replay_fault_buffer_lo_enable_true_v() (0x00000001U)
#define fifo_replay_fault_buffer_lo_enable_false_v() (0x00000000U) #define fifo_replay_fault_buffer_lo_enable_false_v() (0x00000000U)
#define fifo_replay_fault_buffer_lo_base_f(v) (((v)&0xfffffU) << 12U) #define fifo_replay_fault_buffer_lo_base_f(v) ((U32(v) & 0xfffffU) << 12U)
#define fifo_replay_fault_buffer_lo_base_reset_v() (0x00000000U) #define fifo_replay_fault_buffer_lo_base_reset_v() (0x00000000U)
#define fifo_replay_fault_buffer_hi_r() (0x00002a74U) #define fifo_replay_fault_buffer_hi_r() (0x00002a74U)
#define fifo_replay_fault_buffer_hi_base_f(v) (((v)&0xffU) << 0U) #define fifo_replay_fault_buffer_hi_base_f(v) ((U32(v) & 0xffU) << 0U)
#define fifo_replay_fault_buffer_hi_base_reset_v() (0x00000000U) #define fifo_replay_fault_buffer_hi_base_reset_v() (0x00000000U)
#define fifo_replay_fault_buffer_size_r() (0x00002a78U) #define fifo_replay_fault_buffer_size_r() (0x00002a78U)
#define fifo_replay_fault_buffer_size_hw_f(v) (((v)&0x1ffU) << 0U) #define fifo_replay_fault_buffer_size_hw_f(v) ((U32(v) & 0x1ffU) << 0U)
#define fifo_replay_fault_buffer_size_hw_entries_v() (0x000000c0U) #define fifo_replay_fault_buffer_size_hw_entries_v() (0x000000c0U)
#define fifo_replay_fault_buffer_get_r() (0x00002a7cU) #define fifo_replay_fault_buffer_get_r() (0x00002a7cU)
#define fifo_replay_fault_buffer_get_offset_hw_f(v) (((v)&0x1ffU) << 0U) #define fifo_replay_fault_buffer_get_offset_hw_f(v) ((U32(v) & 0x1ffU) << 0U)
#define fifo_replay_fault_buffer_get_offset_hw_init_v() (0x00000000U) #define fifo_replay_fault_buffer_get_offset_hw_init_v() (0x00000000U)
#define fifo_replay_fault_buffer_put_r() (0x00002a80U) #define fifo_replay_fault_buffer_put_r() (0x00002a80U)
#define fifo_replay_fault_buffer_put_offset_hw_f(v) (((v)&0x1ffU) << 0U) #define fifo_replay_fault_buffer_put_offset_hw_f(v) ((U32(v) & 0x1ffU) << 0U)
#define fifo_replay_fault_buffer_put_offset_hw_init_v() (0x00000000U) #define fifo_replay_fault_buffer_put_offset_hw_init_v() (0x00000000U)
#define fifo_replay_fault_buffer_info_r() (0x00002a84U) #define fifo_replay_fault_buffer_info_r() (0x00002a84U)
#define fifo_replay_fault_buffer_info_overflow_f(v) (((v)&0x1U) << 0U) #define fifo_replay_fault_buffer_info_overflow_f(v) ((U32(v) & 0x1U) << 0U)
#define fifo_replay_fault_buffer_info_overflow_false_v() (0x00000000U) #define fifo_replay_fault_buffer_info_overflow_false_v() (0x00000000U)
#define fifo_replay_fault_buffer_info_overflow_true_v() (0x00000001U) #define fifo_replay_fault_buffer_info_overflow_true_v() (0x00000001U)
#define fifo_replay_fault_buffer_info_overflow_clear_v() (0x00000001U) #define fifo_replay_fault_buffer_info_overflow_clear_v() (0x00000001U)
#define fifo_replay_fault_buffer_info_write_nack_f(v) (((v)&0x1U) << 24U) #define fifo_replay_fault_buffer_info_write_nack_f(v) ((U32(v) & 0x1U) << 24U)
#define fifo_replay_fault_buffer_info_write_nack_false_v() (0x00000000U) #define fifo_replay_fault_buffer_info_write_nack_false_v() (0x00000000U)
#define fifo_replay_fault_buffer_info_write_nack_true_v() (0x00000001U) #define fifo_replay_fault_buffer_info_write_nack_true_v() (0x00000001U)
#define fifo_replay_fault_buffer_info_write_nack_clear_v() (0x00000001U) #define fifo_replay_fault_buffer_info_write_nack_clear_v() (0x00000001U)
#define fifo_replay_fault_buffer_info_fault_while_buffer_disabled_f(v)\ #define fifo_replay_fault_buffer_info_fault_while_buffer_disabled_f(v)\
(((v)&0x1U) << 28U) ((U32(v) & 0x1U) << 28U)
#define fifo_replay_fault_buffer_info_fault_while_buffer_disabled_false_v()\ #define fifo_replay_fault_buffer_info_fault_while_buffer_disabled_false_v()\
(0x00000000U) (0x00000000U)
#define fifo_replay_fault_buffer_info_fault_while_buffer_disabled_true_v()\ #define fifo_replay_fault_buffer_info_fault_while_buffer_disabled_true_v()\

6
drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_fuse_gp10b.h
View File

@@ -65,17 +65,17 @@
#define fuse_ctrl_opt_tpc_gpc_r(i)\ #define fuse_ctrl_opt_tpc_gpc_r(i)\
(nvgpu_safe_add_u32(0x00021838U, nvgpu_safe_mult_u32((i), 4U))) (nvgpu_safe_add_u32(0x00021838U, nvgpu_safe_mult_u32((i), 4U)))
#define fuse_ctrl_opt_ram_svop_pdp_r() (0x00021944U) #define fuse_ctrl_opt_ram_svop_pdp_r() (0x00021944U)
#define fuse_ctrl_opt_ram_svop_pdp_data_f(v) (((v)&0xffU) << 0U) #define fuse_ctrl_opt_ram_svop_pdp_data_f(v) ((U32(v) & 0xffU) << 0U)
#define fuse_ctrl_opt_ram_svop_pdp_data_m() (U32(0xffU) << 0U) #define fuse_ctrl_opt_ram_svop_pdp_data_m() (U32(0xffU) << 0U)
#define fuse_ctrl_opt_ram_svop_pdp_data_v(r) (((r) >> 0U) & 0xffU) #define fuse_ctrl_opt_ram_svop_pdp_data_v(r) (((r) >> 0U) & 0xffU)
#define fuse_ctrl_opt_ram_svop_pdp_override_r() (0x00021948U) #define fuse_ctrl_opt_ram_svop_pdp_override_r() (0x00021948U)
#define fuse_ctrl_opt_ram_svop_pdp_override_data_f(v) (((v)&0x1U) << 0U) #define fuse_ctrl_opt_ram_svop_pdp_override_data_f(v) ((U32(v) & 0x1U) << 0U)
#define fuse_ctrl_opt_ram_svop_pdp_override_data_m() (U32(0x1U) << 0U) #define fuse_ctrl_opt_ram_svop_pdp_override_data_m() (U32(0x1U) << 0U)
#define fuse_ctrl_opt_ram_svop_pdp_override_data_v(r) (((r) >> 0U) & 0x1U) #define fuse_ctrl_opt_ram_svop_pdp_override_data_v(r) (((r) >> 0U) & 0x1U)
#define fuse_ctrl_opt_ram_svop_pdp_override_data_yes_f() (0x1U) #define fuse_ctrl_opt_ram_svop_pdp_override_data_yes_f() (0x1U)
#define fuse_ctrl_opt_ram_svop_pdp_override_data_no_f() (0x0U) #define fuse_ctrl_opt_ram_svop_pdp_override_data_no_f() (0x0U)
#define fuse_status_opt_fbio_r() (0x00021c14U) #define fuse_status_opt_fbio_r() (0x00021c14U)
#define fuse_status_opt_fbio_data_f(v) (((v)&0xffffU) << 0U) #define fuse_status_opt_fbio_data_f(v) ((U32(v) & 0xffffU) << 0U)
#define fuse_status_opt_fbio_data_m() (U32(0xffffU) << 0U) #define fuse_status_opt_fbio_data_m() (U32(0xffffU) << 0U)
#define fuse_status_opt_fbio_data_v(r) (((r) >> 0U) & 0xffffU) #define fuse_status_opt_fbio_data_v(r) (((r) >> 0U) & 0xffffU)
#define fuse_status_opt_rop_l2_fbp_r(i)\ #define fuse_status_opt_rop_l2_fbp_r(i)\

16
drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_gmmu_gp10b.h
View File

@@ -66,7 +66,7 @@
#define gmmu_new_pde_aperture_video_memory_f() (0x2U) #define gmmu_new_pde_aperture_video_memory_f() (0x2U)
#define gmmu_new_pde_aperture_sys_mem_coh_f() (0x4U) #define gmmu_new_pde_aperture_sys_mem_coh_f() (0x4U)
#define gmmu_new_pde_aperture_sys_mem_ncoh_f() (0x6U) #define gmmu_new_pde_aperture_sys_mem_ncoh_f() (0x6U)
#define gmmu_new_pde_address_sys_f(v) (((v)&0xffffffU) << 8U) #define gmmu_new_pde_address_sys_f(v) ((U32(v) & 0xffffffU) << 8U)
#define gmmu_new_pde_address_sys_w() (0U) #define gmmu_new_pde_address_sys_w() (0U)
#define gmmu_new_pde_vol_w() (0U) #define gmmu_new_pde_vol_w() (0U)
#define gmmu_new_pde_vol_true_f() (0x8U) #define gmmu_new_pde_vol_true_f() (0x8U)
@@ -80,7 +80,7 @@
#define gmmu_new_dual_pde_aperture_big_video_memory_f() (0x2U) #define gmmu_new_dual_pde_aperture_big_video_memory_f() (0x2U)
#define gmmu_new_dual_pde_aperture_big_sys_mem_coh_f() (0x4U) #define gmmu_new_dual_pde_aperture_big_sys_mem_coh_f() (0x4U)
#define gmmu_new_dual_pde_aperture_big_sys_mem_ncoh_f() (0x6U) #define gmmu_new_dual_pde_aperture_big_sys_mem_ncoh_f() (0x6U)
#define gmmu_new_dual_pde_address_big_sys_f(v) (((v)&0xfffffffU) << 4U) #define gmmu_new_dual_pde_address_big_sys_f(v) ((U32(v) & 0xfffffffU) << 4U)
#define gmmu_new_dual_pde_address_big_sys_w() (0U) #define gmmu_new_dual_pde_address_big_sys_w() (0U)
#define gmmu_new_dual_pde_aperture_small_w() (2U) #define gmmu_new_dual_pde_aperture_small_w() (2U)
#define gmmu_new_dual_pde_aperture_small_invalid_f() (0x0U) #define gmmu_new_dual_pde_aperture_small_invalid_f() (0x0U)
@@ -93,7 +93,7 @@
#define gmmu_new_dual_pde_vol_big_w() (0U) #define gmmu_new_dual_pde_vol_big_w() (0U)
#define gmmu_new_dual_pde_vol_big_true_f() (0x8U) #define gmmu_new_dual_pde_vol_big_true_f() (0x8U)
#define gmmu_new_dual_pde_vol_big_false_f() (0x0U) #define gmmu_new_dual_pde_vol_big_false_f() (0x0U)
#define gmmu_new_dual_pde_address_small_sys_f(v) (((v)&0xffffffU) << 8U) #define gmmu_new_dual_pde_address_small_sys_f(v) ((U32(v) & 0xffffffU) << 8U)
#define gmmu_new_dual_pde_address_small_sys_w() (2U) #define gmmu_new_dual_pde_address_small_sys_w() (2U)
#define gmmu_new_dual_pde_address_shift_v() (0x0000000cU) #define gmmu_new_dual_pde_address_shift_v() (0x0000000cU)
#define gmmu_new_dual_pde_address_big_shift_v() (0x00000008U) #define gmmu_new_dual_pde_address_big_shift_v() (0x00000008U)
@@ -105,9 +105,9 @@
#define gmmu_new_pte_privilege_w() (0U) #define gmmu_new_pte_privilege_w() (0U)
#define gmmu_new_pte_privilege_true_f() (0x20U) #define gmmu_new_pte_privilege_true_f() (0x20U)
#define gmmu_new_pte_privilege_false_f() (0x0U) #define gmmu_new_pte_privilege_false_f() (0x0U)
#define gmmu_new_pte_address_sys_f(v) (((v)&0xffffffU) << 8U) #define gmmu_new_pte_address_sys_f(v) ((U32(v) & 0xffffffU) << 8U)
#define gmmu_new_pte_address_sys_w() (0U) #define gmmu_new_pte_address_sys_w() (0U)
#define gmmu_new_pte_address_vid_f(v) (((v)&0xffffffU) << 8U) #define gmmu_new_pte_address_vid_f(v) ((U32(v) & 0xffffffU) << 8U)
#define gmmu_new_pte_address_vid_w() (0U) #define gmmu_new_pte_address_vid_w() (0U)
#define gmmu_new_pte_vol_w() (0U) #define gmmu_new_pte_vol_w() (0U)
#define gmmu_new_pte_vol_true_f() (0x8U) #define gmmu_new_pte_vol_true_f() (0x8U)
@@ -118,12 +118,12 @@
#define gmmu_new_pte_aperture_sys_mem_ncoh_f() (0x6U) #define gmmu_new_pte_aperture_sys_mem_ncoh_f() (0x6U)
#define gmmu_new_pte_read_only_w() (0U) #define gmmu_new_pte_read_only_w() (0U)
#define gmmu_new_pte_read_only_true_f() (0x40U) #define gmmu_new_pte_read_only_true_f() (0x40U)
#define gmmu_new_pte_comptagline_f(v) (((v)&0x3ffffU) << 4U) #define gmmu_new_pte_comptagline_f(v) ((U32(v) & 0x3ffffU) << 4U)
#define gmmu_new_pte_comptagline_w() (1U) #define gmmu_new_pte_comptagline_w() (1U)
#define gmmu_new_pte_kind_f(v) (((v)&0xffU) << 24U) #define gmmu_new_pte_kind_f(v) ((U32(v) & 0xffU) << 24U)
#define gmmu_new_pte_kind_w() (1U) #define gmmu_new_pte_kind_w() (1U)
#define gmmu_new_pte_address_shift_v() (0x0000000cU) #define gmmu_new_pte_address_shift_v() (0x0000000cU)
#define gmmu_pte_kind_f(v) (((v)&0xffU) << 4U) #define gmmu_pte_kind_f(v) ((U32(v) & 0xffU) << 4U)
#define gmmu_pte_kind_w() (1U) #define gmmu_pte_kind_w() (1U)
#define gmmu_pte_kind_invalid_v() (0x000000ffU) #define gmmu_pte_kind_invalid_v() (0x000000ffU)
#define gmmu_pte_kind_pitch_v() (0x00000000U) #define gmmu_pte_kind_pitch_v() (0x00000000U)

496
drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_gr_gp10b.h
View File

@@ -68,7 +68,7 @@
#define gr_intr_illegal_method_reset_f() (0x10U) #define gr_intr_illegal_method_reset_f() (0x10U)
#define gr_intr_illegal_notify_pending_f() (0x40U) #define gr_intr_illegal_notify_pending_f() (0x40U)
#define gr_intr_illegal_notify_reset_f() (0x40U) #define gr_intr_illegal_notify_reset_f() (0x40U)
#define gr_intr_firmware_method_f(v) (((v)&0x1U) << 8U) #define gr_intr_firmware_method_f(v) ((U32(v) & 0x1U) << 8U)
#define gr_intr_firmware_method_pending_f() (0x100U) #define gr_intr_firmware_method_pending_f() (0x100U)
#define gr_intr_firmware_method_reset_f() (0x100U) #define gr_intr_firmware_method_reset_f() (0x100U)
#define gr_intr_illegal_class_pending_f() (0x20U) #define gr_intr_illegal_class_pending_f() (0x20U)
@@ -103,10 +103,10 @@
#define gr_exception1_en_r() (0x00400130U) #define gr_exception1_en_r() (0x00400130U)
#define gr_exception2_en_r() (0x00400134U) #define gr_exception2_en_r() (0x00400134U)
#define gr_gpfifo_ctl_r() (0x00400500U) #define gr_gpfifo_ctl_r() (0x00400500U)
#define gr_gpfifo_ctl_access_f(v) (((v)&0x1U) << 0U) #define gr_gpfifo_ctl_access_f(v) ((U32(v) & 0x1U) << 0U)
#define gr_gpfifo_ctl_access_disabled_f() (0x0U) #define gr_gpfifo_ctl_access_disabled_f() (0x0U)
#define gr_gpfifo_ctl_access_enabled_f() (0x1U) #define gr_gpfifo_ctl_access_enabled_f() (0x1U)
#define gr_gpfifo_ctl_semaphore_access_f(v) (((v)&0x1U) << 16U) #define gr_gpfifo_ctl_semaphore_access_f(v) ((U32(v) & 0x1U) << 16U)
#define gr_gpfifo_ctl_semaphore_access_enabled_v() (0x00000001U) #define gr_gpfifo_ctl_semaphore_access_enabled_v() (0x00000001U)
#define gr_gpfifo_ctl_semaphore_access_enabled_f() (0x10000U) #define gr_gpfifo_ctl_semaphore_access_enabled_f() (0x10000U)
#define gr_gpfifo_status_r() (0x00400504U) #define gr_gpfifo_status_r() (0x00400504U)
@@ -142,7 +142,7 @@
#define gr_activity_2_r() (0x00400388U) #define gr_activity_2_r() (0x00400388U)
#define gr_activity_4_r() (0x00400390U) #define gr_activity_4_r() (0x00400390U)
#define gr_activity_4_gpc0_s() (3U) #define gr_activity_4_gpc0_s() (3U)
#define gr_activity_4_gpc0_f(v) (((v)&0x7U) << 0U) #define gr_activity_4_gpc0_f(v) ((U32(v) & 0x7U) << 0U)
#define gr_activity_4_gpc0_m() (U32(0x7U) << 0U) #define gr_activity_4_gpc0_m() (U32(0x7U) << 0U)
#define gr_activity_4_gpc0_v(r) (((r) >> 0U) & 0x7U) #define gr_activity_4_gpc0_v(r) (((r) >> 0U) & 0x7U)
#define gr_activity_4_gpc0_empty_v() (0x00000000U) #define gr_activity_4_gpc0_empty_v() (0x00000000U)
@@ -247,7 +247,7 @@
#define gr_fe_hww_esr_en_enable_f() (0x80000000U) #define gr_fe_hww_esr_en_enable_f() (0x80000000U)
#define gr_fe_hww_esr_info_r() (0x004041b0U) #define gr_fe_hww_esr_info_r() (0x004041b0U)
#define gr_fe_go_idle_timeout_r() (0x00404154U) #define gr_fe_go_idle_timeout_r() (0x00404154U)
#define gr_fe_go_idle_timeout_count_f(v) (((v)&0xffffffffU) << 0U) #define gr_fe_go_idle_timeout_count_f(v) ((U32(v) & 0xffffffffU) << 0U)
#define gr_fe_go_idle_timeout_count_disabled_f() (0x0U) #define gr_fe_go_idle_timeout_count_disabled_f() (0x0U)
#define gr_fe_go_idle_timeout_count_prod_f() (0x7fffffffU) #define gr_fe_go_idle_timeout_count_prod_f() (0x7fffffffU)
#define gr_fe_object_table_r(i)\ #define gr_fe_object_table_r(i)\
@@ -265,11 +265,11 @@
#define gr_memfmt_hww_esr_reset_active_f() (0x40000000U) #define gr_memfmt_hww_esr_reset_active_f() (0x40000000U)
#define gr_memfmt_hww_esr_en_enable_f() (0x80000000U) #define gr_memfmt_hww_esr_en_enable_f() (0x80000000U)
#define gr_fecs_cpuctl_r() (0x00409100U) #define gr_fecs_cpuctl_r() (0x00409100U)
#define gr_fecs_cpuctl_startcpu_f(v) (((v)&0x1U) << 1U) #define gr_fecs_cpuctl_startcpu_f(v) ((U32(v) & 0x1U) << 1U)
#define gr_fecs_cpuctl_alias_r() (0x00409130U) #define gr_fecs_cpuctl_alias_r() (0x00409130U)
#define gr_fecs_cpuctl_alias_startcpu_f(v) (((v)&0x1U) << 1U) #define gr_fecs_cpuctl_alias_startcpu_f(v) ((U32(v) & 0x1U) << 1U)
#define gr_fecs_dmactl_r() (0x0040910cU) #define gr_fecs_dmactl_r() (0x0040910cU)
#define gr_fecs_dmactl_require_ctx_f(v) (((v)&0x1U) << 0U) #define gr_fecs_dmactl_require_ctx_f(v) ((U32(v) & 0x1U) << 0U)
#define gr_fecs_dmactl_dmem_scrubbing_m() (U32(0x1U) << 1U) #define gr_fecs_dmactl_dmem_scrubbing_m() (U32(0x1U) << 1U)
#define gr_fecs_dmactl_imem_scrubbing_m() (U32(0x1U) << 2U) #define gr_fecs_dmactl_imem_scrubbing_m() (U32(0x1U) << 2U)
#define gr_fecs_os_r() (0x00409080U) #define gr_fecs_os_r() (0x00409080U)
@@ -287,66 +287,66 @@
#define gr_fecs_debuginfo_r() (0x00409094U) #define gr_fecs_debuginfo_r() (0x00409094U)
#define gr_fecs_icd_cmd_r() (0x00409200U) #define gr_fecs_icd_cmd_r() (0x00409200U)
#define gr_fecs_icd_cmd_opc_s() (4U) #define gr_fecs_icd_cmd_opc_s() (4U)
#define gr_fecs_icd_cmd_opc_f(v) (((v)&0xfU) << 0U) #define gr_fecs_icd_cmd_opc_f(v) ((U32(v) & 0xfU) << 0U)
#define gr_fecs_icd_cmd_opc_m() (U32(0xfU) << 0U) #define gr_fecs_icd_cmd_opc_m() (U32(0xfU) << 0U)
#define gr_fecs_icd_cmd_opc_v(r) (((r) >> 0U) & 0xfU) #define gr_fecs_icd_cmd_opc_v(r) (((r) >> 0U) & 0xfU)
#define gr_fecs_icd_cmd_opc_rreg_f() (0x8U) #define gr_fecs_icd_cmd_opc_rreg_f() (0x8U)
#define gr_fecs_icd_cmd_opc_rstat_f() (0xeU) #define gr_fecs_icd_cmd_opc_rstat_f() (0xeU)
#define gr_fecs_icd_cmd_idx_f(v) (((v)&0x1fU) << 8U) #define gr_fecs_icd_cmd_idx_f(v) ((U32(v) & 0x1fU) << 8U)
#define gr_fecs_icd_rdata_r() (0x0040920cU) #define gr_fecs_icd_rdata_r() (0x0040920cU)
#define gr_fecs_imemc_r(i)\ #define gr_fecs_imemc_r(i)\
(nvgpu_safe_add_u32(0x00409180U, nvgpu_safe_mult_u32((i), 16U))) (nvgpu_safe_add_u32(0x00409180U, nvgpu_safe_mult_u32((i), 16U)))
#define gr_fecs_imemc_offs_f(v) (((v)&0x3fU) << 2U) #define gr_fecs_imemc_offs_f(v) ((U32(v) & 0x3fU) << 2U)
#define gr_fecs_imemc_blk_f(v) (((v)&0xffU) << 8U) #define gr_fecs_imemc_blk_f(v) ((U32(v) & 0xffU) << 8U)
#define gr_fecs_imemc_aincw_f(v) (((v)&0x1U) << 24U) #define gr_fecs_imemc_aincw_f(v) ((U32(v) & 0x1U) << 24U)
#define gr_fecs_imemd_r(i)\ #define gr_fecs_imemd_r(i)\
(nvgpu_safe_add_u32(0x00409184U, nvgpu_safe_mult_u32((i), 16U))) (nvgpu_safe_add_u32(0x00409184U, nvgpu_safe_mult_u32((i), 16U)))
#define gr_fecs_imemt_r(i)\ #define gr_fecs_imemt_r(i)\
(nvgpu_safe_add_u32(0x00409188U, nvgpu_safe_mult_u32((i), 16U))) (nvgpu_safe_add_u32(0x00409188U, nvgpu_safe_mult_u32((i), 16U)))
#define gr_fecs_imemt_tag_f(v) (((v)&0xffffU) << 0U) #define gr_fecs_imemt_tag_f(v) ((U32(v) & 0xffffU) << 0U)
#define gr_fecs_dmemc_r(i)\ #define gr_fecs_dmemc_r(i)\
(nvgpu_safe_add_u32(0x004091c0U, nvgpu_safe_mult_u32((i), 8U))) (nvgpu_safe_add_u32(0x004091c0U, nvgpu_safe_mult_u32((i), 8U)))
#define gr_fecs_dmemc_offs_s() (6U) #define gr_fecs_dmemc_offs_s() (6U)
#define gr_fecs_dmemc_offs_f(v) (((v)&0x3fU) << 2U) #define gr_fecs_dmemc_offs_f(v) ((U32(v) & 0x3fU) << 2U)
#define gr_fecs_dmemc_offs_m() (U32(0x3fU) << 2U) #define gr_fecs_dmemc_offs_m() (U32(0x3fU) << 2U)
#define gr_fecs_dmemc_offs_v(r) (((r) >> 2U) & 0x3fU) #define gr_fecs_dmemc_offs_v(r) (((r) >> 2U) & 0x3fU)
#define gr_fecs_dmemc_blk_f(v) (((v)&0xffU) << 8U) #define gr_fecs_dmemc_blk_f(v) ((U32(v) & 0xffU) << 8U)
#define gr_fecs_dmemc_aincw_f(v) (((v)&0x1U) << 24U) #define gr_fecs_dmemc_aincw_f(v) ((U32(v) & 0x1U) << 24U)
#define gr_fecs_dmemd_r(i)\ #define gr_fecs_dmemd_r(i)\
(nvgpu_safe_add_u32(0x004091c4U, nvgpu_safe_mult_u32((i), 8U))) (nvgpu_safe_add_u32(0x004091c4U, nvgpu_safe_mult_u32((i), 8U)))
#define gr_fecs_dmatrfbase_r() (0x00409110U) #define gr_fecs_dmatrfbase_r() (0x00409110U)
#define gr_fecs_dmatrfmoffs_r() (0x00409114U) #define gr_fecs_dmatrfmoffs_r() (0x00409114U)
#define gr_fecs_dmatrffboffs_r() (0x0040911cU) #define gr_fecs_dmatrffboffs_r() (0x0040911cU)
#define gr_fecs_dmatrfcmd_r() (0x00409118U) #define gr_fecs_dmatrfcmd_r() (0x00409118U)
#define gr_fecs_dmatrfcmd_imem_f(v) (((v)&0x1U) << 4U) #define gr_fecs_dmatrfcmd_imem_f(v) ((U32(v) & 0x1U) << 4U)
#define gr_fecs_dmatrfcmd_write_f(v) (((v)&0x1U) << 5U) #define gr_fecs_dmatrfcmd_write_f(v) ((U32(v) & 0x1U) << 5U)
#define gr_fecs_dmatrfcmd_size_f(v) (((v)&0x7U) << 8U) #define gr_fecs_dmatrfcmd_size_f(v) ((U32(v) & 0x7U) << 8U)
#define gr_fecs_dmatrfcmd_ctxdma_f(v) (((v)&0x7U) << 12U) #define gr_fecs_dmatrfcmd_ctxdma_f(v) ((U32(v) & 0x7U) << 12U)
#define gr_fecs_bootvec_r() (0x00409104U) #define gr_fecs_bootvec_r() (0x00409104U)
#define gr_fecs_bootvec_vec_f(v) (((v)&0xffffffffU) << 0U) #define gr_fecs_bootvec_vec_f(v) ((U32(v) & 0xffffffffU) << 0U)
#define gr_fecs_irqsset_r() (0x00409000U) #define gr_fecs_irqsset_r() (0x00409000U)
#define gr_fecs_falcon_hwcfg_r() (0x00409108U) #define gr_fecs_falcon_hwcfg_r() (0x00409108U)
#define gr_gpcs_gpccs_irqsset_r() (0x0041a000U) #define gr_gpcs_gpccs_irqsset_r() (0x0041a000U)
#define gr_gpcs_gpccs_falcon_hwcfg_r() (0x0041a108U) #define gr_gpcs_gpccs_falcon_hwcfg_r() (0x0041a108U)
#define gr_fecs_falcon_rm_r() (0x00409084U) #define gr_fecs_falcon_rm_r() (0x00409084U)
#define gr_fecs_current_ctx_r() (0x00409b00U) #define gr_fecs_current_ctx_r() (0x00409b00U)
#define gr_fecs_current_ctx_ptr_f(v) (((v)&0xfffffffU) << 0U) #define gr_fecs_current_ctx_ptr_f(v) ((U32(v) & 0xfffffffU) << 0U)
#define gr_fecs_current_ctx_ptr_v(r) (((r) >> 0U) & 0xfffffffU) #define gr_fecs_current_ctx_ptr_v(r) (((r) >> 0U) & 0xfffffffU)
#define gr_fecs_current_ctx_target_s() (2U) #define gr_fecs_current_ctx_target_s() (2U)
#define gr_fecs_current_ctx_target_f(v) (((v)&0x3U) << 28U) #define gr_fecs_current_ctx_target_f(v) ((U32(v) & 0x3U) << 28U)
#define gr_fecs_current_ctx_target_m() (U32(0x3U) << 28U) #define gr_fecs_current_ctx_target_m() (U32(0x3U) << 28U)
#define gr_fecs_current_ctx_target_v(r) (((r) >> 28U) & 0x3U) #define gr_fecs_current_ctx_target_v(r) (((r) >> 28U) & 0x3U)
#define gr_fecs_current_ctx_target_vid_mem_f() (0x0U) #define gr_fecs_current_ctx_target_vid_mem_f() (0x0U)
#define gr_fecs_current_ctx_target_sys_mem_coh_f() (0x20000000U) #define gr_fecs_current_ctx_target_sys_mem_coh_f() (0x20000000U)
#define gr_fecs_current_ctx_target_sys_mem_ncoh_f() (0x30000000U) #define gr_fecs_current_ctx_target_sys_mem_ncoh_f() (0x30000000U)
#define gr_fecs_current_ctx_valid_s() (1U) #define gr_fecs_current_ctx_valid_s() (1U)
#define gr_fecs_current_ctx_valid_f(v) (((v)&0x1U) << 31U) #define gr_fecs_current_ctx_valid_f(v) ((U32(v) & 0x1U) << 31U)
#define gr_fecs_current_ctx_valid_m() (U32(0x1U) << 31U) #define gr_fecs_current_ctx_valid_m() (U32(0x1U) << 31U)
#define gr_fecs_current_ctx_valid_v(r) (((r) >> 31U) & 0x1U) #define gr_fecs_current_ctx_valid_v(r) (((r) >> 31U) & 0x1U)
#define gr_fecs_current_ctx_valid_false_f() (0x0U) #define gr_fecs_current_ctx_valid_false_f() (0x0U)
#define gr_fecs_method_data_r() (0x00409500U) #define gr_fecs_method_data_r() (0x00409500U)
#define gr_fecs_method_push_r() (0x00409504U) #define gr_fecs_method_push_r() (0x00409504U)
#define gr_fecs_method_push_adr_f(v) (((v)&0xfffU) << 0U) #define gr_fecs_method_push_adr_f(v) ((U32(v) & 0xfffU) << 0U)
#define gr_fecs_method_push_adr_bind_pointer_v() (0x00000003U) #define gr_fecs_method_push_adr_bind_pointer_v() (0x00000003U)
#define gr_fecs_method_push_adr_bind_pointer_f() (0x3U) #define gr_fecs_method_push_adr_bind_pointer_f() (0x3U)
#define gr_fecs_method_push_adr_discover_image_size_v() (0x00000010U) #define gr_fecs_method_push_adr_discover_image_size_v() (0x00000010U)
@@ -366,13 +366,15 @@
#define gr_fecs_method_push_adr_configure_interrupt_completion_option_v()\ #define gr_fecs_method_push_adr_configure_interrupt_completion_option_v()\
(0x0000003aU) (0x0000003aU)
#define gr_fecs_host_int_status_r() (0x00409c18U) #define gr_fecs_host_int_status_r() (0x00409c18U)
#define gr_fecs_host_int_status_fault_during_ctxsw_f(v) (((v)&0x1U) << 16U) #define gr_fecs_host_int_status_fault_during_ctxsw_f(v) ((U32(v) & 0x1U) << 16U)
#define gr_fecs_host_int_status_umimp_firmware_method_f(v) (((v)&0x1U) << 17U) #define gr_fecs_host_int_status_umimp_firmware_method_f(v)\
#define gr_fecs_host_int_status_umimp_illegal_method_f(v) (((v)&0x1U) << 18U) ((U32(v) & 0x1U) << 17U)
#define gr_fecs_host_int_status_umimp_illegal_method_f(v)\
((U32(v) & 0x1U) << 18U)
#define gr_fecs_host_int_status_watchdog_active_f() (0x80000U) #define gr_fecs_host_int_status_watchdog_active_f() (0x80000U)
#define gr_fecs_host_int_status_ctxsw_intr_f(v) (((v)&0xffffU) << 0U) #define gr_fecs_host_int_status_ctxsw_intr_f(v) ((U32(v) & 0xffffU) << 0U)
#define gr_fecs_host_int_clear_r() (0x00409c20U) #define gr_fecs_host_int_clear_r() (0x00409c20U)
#define gr_fecs_host_int_clear_ctxsw_intr1_f(v) (((v)&0x1U) << 1U) #define gr_fecs_host_int_clear_ctxsw_intr1_f(v) ((U32(v) & 0x1U) << 1U)
#define gr_fecs_host_int_clear_ctxsw_intr1_clear_f() (0x2U) #define gr_fecs_host_int_clear_ctxsw_intr1_clear_f() (0x2U)
#define gr_fecs_host_int_enable_r() (0x00409c24U) #define gr_fecs_host_int_enable_r() (0x00409c24U)
#define gr_fecs_host_int_enable_ctxsw_intr1_enable_f() (0x2U) #define gr_fecs_host_int_enable_ctxsw_intr1_enable_f() (0x2U)
@@ -392,7 +394,7 @@
#define gr_fecs_ctxsw_reset_ctl_gpc_context_reset_enabled_f() (0x0U) #define gr_fecs_ctxsw_reset_ctl_gpc_context_reset_enabled_f() (0x0U)
#define gr_fecs_ctxsw_reset_ctl_gpc_context_reset_disabled_f() (0x200U) #define gr_fecs_ctxsw_reset_ctl_gpc_context_reset_disabled_f() (0x200U)
#define gr_fecs_ctxsw_reset_ctl_be_context_reset_s() (1U) #define gr_fecs_ctxsw_reset_ctl_be_context_reset_s() (1U)
#define gr_fecs_ctxsw_reset_ctl_be_context_reset_f(v) (((v)&0x1U) << 10U) #define gr_fecs_ctxsw_reset_ctl_be_context_reset_f(v) ((U32(v) & 0x1U) << 10U)
#define gr_fecs_ctxsw_reset_ctl_be_context_reset_m() (U32(0x1U) << 10U) #define gr_fecs_ctxsw_reset_ctl_be_context_reset_m() (U32(0x1U) << 10U)
#define gr_fecs_ctxsw_reset_ctl_be_context_reset_v(r) (((r) >> 10U) & 0x1U) #define gr_fecs_ctxsw_reset_ctl_be_context_reset_v(r) (((r) >> 10U) & 0x1U)
#define gr_fecs_ctxsw_reset_ctl_be_context_reset_enabled_f() (0x0U) #define gr_fecs_ctxsw_reset_ctl_be_context_reset_enabled_f() (0x0U)
@@ -401,60 +403,60 @@
#define gr_fecs_ctxsw_mailbox_r(i)\ #define gr_fecs_ctxsw_mailbox_r(i)\
(nvgpu_safe_add_u32(0x00409800U, nvgpu_safe_mult_u32((i), 4U))) (nvgpu_safe_add_u32(0x00409800U, nvgpu_safe_mult_u32((i), 4U)))
#define gr_fecs_ctxsw_mailbox__size_1_v() (0x00000010U) #define gr_fecs_ctxsw_mailbox__size_1_v() (0x00000010U)
#define gr_fecs_ctxsw_mailbox_value_f(v) (((v)&0xffffffffU) << 0U) #define gr_fecs_ctxsw_mailbox_value_f(v) ((U32(v) & 0xffffffffU) << 0U)
#define gr_fecs_ctxsw_mailbox_value_pass_v() (0x00000001U) #define gr_fecs_ctxsw_mailbox_value_pass_v() (0x00000001U)
#define gr_fecs_ctxsw_mailbox_value_fail_v() (0x00000002U) #define gr_fecs_ctxsw_mailbox_value_fail_v() (0x00000002U)
#define gr_fecs_ctxsw_mailbox_set_r(i)\ #define gr_fecs_ctxsw_mailbox_set_r(i)\
(nvgpu_safe_add_u32(0x004098c0U, nvgpu_safe_mult_u32((i), 4U))) (nvgpu_safe_add_u32(0x004098c0U, nvgpu_safe_mult_u32((i), 4U)))
#define gr_fecs_ctxsw_mailbox_set_value_f(v) (((v)&0xffffffffU) << 0U) #define gr_fecs_ctxsw_mailbox_set_value_f(v) ((U32(v) & 0xffffffffU) << 0U)
#define gr_fecs_ctxsw_mailbox_clear_r(i)\ #define gr_fecs_ctxsw_mailbox_clear_r(i)\
(nvgpu_safe_add_u32(0x00409840U, nvgpu_safe_mult_u32((i), 4U))) (nvgpu_safe_add_u32(0x00409840U, nvgpu_safe_mult_u32((i), 4U)))
#define gr_fecs_ctxsw_mailbox_clear_value_f(v) (((v)&0xffffffffU) << 0U) #define gr_fecs_ctxsw_mailbox_clear_value_f(v) ((U32(v) & 0xffffffffU) << 0U)
#define gr_fecs_fs_r() (0x00409604U) #define gr_fecs_fs_r() (0x00409604U)
#define gr_fecs_fs_num_available_gpcs_s() (5U) #define gr_fecs_fs_num_available_gpcs_s() (5U)
#define gr_fecs_fs_num_available_gpcs_f(v) (((v)&0x1fU) << 0U) #define gr_fecs_fs_num_available_gpcs_f(v) ((U32(v) & 0x1fU) << 0U)
#define gr_fecs_fs_num_available_gpcs_m() (U32(0x1fU) << 0U) #define gr_fecs_fs_num_available_gpcs_m() (U32(0x1fU) << 0U)
#define gr_fecs_fs_num_available_gpcs_v(r) (((r) >> 0U) & 0x1fU) #define gr_fecs_fs_num_available_gpcs_v(r) (((r) >> 0U) & 0x1fU)
#define gr_fecs_fs_num_available_fbps_s() (5U) #define gr_fecs_fs_num_available_fbps_s() (5U)
#define gr_fecs_fs_num_available_fbps_f(v) (((v)&0x1fU) << 16U) #define gr_fecs_fs_num_available_fbps_f(v) ((U32(v) & 0x1fU) << 16U)
#define gr_fecs_fs_num_available_fbps_m() (U32(0x1fU) << 16U) #define gr_fecs_fs_num_available_fbps_m() (U32(0x1fU) << 16U)
#define gr_fecs_fs_num_available_fbps_v(r) (((r) >> 16U) & 0x1fU) #define gr_fecs_fs_num_available_fbps_v(r) (((r) >> 16U) & 0x1fU)
#define gr_fecs_cfg_r() (0x00409620U) #define gr_fecs_cfg_r() (0x00409620U)
#define gr_fecs_cfg_imem_sz_v(r) (((r) >> 0U) & 0xffU) #define gr_fecs_cfg_imem_sz_v(r) (((r) >> 0U) & 0xffU)
#define gr_fecs_rc_lanes_r() (0x00409880U) #define gr_fecs_rc_lanes_r() (0x00409880U)
#define gr_fecs_rc_lanes_num_chains_s() (6U) #define gr_fecs_rc_lanes_num_chains_s() (6U)
#define gr_fecs_rc_lanes_num_chains_f(v) (((v)&0x3fU) << 0U) #define gr_fecs_rc_lanes_num_chains_f(v) ((U32(v) & 0x3fU) << 0U)
#define gr_fecs_rc_lanes_num_chains_m() (U32(0x3fU) << 0U) #define gr_fecs_rc_lanes_num_chains_m() (U32(0x3fU) << 0U)
#define gr_fecs_rc_lanes_num_chains_v(r) (((r) >> 0U) & 0x3fU) #define gr_fecs_rc_lanes_num_chains_v(r) (((r) >> 0U) & 0x3fU)
#define gr_fecs_ctxsw_status_1_r() (0x00409400U) #define gr_fecs_ctxsw_status_1_r() (0x00409400U)
#define gr_fecs_ctxsw_status_1_arb_busy_s() (1U) #define gr_fecs_ctxsw_status_1_arb_busy_s() (1U)
#define gr_fecs_ctxsw_status_1_arb_busy_f(v) (((v)&0x1U) << 12U) #define gr_fecs_ctxsw_status_1_arb_busy_f(v) ((U32(v) & 0x1U) << 12U)
#define gr_fecs_ctxsw_status_1_arb_busy_m() (U32(0x1U) << 12U) #define gr_fecs_ctxsw_status_1_arb_busy_m() (U32(0x1U) << 12U)
#define gr_fecs_ctxsw_status_1_arb_busy_v(r) (((r) >> 12U) & 0x1U) #define gr_fecs_ctxsw_status_1_arb_busy_v(r) (((r) >> 12U) & 0x1U)
#define gr_fecs_arb_ctx_adr_r() (0x00409a24U) #define gr_fecs_arb_ctx_adr_r() (0x00409a24U)
#define gr_fecs_new_ctx_r() (0x00409b04U) #define gr_fecs_new_ctx_r() (0x00409b04U)
#define gr_fecs_new_ctx_ptr_s() (28U) #define gr_fecs_new_ctx_ptr_s() (28U)
#define gr_fecs_new_ctx_ptr_f(v) (((v)&0xfffffffU) << 0U) #define gr_fecs_new_ctx_ptr_f(v) ((U32(v) & 0xfffffffU) << 0U)
#define gr_fecs_new_ctx_ptr_m() (U32(0xfffffffU) << 0U) #define gr_fecs_new_ctx_ptr_m() (U32(0xfffffffU) << 0U)
#define gr_fecs_new_ctx_ptr_v(r) (((r) >> 0U) & 0xfffffffU) #define gr_fecs_new_ctx_ptr_v(r) (((r) >> 0U) & 0xfffffffU)
#define gr_fecs_new_ctx_target_s() (2U) #define gr_fecs_new_ctx_target_s() (2U)
#define gr_fecs_new_ctx_target_f(v) (((v)&0x3U) << 28U) #define gr_fecs_new_ctx_target_f(v) ((U32(v) & 0x3U) << 28U)
#define gr_fecs_new_ctx_target_m() (U32(0x3U) << 28U) #define gr_fecs_new_ctx_target_m() (U32(0x3U) << 28U)
#define gr_fecs_new_ctx_target_v(r) (((r) >> 28U) & 0x3U) #define gr_fecs_new_ctx_target_v(r) (((r) >> 28U) & 0x3U)
#define gr_fecs_new_ctx_target_vid_mem_f() (0x0U) #define gr_fecs_new_ctx_target_vid_mem_f() (0x0U)
#define gr_fecs_new_ctx_target_sys_mem_ncoh_f() (0x30000000U) #define gr_fecs_new_ctx_target_sys_mem_ncoh_f() (0x30000000U)
#define gr_fecs_new_ctx_target_sys_mem_coh_f() (0x20000000U) #define gr_fecs_new_ctx_target_sys_mem_coh_f() (0x20000000U)
#define gr_fecs_new_ctx_valid_s() (1U) #define gr_fecs_new_ctx_valid_s() (1U)
#define gr_fecs_new_ctx_valid_f(v) (((v)&0x1U) << 31U) #define gr_fecs_new_ctx_valid_f(v) ((U32(v) & 0x1U) << 31U)
#define gr_fecs_new_ctx_valid_m() (U32(0x1U) << 31U) #define gr_fecs_new_ctx_valid_m() (U32(0x1U) << 31U)
#define gr_fecs_new_ctx_valid_v(r) (((r) >> 31U) & 0x1U) #define gr_fecs_new_ctx_valid_v(r) (((r) >> 31U) & 0x1U)
#define gr_fecs_arb_ctx_ptr_r() (0x00409a0cU) #define gr_fecs_arb_ctx_ptr_r() (0x00409a0cU)
#define gr_fecs_arb_ctx_ptr_ptr_s() (28U) #define gr_fecs_arb_ctx_ptr_ptr_s() (28U)
#define gr_fecs_arb_ctx_ptr_ptr_f(v) (((v)&0xfffffffU) << 0U) #define gr_fecs_arb_ctx_ptr_ptr_f(v) ((U32(v) & 0xfffffffU) << 0U)
#define gr_fecs_arb_ctx_ptr_ptr_m() (U32(0xfffffffU) << 0U) #define gr_fecs_arb_ctx_ptr_ptr_m() (U32(0xfffffffU) << 0U)
#define gr_fecs_arb_ctx_ptr_ptr_v(r) (((r) >> 0U) & 0xfffffffU) #define gr_fecs_arb_ctx_ptr_ptr_v(r) (((r) >> 0U) & 0xfffffffU)
#define gr_fecs_arb_ctx_ptr_target_s() (2U) #define gr_fecs_arb_ctx_ptr_target_s() (2U)
#define gr_fecs_arb_ctx_ptr_target_f(v) (((v)&0x3U) << 28U) #define gr_fecs_arb_ctx_ptr_target_f(v) ((U32(v) & 0x3U) << 28U)
#define gr_fecs_arb_ctx_ptr_target_m() (U32(0x3U) << 28U) #define gr_fecs_arb_ctx_ptr_target_m() (U32(0x3U) << 28U)
#define gr_fecs_arb_ctx_ptr_target_v(r) (((r) >> 28U) & 0x3U) #define gr_fecs_arb_ctx_ptr_target_v(r) (((r) >> 28U) & 0x3U)
#define gr_fecs_arb_ctx_ptr_target_vid_mem_f() (0x0U) #define gr_fecs_arb_ctx_ptr_target_vid_mem_f() (0x0U)
@@ -462,7 +464,7 @@
#define gr_fecs_arb_ctx_ptr_target_sys_mem_coh_f() (0x20000000U) #define gr_fecs_arb_ctx_ptr_target_sys_mem_coh_f() (0x20000000U)
#define gr_fecs_arb_ctx_cmd_r() (0x00409a10U) #define gr_fecs_arb_ctx_cmd_r() (0x00409a10U)
#define gr_fecs_arb_ctx_cmd_cmd_s() (5U) #define gr_fecs_arb_ctx_cmd_cmd_s() (5U)
#define gr_fecs_arb_ctx_cmd_cmd_f(v) (((v)&0x1fU) << 0U) #define gr_fecs_arb_ctx_cmd_cmd_f(v) ((U32(v) & 0x1fU) << 0U)
#define gr_fecs_arb_ctx_cmd_cmd_m() (U32(0x1fU) << 0U) #define gr_fecs_arb_ctx_cmd_cmd_m() (U32(0x1fU) << 0U)
#define gr_fecs_arb_ctx_cmd_cmd_v(r) (((r) >> 0U) & 0x1fU) #define gr_fecs_arb_ctx_cmd_cmd_v(r) (((r) >> 0U) & 0x1fU)
#define gr_fecs_ctxsw_status_fe_0_r() (0x00409c00U) #define gr_fecs_ctxsw_status_fe_0_r() (0x00409c00U)
@@ -486,55 +488,55 @@
#define gr_rstr2d_gpc_map4_r() (0x0040781cU) #define gr_rstr2d_gpc_map4_r() (0x0040781cU)
#define gr_rstr2d_gpc_map5_r() (0x00407820U) #define gr_rstr2d_gpc_map5_r() (0x00407820U)
#define gr_rstr2d_map_table_cfg_r() (0x004078bcU) #define gr_rstr2d_map_table_cfg_r() (0x004078bcU)
#define gr_rstr2d_map_table_cfg_row_offset_f(v) (((v)&0xffU) << 0U) #define gr_rstr2d_map_table_cfg_row_offset_f(v) ((U32(v) & 0xffU) << 0U)
#define gr_rstr2d_map_table_cfg_num_entries_f(v) (((v)&0xffU) << 8U) #define gr_rstr2d_map_table_cfg_num_entries_f(v) ((U32(v) & 0xffU) << 8U)
#define gr_pd_hww_esr_r() (0x00406018U) #define gr_pd_hww_esr_r() (0x00406018U)
#define gr_pd_hww_esr_reset_active_f() (0x40000000U) #define gr_pd_hww_esr_reset_active_f() (0x40000000U)
#define gr_pd_hww_esr_en_enable_f() (0x80000000U) #define gr_pd_hww_esr_en_enable_f() (0x80000000U)
#define gr_pd_num_tpc_per_gpc_r(i)\ #define gr_pd_num_tpc_per_gpc_r(i)\
(nvgpu_safe_add_u32(0x00406028U, nvgpu_safe_mult_u32((i), 4U))) (nvgpu_safe_add_u32(0x00406028U, nvgpu_safe_mult_u32((i), 4U)))
#define gr_pd_num_tpc_per_gpc__size_1_v() (0x00000004U) #define gr_pd_num_tpc_per_gpc__size_1_v() (0x00000004U)
#define gr_pd_num_tpc_per_gpc_count0_f(v) (((v)&0xfU) << 0U) #define gr_pd_num_tpc_per_gpc_count0_f(v) ((U32(v) & 0xfU) << 0U)
#define gr_pd_num_tpc_per_gpc_count1_f(v) (((v)&0xfU) << 4U) #define gr_pd_num_tpc_per_gpc_count1_f(v) ((U32(v) & 0xfU) << 4U)
#define gr_pd_num_tpc_per_gpc_count2_f(v) (((v)&0xfU) << 8U) #define gr_pd_num_tpc_per_gpc_count2_f(v) ((U32(v) & 0xfU) << 8U)
#define gr_pd_num_tpc_per_gpc_count3_f(v) (((v)&0xfU) << 12U) #define gr_pd_num_tpc_per_gpc_count3_f(v) ((U32(v) & 0xfU) << 12U)
#define gr_pd_num_tpc_per_gpc_count4_f(v) (((v)&0xfU) << 16U) #define gr_pd_num_tpc_per_gpc_count4_f(v) ((U32(v) & 0xfU) << 16U)
#define gr_pd_num_tpc_per_gpc_count5_f(v) (((v)&0xfU) << 20U) #define gr_pd_num_tpc_per_gpc_count5_f(v) ((U32(v) & 0xfU) << 20U)
#define gr_pd_num_tpc_per_gpc_count6_f(v) (((v)&0xfU) << 24U) #define gr_pd_num_tpc_per_gpc_count6_f(v) ((U32(v) & 0xfU) << 24U)
#define gr_pd_num_tpc_per_gpc_count7_f(v) (((v)&0xfU) << 28U) #define gr_pd_num_tpc_per_gpc_count7_f(v) ((U32(v) & 0xfU) << 28U)
#define gr_pd_ab_dist_cfg0_r() (0x004064c0U) #define gr_pd_ab_dist_cfg0_r() (0x004064c0U)
#define gr_pd_ab_dist_cfg0_timeslice_enable_en_f() (0x80000000U) #define gr_pd_ab_dist_cfg0_timeslice_enable_en_f() (0x80000000U)
#define gr_pd_ab_dist_cfg0_timeslice_enable_dis_f() (0x0U) #define gr_pd_ab_dist_cfg0_timeslice_enable_dis_f() (0x0U)
#define gr_pd_ab_dist_cfg1_r() (0x004064c4U) #define gr_pd_ab_dist_cfg1_r() (0x004064c4U)
#define gr_pd_ab_dist_cfg1_max_batches_init_f() (0xffffU) #define gr_pd_ab_dist_cfg1_max_batches_init_f() (0xffffU)
#define gr_pd_ab_dist_cfg1_max_output_f(v) (((v)&0xffffU) << 16U) #define gr_pd_ab_dist_cfg1_max_output_f(v) ((U32(v) & 0xffffU) << 16U)
#define gr_pd_ab_dist_cfg1_max_output_granularity_v() (0x00000080U) #define gr_pd_ab_dist_cfg1_max_output_granularity_v() (0x00000080U)
#define gr_pd_ab_dist_cfg2_r() (0x004064c8U) #define gr_pd_ab_dist_cfg2_r() (0x004064c8U)
#define gr_pd_ab_dist_cfg2_token_limit_f(v) (((v)&0x1fffU) << 0U) #define gr_pd_ab_dist_cfg2_token_limit_f(v) ((U32(v) & 0x1fffU) << 0U)
#define gr_pd_ab_dist_cfg2_token_limit_init_v() (0x000001c0U) #define gr_pd_ab_dist_cfg2_token_limit_init_v() (0x000001c0U)
#define gr_pd_ab_dist_cfg2_state_limit_f(v) (((v)&0x1fffU) << 16U) #define gr_pd_ab_dist_cfg2_state_limit_f(v) ((U32(v) & 0x1fffU) << 16U)
#define gr_pd_ab_dist_cfg2_state_limit_scc_bundle_granularity_v() (0x00000020U) #define gr_pd_ab_dist_cfg2_state_limit_scc_bundle_granularity_v() (0x00000020U)
#define gr_pd_ab_dist_cfg2_state_limit_min_gpm_fifo_depths_v() (0x00000182U) #define gr_pd_ab_dist_cfg2_state_limit_min_gpm_fifo_depths_v() (0x00000182U)
#define gr_pd_dist_skip_table_r(i)\ #define gr_pd_dist_skip_table_r(i)\
(nvgpu_safe_add_u32(0x004064d0U, nvgpu_safe_mult_u32((i), 4U))) (nvgpu_safe_add_u32(0x004064d0U, nvgpu_safe_mult_u32((i), 4U)))
#define gr_pd_dist_skip_table__size_1_v() (0x00000008U) #define gr_pd_dist_skip_table__size_1_v() (0x00000008U)
#define gr_pd_dist_skip_table_gpc_4n0_mask_f(v) (((v)&0xffU) << 0U) #define gr_pd_dist_skip_table_gpc_4n0_mask_f(v) ((U32(v) & 0xffU) << 0U)
#define gr_pd_dist_skip_table_gpc_4n1_mask_f(v) (((v)&0xffU) << 8U) #define gr_pd_dist_skip_table_gpc_4n1_mask_f(v) ((U32(v) & 0xffU) << 8U)
#define gr_pd_dist_skip_table_gpc_4n2_mask_f(v) (((v)&0xffU) << 16U) #define gr_pd_dist_skip_table_gpc_4n2_mask_f(v) ((U32(v) & 0xffU) << 16U)
#define gr_pd_dist_skip_table_gpc_4n3_mask_f(v) (((v)&0xffU) << 24U) #define gr_pd_dist_skip_table_gpc_4n3_mask_f(v) ((U32(v) & 0xffU) << 24U)
#define gr_ds_debug_r() (0x00405800U) #define gr_ds_debug_r() (0x00405800U)
#define gr_ds_debug_timeslice_mode_disable_f() (0x0U) #define gr_ds_debug_timeslice_mode_disable_f() (0x0U)
#define gr_ds_debug_timeslice_mode_enable_f() (0x8000000U) #define gr_ds_debug_timeslice_mode_enable_f() (0x8000000U)
#define gr_ds_zbc_color_r_r() (0x00405804U) #define gr_ds_zbc_color_r_r() (0x00405804U)
#define gr_ds_zbc_color_r_val_f(v) (((v)&0xffffffffU) << 0U) #define gr_ds_zbc_color_r_val_f(v) ((U32(v) & 0xffffffffU) << 0U)
#define gr_ds_zbc_color_g_r() (0x00405808U) #define gr_ds_zbc_color_g_r() (0x00405808U)
#define gr_ds_zbc_color_g_val_f(v) (((v)&0xffffffffU) << 0U) #define gr_ds_zbc_color_g_val_f(v) ((U32(v) & 0xffffffffU) << 0U)
#define gr_ds_zbc_color_b_r() (0x0040580cU) #define gr_ds_zbc_color_b_r() (0x0040580cU)
#define gr_ds_zbc_color_b_val_f(v) (((v)&0xffffffffU) << 0U) #define gr_ds_zbc_color_b_val_f(v) ((U32(v) & 0xffffffffU) << 0U)
#define gr_ds_zbc_color_a_r() (0x00405810U) #define gr_ds_zbc_color_a_r() (0x00405810U)
#define gr_ds_zbc_color_a_val_f(v) (((v)&0xffffffffU) << 0U) #define gr_ds_zbc_color_a_val_f(v) ((U32(v) & 0xffffffffU) << 0U)
#define gr_ds_zbc_color_fmt_r() (0x00405814U) #define gr_ds_zbc_color_fmt_r() (0x00405814U)
#define gr_ds_zbc_color_fmt_val_f(v) (((v)&0x7fU) << 0U) #define gr_ds_zbc_color_fmt_val_f(v) ((U32(v) & 0x7fU) << 0U)
#define gr_ds_zbc_color_fmt_val_invalid_f() (0x0U) #define gr_ds_zbc_color_fmt_val_invalid_f() (0x0U)
#define gr_ds_zbc_color_fmt_val_zero_v() (0x00000001U) #define gr_ds_zbc_color_fmt_val_zero_v() (0x00000001U)
#define gr_ds_zbc_color_fmt_val_unorm_one_v() (0x00000002U) #define gr_ds_zbc_color_fmt_val_unorm_one_v() (0x00000002U)
@@ -542,29 +544,29 @@
#define gr_ds_zbc_color_fmt_val_a8_b8_g8_r8_v() (0x00000028U) #define gr_ds_zbc_color_fmt_val_a8_b8_g8_r8_v() (0x00000028U)
#define gr_ds_zbc_z_r() (0x00405818U) #define gr_ds_zbc_z_r() (0x00405818U)
#define gr_ds_zbc_z_val_s() (32U) #define gr_ds_zbc_z_val_s() (32U)
#define gr_ds_zbc_z_val_f(v) (((v)&0xffffffffU) << 0U) #define gr_ds_zbc_z_val_f(v) ((U32(v) & 0xffffffffU) << 0U)
#define gr_ds_zbc_z_val_m() (U32(0xffffffffU) << 0U) #define gr_ds_zbc_z_val_m() (U32(0xffffffffU) << 0U)
#define gr_ds_zbc_z_val_v(r) (((r) >> 0U) & 0xffffffffU) #define gr_ds_zbc_z_val_v(r) (((r) >> 0U) & 0xffffffffU)
#define gr_ds_zbc_z_val__init_v() (0x00000000U) #define gr_ds_zbc_z_val__init_v() (0x00000000U)
#define gr_ds_zbc_z_val__init_f() (0x0U) #define gr_ds_zbc_z_val__init_f() (0x0U)
#define gr_ds_zbc_z_fmt_r() (0x0040581cU) #define gr_ds_zbc_z_fmt_r() (0x0040581cU)
#define gr_ds_zbc_z_fmt_val_f(v) (((v)&0x1U) << 0U) #define gr_ds_zbc_z_fmt_val_f(v) ((U32(v) & 0x1U) << 0U)
#define gr_ds_zbc_z_fmt_val_invalid_f() (0x0U) #define gr_ds_zbc_z_fmt_val_invalid_f() (0x0U)
#define gr_ds_zbc_z_fmt_val_fp32_v() (0x00000001U) #define gr_ds_zbc_z_fmt_val_fp32_v() (0x00000001U)
#define gr_ds_zbc_tbl_index_r() (0x00405820U) #define gr_ds_zbc_tbl_index_r() (0x00405820U)
#define gr_ds_zbc_tbl_index_val_f(v) (((v)&0xfU) << 0U) #define gr_ds_zbc_tbl_index_val_f(v) ((U32(v) & 0xfU) << 0U)
#define gr_ds_zbc_tbl_ld_r() (0x00405824U) #define gr_ds_zbc_tbl_ld_r() (0x00405824U)
#define gr_ds_zbc_tbl_ld_select_c_f() (0x0U) #define gr_ds_zbc_tbl_ld_select_c_f() (0x0U)
#define gr_ds_zbc_tbl_ld_select_z_f() (0x1U) #define gr_ds_zbc_tbl_ld_select_z_f() (0x1U)
#define gr_ds_zbc_tbl_ld_action_write_f() (0x0U) #define gr_ds_zbc_tbl_ld_action_write_f() (0x0U)
#define gr_ds_zbc_tbl_ld_trigger_active_f() (0x4U) #define gr_ds_zbc_tbl_ld_trigger_active_f() (0x4U)
#define gr_ds_tga_constraintlogic_beta_r() (0x00405830U) #define gr_ds_tga_constraintlogic_beta_r() (0x00405830U)
#define gr_ds_tga_constraintlogic_beta_cbsize_f(v) (((v)&0x3fffffU) << 0U) #define gr_ds_tga_constraintlogic_beta_cbsize_f(v) ((U32(v) & 0x3fffffU) << 0U)
#define gr_ds_tga_constraintlogic_alpha_r() (0x0040585cU) #define gr_ds_tga_constraintlogic_alpha_r() (0x0040585cU)
#define gr_ds_tga_constraintlogic_alpha_cbsize_f(v) (((v)&0xffffU) << 0U) #define gr_ds_tga_constraintlogic_alpha_cbsize_f(v) ((U32(v) & 0xffffU) << 0U)
#define gr_ds_hww_esr_r() (0x00405840U) #define gr_ds_hww_esr_r() (0x00405840U)
#define gr_ds_hww_esr_reset_s() (1U) #define gr_ds_hww_esr_reset_s() (1U)
#define gr_ds_hww_esr_reset_f(v) (((v)&0x1U) << 30U) #define gr_ds_hww_esr_reset_f(v) ((U32(v) & 0x1U) << 30U)
#define gr_ds_hww_esr_reset_m() (U32(0x1U) << 30U) #define gr_ds_hww_esr_reset_m() (U32(0x1U) << 30U)
#define gr_ds_hww_esr_reset_v(r) (((r) >> 30U) & 0x1U) #define gr_ds_hww_esr_reset_v(r) (((r) >> 30U) & 0x1U)
#define gr_ds_hww_esr_reset_task_v() (0x00000001U) #define gr_ds_hww_esr_reset_task_v() (0x00000001U)
@@ -572,7 +574,7 @@
#define gr_ds_hww_esr_en_enabled_f() (0x80000000U) #define gr_ds_hww_esr_en_enabled_f() (0x80000000U)
#define gr_ds_hww_esr_2_r() (0x00405848U) #define gr_ds_hww_esr_2_r() (0x00405848U)
#define gr_ds_hww_esr_2_reset_s() (1U) #define gr_ds_hww_esr_2_reset_s() (1U)
#define gr_ds_hww_esr_2_reset_f(v) (((v)&0x1U) << 30U) #define gr_ds_hww_esr_2_reset_f(v) ((U32(v) & 0x1U) << 30U)
#define gr_ds_hww_esr_2_reset_m() (U32(0x1U) << 30U) #define gr_ds_hww_esr_2_reset_m() (U32(0x1U) << 30U)
#define gr_ds_hww_esr_2_reset_v(r) (((r) >> 30U) & 0x1U) #define gr_ds_hww_esr_2_reset_v(r) (((r) >> 30U) & 0x1U)
#define gr_ds_hww_esr_2_reset_task_v() (0x00000001U) #define gr_ds_hww_esr_2_reset_task_v() (0x00000001U)
@@ -608,25 +610,25 @@
#define gr_ds_num_tpc_per_gpc_r(i)\ #define gr_ds_num_tpc_per_gpc_r(i)\
(nvgpu_safe_add_u32(0x00405870U, nvgpu_safe_mult_u32((i), 4U))) (nvgpu_safe_add_u32(0x00405870U, nvgpu_safe_mult_u32((i), 4U)))
#define gr_scc_bundle_cb_base_r() (0x00408004U) #define gr_scc_bundle_cb_base_r() (0x00408004U)
#define gr_scc_bundle_cb_base_addr_39_8_f(v) (((v)&0xffffffffU) << 0U) #define gr_scc_bundle_cb_base_addr_39_8_f(v) ((U32(v) & 0xffffffffU) << 0U)
#define gr_scc_bundle_cb_base_addr_39_8_align_bits_v() (0x00000008U) #define gr_scc_bundle_cb_base_addr_39_8_align_bits_v() (0x00000008U)
#define gr_scc_bundle_cb_size_r() (0x00408008U) #define gr_scc_bundle_cb_size_r() (0x00408008U)
#define gr_scc_bundle_cb_size_div_256b_f(v) (((v)&0x7ffU) << 0U) #define gr_scc_bundle_cb_size_div_256b_f(v) ((U32(v) & 0x7ffU) << 0U)
#define gr_scc_bundle_cb_size_div_256b__prod_v() (0x00000018U) #define gr_scc_bundle_cb_size_div_256b__prod_v() (0x00000018U)
#define gr_scc_bundle_cb_size_div_256b_byte_granularity_v() (0x00000100U) #define gr_scc_bundle_cb_size_div_256b_byte_granularity_v() (0x00000100U)
#define gr_scc_bundle_cb_size_valid_false_v() (0x00000000U) #define gr_scc_bundle_cb_size_valid_false_v() (0x00000000U)
#define gr_scc_bundle_cb_size_valid_false_f() (0x0U) #define gr_scc_bundle_cb_size_valid_false_f() (0x0U)
#define gr_scc_bundle_cb_size_valid_true_f() (0x80000000U) #define gr_scc_bundle_cb_size_valid_true_f() (0x80000000U)
#define gr_scc_pagepool_base_r() (0x0040800cU) #define gr_scc_pagepool_base_r() (0x0040800cU)
#define gr_scc_pagepool_base_addr_39_8_f(v) (((v)&0xffffffffU) << 0U) #define gr_scc_pagepool_base_addr_39_8_f(v) ((U32(v) & 0xffffffffU) << 0U)
#define gr_scc_pagepool_base_addr_39_8_align_bits_v() (0x00000008U) #define gr_scc_pagepool_base_addr_39_8_align_bits_v() (0x00000008U)
#define gr_scc_pagepool_r() (0x00408010U) #define gr_scc_pagepool_r() (0x00408010U)
#define gr_scc_pagepool_total_pages_f(v) (((v)&0x3ffU) << 0U) #define gr_scc_pagepool_total_pages_f(v) ((U32(v) & 0x3ffU) << 0U)
#define gr_scc_pagepool_total_pages_hwmax_v() (0x00000000U) #define gr_scc_pagepool_total_pages_hwmax_v() (0x00000000U)
#define gr_scc_pagepool_total_pages_hwmax_value_v() (0x00000200U) #define gr_scc_pagepool_total_pages_hwmax_value_v() (0x00000200U)
#define gr_scc_pagepool_total_pages_byte_granularity_v() (0x00000100U) #define gr_scc_pagepool_total_pages_byte_granularity_v() (0x00000100U)
#define gr_scc_pagepool_max_valid_pages_s() (10U) #define gr_scc_pagepool_max_valid_pages_s() (10U)
#define gr_scc_pagepool_max_valid_pages_f(v) (((v)&0x3ffU) << 10U) #define gr_scc_pagepool_max_valid_pages_f(v) ((U32(v) & 0x3ffU) << 10U)
#define gr_scc_pagepool_max_valid_pages_m() (U32(0x3ffU) << 10U) #define gr_scc_pagepool_max_valid_pages_m() (U32(0x3ffU) << 10U)
#define gr_scc_pagepool_max_valid_pages_v(r) (((r) >> 10U) & 0x3ffU) #define gr_scc_pagepool_max_valid_pages_v(r) (((r) >> 10U) & 0x3ffU)
#define gr_scc_pagepool_valid_true_f() (0x80000000U) #define gr_scc_pagepool_valid_true_f() (0x80000000U)
@@ -636,20 +638,20 @@
#define gr_sked_hww_esr_r() (0x00407020U) #define gr_sked_hww_esr_r() (0x00407020U)
#define gr_sked_hww_esr_reset_active_f() (0x40000000U) #define gr_sked_hww_esr_reset_active_f() (0x40000000U)
#define gr_cwd_fs_r() (0x00405b00U) #define gr_cwd_fs_r() (0x00405b00U)
#define gr_cwd_fs_num_gpcs_f(v) (((v)&0xffU) << 0U) #define gr_cwd_fs_num_gpcs_f(v) ((U32(v) & 0xffU) << 0U)
#define gr_cwd_fs_num_tpcs_f(v) (((v)&0xffU) << 8U) #define gr_cwd_fs_num_tpcs_f(v) ((U32(v) & 0xffU) << 8U)
#define gr_cwd_gpc_tpc_id_r(i)\ #define gr_cwd_gpc_tpc_id_r(i)\
(nvgpu_safe_add_u32(0x00405b60U, nvgpu_safe_mult_u32((i), 4U))) (nvgpu_safe_add_u32(0x00405b60U, nvgpu_safe_mult_u32((i), 4U)))
#define gr_cwd_gpc_tpc_id_tpc0_s() (4U) #define gr_cwd_gpc_tpc_id_tpc0_s() (4U)
#define gr_cwd_gpc_tpc_id_tpc0_f(v) (((v)&0xfU) << 0U) #define gr_cwd_gpc_tpc_id_tpc0_f(v) ((U32(v) & 0xfU) << 0U)
#define gr_cwd_gpc_tpc_id_gpc0_s() (4U) #define gr_cwd_gpc_tpc_id_gpc0_s() (4U)
#define gr_cwd_gpc_tpc_id_gpc0_f(v) (((v)&0xfU) << 4U) #define gr_cwd_gpc_tpc_id_gpc0_f(v) ((U32(v) & 0xfU) << 4U)
#define gr_cwd_gpc_tpc_id_tpc1_f(v) (((v)&0xfU) << 8U) #define gr_cwd_gpc_tpc_id_tpc1_f(v) ((U32(v) & 0xfU) << 8U)
#define gr_cwd_sm_id_r(i)\ #define gr_cwd_sm_id_r(i)\
(nvgpu_safe_add_u32(0x00405ba0U, nvgpu_safe_mult_u32((i), 4U))) (nvgpu_safe_add_u32(0x00405ba0U, nvgpu_safe_mult_u32((i), 4U)))
#define gr_cwd_sm_id__size_1_v() (0x00000010U) #define gr_cwd_sm_id__size_1_v() (0x00000010U)
#define gr_cwd_sm_id_tpc0_f(v) (((v)&0xffU) << 0U) #define gr_cwd_sm_id_tpc0_f(v) ((U32(v) & 0xffU) << 0U)
#define gr_cwd_sm_id_tpc1_f(v) (((v)&0xffU) << 8U) #define gr_cwd_sm_id_tpc1_f(v) ((U32(v) & 0xffU) << 8U)
#define gr_gpc0_fs_gpc_r() (0x00502608U) #define gr_gpc0_fs_gpc_r() (0x00502608U)
#define gr_gpc0_fs_gpc_num_available_tpcs_v(r) (((r) >> 0U) & 0x1fU) #define gr_gpc0_fs_gpc_num_available_tpcs_v(r) (((r) >> 0U) & 0x1fU)
#define gr_gpc0_fs_gpc_num_available_zculls_v(r) (((r) >> 16U) & 0x1fU) #define gr_gpc0_fs_gpc_num_available_zculls_v(r) (((r) >> 16U) & 0x1fU)
@@ -657,42 +659,43 @@
#define gr_gpc0_cfg_imem_sz_v(r) (((r) >> 0U) & 0xffU) #define gr_gpc0_cfg_imem_sz_v(r) (((r) >> 0U) & 0xffU)
#define gr_gpccs_rc_lanes_r() (0x00502880U) #define gr_gpccs_rc_lanes_r() (0x00502880U)
#define gr_gpccs_rc_lanes_num_chains_s() (6U) #define gr_gpccs_rc_lanes_num_chains_s() (6U)
#define gr_gpccs_rc_lanes_num_chains_f(v) (((v)&0x3fU) << 0U) #define gr_gpccs_rc_lanes_num_chains_f(v) ((U32(v) & 0x3fU) << 0U)
#define gr_gpccs_rc_lanes_num_chains_m() (U32(0x3fU) << 0U) #define gr_gpccs_rc_lanes_num_chains_m() (U32(0x3fU) << 0U)
#define gr_gpccs_rc_lanes_num_chains_v(r) (((r) >> 0U) & 0x3fU) #define gr_gpccs_rc_lanes_num_chains_v(r) (((r) >> 0U) & 0x3fU)
#define gr_gpccs_rc_lane_size_r() (0x00502910U) #define gr_gpccs_rc_lane_size_r() (0x00502910U)
#define gr_gpccs_rc_lane_size_v_s() (24U) #define gr_gpccs_rc_lane_size_v_s() (24U)
#define gr_gpccs_rc_lane_size_v_f(v) (((v)&0xffffffU) << 0U) #define gr_gpccs_rc_lane_size_v_f(v) ((U32(v) & 0xffffffU) << 0U)
#define gr_gpccs_rc_lane_size_v_m() (U32(0xffffffU) << 0U) #define gr_gpccs_rc_lane_size_v_m() (U32(0xffffffU) << 0U)
#define gr_gpccs_rc_lane_size_v_v(r) (((r) >> 0U) & 0xffffffU) #define gr_gpccs_rc_lane_size_v_v(r) (((r) >> 0U) & 0xffffffU)
#define gr_gpccs_rc_lane_size_v_0_v() (0x00000000U) #define gr_gpccs_rc_lane_size_v_0_v() (0x00000000U)
#define gr_gpccs_rc_lane_size_v_0_f() (0x0U) #define gr_gpccs_rc_lane_size_v_0_f() (0x0U)
#define gr_gpc0_zcull_fs_r() (0x00500910U) #define gr_gpc0_zcull_fs_r() (0x00500910U)
#define gr_gpc0_zcull_fs_num_sms_f(v) (((v)&0x1ffU) << 0U) #define gr_gpc0_zcull_fs_num_sms_f(v) ((U32(v) & 0x1ffU) << 0U)
#define gr_gpc0_zcull_fs_num_active_banks_f(v) (((v)&0xfU) << 16U) #define gr_gpc0_zcull_fs_num_active_banks_f(v) ((U32(v) & 0xfU) << 16U)
#define gr_gpc0_zcull_ram_addr_r() (0x00500914U) #define gr_gpc0_zcull_ram_addr_r() (0x00500914U)
#define gr_gpc0_zcull_ram_addr_tiles_per_hypertile_row_per_gpc_f(v)\ #define gr_gpc0_zcull_ram_addr_tiles_per_hypertile_row_per_gpc_f(v)\
(((v)&0xfU) << 0U) ((U32(v) & 0xfU) << 0U)
#define gr_gpc0_zcull_ram_addr_row_offset_f(v) (((v)&0xfU) << 8U) #define gr_gpc0_zcull_ram_addr_row_offset_f(v) ((U32(v) & 0xfU) << 8U)
#define gr_gpc0_zcull_sm_num_rcp_r() (0x00500918U) #define gr_gpc0_zcull_sm_num_rcp_r() (0x00500918U)
#define gr_gpc0_zcull_sm_num_rcp_conservative_f(v) (((v)&0xffffffU) << 0U) #define gr_gpc0_zcull_sm_num_rcp_conservative_f(v) ((U32(v) & 0xffffffU) << 0U)
#define gr_gpc0_zcull_sm_num_rcp_conservative__max_v() (0x00800000U) #define gr_gpc0_zcull_sm_num_rcp_conservative__max_v() (0x00800000U)
#define gr_gpc0_zcull_total_ram_size_r() (0x00500920U) #define gr_gpc0_zcull_total_ram_size_r() (0x00500920U)
#define gr_gpc0_zcull_total_ram_size_num_aliquots_f(v) (((v)&0xffffU) << 0U) #define gr_gpc0_zcull_total_ram_size_num_aliquots_f(v)\
((U32(v) & 0xffffU) << 0U)
#define gr_gpc0_zcull_zcsize_r(i)\ #define gr_gpc0_zcull_zcsize_r(i)\
(nvgpu_safe_add_u32(0x00500a04U, nvgpu_safe_mult_u32((i), 32U))) (nvgpu_safe_add_u32(0x00500a04U, nvgpu_safe_mult_u32((i), 32U)))
#define gr_gpc0_zcull_zcsize_height_subregion__multiple_v() (0x00000040U) #define gr_gpc0_zcull_zcsize_height_subregion__multiple_v() (0x00000040U)
#define gr_gpc0_zcull_zcsize_width_subregion__multiple_v() (0x00000010U) #define gr_gpc0_zcull_zcsize_width_subregion__multiple_v() (0x00000010U)
#define gr_gpc0_gpm_pd_sm_id_r(i)\ #define gr_gpc0_gpm_pd_sm_id_r(i)\
(nvgpu_safe_add_u32(0x00500c10U, nvgpu_safe_mult_u32((i), 4U))) (nvgpu_safe_add_u32(0x00500c10U, nvgpu_safe_mult_u32((i), 4U)))
#define gr_gpc0_gpm_pd_sm_id_id_f(v) (((v)&0xffU) << 0U) #define gr_gpc0_gpm_pd_sm_id_id_f(v) ((U32(v) & 0xffU) << 0U)
#define gr_gpc0_gpm_pd_pes_tpc_id_mask_r(i)\ #define gr_gpc0_gpm_pd_pes_tpc_id_mask_r(i)\
(nvgpu_safe_add_u32(0x00500c30U, nvgpu_safe_mult_u32((i), 4U))) (nvgpu_safe_add_u32(0x00500c30U, nvgpu_safe_mult_u32((i), 4U)))
#define gr_gpc0_gpm_pd_pes_tpc_id_mask_mask_v(r) (((r) >> 0U) & 0xffU) #define gr_gpc0_gpm_pd_pes_tpc_id_mask_mask_v(r) (((r) >> 0U) & 0xffU)
#define gr_gpc0_tpc0_pe_cfg_smid_r() (0x00504088U) #define gr_gpc0_tpc0_pe_cfg_smid_r() (0x00504088U)
#define gr_gpc0_tpc0_pe_cfg_smid_value_f(v) (((v)&0xffffU) << 0U) #define gr_gpc0_tpc0_pe_cfg_smid_value_f(v) ((U32(v) & 0xffffU) << 0U)
#define gr_gpc0_tpc0_sm_cfg_r() (0x00504698U) #define gr_gpc0_tpc0_sm_cfg_r() (0x00504698U)
#define gr_gpc0_tpc0_sm_cfg_sm_id_f(v) (((v)&0xffffU) << 0U) #define gr_gpc0_tpc0_sm_cfg_sm_id_f(v) ((U32(v) & 0xffffU) << 0U)
#define gr_gpc0_tpc0_sm_cfg_sm_id_v(r) (((r) >> 0U) & 0xffffU) #define gr_gpc0_tpc0_sm_cfg_sm_id_v(r) (((r) >> 0U) & 0xffffU)
#define gr_gpc0_tpc0_sm_arch_r() (0x0050469cU) #define gr_gpc0_tpc0_sm_arch_r() (0x0050469cU)
#define gr_gpc0_tpc0_sm_arch_warp_count_v(r) (((r) >> 0U) & 0xffU) #define gr_gpc0_tpc0_sm_arch_warp_count_v(r) (((r) >> 0U) & 0xffU)
@@ -702,100 +705,102 @@
#define gr_gpc0_ppc0_pes_vsc_strem_master_pe_m() (U32(0x1U) << 0U) #define gr_gpc0_ppc0_pes_vsc_strem_master_pe_m() (U32(0x1U) << 0U)
#define gr_gpc0_ppc0_pes_vsc_strem_master_pe_true_f() (0x1U) #define gr_gpc0_ppc0_pes_vsc_strem_master_pe_true_f() (0x1U)
#define gr_gpc0_ppc0_cbm_beta_cb_size_r() (0x005030c0U) #define gr_gpc0_ppc0_cbm_beta_cb_size_r() (0x005030c0U)
#define gr_gpc0_ppc0_cbm_beta_cb_size_v_f(v) (((v)&0x3fffffU) << 0U) #define gr_gpc0_ppc0_cbm_beta_cb_size_v_f(v) ((U32(v) & 0x3fffffU) << 0U)
#define gr_gpc0_ppc0_cbm_beta_cb_size_v_m() (U32(0x3fffffU) << 0U) #define gr_gpc0_ppc0_cbm_beta_cb_size_v_m() (U32(0x3fffffU) << 0U)
#define gr_gpc0_ppc0_cbm_beta_cb_size_v_default_v() (0x00030000U) #define gr_gpc0_ppc0_cbm_beta_cb_size_v_default_v() (0x00030000U)
#define gr_gpc0_ppc0_cbm_beta_cb_size_v_gfxp_v() (0x00030a00U) #define gr_gpc0_ppc0_cbm_beta_cb_size_v_gfxp_v() (0x00030a00U)
#define gr_gpc0_ppc0_cbm_beta_cb_size_v_granularity_v() (0x00000020U) #define gr_gpc0_ppc0_cbm_beta_cb_size_v_granularity_v() (0x00000020U)
#define gr_gpc0_ppc0_cbm_beta_cb_offset_r() (0x005030f4U) #define gr_gpc0_ppc0_cbm_beta_cb_offset_r() (0x005030f4U)
#define gr_gpc0_ppc0_cbm_alpha_cb_size_r() (0x005030e4U) #define gr_gpc0_ppc0_cbm_alpha_cb_size_r() (0x005030e4U)
#define gr_gpc0_ppc0_cbm_alpha_cb_size_v_f(v) (((v)&0xffffU) << 0U) #define gr_gpc0_ppc0_cbm_alpha_cb_size_v_f(v) ((U32(v) & 0xffffU) << 0U)
#define gr_gpc0_ppc0_cbm_alpha_cb_size_v_m() (U32(0xffffU) << 0U) #define gr_gpc0_ppc0_cbm_alpha_cb_size_v_m() (U32(0xffffU) << 0U)
#define gr_gpc0_ppc0_cbm_alpha_cb_size_v_default_v() (0x00000800U) #define gr_gpc0_ppc0_cbm_alpha_cb_size_v_default_v() (0x00000800U)
#define gr_gpc0_ppc0_cbm_alpha_cb_size_v_granularity_v() (0x00000020U) #define gr_gpc0_ppc0_cbm_alpha_cb_size_v_granularity_v() (0x00000020U)
#define gr_gpc0_ppc0_cbm_alpha_cb_offset_r() (0x005030f8U) #define gr_gpc0_ppc0_cbm_alpha_cb_offset_r() (0x005030f8U)
#define gr_gpc0_ppc0_cbm_beta_steady_state_cb_size_r() (0x005030f0U) #define gr_gpc0_ppc0_cbm_beta_steady_state_cb_size_r() (0x005030f0U)
#define gr_gpc0_ppc0_cbm_beta_steady_state_cb_size_v_f(v)\ #define gr_gpc0_ppc0_cbm_beta_steady_state_cb_size_v_f(v)\
(((v)&0x3fffffU) << 0U) ((U32(v) & 0x3fffffU) << 0U)
#define gr_gpc0_ppc0_cbm_beta_steady_state_cb_size_v_default_v() (0x00030000U) #define gr_gpc0_ppc0_cbm_beta_steady_state_cb_size_v_default_v() (0x00030000U)
#define gr_gpcs_tpcs_tex_rm_cb_0_r() (0x00419b00U) #define gr_gpcs_tpcs_tex_rm_cb_0_r() (0x00419b00U)
#define gr_gpcs_tpcs_tex_rm_cb_0_base_addr_43_12_f(v) (((v)&0xffffffffU) << 0U) #define gr_gpcs_tpcs_tex_rm_cb_0_base_addr_43_12_f(v)\
((U32(v) & 0xffffffffU) << 0U)
#define gr_gpcs_tpcs_tex_rm_cb_1_r() (0x00419b04U) #define gr_gpcs_tpcs_tex_rm_cb_1_r() (0x00419b04U)
#define gr_gpcs_tpcs_tex_rm_cb_1_size_div_128b_s() (21U) #define gr_gpcs_tpcs_tex_rm_cb_1_size_div_128b_s() (21U)
#define gr_gpcs_tpcs_tex_rm_cb_1_size_div_128b_f(v) (((v)&0x1fffffU) << 0U) #define gr_gpcs_tpcs_tex_rm_cb_1_size_div_128b_f(v) ((U32(v) & 0x1fffffU) << 0U)
#define gr_gpcs_tpcs_tex_rm_cb_1_size_div_128b_m() (U32(0x1fffffU) << 0U) #define gr_gpcs_tpcs_tex_rm_cb_1_size_div_128b_m() (U32(0x1fffffU) << 0U)
#define gr_gpcs_tpcs_tex_rm_cb_1_size_div_128b_v(r) (((r) >> 0U) & 0x1fffffU) #define gr_gpcs_tpcs_tex_rm_cb_1_size_div_128b_v(r) (((r) >> 0U) & 0x1fffffU)
#define gr_gpcs_tpcs_tex_rm_cb_1_size_div_128b_granularity_f() (0x80U) #define gr_gpcs_tpcs_tex_rm_cb_1_size_div_128b_granularity_f() (0x80U)
#define gr_gpcs_tpcs_tex_rm_cb_1_valid_s() (1U) #define gr_gpcs_tpcs_tex_rm_cb_1_valid_s() (1U)
#define gr_gpcs_tpcs_tex_rm_cb_1_valid_f(v) (((v)&0x1U) << 31U) #define gr_gpcs_tpcs_tex_rm_cb_1_valid_f(v) ((U32(v) & 0x1U) << 31U)
#define gr_gpcs_tpcs_tex_rm_cb_1_valid_m() (U32(0x1U) << 31U) #define gr_gpcs_tpcs_tex_rm_cb_1_valid_m() (U32(0x1U) << 31U)
#define gr_gpcs_tpcs_tex_rm_cb_1_valid_v(r) (((r) >> 31U) & 0x1U) #define gr_gpcs_tpcs_tex_rm_cb_1_valid_v(r) (((r) >> 31U) & 0x1U)
#define gr_gpcs_tpcs_tex_rm_cb_1_valid_true_f() (0x80000000U) #define gr_gpcs_tpcs_tex_rm_cb_1_valid_true_f() (0x80000000U)
#define gr_gpcs_tpcs_tex_m_dbg2_r() (0x00419a3cU) #define gr_gpcs_tpcs_tex_m_dbg2_r() (0x00419a3cU)
#define gr_gpcs_tpcs_tex_m_dbg2_lg_rd_coalesce_en_f(v) (((v)&0x1U) << 2U) #define gr_gpcs_tpcs_tex_m_dbg2_lg_rd_coalesce_en_f(v) ((U32(v) & 0x1U) << 2U)
#define gr_gpcs_tpcs_tex_m_dbg2_lg_rd_coalesce_en_m() (U32(0x1U) << 2U) #define gr_gpcs_tpcs_tex_m_dbg2_lg_rd_coalesce_en_m() (U32(0x1U) << 2U)
#define gr_gpcs_tpcs_tex_m_dbg2_su_rd_coalesce_en_f(v) (((v)&0x1U) << 4U) #define gr_gpcs_tpcs_tex_m_dbg2_su_rd_coalesce_en_f(v) ((U32(v) & 0x1U) << 4U)
#define gr_gpcs_tpcs_tex_m_dbg2_su_rd_coalesce_en_m() (U32(0x1U) << 4U) #define gr_gpcs_tpcs_tex_m_dbg2_su_rd_coalesce_en_m() (U32(0x1U) << 4U)
#define gr_gpccs_falcon_addr_r() (0x0041a0acU) #define gr_gpccs_falcon_addr_r() (0x0041a0acU)
#define gr_gpccs_falcon_addr_lsb_s() (6U) #define gr_gpccs_falcon_addr_lsb_s() (6U)
#define gr_gpccs_falcon_addr_lsb_f(v) (((v)&0x3fU) << 0U) #define gr_gpccs_falcon_addr_lsb_f(v) ((U32(v) & 0x3fU) << 0U)
#define gr_gpccs_falcon_addr_lsb_m() (U32(0x3fU) << 0U) #define gr_gpccs_falcon_addr_lsb_m() (U32(0x3fU) << 0U)
#define gr_gpccs_falcon_addr_lsb_v(r) (((r) >> 0U) & 0x3fU) #define gr_gpccs_falcon_addr_lsb_v(r) (((r) >> 0U) & 0x3fU)
#define gr_gpccs_falcon_addr_lsb_init_v() (0x00000000U) #define gr_gpccs_falcon_addr_lsb_init_v() (0x00000000U)
#define gr_gpccs_falcon_addr_lsb_init_f() (0x0U) #define gr_gpccs_falcon_addr_lsb_init_f() (0x0U)
#define gr_gpccs_falcon_addr_msb_s() (6U) #define gr_gpccs_falcon_addr_msb_s() (6U)
#define gr_gpccs_falcon_addr_msb_f(v) (((v)&0x3fU) << 6U) #define gr_gpccs_falcon_addr_msb_f(v) ((U32(v) & 0x3fU) << 6U)
#define gr_gpccs_falcon_addr_msb_m() (U32(0x3fU) << 6U) #define gr_gpccs_falcon_addr_msb_m() (U32(0x3fU) << 6U)
#define gr_gpccs_falcon_addr_msb_v(r) (((r) >> 6U) & 0x3fU) #define gr_gpccs_falcon_addr_msb_v(r) (((r) >> 6U) & 0x3fU)
#define gr_gpccs_falcon_addr_msb_init_v() (0x00000000U) #define gr_gpccs_falcon_addr_msb_init_v() (0x00000000U)
#define gr_gpccs_falcon_addr_msb_init_f() (0x0U) #define gr_gpccs_falcon_addr_msb_init_f() (0x0U)
#define gr_gpccs_falcon_addr_ext_s() (12U) #define gr_gpccs_falcon_addr_ext_s() (12U)
#define gr_gpccs_falcon_addr_ext_f(v) (((v)&0xfffU) << 0U) #define gr_gpccs_falcon_addr_ext_f(v) ((U32(v) & 0xfffU) << 0U)
#define gr_gpccs_falcon_addr_ext_m() (U32(0xfffU) << 0U) #define gr_gpccs_falcon_addr_ext_m() (U32(0xfffU) << 0U)
#define gr_gpccs_falcon_addr_ext_v(r) (((r) >> 0U) & 0xfffU) #define gr_gpccs_falcon_addr_ext_v(r) (((r) >> 0U) & 0xfffU)
#define gr_gpccs_cpuctl_r() (0x0041a100U) #define gr_gpccs_cpuctl_r() (0x0041a100U)
#define gr_gpccs_cpuctl_startcpu_f(v) (((v)&0x1U) << 1U) #define gr_gpccs_cpuctl_startcpu_f(v) ((U32(v) & 0x1U) << 1U)
#define gr_gpccs_dmactl_r() (0x0041a10cU) #define gr_gpccs_dmactl_r() (0x0041a10cU)
#define gr_gpccs_dmactl_require_ctx_f(v) (((v)&0x1U) << 0U) #define gr_gpccs_dmactl_require_ctx_f(v) ((U32(v) & 0x1U) << 0U)
#define gr_gpccs_dmactl_dmem_scrubbing_m() (U32(0x1U) << 1U) #define gr_gpccs_dmactl_dmem_scrubbing_m() (U32(0x1U) << 1U)
#define gr_gpccs_dmactl_imem_scrubbing_m() (U32(0x1U) << 2U) #define gr_gpccs_dmactl_imem_scrubbing_m() (U32(0x1U) << 2U)
#define gr_gpccs_imemc_r(i)\ #define gr_gpccs_imemc_r(i)\
(nvgpu_safe_add_u32(0x0041a180U, nvgpu_safe_mult_u32((i), 16U))) (nvgpu_safe_add_u32(0x0041a180U, nvgpu_safe_mult_u32((i), 16U)))
#define gr_gpccs_imemc_offs_f(v) (((v)&0x3fU) << 2U) #define gr_gpccs_imemc_offs_f(v) ((U32(v) & 0x3fU) << 2U)
#define gr_gpccs_imemc_blk_f(v) (((v)&0xffU) << 8U) #define gr_gpccs_imemc_blk_f(v) ((U32(v) & 0xffU) << 8U)
#define gr_gpccs_imemc_aincw_f(v) (((v)&0x1U) << 24U) #define gr_gpccs_imemc_aincw_f(v) ((U32(v) & 0x1U) << 24U)
#define gr_gpccs_imemd_r(i)\ #define gr_gpccs_imemd_r(i)\
(nvgpu_safe_add_u32(0x0041a184U, nvgpu_safe_mult_u32((i), 16U))) (nvgpu_safe_add_u32(0x0041a184U, nvgpu_safe_mult_u32((i), 16U)))
#define gr_gpccs_imemt_r(i)\ #define gr_gpccs_imemt_r(i)\
(nvgpu_safe_add_u32(0x0041a188U, nvgpu_safe_mult_u32((i), 16U))) (nvgpu_safe_add_u32(0x0041a188U, nvgpu_safe_mult_u32((i), 16U)))
#define gr_gpccs_imemt__size_1_v() (0x00000004U) #define gr_gpccs_imemt__size_1_v() (0x00000004U)
#define gr_gpccs_imemt_tag_f(v) (((v)&0xffffU) << 0U) #define gr_gpccs_imemt_tag_f(v) ((U32(v) & 0xffffU) << 0U)
#define gr_gpccs_dmemc_r(i)\ #define gr_gpccs_dmemc_r(i)\
(nvgpu_safe_add_u32(0x0041a1c0U, nvgpu_safe_mult_u32((i), 8U))) (nvgpu_safe_add_u32(0x0041a1c0U, nvgpu_safe_mult_u32((i), 8U)))
#define gr_gpccs_dmemc_offs_f(v) (((v)&0x3fU) << 2U) #define gr_gpccs_dmemc_offs_f(v) ((U32(v) & 0x3fU) << 2U)
#define gr_gpccs_dmemc_blk_f(v) (((v)&0xffU) << 8U) #define gr_gpccs_dmemc_blk_f(v) ((U32(v) & 0xffU) << 8U)
#define gr_gpccs_dmemc_aincw_f(v) (((v)&0x1U) << 24U) #define gr_gpccs_dmemc_aincw_f(v) ((U32(v) & 0x1U) << 24U)
#define gr_gpccs_dmemd_r(i)\ #define gr_gpccs_dmemd_r(i)\
(nvgpu_safe_add_u32(0x0041a1c4U, nvgpu_safe_mult_u32((i), 8U))) (nvgpu_safe_add_u32(0x0041a1c4U, nvgpu_safe_mult_u32((i), 8U)))
#define gr_gpccs_ctxsw_mailbox_r(i)\ #define gr_gpccs_ctxsw_mailbox_r(i)\
(nvgpu_safe_add_u32(0x0041a800U, nvgpu_safe_mult_u32((i), 4U))) (nvgpu_safe_add_u32(0x0041a800U, nvgpu_safe_mult_u32((i), 4U)))
#define gr_gpccs_ctxsw_mailbox_value_f(v) (((v)&0xffffffffU) << 0U) #define gr_gpccs_ctxsw_mailbox_value_f(v) ((U32(v) & 0xffffffffU) << 0U)
#define gr_gpcs_swdx_bundle_cb_base_r() (0x00418e24U) #define gr_gpcs_swdx_bundle_cb_base_r() (0x00418e24U)
#define gr_gpcs_swdx_bundle_cb_base_addr_39_8_s() (32U) #define gr_gpcs_swdx_bundle_cb_base_addr_39_8_s() (32U)
#define gr_gpcs_swdx_bundle_cb_base_addr_39_8_f(v) (((v)&0xffffffffU) << 0U) #define gr_gpcs_swdx_bundle_cb_base_addr_39_8_f(v)\
((U32(v) & 0xffffffffU) << 0U)
#define gr_gpcs_swdx_bundle_cb_base_addr_39_8_m() (U32(0xffffffffU) << 0U) #define gr_gpcs_swdx_bundle_cb_base_addr_39_8_m() (U32(0xffffffffU) << 0U)
#define gr_gpcs_swdx_bundle_cb_base_addr_39_8_v(r) (((r) >> 0U) & 0xffffffffU) #define gr_gpcs_swdx_bundle_cb_base_addr_39_8_v(r) (((r) >> 0U) & 0xffffffffU)
#define gr_gpcs_swdx_bundle_cb_base_addr_39_8_init_v() (0x00000000U) #define gr_gpcs_swdx_bundle_cb_base_addr_39_8_init_v() (0x00000000U)
#define gr_gpcs_swdx_bundle_cb_base_addr_39_8_init_f() (0x0U) #define gr_gpcs_swdx_bundle_cb_base_addr_39_8_init_f() (0x0U)
#define gr_gpcs_swdx_bundle_cb_size_r() (0x00418e28U) #define gr_gpcs_swdx_bundle_cb_size_r() (0x00418e28U)
#define gr_gpcs_swdx_bundle_cb_size_div_256b_s() (11U) #define gr_gpcs_swdx_bundle_cb_size_div_256b_s() (11U)
#define gr_gpcs_swdx_bundle_cb_size_div_256b_f(v) (((v)&0x7ffU) << 0U) #define gr_gpcs_swdx_bundle_cb_size_div_256b_f(v) ((U32(v) & 0x7ffU) << 0U)
#define gr_gpcs_swdx_bundle_cb_size_div_256b_m() (U32(0x7ffU) << 0U) #define gr_gpcs_swdx_bundle_cb_size_div_256b_m() (U32(0x7ffU) << 0U)
#define gr_gpcs_swdx_bundle_cb_size_div_256b_v(r) (((r) >> 0U) & 0x7ffU) #define gr_gpcs_swdx_bundle_cb_size_div_256b_v(r) (((r) >> 0U) & 0x7ffU)
#define gr_gpcs_swdx_bundle_cb_size_div_256b_init_v() (0x00000018U) #define gr_gpcs_swdx_bundle_cb_size_div_256b_init_v() (0x00000018U)
#define gr_gpcs_swdx_bundle_cb_size_div_256b_init_f() (0x18U) #define gr_gpcs_swdx_bundle_cb_size_div_256b_init_f() (0x18U)
#define gr_gpcs_swdx_bundle_cb_size_valid_s() (1U) #define gr_gpcs_swdx_bundle_cb_size_valid_s() (1U)
#define gr_gpcs_swdx_bundle_cb_size_valid_f(v) (((v)&0x1U) << 31U) #define gr_gpcs_swdx_bundle_cb_size_valid_f(v) ((U32(v) & 0x1U) << 31U)
#define gr_gpcs_swdx_bundle_cb_size_valid_m() (U32(0x1U) << 31U) #define gr_gpcs_swdx_bundle_cb_size_valid_m() (U32(0x1U) << 31U)
#define gr_gpcs_swdx_bundle_cb_size_valid_v(r) (((r) >> 31U) & 0x1U) #define gr_gpcs_swdx_bundle_cb_size_valid_v(r) (((r) >> 31U) & 0x1U)
#define gr_gpcs_swdx_bundle_cb_size_valid_false_v() (0x00000000U) #define gr_gpcs_swdx_bundle_cb_size_valid_false_v() (0x00000000U)
@@ -803,146 +808,168 @@
#define gr_gpcs_swdx_bundle_cb_size_valid_true_v() (0x00000001U) #define gr_gpcs_swdx_bundle_cb_size_valid_true_v() (0x00000001U)
#define gr_gpcs_swdx_bundle_cb_size_valid_true_f() (0x80000000U) #define gr_gpcs_swdx_bundle_cb_size_valid_true_f() (0x80000000U)
#define gr_gpc0_swdx_rm_spill_buffer_size_r() (0x00500ee4U) #define gr_gpc0_swdx_rm_spill_buffer_size_r() (0x00500ee4U)
#define gr_gpc0_swdx_rm_spill_buffer_size_256b_f(v) (((v)&0xffffU) << 0U) #define gr_gpc0_swdx_rm_spill_buffer_size_256b_f(v) ((U32(v) & 0xffffU) << 0U)
#define gr_gpc0_swdx_rm_spill_buffer_size_256b_default_v() (0x00000250U) #define gr_gpc0_swdx_rm_spill_buffer_size_256b_default_v() (0x00000250U)
#define gr_gpc0_swdx_rm_spill_buffer_size_256b_byte_granularity_v()\ #define gr_gpc0_swdx_rm_spill_buffer_size_256b_byte_granularity_v()\
(0x00000100U) (0x00000100U)
#define gr_gpc0_swdx_rm_spill_buffer_addr_r() (0x00500ee0U) #define gr_gpc0_swdx_rm_spill_buffer_addr_r() (0x00500ee0U)
#define gr_gpc0_swdx_rm_spill_buffer_addr_39_8_f(v) (((v)&0xffffffffU) << 0U) #define gr_gpc0_swdx_rm_spill_buffer_addr_39_8_f(v)\
((U32(v) & 0xffffffffU) << 0U)
#define gr_gpc0_swdx_rm_spill_buffer_addr_39_8_align_bits_v() (0x00000008U) #define gr_gpc0_swdx_rm_spill_buffer_addr_39_8_align_bits_v() (0x00000008U)
#define gr_gpcs_swdx_beta_cb_ctrl_r() (0x00418eecU) #define gr_gpcs_swdx_beta_cb_ctrl_r() (0x00418eecU)
#define gr_gpcs_swdx_beta_cb_ctrl_cbes_reserve_f(v) (((v)&0xfffU) << 0U) #define gr_gpcs_swdx_beta_cb_ctrl_cbes_reserve_f(v) ((U32(v) & 0xfffU) << 0U)
#define gr_gpcs_swdx_beta_cb_ctrl_cbes_reserve_gfxp_v() (0x00000100U) #define gr_gpcs_swdx_beta_cb_ctrl_cbes_reserve_gfxp_v() (0x00000100U)
#define gr_gpcs_ppcs_cbm_beta_cb_ctrl_r() (0x0041befcU) #define gr_gpcs_ppcs_cbm_beta_cb_ctrl_r() (0x0041befcU)
#define gr_gpcs_ppcs_cbm_beta_cb_ctrl_cbes_reserve_f(v) (((v)&0xfffU) << 0U) #define gr_gpcs_ppcs_cbm_beta_cb_ctrl_cbes_reserve_f(v)\
((U32(v) & 0xfffU) << 0U)
#define gr_gpcs_swdx_tc_beta_cb_size_r(i)\ #define gr_gpcs_swdx_tc_beta_cb_size_r(i)\
(nvgpu_safe_add_u32(0x00418ea0U, nvgpu_safe_mult_u32((i), 4U))) (nvgpu_safe_add_u32(0x00418ea0U, nvgpu_safe_mult_u32((i), 4U)))
#define gr_gpcs_swdx_tc_beta_cb_size_v_f(v) (((v)&0x3fffffU) << 0U) #define gr_gpcs_swdx_tc_beta_cb_size_v_f(v) ((U32(v) & 0x3fffffU) << 0U)
#define gr_gpcs_swdx_tc_beta_cb_size_v_m() (U32(0x3fffffU) << 0U) #define gr_gpcs_swdx_tc_beta_cb_size_v_m() (U32(0x3fffffU) << 0U)
#define gr_gpcs_swdx_dss_zbc_color_r_r(i)\ #define gr_gpcs_swdx_dss_zbc_color_r_r(i)\
(nvgpu_safe_add_u32(0x00418010U, nvgpu_safe_mult_u32((i), 4U))) (nvgpu_safe_add_u32(0x00418010U, nvgpu_safe_mult_u32((i), 4U)))
#define gr_gpcs_swdx_dss_zbc_color_r_val_f(v) (((v)&0xffffffffU) << 0U) #define gr_gpcs_swdx_dss_zbc_color_r_val_f(v) ((U32(v) & 0xffffffffU) << 0U)
#define gr_gpcs_swdx_dss_zbc_color_g_r(i)\ #define gr_gpcs_swdx_dss_zbc_color_g_r(i)\
(nvgpu_safe_add_u32(0x0041804cU, nvgpu_safe_mult_u32((i), 4U))) (nvgpu_safe_add_u32(0x0041804cU, nvgpu_safe_mult_u32((i), 4U)))
#define gr_gpcs_swdx_dss_zbc_color_g_val_f(v) (((v)&0xffffffffU) << 0U) #define gr_gpcs_swdx_dss_zbc_color_g_val_f(v) ((U32(v) & 0xffffffffU) << 0U)
#define gr_gpcs_swdx_dss_zbc_color_b_r(i)\ #define gr_gpcs_swdx_dss_zbc_color_b_r(i)\
(nvgpu_safe_add_u32(0x00418088U, nvgpu_safe_mult_u32((i), 4U))) (nvgpu_safe_add_u32(0x00418088U, nvgpu_safe_mult_u32((i), 4U)))
#define gr_gpcs_swdx_dss_zbc_color_b_val_f(v) (((v)&0xffffffffU) << 0U) #define gr_gpcs_swdx_dss_zbc_color_b_val_f(v) ((U32(v) & 0xffffffffU) << 0U)
#define gr_gpcs_swdx_dss_zbc_color_a_r(i)\ #define gr_gpcs_swdx_dss_zbc_color_a_r(i)\
(nvgpu_safe_add_u32(0x004180c4U, nvgpu_safe_mult_u32((i), 4U))) (nvgpu_safe_add_u32(0x004180c4U, nvgpu_safe_mult_u32((i), 4U)))
#define gr_gpcs_swdx_dss_zbc_color_a_val_f(v) (((v)&0xffffffffU) << 0U) #define gr_gpcs_swdx_dss_zbc_color_a_val_f(v) ((U32(v) & 0xffffffffU) << 0U)
#define gr_gpcs_swdx_dss_zbc_c_01_to_04_format_r() (0x00500100U) #define gr_gpcs_swdx_dss_zbc_c_01_to_04_format_r() (0x00500100U)
#define gr_gpcs_swdx_dss_zbc_z_r(i)\ #define gr_gpcs_swdx_dss_zbc_z_r(i)\
(nvgpu_safe_add_u32(0x00418110U, nvgpu_safe_mult_u32((i), 4U))) (nvgpu_safe_add_u32(0x00418110U, nvgpu_safe_mult_u32((i), 4U)))
#define gr_gpcs_swdx_dss_zbc_z_val_f(v) (((v)&0xffffffffU) << 0U) #define gr_gpcs_swdx_dss_zbc_z_val_f(v) ((U32(v) & 0xffffffffU) << 0U)
#define gr_gpcs_swdx_dss_zbc_z_01_to_04_format_r() (0x0050014cU) #define gr_gpcs_swdx_dss_zbc_z_01_to_04_format_r() (0x0050014cU)
#define gr_gpcs_setup_attrib_cb_base_r() (0x00418810U) #define gr_gpcs_setup_attrib_cb_base_r() (0x00418810U)
#define gr_gpcs_setup_attrib_cb_base_addr_39_12_f(v) (((v)&0xfffffffU) << 0U) #define gr_gpcs_setup_attrib_cb_base_addr_39_12_f(v)\
((U32(v) & 0xfffffffU) << 0U)
#define gr_gpcs_setup_attrib_cb_base_addr_39_12_align_bits_v() (0x0000000cU) #define gr_gpcs_setup_attrib_cb_base_addr_39_12_align_bits_v() (0x0000000cU)
#define gr_gpcs_setup_attrib_cb_base_valid_true_f() (0x80000000U) #define gr_gpcs_setup_attrib_cb_base_valid_true_f() (0x80000000U)
#define gr_crstr_gpc_map0_r() (0x00418b08U) #define gr_crstr_gpc_map0_r() (0x00418b08U)
#define gr_crstr_gpc_map0_tile0_f(v) (((v)&0x7U) << 0U) #define gr_crstr_gpc_map0_tile0_f(v) ((U32(v) & 0x7U) << 0U)
#define gr_crstr_gpc_map0_tile1_f(v) (((v)&0x7U) << 5U) #define gr_crstr_gpc_map0_tile1_f(v) ((U32(v) & 0x7U) << 5U)
#define gr_crstr_gpc_map0_tile2_f(v) (((v)&0x7U) << 10U) #define gr_crstr_gpc_map0_tile2_f(v) ((U32(v) & 0x7U) << 10U)
#define gr_crstr_gpc_map0_tile3_f(v) (((v)&0x7U) << 15U) #define gr_crstr_gpc_map0_tile3_f(v) ((U32(v) & 0x7U) << 15U)
#define gr_crstr_gpc_map0_tile4_f(v) (((v)&0x7U) << 20U) #define gr_crstr_gpc_map0_tile4_f(v) ((U32(v) & 0x7U) << 20U)
#define gr_crstr_gpc_map0_tile5_f(v) (((v)&0x7U) << 25U) #define gr_crstr_gpc_map0_tile5_f(v) ((U32(v) & 0x7U) << 25U)
#define gr_crstr_gpc_map1_r() (0x00418b0cU) #define gr_crstr_gpc_map1_r() (0x00418b0cU)
#define gr_crstr_gpc_map1_tile6_f(v) (((v)&0x7U) << 0U) #define gr_crstr_gpc_map1_tile6_f(v) ((U32(v) & 0x7U) << 0U)
#define gr_crstr_gpc_map1_tile7_f(v) (((v)&0x7U) << 5U) #define gr_crstr_gpc_map1_tile7_f(v) ((U32(v) & 0x7U) << 5U)
#define gr_crstr_gpc_map1_tile8_f(v) (((v)&0x7U) << 10U) #define gr_crstr_gpc_map1_tile8_f(v) ((U32(v) & 0x7U) << 10U)
#define gr_crstr_gpc_map1_tile9_f(v) (((v)&0x7U) << 15U) #define gr_crstr_gpc_map1_tile9_f(v) ((U32(v) & 0x7U) << 15U)
#define gr_crstr_gpc_map1_tile10_f(v) (((v)&0x7U) << 20U) #define gr_crstr_gpc_map1_tile10_f(v) ((U32(v) & 0x7U) << 20U)
#define gr_crstr_gpc_map1_tile11_f(v) (((v)&0x7U) << 25U) #define gr_crstr_gpc_map1_tile11_f(v) ((U32(v) & 0x7U) << 25U)
#define gr_crstr_gpc_map2_r() (0x00418b10U) #define gr_crstr_gpc_map2_r() (0x00418b10U)
#define gr_crstr_gpc_map2_tile12_f(v) (((v)&0x7U) << 0U) #define gr_crstr_gpc_map2_tile12_f(v) ((U32(v) & 0x7U) << 0U)
#define gr_crstr_gpc_map2_tile13_f(v) (((v)&0x7U) << 5U) #define gr_crstr_gpc_map2_tile13_f(v) ((U32(v) & 0x7U) << 5U)
#define gr_crstr_gpc_map2_tile14_f(v) (((v)&0x7U) << 10U) #define gr_crstr_gpc_map2_tile14_f(v) ((U32(v) & 0x7U) << 10U)
#define gr_crstr_gpc_map2_tile15_f(v) (((v)&0x7U) << 15U) #define gr_crstr_gpc_map2_tile15_f(v) ((U32(v) & 0x7U) << 15U)
#define gr_crstr_gpc_map2_tile16_f(v) (((v)&0x7U) << 20U) #define gr_crstr_gpc_map2_tile16_f(v) ((U32(v) & 0x7U) << 20U)
#define gr_crstr_gpc_map2_tile17_f(v) (((v)&0x7U) << 25U) #define gr_crstr_gpc_map2_tile17_f(v) ((U32(v) & 0x7U) << 25U)
#define gr_crstr_gpc_map3_r() (0x00418b14U) #define gr_crstr_gpc_map3_r() (0x00418b14U)
#define gr_crstr_gpc_map3_tile18_f(v) (((v)&0x7U) << 0U) #define gr_crstr_gpc_map3_tile18_f(v) ((U32(v) & 0x7U) << 0U)
#define gr_crstr_gpc_map3_tile19_f(v) (((v)&0x7U) << 5U) #define gr_crstr_gpc_map3_tile19_f(v) ((U32(v) & 0x7U) << 5U)
#define gr_crstr_gpc_map3_tile20_f(v) (((v)&0x7U) << 10U) #define gr_crstr_gpc_map3_tile20_f(v) ((U32(v) & 0x7U) << 10U)
#define gr_crstr_gpc_map3_tile21_f(v) (((v)&0x7U) << 15U) #define gr_crstr_gpc_map3_tile21_f(v) ((U32(v) & 0x7U) << 15U)
#define gr_crstr_gpc_map3_tile22_f(v) (((v)&0x7U) << 20U) #define gr_crstr_gpc_map3_tile22_f(v) ((U32(v) & 0x7U) << 20U)
#define gr_crstr_gpc_map3_tile23_f(v) (((v)&0x7U) << 25U) #define gr_crstr_gpc_map3_tile23_f(v) ((U32(v) & 0x7U) << 25U)
#define gr_crstr_gpc_map4_r() (0x00418b18U) #define gr_crstr_gpc_map4_r() (0x00418b18U)
#define gr_crstr_gpc_map4_tile24_f(v) (((v)&0x7U) << 0U) #define gr_crstr_gpc_map4_tile24_f(v) ((U32(v) & 0x7U) << 0U)
#define gr_crstr_gpc_map4_tile25_f(v) (((v)&0x7U) << 5U) #define gr_crstr_gpc_map4_tile25_f(v) ((U32(v) & 0x7U) << 5U)
#define gr_crstr_gpc_map4_tile26_f(v) (((v)&0x7U) << 10U) #define gr_crstr_gpc_map4_tile26_f(v) ((U32(v) & 0x7U) << 10U)
#define gr_crstr_gpc_map4_tile27_f(v) (((v)&0x7U) << 15U) #define gr_crstr_gpc_map4_tile27_f(v) ((U32(v) & 0x7U) << 15U)
#define gr_crstr_gpc_map4_tile28_f(v) (((v)&0x7U) << 20U) #define gr_crstr_gpc_map4_tile28_f(v) ((U32(v) & 0x7U) << 20U)
#define gr_crstr_gpc_map4_tile29_f(v) (((v)&0x7U) << 25U) #define gr_crstr_gpc_map4_tile29_f(v) ((U32(v) & 0x7U) << 25U)
#define gr_crstr_gpc_map5_r() (0x00418b1cU) #define gr_crstr_gpc_map5_r() (0x00418b1cU)
#define gr_crstr_gpc_map5_tile30_f(v) (((v)&0x7U) << 0U) #define gr_crstr_gpc_map5_tile30_f(v) ((U32(v) & 0x7U) << 0U)
#define gr_crstr_gpc_map5_tile31_f(v) (((v)&0x7U) << 5U) #define gr_crstr_gpc_map5_tile31_f(v) ((U32(v) & 0x7U) << 5U)
#define gr_crstr_gpc_map5_tile32_f(v) (((v)&0x7U) << 10U) #define gr_crstr_gpc_map5_tile32_f(v) ((U32(v) & 0x7U) << 10U)
#define gr_crstr_gpc_map5_tile33_f(v) (((v)&0x7U) << 15U) #define gr_crstr_gpc_map5_tile33_f(v) ((U32(v) & 0x7U) << 15U)
#define gr_crstr_gpc_map5_tile34_f(v) (((v)&0x7U) << 20U) #define gr_crstr_gpc_map5_tile34_f(v) ((U32(v) & 0x7U) << 20U)
#define gr_crstr_gpc_map5_tile35_f(v) (((v)&0x7U) << 25U) #define gr_crstr_gpc_map5_tile35_f(v) ((U32(v) & 0x7U) << 25U)
#define gr_crstr_map_table_cfg_r() (0x00418bb8U) #define gr_crstr_map_table_cfg_r() (0x00418bb8U)
#define gr_crstr_map_table_cfg_row_offset_f(v) (((v)&0xffU) << 0U) #define gr_crstr_map_table_cfg_row_offset_f(v) ((U32(v) & 0xffU) << 0U)
#define gr_crstr_map_table_cfg_num_entries_f(v) (((v)&0xffU) << 8U) #define gr_crstr_map_table_cfg_num_entries_f(v) ((U32(v) & 0xffU) << 8U)
#define gr_gpcs_zcull_sm_in_gpc_number_map0_r() (0x00418980U) #define gr_gpcs_zcull_sm_in_gpc_number_map0_r() (0x00418980U)
#define gr_gpcs_zcull_sm_in_gpc_number_map0_tile_0_f(v) (((v)&0x7U) << 0U) #define gr_gpcs_zcull_sm_in_gpc_number_map0_tile_0_f(v) ((U32(v) & 0x7U) << 0U)
#define gr_gpcs_zcull_sm_in_gpc_number_map0_tile_1_f(v) (((v)&0x7U) << 4U) #define gr_gpcs_zcull_sm_in_gpc_number_map0_tile_1_f(v) ((U32(v) & 0x7U) << 4U)
#define gr_gpcs_zcull_sm_in_gpc_number_map0_tile_2_f(v) (((v)&0x7U) << 8U) #define gr_gpcs_zcull_sm_in_gpc_number_map0_tile_2_f(v) ((U32(v) & 0x7U) << 8U)
#define gr_gpcs_zcull_sm_in_gpc_number_map0_tile_3_f(v) (((v)&0x7U) << 12U) #define gr_gpcs_zcull_sm_in_gpc_number_map0_tile_3_f(v) ((U32(v) & 0x7U) << 12U)
#define gr_gpcs_zcull_sm_in_gpc_number_map0_tile_4_f(v) (((v)&0x7U) << 16U) #define gr_gpcs_zcull_sm_in_gpc_number_map0_tile_4_f(v) ((U32(v) & 0x7U) << 16U)
#define gr_gpcs_zcull_sm_in_gpc_number_map0_tile_5_f(v) (((v)&0x7U) << 20U) #define gr_gpcs_zcull_sm_in_gpc_number_map0_tile_5_f(v) ((U32(v) & 0x7U) << 20U)
#define gr_gpcs_zcull_sm_in_gpc_number_map0_tile_6_f(v) (((v)&0x7U) << 24U) #define gr_gpcs_zcull_sm_in_gpc_number_map0_tile_6_f(v) ((U32(v) & 0x7U) << 24U)
#define gr_gpcs_zcull_sm_in_gpc_number_map0_tile_7_f(v) (((v)&0x7U) << 28U) #define gr_gpcs_zcull_sm_in_gpc_number_map0_tile_7_f(v) ((U32(v) & 0x7U) << 28U)
#define gr_gpcs_zcull_sm_in_gpc_number_map1_r() (0x00418984U) #define gr_gpcs_zcull_sm_in_gpc_number_map1_r() (0x00418984U)
#define gr_gpcs_zcull_sm_in_gpc_number_map1_tile_8_f(v) (((v)&0x7U) << 0U) #define gr_gpcs_zcull_sm_in_gpc_number_map1_tile_8_f(v) ((U32(v) & 0x7U) << 0U)
#define gr_gpcs_zcull_sm_in_gpc_number_map1_tile_9_f(v) (((v)&0x7U) << 4U) #define gr_gpcs_zcull_sm_in_gpc_number_map1_tile_9_f(v) ((U32(v) & 0x7U) << 4U)
#define gr_gpcs_zcull_sm_in_gpc_number_map1_tile_10_f(v) (((v)&0x7U) << 8U) #define gr_gpcs_zcull_sm_in_gpc_number_map1_tile_10_f(v) ((U32(v) & 0x7U) << 8U)
#define gr_gpcs_zcull_sm_in_gpc_number_map1_tile_11_f(v) (((v)&0x7U) << 12U) #define gr_gpcs_zcull_sm_in_gpc_number_map1_tile_11_f(v)\
#define gr_gpcs_zcull_sm_in_gpc_number_map1_tile_12_f(v) (((v)&0x7U) << 16U) ((U32(v) & 0x7U) << 12U)
#define gr_gpcs_zcull_sm_in_gpc_number_map1_tile_13_f(v) (((v)&0x7U) << 20U) #define gr_gpcs_zcull_sm_in_gpc_number_map1_tile_12_f(v)\
#define gr_gpcs_zcull_sm_in_gpc_number_map1_tile_14_f(v) (((v)&0x7U) << 24U) ((U32(v) & 0x7U) << 16U)
#define gr_gpcs_zcull_sm_in_gpc_number_map1_tile_15_f(v) (((v)&0x7U) << 28U) #define gr_gpcs_zcull_sm_in_gpc_number_map1_tile_13_f(v)\
((U32(v) & 0x7U) << 20U)
#define gr_gpcs_zcull_sm_in_gpc_number_map1_tile_14_f(v)\
((U32(v) & 0x7U) << 24U)
#define gr_gpcs_zcull_sm_in_gpc_number_map1_tile_15_f(v)\
((U32(v) & 0x7U) << 28U)
#define gr_gpcs_zcull_sm_in_gpc_number_map2_r() (0x00418988U) #define gr_gpcs_zcull_sm_in_gpc_number_map2_r() (0x00418988U)
#define gr_gpcs_zcull_sm_in_gpc_number_map2_tile_16_f(v) (((v)&0x7U) << 0U) #define gr_gpcs_zcull_sm_in_gpc_number_map2_tile_16_f(v) ((U32(v) & 0x7U) << 0U)
#define gr_gpcs_zcull_sm_in_gpc_number_map2_tile_17_f(v) (((v)&0x7U) << 4U) #define gr_gpcs_zcull_sm_in_gpc_number_map2_tile_17_f(v) ((U32(v) & 0x7U) << 4U)
#define gr_gpcs_zcull_sm_in_gpc_number_map2_tile_18_f(v) (((v)&0x7U) << 8U) #define gr_gpcs_zcull_sm_in_gpc_number_map2_tile_18_f(v) ((U32(v) & 0x7U) << 8U)
#define gr_gpcs_zcull_sm_in_gpc_number_map2_tile_19_f(v) (((v)&0x7U) << 12U) #define gr_gpcs_zcull_sm_in_gpc_number_map2_tile_19_f(v)\
#define gr_gpcs_zcull_sm_in_gpc_number_map2_tile_20_f(v) (((v)&0x7U) << 16U) ((U32(v) & 0x7U) << 12U)
#define gr_gpcs_zcull_sm_in_gpc_number_map2_tile_21_f(v) (((v)&0x7U) << 20U) #define gr_gpcs_zcull_sm_in_gpc_number_map2_tile_20_f(v)\
#define gr_gpcs_zcull_sm_in_gpc_number_map2_tile_22_f(v) (((v)&0x7U) << 24U) ((U32(v) & 0x7U) << 16U)
#define gr_gpcs_zcull_sm_in_gpc_number_map2_tile_21_f(v)\
((U32(v) & 0x7U) << 20U)
#define gr_gpcs_zcull_sm_in_gpc_number_map2_tile_22_f(v)\
((U32(v) & 0x7U) << 24U)
#define gr_gpcs_zcull_sm_in_gpc_number_map2_tile_23_s() (3U) #define gr_gpcs_zcull_sm_in_gpc_number_map2_tile_23_s() (3U)
#define gr_gpcs_zcull_sm_in_gpc_number_map2_tile_23_f(v) (((v)&0x7U) << 28U) #define gr_gpcs_zcull_sm_in_gpc_number_map2_tile_23_f(v)\
((U32(v) & 0x7U) << 28U)
#define gr_gpcs_zcull_sm_in_gpc_number_map2_tile_23_m() (U32(0x7U) << 28U) #define gr_gpcs_zcull_sm_in_gpc_number_map2_tile_23_m() (U32(0x7U) << 28U)
#define gr_gpcs_zcull_sm_in_gpc_number_map2_tile_23_v(r) (((r) >> 28U) & 0x7U) #define gr_gpcs_zcull_sm_in_gpc_number_map2_tile_23_v(r) (((r) >> 28U) & 0x7U)
#define gr_gpcs_zcull_sm_in_gpc_number_map3_r() (0x0041898cU) #define gr_gpcs_zcull_sm_in_gpc_number_map3_r() (0x0041898cU)
#define gr_gpcs_zcull_sm_in_gpc_number_map3_tile_24_f(v) (((v)&0x7U) << 0U) #define gr_gpcs_zcull_sm_in_gpc_number_map3_tile_24_f(v) ((U32(v) & 0x7U) << 0U)
#define gr_gpcs_zcull_sm_in_gpc_number_map3_tile_25_f(v) (((v)&0x7U) << 4U) #define gr_gpcs_zcull_sm_in_gpc_number_map3_tile_25_f(v) ((U32(v) & 0x7U) << 4U)
#define gr_gpcs_zcull_sm_in_gpc_number_map3_tile_26_f(v) (((v)&0x7U) << 8U) #define gr_gpcs_zcull_sm_in_gpc_number_map3_tile_26_f(v) ((U32(v) & 0x7U) << 8U)
#define gr_gpcs_zcull_sm_in_gpc_number_map3_tile_27_f(v) (((v)&0x7U) << 12U) #define gr_gpcs_zcull_sm_in_gpc_number_map3_tile_27_f(v)\
#define gr_gpcs_zcull_sm_in_gpc_number_map3_tile_28_f(v) (((v)&0x7U) << 16U) ((U32(v) & 0x7U) << 12U)
#define gr_gpcs_zcull_sm_in_gpc_number_map3_tile_29_f(v) (((v)&0x7U) << 20U) #define gr_gpcs_zcull_sm_in_gpc_number_map3_tile_28_f(v)\
#define gr_gpcs_zcull_sm_in_gpc_number_map3_tile_30_f(v) (((v)&0x7U) << 24U) ((U32(v) & 0x7U) << 16U)
#define gr_gpcs_zcull_sm_in_gpc_number_map3_tile_31_f(v) (((v)&0x7U) << 28U) #define gr_gpcs_zcull_sm_in_gpc_number_map3_tile_29_f(v)\
((U32(v) & 0x7U) << 20U)
#define gr_gpcs_zcull_sm_in_gpc_number_map3_tile_30_f(v)\
((U32(v) & 0x7U) << 24U)
#define gr_gpcs_zcull_sm_in_gpc_number_map3_tile_31_f(v)\
((U32(v) & 0x7U) << 28U)
#define gr_gpcs_gpm_pd_cfg_r() (0x00418c6cU) #define gr_gpcs_gpm_pd_cfg_r() (0x00418c6cU)
#define gr_gpcs_gpm_pd_cfg_timeslice_mode_disable_f() (0x0U) #define gr_gpcs_gpm_pd_cfg_timeslice_mode_disable_f() (0x0U)
#define gr_gpcs_gpm_pd_cfg_timeslice_mode_enable_f() (0x1U) #define gr_gpcs_gpm_pd_cfg_timeslice_mode_enable_f() (0x1U)
#define gr_gpcs_gcc_pagepool_base_r() (0x00419004U) #define gr_gpcs_gcc_pagepool_base_r() (0x00419004U)
#define gr_gpcs_gcc_pagepool_base_addr_39_8_f(v) (((v)&0xffffffffU) << 0U) #define gr_gpcs_gcc_pagepool_base_addr_39_8_f(v) ((U32(v) & 0xffffffffU) << 0U)
#define gr_gpcs_gcc_pagepool_r() (0x00419008U) #define gr_gpcs_gcc_pagepool_r() (0x00419008U)
#define gr_gpcs_gcc_pagepool_total_pages_f(v) (((v)&0x3ffU) << 0U) #define gr_gpcs_gcc_pagepool_total_pages_f(v) ((U32(v) & 0x3ffU) << 0U)
#define gr_gpcs_tpcs_pe_vaf_r() (0x0041980cU) #define gr_gpcs_tpcs_pe_vaf_r() (0x0041980cU)
#define gr_gpcs_tpcs_pe_vaf_fast_mode_switch_true_f() (0x10U) #define gr_gpcs_tpcs_pe_vaf_fast_mode_switch_true_f() (0x10U)
#define gr_gpcs_tpcs_pe_pin_cb_global_base_addr_r() (0x00419848U) #define gr_gpcs_tpcs_pe_pin_cb_global_base_addr_r() (0x00419848U)
#define gr_gpcs_tpcs_pe_pin_cb_global_base_addr_v_f(v) (((v)&0xfffffffU) << 0U) #define gr_gpcs_tpcs_pe_pin_cb_global_base_addr_v_f(v)\
#define gr_gpcs_tpcs_pe_pin_cb_global_base_addr_valid_f(v) (((v)&0x1U) << 28U) ((U32(v) & 0xfffffffU) << 0U)
#define gr_gpcs_tpcs_pe_pin_cb_global_base_addr_valid_f(v)\
((U32(v) & 0x1U) << 28U)
#define gr_gpcs_tpcs_pe_pin_cb_global_base_addr_valid_true_f() (0x10000000U) #define gr_gpcs_tpcs_pe_pin_cb_global_base_addr_valid_true_f() (0x10000000U)
#define gr_gpcs_tpcs_mpc_vtg_debug_r() (0x00419c00U) #define gr_gpcs_tpcs_mpc_vtg_debug_r() (0x00419c00U)
#define gr_gpcs_tpcs_mpc_vtg_debug_timeslice_mode_disabled_f() (0x0U) #define gr_gpcs_tpcs_mpc_vtg_debug_timeslice_mode_disabled_f() (0x0U)
#define gr_gpcs_tpcs_mpc_vtg_debug_timeslice_mode_enabled_f() (0x8U) #define gr_gpcs_tpcs_mpc_vtg_debug_timeslice_mode_enabled_f() (0x8U)
#define gr_gpcs_tpcs_mpc_vtg_cb_global_base_addr_r() (0x00419c2cU) #define gr_gpcs_tpcs_mpc_vtg_cb_global_base_addr_r() (0x00419c2cU)
#define gr_gpcs_tpcs_mpc_vtg_cb_global_base_addr_v_f(v) (((v)&0xfffffffU) << 0U) #define gr_gpcs_tpcs_mpc_vtg_cb_global_base_addr_v_f(v)\
#define gr_gpcs_tpcs_mpc_vtg_cb_global_base_addr_valid_f(v) (((v)&0x1U) << 28U) ((U32(v) & 0xfffffffU) << 0U)
#define gr_gpcs_tpcs_mpc_vtg_cb_global_base_addr_valid_f(v)\
((U32(v) & 0x1U) << 28U)
#define gr_gpcs_tpcs_mpc_vtg_cb_global_base_addr_valid_true_f() (0x10000000U) #define gr_gpcs_tpcs_mpc_vtg_cb_global_base_addr_valid_true_f() (0x10000000U)
#define gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_r() (0x00419e44U) #define gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_r() (0x00419e44U)
#define gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_stack_error_report_f() (0x2U) #define gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_stack_error_report_f() (0x2U)
@@ -1009,7 +1036,7 @@
#define gr_gpc0_tpc0_tpccs_tpc_exception_en_sm_v(r) (((r) >> 1U) & 0x1U) #define gr_gpc0_tpc0_tpccs_tpc_exception_en_sm_v(r) (((r) >> 1U) & 0x1U)
#define gr_gpc0_tpc0_tpccs_tpc_exception_en_sm_enabled_f() (0x2U) #define gr_gpc0_tpc0_tpccs_tpc_exception_en_sm_enabled_f() (0x2U)
#define gr_gpcs_gpccs_gpc_exception_en_r() (0x0041ac94U) #define gr_gpcs_gpccs_gpc_exception_en_r() (0x0041ac94U)
#define gr_gpcs_gpccs_gpc_exception_en_tpc_f(v) (((v)&0xffU) << 16U) #define gr_gpcs_gpccs_gpc_exception_en_tpc_f(v) ((U32(v) & 0xffU) << 16U)
#define gr_gpc0_gpccs_gpc_exception_r() (0x00502c90U) #define gr_gpc0_gpccs_gpc_exception_r() (0x00502c90U)
#define gr_gpc0_gpccs_gpc_exception_gcc_v(r) (((r) >> 2U) & 0x1U) #define gr_gpc0_gpccs_gpc_exception_gcc_v(r) (((r) >> 2U) & 0x1U)
#define gr_gpc0_gpccs_gpc_exception_tpc_v(r) (((r) >> 16U) & 0xffU) #define gr_gpc0_gpccs_gpc_exception_tpc_v(r) (((r) >> 16U) & 0xffU)
@@ -1090,11 +1117,13 @@
#define gr_gpc0_tpc0_sm_halfctl_ctrl_r() (0x00504770U) #define gr_gpc0_tpc0_sm_halfctl_ctrl_r() (0x00504770U)
#define gr_gpcs_tpcs_sm_halfctl_ctrl_r() (0x00419f70U) #define gr_gpcs_tpcs_sm_halfctl_ctrl_r() (0x00419f70U)
#define gr_gpcs_tpcs_sm_halfctl_ctrl_sctl_read_quad_ctl_m() (U32(0x1U) << 4U) #define gr_gpcs_tpcs_sm_halfctl_ctrl_sctl_read_quad_ctl_m() (U32(0x1U) << 4U)
#define gr_gpcs_tpcs_sm_halfctl_ctrl_sctl_read_quad_ctl_f(v) (((v)&0x1U) << 4U) #define gr_gpcs_tpcs_sm_halfctl_ctrl_sctl_read_quad_ctl_f(v)\
((U32(v) & 0x1U) << 4U)
#define gr_gpc0_tpc0_sm_debug_sfe_control_r() (0x0050477cU) #define gr_gpc0_tpc0_sm_debug_sfe_control_r() (0x0050477cU)
#define gr_gpcs_tpcs_sm_debug_sfe_control_r() (0x00419f7cU) #define gr_gpcs_tpcs_sm_debug_sfe_control_r() (0x00419f7cU)
#define gr_gpcs_tpcs_sm_debug_sfe_control_read_half_ctl_m() (U32(0x1U) << 0U) #define gr_gpcs_tpcs_sm_debug_sfe_control_read_half_ctl_m() (U32(0x1U) << 0U)
#define gr_gpcs_tpcs_sm_debug_sfe_control_read_half_ctl_f(v) (((v)&0x1U) << 0U) #define gr_gpcs_tpcs_sm_debug_sfe_control_read_half_ctl_f(v)\
((U32(v) & 0x1U) << 0U)
#define gr_gpcs_tpcs_pes_vsc_vpc_r() (0x0041be08U) #define gr_gpcs_tpcs_pes_vsc_vpc_r() (0x0041be08U)
#define gr_gpcs_tpcs_pes_vsc_vpc_fast_mode_switch_true_f() (0x4U) #define gr_gpcs_tpcs_pes_vsc_vpc_fast_mode_switch_true_f() (0x4U)
#define gr_ppcs_wwdx_map_gpc_map0_r() (0x0041bf00U) #define gr_ppcs_wwdx_map_gpc_map0_r() (0x0041bf00U)
@@ -1104,24 +1133,32 @@
#define gr_ppcs_wwdx_map_gpc_map4_r() (0x0041bf10U) #define gr_ppcs_wwdx_map_gpc_map4_r() (0x0041bf10U)
#define gr_ppcs_wwdx_map_gpc_map5_r() (0x0041bf14U) #define gr_ppcs_wwdx_map_gpc_map5_r() (0x0041bf14U)
#define gr_ppcs_wwdx_map_table_cfg_r() (0x0041bfd0U) #define gr_ppcs_wwdx_map_table_cfg_r() (0x0041bfd0U)
#define gr_ppcs_wwdx_map_table_cfg_row_offset_f(v) (((v)&0xffU) << 0U) #define gr_ppcs_wwdx_map_table_cfg_row_offset_f(v) ((U32(v) & 0xffU) << 0U)
#define gr_ppcs_wwdx_map_table_cfg_num_entries_f(v) (((v)&0xffU) << 8U) #define gr_ppcs_wwdx_map_table_cfg_num_entries_f(v) ((U32(v) & 0xffU) << 8U)
#define gr_ppcs_wwdx_map_table_cfg_normalized_num_entries_f(v)\ #define gr_ppcs_wwdx_map_table_cfg_normalized_num_entries_f(v)\
(((v)&0x1fU) << 16U) ((U32(v) & 0x1fU) << 16U)
#define gr_ppcs_wwdx_map_table_cfg_normalized_shift_value_f(v)\ #define gr_ppcs_wwdx_map_table_cfg_normalized_shift_value_f(v)\
(((v)&0x7U) << 21U) ((U32(v) & 0x7U) << 21U)
#define gr_ppcs_wwdx_map_table_cfg_coeff5_mod_value_f(v) (((v)&0x1fU) << 24U) #define gr_ppcs_wwdx_map_table_cfg_coeff5_mod_value_f(v)\
((U32(v) & 0x1fU) << 24U)
#define gr_gpcs_ppcs_wwdx_sm_num_rcp_r() (0x0041bfd4U) #define gr_gpcs_ppcs_wwdx_sm_num_rcp_r() (0x0041bfd4U)
#define gr_gpcs_ppcs_wwdx_sm_num_rcp_conservative_f(v) (((v)&0xffffffU) << 0U) #define gr_gpcs_ppcs_wwdx_sm_num_rcp_conservative_f(v)\
((U32(v) & 0xffffffU) << 0U)
#define gr_ppcs_wwdx_map_table_cfg2_r() (0x0041bfe4U) #define gr_ppcs_wwdx_map_table_cfg2_r() (0x0041bfe4U)
#define gr_ppcs_wwdx_map_table_cfg2_coeff6_mod_value_f(v) (((v)&0x1fU) << 0U) #define gr_ppcs_wwdx_map_table_cfg2_coeff6_mod_value_f(v)\
#define gr_ppcs_wwdx_map_table_cfg2_coeff7_mod_value_f(v) (((v)&0x1fU) << 5U) ((U32(v) & 0x1fU) << 0U)
#define gr_ppcs_wwdx_map_table_cfg2_coeff8_mod_value_f(v) (((v)&0x1fU) << 10U) #define gr_ppcs_wwdx_map_table_cfg2_coeff7_mod_value_f(v)\
#define gr_ppcs_wwdx_map_table_cfg2_coeff9_mod_value_f(v) (((v)&0x1fU) << 15U) ((U32(v) & 0x1fU) << 5U)
#define gr_ppcs_wwdx_map_table_cfg2_coeff10_mod_value_f(v) (((v)&0x1fU) << 20U) #define gr_ppcs_wwdx_map_table_cfg2_coeff8_mod_value_f(v)\
#define gr_ppcs_wwdx_map_table_cfg2_coeff11_mod_value_f(v) (((v)&0x1fU) << 25U) ((U32(v) & 0x1fU) << 10U)
#define gr_ppcs_wwdx_map_table_cfg2_coeff9_mod_value_f(v)\
((U32(v) & 0x1fU) << 15U)
#define gr_ppcs_wwdx_map_table_cfg2_coeff10_mod_value_f(v)\
((U32(v) & 0x1fU) << 20U)
#define gr_ppcs_wwdx_map_table_cfg2_coeff11_mod_value_f(v)\
((U32(v) & 0x1fU) << 25U)
#define gr_bes_zrop_settings_r() (0x00408850U) #define gr_bes_zrop_settings_r() (0x00408850U)
#define gr_bes_zrop_settings_num_active_ltcs_f(v) (((v)&0xfU) << 0U) #define gr_bes_zrop_settings_num_active_ltcs_f(v) ((U32(v) & 0xfU) << 0U)
#define gr_be0_crop_debug3_r() (0x00410108U) #define gr_be0_crop_debug3_r() (0x00410108U)
#define gr_bes_crop_debug3_r() (0x00408908U) #define gr_bes_crop_debug3_r() (0x00408908U)
#define gr_bes_crop_debug3_comp_vdc_4to2_disable_m() (U32(0x1U) << 31U) #define gr_bes_crop_debug3_comp_vdc_4to2_disable_m() (U32(0x1U) << 31U)
@@ -1136,7 +1173,7 @@
#define gr_bes_crop_debug4_clamp_fp_blend_to_inf_f() (0x0U) #define gr_bes_crop_debug4_clamp_fp_blend_to_inf_f() (0x0U)
#define gr_bes_crop_debug4_clamp_fp_blend_to_maxval_f() (0x40000U) #define gr_bes_crop_debug4_clamp_fp_blend_to_maxval_f() (0x40000U)
#define gr_bes_crop_settings_r() (0x00408958U) #define gr_bes_crop_settings_r() (0x00408958U)
#define gr_bes_crop_settings_num_active_ltcs_f(v) (((v)&0xfU) << 0U) #define gr_bes_crop_settings_num_active_ltcs_f(v) ((U32(v) & 0xfU) << 0U)
#define gr_zcull_bytes_per_aliquot_per_gpu_v() (0x00000020U) #define gr_zcull_bytes_per_aliquot_per_gpu_v() (0x00000020U)
#define gr_zcull_save_restore_header_bytes_per_gpc_v() (0x00000020U) #define gr_zcull_save_restore_header_bytes_per_gpc_v() (0x00000020U)
#define gr_zcull_save_restore_subregion_header_bytes_per_gpc_v() (0x000000c0U) #define gr_zcull_save_restore_subregion_header_bytes_per_gpc_v() (0x000000c0U)
@@ -1192,7 +1229,7 @@
#define gr_gpcs_pri_mmu_debug_rd_r() (0x004188b8U) #define gr_gpcs_pri_mmu_debug_rd_r() (0x004188b8U)
#define gr_gpcs_mmu_num_active_ltcs_r() (0x004188acU) #define gr_gpcs_mmu_num_active_ltcs_r() (0x004188acU)
#define gr_gpcs_tpcs_sm_dbgr_control0_r() (0x00419e10U) #define gr_gpcs_tpcs_sm_dbgr_control0_r() (0x00419e10U)
#define gr_gpcs_tpcs_sm_dbgr_control0_debugger_mode_f(v) (((v)&0x1U) << 0U) #define gr_gpcs_tpcs_sm_dbgr_control0_debugger_mode_f(v) ((U32(v) & 0x1U) << 0U)
#define gr_gpcs_tpcs_sm_dbgr_control0_debugger_mode_on_v() (0x00000001U) #define gr_gpcs_tpcs_sm_dbgr_control0_debugger_mode_on_v() (0x00000001U)
#define gr_gpcs_tpcs_sm_dbgr_control0_stop_trigger_m() (U32(0x1U) << 31U) #define gr_gpcs_tpcs_sm_dbgr_control0_stop_trigger_m() (U32(0x1U) << 31U)
#define gr_gpcs_tpcs_sm_dbgr_control0_stop_trigger_v(r) (((r) >> 31U) & 0x1U) #define gr_gpcs_tpcs_sm_dbgr_control0_stop_trigger_v(r) (((r) >> 31U) & 0x1U)
@@ -1205,7 +1242,7 @@
#define gr_gpcs_tpcs_sm_dbgr_control0_run_trigger_v(r) (((r) >> 30U) & 0x1U) #define gr_gpcs_tpcs_sm_dbgr_control0_run_trigger_v(r) (((r) >> 30U) & 0x1U)
#define gr_gpcs_tpcs_sm_dbgr_control0_run_trigger_task_f() (0x40000000U) #define gr_gpcs_tpcs_sm_dbgr_control0_run_trigger_task_f() (0x40000000U)
#define gr_fe_gfxp_wfi_timeout_r() (0x004041c0U) #define gr_fe_gfxp_wfi_timeout_r() (0x004041c0U)
#define gr_fe_gfxp_wfi_timeout_count_f(v) (((v)&0xffffffffU) << 0U) #define gr_fe_gfxp_wfi_timeout_count_f(v) ((U32(v) & 0xffffffffU) << 0U)
#define gr_fe_gfxp_wfi_timeout_count_disabled_f() (0x0U) #define gr_fe_gfxp_wfi_timeout_count_disabled_f() (0x0U)
#define gr_debug_2_r() (0x00400088U) #define gr_debug_2_r() (0x00400088U)
#define gr_debug_2_gfxp_wfi_always_injects_wfi_m() (U32(0x1U) << 23U) #define gr_debug_2_gfxp_wfi_always_injects_wfi_m() (U32(0x1U) << 23U)
@@ -1214,7 +1251,7 @@
#define gr_debug_2_gfxp_wfi_always_injects_wfi_disabled_f() (0x0U) #define gr_debug_2_gfxp_wfi_always_injects_wfi_disabled_f() (0x0U)
#define gr_gpcs_tpcs_sm_texio_control_r() (0x00419c84U) #define gr_gpcs_tpcs_sm_texio_control_r() (0x00419c84U)
#define gr_gpcs_tpcs_sm_texio_control_oor_addr_check_mode_f(v)\ #define gr_gpcs_tpcs_sm_texio_control_oor_addr_check_mode_f(v)\
(((v)&0x7U) << 8U) ((U32(v) & 0x7U) << 8U)
#define gr_gpcs_tpcs_sm_texio_control_oor_addr_check_mode_m() (U32(0x7U) << 8U) #define gr_gpcs_tpcs_sm_texio_control_oor_addr_check_mode_m() (U32(0x7U) << 8U)
#define gr_gpcs_tpcs_sm_texio_control_oor_addr_check_mode_arm_63_48_match_f()\ #define gr_gpcs_tpcs_sm_texio_control_oor_addr_check_mode_arm_63_48_match_f()\
(0x100U) (0x100U)
@@ -1222,6 +1259,7 @@
#define gr_gpcs_tpcs_sm_disp_ctrl_re_suppress_m() (U32(0x3U) << 11U) #define gr_gpcs_tpcs_sm_disp_ctrl_re_suppress_m() (U32(0x3U) << 11U)
#define gr_gpcs_tpcs_sm_disp_ctrl_re_suppress_disable_f() (0x1000U) #define gr_gpcs_tpcs_sm_disp_ctrl_re_suppress_disable_f() (0x1000U)
#define gr_gpcs_tc_debug0_r() (0x00418708U) #define gr_gpcs_tc_debug0_r() (0x00418708U)
#define gr_gpcs_tc_debug0_limit_coalesce_buffer_size_f(v) (((v)&0xffU) << 0U) #define gr_gpcs_tc_debug0_limit_coalesce_buffer_size_f(v)\
((U32(v) & 0xffU) << 0U)
#define gr_gpcs_tc_debug0_limit_coalesce_buffer_size_m() (U32(0xffU) << 0U) #define gr_gpcs_tc_debug0_limit_coalesce_buffer_size_m() (U32(0xffU) << 0U)
#endif #endif

14
drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_ltc_gp10b.h
View File

@@ -82,9 +82,11 @@
#define ltc_ltcs_ltss_cbc_ctrl1_clear_active_f() (0x4U) #define ltc_ltcs_ltss_cbc_ctrl1_clear_active_f() (0x4U)
#define ltc_ltc0_lts0_cbc_ctrl1_r() (0x0014046cU) #define ltc_ltc0_lts0_cbc_ctrl1_r() (0x0014046cU)
#define ltc_ltcs_ltss_cbc_ctrl2_r() (0x0017e270U) #define ltc_ltcs_ltss_cbc_ctrl2_r() (0x0017e270U)
#define ltc_ltcs_ltss_cbc_ctrl2_clear_lower_bound_f(v) (((v)&0x3ffffU) << 0U) #define ltc_ltcs_ltss_cbc_ctrl2_clear_lower_bound_f(v)\
((U32(v) & 0x3ffffU) << 0U)
#define ltc_ltcs_ltss_cbc_ctrl3_r() (0x0017e274U) #define ltc_ltcs_ltss_cbc_ctrl3_r() (0x0017e274U)
#define ltc_ltcs_ltss_cbc_ctrl3_clear_upper_bound_f(v) (((v)&0x3ffffU) << 0U) #define ltc_ltcs_ltss_cbc_ctrl3_clear_upper_bound_f(v)\
((U32(v) & 0x3ffffU) << 0U)
#define ltc_ltcs_ltss_cbc_ctrl3_clear_upper_bound_init_v() (0x0003ffffU) #define ltc_ltcs_ltss_cbc_ctrl3_clear_upper_bound_init_v() (0x0003ffffU)
#define ltc_ltcs_ltss_cbc_base_r() (0x0017e278U) #define ltc_ltcs_ltss_cbc_base_r() (0x0017e278U)
#define ltc_ltcs_ltss_cbc_base_alignment_shift_v() (0x0000000bU) #define ltc_ltcs_ltss_cbc_base_alignment_shift_v() (0x0000000bU)
@@ -101,16 +103,16 @@
(((r) >> 0U) & 0xffffU) (((r) >> 0U) & 0xffffU)
#define ltc_ltcs_ltss_tstg_set_mgmt_r() (0x0017e2acU) #define ltc_ltcs_ltss_tstg_set_mgmt_r() (0x0017e2acU)
#define ltc_ltcs_ltss_tstg_set_mgmt_max_ways_evict_last_f(v)\ #define ltc_ltcs_ltss_tstg_set_mgmt_max_ways_evict_last_f(v)\
(((v)&0x1fU) << 16U) ((U32(v) & 0x1fU) << 16U)
#define ltc_ltcs_ltss_dstg_zbc_index_r() (0x0017e338U) #define ltc_ltcs_ltss_dstg_zbc_index_r() (0x0017e338U)
#define ltc_ltcs_ltss_dstg_zbc_index_address_f(v) (((v)&0xfU) << 0U) #define ltc_ltcs_ltss_dstg_zbc_index_address_f(v) ((U32(v) & 0xfU) << 0U)
#define ltc_ltcs_ltss_dstg_zbc_color_clear_value_r(i)\ #define ltc_ltcs_ltss_dstg_zbc_color_clear_value_r(i)\
(nvgpu_safe_add_u32(0x0017e33cU, nvgpu_safe_mult_u32((i), 4U))) (nvgpu_safe_add_u32(0x0017e33cU, nvgpu_safe_mult_u32((i), 4U)))
#define ltc_ltcs_ltss_dstg_zbc_color_clear_value__size_1_v() (0x00000004U) #define ltc_ltcs_ltss_dstg_zbc_color_clear_value__size_1_v() (0x00000004U)
#define ltc_ltcs_ltss_dstg_zbc_depth_clear_value_r() (0x0017e34cU) #define ltc_ltcs_ltss_dstg_zbc_depth_clear_value_r() (0x0017e34cU)
#define ltc_ltcs_ltss_dstg_zbc_depth_clear_value_field_s() (32U) #define ltc_ltcs_ltss_dstg_zbc_depth_clear_value_field_s() (32U)
#define ltc_ltcs_ltss_dstg_zbc_depth_clear_value_field_f(v)\ #define ltc_ltcs_ltss_dstg_zbc_depth_clear_value_field_f(v)\
(((v)&0xffffffffU) << 0U) ((U32(v) & 0xffffffffU) << 0U)
#define ltc_ltcs_ltss_dstg_zbc_depth_clear_value_field_m()\ #define ltc_ltcs_ltss_dstg_zbc_depth_clear_value_field_m()\
(U32(0xffffffffU) << 0U) (U32(0xffffffffU) << 0U)
#define ltc_ltcs_ltss_dstg_zbc_depth_clear_value_field_v(r)\ #define ltc_ltcs_ltss_dstg_zbc_depth_clear_value_field_v(r)\
@@ -204,5 +206,5 @@
#define ltc_ltc0_lts0_tstg_info_1_slice_size_in_kb_v(r) (((r) >> 0U) & 0xffffU) #define ltc_ltc0_lts0_tstg_info_1_slice_size_in_kb_v(r) (((r) >> 0U) & 0xffffU)
#define ltc_ltc0_lts0_tstg_info_1_slices_per_l2_v(r) (((r) >> 16U) & 0x1fU) #define ltc_ltc0_lts0_tstg_info_1_slices_per_l2_v(r) (((r) >> 16U) & 0x1fU)
#define ltc_ltca_g_axi_pctrl_r() (0x00160000U) #define ltc_ltca_g_axi_pctrl_r() (0x00160000U)
#define ltc_ltca_g_axi_pctrl_user_sid_f(v) (((v)&0xffU) << 2U) #define ltc_ltca_g_axi_pctrl_user_sid_f(v) ((U32(v) & 0xffU) << 2U)
#endif #endif

6
drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_mc_gp10b.h
View File

@@ -84,7 +84,7 @@
#define mc_enable_xbar_enabled_f() (0x4U) #define mc_enable_xbar_enabled_f() (0x4U)
#define mc_enable_l2_enabled_f() (0x8U) #define mc_enable_l2_enabled_f() (0x8U)
#define mc_enable_pmedia_s() (1U) #define mc_enable_pmedia_s() (1U)
#define mc_enable_pmedia_f(v) (((v)&0x1U) << 4U) #define mc_enable_pmedia_f(v) ((U32(v) & 0x1U) << 4U)
#define mc_enable_pmedia_m() (U32(0x1U) << 4U) #define mc_enable_pmedia_m() (U32(0x1U) << 4U)
#define mc_enable_pmedia_v(r) (((r) >> 4U) & 0x1U) #define mc_enable_pmedia_v(r) (((r) >> 4U) & 0x1U)
#define mc_enable_priv_ring_enabled_f() (0x20U) #define mc_enable_priv_ring_enabled_f() (0x20U)
@@ -103,12 +103,12 @@
#define mc_intr_ltc_r() (0x000001c0U) #define mc_intr_ltc_r() (0x000001c0U)
#define mc_enable_pb_r() (0x00000204U) #define mc_enable_pb_r() (0x00000204U)
#define mc_enable_pb_0_s() (1U) #define mc_enable_pb_0_s() (1U)
#define mc_enable_pb_0_f(v) (((v)&0x1U) << 0U) #define mc_enable_pb_0_f(v) ((U32(v) & 0x1U) << 0U)
#define mc_enable_pb_0_m() (U32(0x1U) << 0U) #define mc_enable_pb_0_m() (U32(0x1U) << 0U)
#define mc_enable_pb_0_v(r) (((r) >> 0U) & 0x1U) #define mc_enable_pb_0_v(r) (((r) >> 0U) & 0x1U)
#define mc_enable_pb_0_enabled_v() (0x00000001U) #define mc_enable_pb_0_enabled_v() (0x00000001U)
#define mc_enable_pb_sel_f(v, i)\ #define mc_enable_pb_sel_f(v, i)\
(((v) & 0x1) << (0U + i*1U)) ((U32(v) & 0x1U) << (0U + (i)*1U))
#define mc_elpg_enable_r() (0x0000020cU) #define mc_elpg_enable_r() (0x0000020cU)
#define mc_elpg_enable_xbar_enabled_f() (0x4U) #define mc_elpg_enable_xbar_enabled_f() (0x4U)
#define mc_elpg_enable_pfb_enabled_f() (0x100000U) #define mc_elpg_enable_pfb_enabled_f() (0x100000U)

28
drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_pbdma_gp10b.h
View File

@@ -61,17 +61,17 @@
#define pbdma_gp_entry1_r() (0x10000004U) #define pbdma_gp_entry1_r() (0x10000004U)
#define pbdma_gp_entry1_get_hi_v(r) (((r) >> 0U) & 0xffU) #define pbdma_gp_entry1_get_hi_v(r) (((r) >> 0U) & 0xffU)
#define pbdma_gp_entry1_length_f(v) (((v)&0x1fffffU) << 10U) #define pbdma_gp_entry1_length_f(v) ((U32(v) & 0x1fffffU) << 10U)
#define pbdma_gp_entry1_length_v(r) (((r) >> 10U) & 0x1fffffU) #define pbdma_gp_entry1_length_v(r) (((r) >> 10U) & 0x1fffffU)
#define pbdma_gp_base_r(i)\ #define pbdma_gp_base_r(i)\
(nvgpu_safe_add_u32(0x00040048U, nvgpu_safe_mult_u32((i), 8192U))) (nvgpu_safe_add_u32(0x00040048U, nvgpu_safe_mult_u32((i), 8192U)))
#define pbdma_gp_base__size_1_v() (0x00000001U) #define pbdma_gp_base__size_1_v() (0x00000001U)
#define pbdma_gp_base_offset_f(v) (((v)&0x1fffffffU) << 3U) #define pbdma_gp_base_offset_f(v) ((U32(v) & 0x1fffffffU) << 3U)
#define pbdma_gp_base_rsvd_s() (3U) #define pbdma_gp_base_rsvd_s() (3U)
#define pbdma_gp_base_hi_r(i)\ #define pbdma_gp_base_hi_r(i)\
(nvgpu_safe_add_u32(0x0004004cU, nvgpu_safe_mult_u32((i), 8192U))) (nvgpu_safe_add_u32(0x0004004cU, nvgpu_safe_mult_u32((i), 8192U)))
#define pbdma_gp_base_hi_offset_f(v) (((v)&0xffU) << 0U) #define pbdma_gp_base_hi_offset_f(v) ((U32(v) & 0xffU) << 0U)
#define pbdma_gp_base_hi_limit2_f(v) (((v)&0x1fU) << 16U) #define pbdma_gp_base_hi_limit2_f(v) ((U32(v) & 0x1fU) << 16U)
#define pbdma_gp_fetch_r(i)\ #define pbdma_gp_fetch_r(i)\
(nvgpu_safe_add_u32(0x00040050U, nvgpu_safe_mult_u32((i), 8192U))) (nvgpu_safe_add_u32(0x00040050U, nvgpu_safe_mult_u32((i), 8192U)))
#define pbdma_gp_get_r(i)\ #define pbdma_gp_get_r(i)\
@@ -117,13 +117,13 @@
(nvgpu_safe_add_u32(0x00040114U, nvgpu_safe_mult_u32((i), 8192U))) (nvgpu_safe_add_u32(0x00040114U, nvgpu_safe_mult_u32((i), 8192U)))
#define pbdma_subdevice_r(i)\ #define pbdma_subdevice_r(i)\
(nvgpu_safe_add_u32(0x00040094U, nvgpu_safe_mult_u32((i), 8192U))) (nvgpu_safe_add_u32(0x00040094U, nvgpu_safe_mult_u32((i), 8192U)))
#define pbdma_subdevice_id_f(v) (((v)&0xfffU) << 0U) #define pbdma_subdevice_id_f(v) ((U32(v) & 0xfffU) << 0U)
#define pbdma_subdevice_status_active_f() (0x10000000U) #define pbdma_subdevice_status_active_f() (0x10000000U)
#define pbdma_subdevice_channel_dma_enable_f() (0x20000000U) #define pbdma_subdevice_channel_dma_enable_f() (0x20000000U)
#define pbdma_method0_r(i)\ #define pbdma_method0_r(i)\
(nvgpu_safe_add_u32(0x000400c0U, nvgpu_safe_mult_u32((i), 8192U))) (nvgpu_safe_add_u32(0x000400c0U, nvgpu_safe_mult_u32((i), 8192U)))
#define pbdma_method0_fifo_size_v() (0x00000004U) #define pbdma_method0_fifo_size_v() (0x00000004U)
#define pbdma_method0_addr_f(v) (((v)&0xfffU) << 2U) #define pbdma_method0_addr_f(v) ((U32(v) & 0xfffU) << 2U)
#define pbdma_method0_addr_v(r) (((r) >> 2U) & 0xfffU) #define pbdma_method0_addr_v(r) (((r) >> 2U) & 0xfffU)
#define pbdma_method0_subch_v(r) (((r) >> 16U) & 0x7U) #define pbdma_method0_subch_v(r) (((r) >> 16U) & 0x7U)
#define pbdma_method0_first_true_f() (0x400000U) #define pbdma_method0_first_true_f() (0x400000U)
@@ -143,10 +143,10 @@
(nvgpu_safe_add_u32(0x00040030U, nvgpu_safe_mult_u32((i), 8192U))) (nvgpu_safe_add_u32(0x00040030U, nvgpu_safe_mult_u32((i), 8192U)))
#define pbdma_acquire_retry_man_2_f() (0x2U) #define pbdma_acquire_retry_man_2_f() (0x2U)
#define pbdma_acquire_retry_exp_2_f() (0x100U) #define pbdma_acquire_retry_exp_2_f() (0x100U)
#define pbdma_acquire_timeout_exp_f(v) (((v)&0xfU) << 11U) #define pbdma_acquire_timeout_exp_f(v) ((U32(v) & 0xfU) << 11U)
#define pbdma_acquire_timeout_exp_max_v() (0x0000000fU) #define pbdma_acquire_timeout_exp_max_v() (0x0000000fU)
#define pbdma_acquire_timeout_exp_max_f() (0x7800U) #define pbdma_acquire_timeout_exp_max_f() (0x7800U)
#define pbdma_acquire_timeout_man_f(v) (((v)&0xffffU) << 15U) #define pbdma_acquire_timeout_man_f(v) ((U32(v) & 0xffffU) << 15U)
#define pbdma_acquire_timeout_man_max_v() (0x0000ffffU) #define pbdma_acquire_timeout_man_max_v() (0x0000ffffU)
#define pbdma_acquire_timeout_man_max_f() (0x7fff8000U) #define pbdma_acquire_timeout_man_max_f() (0x7fff8000U)
#define pbdma_acquire_timeout_en_enable_f() (0x80000000U) #define pbdma_acquire_timeout_en_enable_f() (0x80000000U)
@@ -164,10 +164,10 @@
#define pbdma_userd_target_vid_mem_f() (0x0U) #define pbdma_userd_target_vid_mem_f() (0x0U)
#define pbdma_userd_target_sys_mem_coh_f() (0x2U) #define pbdma_userd_target_sys_mem_coh_f() (0x2U)
#define pbdma_userd_target_sys_mem_ncoh_f() (0x3U) #define pbdma_userd_target_sys_mem_ncoh_f() (0x3U)
#define pbdma_userd_addr_f(v) (((v)&0x7fffffU) << 9U) #define pbdma_userd_addr_f(v) ((U32(v) & 0x7fffffU) << 9U)
#define pbdma_userd_hi_r(i)\ #define pbdma_userd_hi_r(i)\
(nvgpu_safe_add_u32(0x0004000cU, nvgpu_safe_mult_u32((i), 8192U))) (nvgpu_safe_add_u32(0x0004000cU, nvgpu_safe_mult_u32((i), 8192U)))
#define pbdma_userd_hi_addr_f(v) (((v)&0xffU) << 0U) #define pbdma_userd_hi_addr_f(v) ((U32(v) & 0xffU) << 0U)
#define pbdma_config_r(i)\ #define pbdma_config_r(i)\
(nvgpu_safe_add_u32(0x000400f4U, nvgpu_safe_mult_u32((i), 8192U))) (nvgpu_safe_add_u32(0x000400f4U, nvgpu_safe_mult_u32((i), 8192U)))
#define pbdma_config_auth_level_privileged_f() (0x100U) #define pbdma_config_auth_level_privileged_f() (0x100U)
@@ -224,11 +224,11 @@
#define pbdma_udma_nop_r() (0x00000008U) #define pbdma_udma_nop_r() (0x00000008U)
#define pbdma_allowed_syncpoints_r(i)\ #define pbdma_allowed_syncpoints_r(i)\
(nvgpu_safe_add_u32(0x000400e8U, nvgpu_safe_mult_u32((i), 8192U))) (nvgpu_safe_add_u32(0x000400e8U, nvgpu_safe_mult_u32((i), 8192U)))
#define pbdma_allowed_syncpoints_0_valid_f(v) (((v)&0x1U) << 31U) #define pbdma_allowed_syncpoints_0_valid_f(v) ((U32(v) & 0x1U) << 31U)
#define pbdma_allowed_syncpoints_0_index_f(v) (((v)&0x7fffU) << 16U) #define pbdma_allowed_syncpoints_0_index_f(v) ((U32(v) & 0x7fffU) << 16U)
#define pbdma_allowed_syncpoints_0_index_v(r) (((r) >> 16U) & 0x7fffU) #define pbdma_allowed_syncpoints_0_index_v(r) (((r) >> 16U) & 0x7fffU)
#define pbdma_allowed_syncpoints_1_valid_f(v) (((v)&0x1U) << 15U) #define pbdma_allowed_syncpoints_1_valid_f(v) ((U32(v) & 0x1U) << 15U)
#define pbdma_allowed_syncpoints_1_index_f(v) (((v)&0x7fffU) << 0U) #define pbdma_allowed_syncpoints_1_index_f(v) ((U32(v) & 0x7fffU) << 0U)
#define pbdma_syncpointa_r(i)\ #define pbdma_syncpointa_r(i)\
(nvgpu_safe_add_u32(0x000400a4U, nvgpu_safe_mult_u32((i), 8192U))) (nvgpu_safe_add_u32(0x000400a4U, nvgpu_safe_mult_u32((i), 8192U)))
#define pbdma_syncpointa_payload_v(r) (((r) >> 0U) & 0xffffffffU) #define pbdma_syncpointa_payload_v(r) (((r) >> 0U) & 0xffffffffU)

20
drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_perf_gp10b.h
View File

@@ -65,13 +65,13 @@
#define perf_pmasys_control_membuf_status_v(r) (((r) >> 4U) & 0x1U) #define perf_pmasys_control_membuf_status_v(r) (((r) >> 4U) & 0x1U)
#define perf_pmasys_control_membuf_status_overflowed_v() (0x00000001U) #define perf_pmasys_control_membuf_status_overflowed_v() (0x00000001U)
#define perf_pmasys_control_membuf_status_overflowed_f() (0x10U) #define perf_pmasys_control_membuf_status_overflowed_f() (0x10U)
#define perf_pmasys_control_membuf_clear_status_f(v) (((v)&0x1U) << 5U) #define perf_pmasys_control_membuf_clear_status_f(v) ((U32(v) & 0x1U) << 5U)
#define perf_pmasys_control_membuf_clear_status_v(r) (((r) >> 5U) & 0x1U) #define perf_pmasys_control_membuf_clear_status_v(r) (((r) >> 5U) & 0x1U)
#define perf_pmasys_control_membuf_clear_status_doit_v() (0x00000001U) #define perf_pmasys_control_membuf_clear_status_doit_v() (0x00000001U)
#define perf_pmasys_control_membuf_clear_status_doit_f() (0x20U) #define perf_pmasys_control_membuf_clear_status_doit_f() (0x20U)
#define perf_pmasys_mem_block_r() (0x001b4070U) #define perf_pmasys_mem_block_r() (0x001b4070U)
#define perf_pmasys_mem_block_base_f(v) (((v)&0xfffffffU) << 0U) #define perf_pmasys_mem_block_base_f(v) ((U32(v) & 0xfffffffU) << 0U)
#define perf_pmasys_mem_block_target_f(v) (((v)&0x3U) << 28U) #define perf_pmasys_mem_block_target_f(v) ((U32(v) & 0x3U) << 28U)
#define perf_pmasys_mem_block_target_v(r) (((r) >> 28U) & 0x3U) #define perf_pmasys_mem_block_target_v(r) (((r) >> 28U) & 0x3U)
#define perf_pmasys_mem_block_target_lfb_v() (0x00000000U) #define perf_pmasys_mem_block_target_lfb_v() (0x00000000U)
#define perf_pmasys_mem_block_target_lfb_f() (0x0U) #define perf_pmasys_mem_block_target_lfb_f() (0x0U)
@@ -79,24 +79,24 @@
#define perf_pmasys_mem_block_target_sys_coh_f() (0x20000000U) #define perf_pmasys_mem_block_target_sys_coh_f() (0x20000000U)
#define perf_pmasys_mem_block_target_sys_ncoh_v() (0x00000003U) #define perf_pmasys_mem_block_target_sys_ncoh_v() (0x00000003U)
#define perf_pmasys_mem_block_target_sys_ncoh_f() (0x30000000U) #define perf_pmasys_mem_block_target_sys_ncoh_f() (0x30000000U)
#define perf_pmasys_mem_block_valid_f(v) (((v)&0x1U) << 31U) #define perf_pmasys_mem_block_valid_f(v) ((U32(v) & 0x1U) << 31U)
#define perf_pmasys_mem_block_valid_v(r) (((r) >> 31U) & 0x1U) #define perf_pmasys_mem_block_valid_v(r) (((r) >> 31U) & 0x1U)
#define perf_pmasys_mem_block_valid_true_v() (0x00000001U) #define perf_pmasys_mem_block_valid_true_v() (0x00000001U)
#define perf_pmasys_mem_block_valid_true_f() (0x80000000U) #define perf_pmasys_mem_block_valid_true_f() (0x80000000U)
#define perf_pmasys_mem_block_valid_false_v() (0x00000000U) #define perf_pmasys_mem_block_valid_false_v() (0x00000000U)
#define perf_pmasys_mem_block_valid_false_f() (0x0U) #define perf_pmasys_mem_block_valid_false_f() (0x0U)
#define perf_pmasys_outbase_r() (0x001b4074U) #define perf_pmasys_outbase_r() (0x001b4074U)
#define perf_pmasys_outbase_ptr_f(v) (((v)&0x7ffffffU) << 5U) #define perf_pmasys_outbase_ptr_f(v) ((U32(v) & 0x7ffffffU) << 5U)
#define perf_pmasys_outbaseupper_r() (0x001b4078U) #define perf_pmasys_outbaseupper_r() (0x001b4078U)
#define perf_pmasys_outbaseupper_ptr_f(v) (((v)&0xffU) << 0U) #define perf_pmasys_outbaseupper_ptr_f(v) ((U32(v) & 0xffU) << 0U)
#define perf_pmasys_outsize_r() (0x001b407cU) #define perf_pmasys_outsize_r() (0x001b407cU)
#define perf_pmasys_outsize_numbytes_f(v) (((v)&0x7ffffffU) << 5U) #define perf_pmasys_outsize_numbytes_f(v) ((U32(v) & 0x7ffffffU) << 5U)
#define perf_pmasys_mem_bytes_r() (0x001b4084U) #define perf_pmasys_mem_bytes_r() (0x001b4084U)
#define perf_pmasys_mem_bytes_numbytes_f(v) (((v)&0xfffffffU) << 4U) #define perf_pmasys_mem_bytes_numbytes_f(v) ((U32(v) & 0xfffffffU) << 4U)
#define perf_pmasys_mem_bump_r() (0x001b4088U) #define perf_pmasys_mem_bump_r() (0x001b4088U)
#define perf_pmasys_mem_bump_numbytes_f(v) (((v)&0xfffffffU) << 4U) #define perf_pmasys_mem_bump_numbytes_f(v) ((U32(v) & 0xfffffffU) << 4U)
#define perf_pmasys_enginestatus_r() (0x001b40a4U) #define perf_pmasys_enginestatus_r() (0x001b40a4U)
#define perf_pmasys_enginestatus_rbufempty_f(v) (((v)&0x1U) << 4U) #define perf_pmasys_enginestatus_rbufempty_f(v) ((U32(v) & 0x1U) << 4U)
#define perf_pmasys_enginestatus_rbufempty_empty_v() (0x00000001U) #define perf_pmasys_enginestatus_rbufempty_empty_v() (0x00000001U)
#define perf_pmasys_enginestatus_rbufempty_empty_f() (0x10U) #define perf_pmasys_enginestatus_rbufempty_empty_f() (0x10U)
#endif #endif

136
drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_pwr_gp10b.h
View File

@@ -68,44 +68,44 @@
#define pwr_falcon_irqstat_swgen0_true_f() (0x40U) #define pwr_falcon_irqstat_swgen0_true_f() (0x40U)
#define pwr_falcon_irqmode_r() (0x0010a00cU) #define pwr_falcon_irqmode_r() (0x0010a00cU)
#define pwr_falcon_irqmset_r() (0x0010a010U) #define pwr_falcon_irqmset_r() (0x0010a010U)
#define pwr_falcon_irqmset_gptmr_f(v) (((v)&0x1U) << 0U) #define pwr_falcon_irqmset_gptmr_f(v) ((U32(v) & 0x1U) << 0U)
#define pwr_falcon_irqmset_wdtmr_f(v) (((v)&0x1U) << 1U) #define pwr_falcon_irqmset_wdtmr_f(v) ((U32(v) & 0x1U) << 1U)
#define pwr_falcon_irqmset_mthd_f(v) (((v)&0x1U) << 2U) #define pwr_falcon_irqmset_mthd_f(v) ((U32(v) & 0x1U) << 2U)
#define pwr_falcon_irqmset_ctxsw_f(v) (((v)&0x1U) << 3U) #define pwr_falcon_irqmset_ctxsw_f(v) ((U32(v) & 0x1U) << 3U)
#define pwr_falcon_irqmset_halt_f(v) (((v)&0x1U) << 4U) #define pwr_falcon_irqmset_halt_f(v) ((U32(v) & 0x1U) << 4U)
#define pwr_falcon_irqmset_exterr_f(v) (((v)&0x1U) << 5U) #define pwr_falcon_irqmset_exterr_f(v) ((U32(v) & 0x1U) << 5U)
#define pwr_falcon_irqmset_swgen0_f(v) (((v)&0x1U) << 6U) #define pwr_falcon_irqmset_swgen0_f(v) ((U32(v) & 0x1U) << 6U)
#define pwr_falcon_irqmset_swgen1_f(v) (((v)&0x1U) << 7U) #define pwr_falcon_irqmset_swgen1_f(v) ((U32(v) & 0x1U) << 7U)
#define pwr_falcon_irqmclr_r() (0x0010a014U) #define pwr_falcon_irqmclr_r() (0x0010a014U)
#define pwr_falcon_irqmclr_gptmr_f(v) (((v)&0x1U) << 0U) #define pwr_falcon_irqmclr_gptmr_f(v) ((U32(v) & 0x1U) << 0U)
#define pwr_falcon_irqmclr_wdtmr_f(v) (((v)&0x1U) << 1U) #define pwr_falcon_irqmclr_wdtmr_f(v) ((U32(v) & 0x1U) << 1U)
#define pwr_falcon_irqmclr_mthd_f(v) (((v)&0x1U) << 2U) #define pwr_falcon_irqmclr_mthd_f(v) ((U32(v) & 0x1U) << 2U)
#define pwr_falcon_irqmclr_ctxsw_f(v) (((v)&0x1U) << 3U) #define pwr_falcon_irqmclr_ctxsw_f(v) ((U32(v) & 0x1U) << 3U)
#define pwr_falcon_irqmclr_halt_f(v) (((v)&0x1U) << 4U) #define pwr_falcon_irqmclr_halt_f(v) ((U32(v) & 0x1U) << 4U)
#define pwr_falcon_irqmclr_exterr_f(v) (((v)&0x1U) << 5U) #define pwr_falcon_irqmclr_exterr_f(v) ((U32(v) & 0x1U) << 5U)
#define pwr_falcon_irqmclr_swgen0_f(v) (((v)&0x1U) << 6U) #define pwr_falcon_irqmclr_swgen0_f(v) ((U32(v) & 0x1U) << 6U)
#define pwr_falcon_irqmclr_swgen1_f(v) (((v)&0x1U) << 7U) #define pwr_falcon_irqmclr_swgen1_f(v) ((U32(v) & 0x1U) << 7U)
#define pwr_falcon_irqmclr_ext_f(v) (((v)&0xffU) << 8U) #define pwr_falcon_irqmclr_ext_f(v) ((U32(v) & 0xffU) << 8U)
#define pwr_falcon_irqmask_r() (0x0010a018U) #define pwr_falcon_irqmask_r() (0x0010a018U)
#define pwr_falcon_irqdest_r() (0x0010a01cU) #define pwr_falcon_irqdest_r() (0x0010a01cU)
#define pwr_falcon_irqdest_host_gptmr_f(v) (((v)&0x1U) << 0U) #define pwr_falcon_irqdest_host_gptmr_f(v) ((U32(v) & 0x1U) << 0U)
#define pwr_falcon_irqdest_host_wdtmr_f(v) (((v)&0x1U) << 1U) #define pwr_falcon_irqdest_host_wdtmr_f(v) ((U32(v) & 0x1U) << 1U)
#define pwr_falcon_irqdest_host_mthd_f(v) (((v)&0x1U) << 2U) #define pwr_falcon_irqdest_host_mthd_f(v) ((U32(v) & 0x1U) << 2U)
#define pwr_falcon_irqdest_host_ctxsw_f(v) (((v)&0x1U) << 3U) #define pwr_falcon_irqdest_host_ctxsw_f(v) ((U32(v) & 0x1U) << 3U)
#define pwr_falcon_irqdest_host_halt_f(v) (((v)&0x1U) << 4U) #define pwr_falcon_irqdest_host_halt_f(v) ((U32(v) & 0x1U) << 4U)
#define pwr_falcon_irqdest_host_exterr_f(v) (((v)&0x1U) << 5U) #define pwr_falcon_irqdest_host_exterr_f(v) ((U32(v) & 0x1U) << 5U)
#define pwr_falcon_irqdest_host_swgen0_f(v) (((v)&0x1U) << 6U) #define pwr_falcon_irqdest_host_swgen0_f(v) ((U32(v) & 0x1U) << 6U)
#define pwr_falcon_irqdest_host_swgen1_f(v) (((v)&0x1U) << 7U) #define pwr_falcon_irqdest_host_swgen1_f(v) ((U32(v) & 0x1U) << 7U)
#define pwr_falcon_irqdest_host_ext_f(v) (((v)&0xffU) << 8U) #define pwr_falcon_irqdest_host_ext_f(v) ((U32(v) & 0xffU) << 8U)
#define pwr_falcon_irqdest_target_gptmr_f(v) (((v)&0x1U) << 16U) #define pwr_falcon_irqdest_target_gptmr_f(v) ((U32(v) & 0x1U) << 16U)
#define pwr_falcon_irqdest_target_wdtmr_f(v) (((v)&0x1U) << 17U) #define pwr_falcon_irqdest_target_wdtmr_f(v) ((U32(v) & 0x1U) << 17U)
#define pwr_falcon_irqdest_target_mthd_f(v) (((v)&0x1U) << 18U) #define pwr_falcon_irqdest_target_mthd_f(v) ((U32(v) & 0x1U) << 18U)
#define pwr_falcon_irqdest_target_ctxsw_f(v) (((v)&0x1U) << 19U) #define pwr_falcon_irqdest_target_ctxsw_f(v) ((U32(v) & 0x1U) << 19U)
#define pwr_falcon_irqdest_target_halt_f(v) (((v)&0x1U) << 20U) #define pwr_falcon_irqdest_target_halt_f(v) ((U32(v) & 0x1U) << 20U)
#define pwr_falcon_irqdest_target_exterr_f(v) (((v)&0x1U) << 21U) #define pwr_falcon_irqdest_target_exterr_f(v) ((U32(v) & 0x1U) << 21U)
#define pwr_falcon_irqdest_target_swgen0_f(v) (((v)&0x1U) << 22U) #define pwr_falcon_irqdest_target_swgen0_f(v) ((U32(v) & 0x1U) << 22U)
#define pwr_falcon_irqdest_target_swgen1_f(v) (((v)&0x1U) << 23U) #define pwr_falcon_irqdest_target_swgen1_f(v) ((U32(v) & 0x1U) << 23U)
#define pwr_falcon_irqdest_target_ext_f(v) (((v)&0xffU) << 24U) #define pwr_falcon_irqdest_target_ext_f(v) ((U32(v) & 0xffU) << 24U)
#define pwr_falcon_curctx_r() (0x0010a050U) #define pwr_falcon_curctx_r() (0x0010a050U)
#define pwr_falcon_nxtctx_r() (0x0010a054U) #define pwr_falcon_nxtctx_r() (0x0010a054U)
#define pwr_falcon_mailbox0_r() (0x0010a040U) #define pwr_falcon_mailbox0_r() (0x0010a040U)
@@ -118,24 +118,24 @@
#define pwr_falcon_os_r() (0x0010a080U) #define pwr_falcon_os_r() (0x0010a080U)
#define pwr_falcon_engctl_r() (0x0010a0a4U) #define pwr_falcon_engctl_r() (0x0010a0a4U)
#define pwr_falcon_cpuctl_r() (0x0010a100U) #define pwr_falcon_cpuctl_r() (0x0010a100U)
#define pwr_falcon_cpuctl_startcpu_f(v) (((v)&0x1U) << 1U) #define pwr_falcon_cpuctl_startcpu_f(v) ((U32(v) & 0x1U) << 1U)
#define pwr_falcon_cpuctl_halt_intr_f(v) (((v)&0x1U) << 4U) #define pwr_falcon_cpuctl_halt_intr_f(v) ((U32(v) & 0x1U) << 4U)
#define pwr_falcon_cpuctl_halt_intr_m() (U32(0x1U) << 4U) #define pwr_falcon_cpuctl_halt_intr_m() (U32(0x1U) << 4U)
#define pwr_falcon_cpuctl_halt_intr_v(r) (((r) >> 4U) & 0x1U) #define pwr_falcon_cpuctl_halt_intr_v(r) (((r) >> 4U) & 0x1U)
#define pwr_falcon_cpuctl_cpuctl_alias_en_f(v) (((v)&0x1U) << 6U) #define pwr_falcon_cpuctl_cpuctl_alias_en_f(v) ((U32(v) & 0x1U) << 6U)
#define pwr_falcon_cpuctl_cpuctl_alias_en_m() (U32(0x1U) << 6U) #define pwr_falcon_cpuctl_cpuctl_alias_en_m() (U32(0x1U) << 6U)
#define pwr_falcon_cpuctl_cpuctl_alias_en_v(r) (((r) >> 6U) & 0x1U) #define pwr_falcon_cpuctl_cpuctl_alias_en_v(r) (((r) >> 6U) & 0x1U)
#define pwr_falcon_cpuctl_alias_r() (0x0010a130U) #define pwr_falcon_cpuctl_alias_r() (0x0010a130U)
#define pwr_falcon_cpuctl_alias_startcpu_f(v) (((v)&0x1U) << 1U) #define pwr_falcon_cpuctl_alias_startcpu_f(v) ((U32(v) & 0x1U) << 1U)
#define pwr_pmu_scpctl_stat_r() (0x0010ac08U) #define pwr_pmu_scpctl_stat_r() (0x0010ac08U)
#define pwr_pmu_scpctl_stat_debug_mode_f(v) (((v)&0x1U) << 20U) #define pwr_pmu_scpctl_stat_debug_mode_f(v) ((U32(v) & 0x1U) << 20U)
#define pwr_pmu_scpctl_stat_debug_mode_m() (U32(0x1U) << 20U) #define pwr_pmu_scpctl_stat_debug_mode_m() (U32(0x1U) << 20U)
#define pwr_pmu_scpctl_stat_debug_mode_v(r) (((r) >> 20U) & 0x1U) #define pwr_pmu_scpctl_stat_debug_mode_v(r) (((r) >> 20U) & 0x1U)
#define pwr_falcon_imemc_r(i)\ #define pwr_falcon_imemc_r(i)\
(nvgpu_safe_add_u32(0x0010a180U, nvgpu_safe_mult_u32((i), 16U))) (nvgpu_safe_add_u32(0x0010a180U, nvgpu_safe_mult_u32((i), 16U)))
#define pwr_falcon_imemc_offs_f(v) (((v)&0x3fU) << 2U) #define pwr_falcon_imemc_offs_f(v) ((U32(v) & 0x3fU) << 2U)
#define pwr_falcon_imemc_blk_f(v) (((v)&0xffU) << 8U) #define pwr_falcon_imemc_blk_f(v) ((U32(v) & 0xffU) << 8U)
#define pwr_falcon_imemc_aincw_f(v) (((v)&0x1U) << 24U) #define pwr_falcon_imemc_aincw_f(v) ((U32(v) & 0x1U) << 24U)
#define pwr_falcon_imemd_r(i)\ #define pwr_falcon_imemd_r(i)\
(nvgpu_safe_add_u32(0x0010a184U, nvgpu_safe_mult_u32((i), 16U))) (nvgpu_safe_add_u32(0x0010a184U, nvgpu_safe_mult_u32((i), 16U)))
#define pwr_falcon_imemt_r(i)\ #define pwr_falcon_imemt_r(i)\
@@ -143,7 +143,7 @@
#define pwr_falcon_sctl_r() (0x0010a240U) #define pwr_falcon_sctl_r() (0x0010a240U)
#define pwr_falcon_mmu_phys_sec_r() (0x00100ce4U) #define pwr_falcon_mmu_phys_sec_r() (0x00100ce4U)
#define pwr_falcon_bootvec_r() (0x0010a104U) #define pwr_falcon_bootvec_r() (0x0010a104U)
#define pwr_falcon_bootvec_vec_f(v) (((v)&0xffffffffU) << 0U) #define pwr_falcon_bootvec_vec_f(v) ((U32(v) & 0xffffffffU) << 0U)
#define pwr_falcon_dmactl_r() (0x0010a10cU) #define pwr_falcon_dmactl_r() (0x0010a10cU)
#define pwr_falcon_dmactl_dmem_scrubbing_m() (U32(0x1U) << 1U) #define pwr_falcon_dmactl_dmem_scrubbing_m() (U32(0x1U) << 1U)
#define pwr_falcon_dmactl_imem_scrubbing_m() (U32(0x1U) << 2U) #define pwr_falcon_dmactl_imem_scrubbing_m() (U32(0x1U) << 2U)
@@ -154,10 +154,10 @@
#define pwr_falcon_dmatrfbase1_r() (0x0010a128U) #define pwr_falcon_dmatrfbase1_r() (0x0010a128U)
#define pwr_falcon_dmatrfmoffs_r() (0x0010a114U) #define pwr_falcon_dmatrfmoffs_r() (0x0010a114U)
#define pwr_falcon_dmatrfcmd_r() (0x0010a118U) #define pwr_falcon_dmatrfcmd_r() (0x0010a118U)
#define pwr_falcon_dmatrfcmd_imem_f(v) (((v)&0x1U) << 4U) #define pwr_falcon_dmatrfcmd_imem_f(v) ((U32(v) & 0x1U) << 4U)
#define pwr_falcon_dmatrfcmd_write_f(v) (((v)&0x1U) << 5U) #define pwr_falcon_dmatrfcmd_write_f(v) ((U32(v) & 0x1U) << 5U)
#define pwr_falcon_dmatrfcmd_size_f(v) (((v)&0x7U) << 8U) #define pwr_falcon_dmatrfcmd_size_f(v) ((U32(v) & 0x7U) << 8U)
#define pwr_falcon_dmatrfcmd_ctxdma_f(v) (((v)&0x7U) << 12U) #define pwr_falcon_dmatrfcmd_ctxdma_f(v) ((U32(v) & 0x7U) << 12U)
#define pwr_falcon_dmatrffboffs_r() (0x0010a11cU) #define pwr_falcon_dmatrffboffs_r() (0x0010a11cU)
#define pwr_falcon_exterraddr_r() (0x0010a168U) #define pwr_falcon_exterraddr_r() (0x0010a168U)
#define pwr_falcon_exterrstat_r() (0x0010a16cU) #define pwr_falcon_exterrstat_r() (0x0010a16cU)
@@ -166,59 +166,59 @@
#define pwr_falcon_exterrstat_valid_true_v() (0x00000001U) #define pwr_falcon_exterrstat_valid_true_v() (0x00000001U)
#define pwr_pmu_falcon_icd_cmd_r() (0x0010a200U) #define pwr_pmu_falcon_icd_cmd_r() (0x0010a200U)
#define pwr_pmu_falcon_icd_cmd_opc_s() (4U) #define pwr_pmu_falcon_icd_cmd_opc_s() (4U)
#define pwr_pmu_falcon_icd_cmd_opc_f(v) (((v)&0xfU) << 0U) #define pwr_pmu_falcon_icd_cmd_opc_f(v) ((U32(v) & 0xfU) << 0U)
#define pwr_pmu_falcon_icd_cmd_opc_m() (U32(0xfU) << 0U) #define pwr_pmu_falcon_icd_cmd_opc_m() (U32(0xfU) << 0U)
#define pwr_pmu_falcon_icd_cmd_opc_v(r) (((r) >> 0U) & 0xfU) #define pwr_pmu_falcon_icd_cmd_opc_v(r) (((r) >> 0U) & 0xfU)
#define pwr_pmu_falcon_icd_cmd_opc_rreg_f() (0x8U) #define pwr_pmu_falcon_icd_cmd_opc_rreg_f() (0x8U)
#define pwr_pmu_falcon_icd_cmd_opc_rstat_f() (0xeU) #define pwr_pmu_falcon_icd_cmd_opc_rstat_f() (0xeU)
#define pwr_pmu_falcon_icd_cmd_idx_f(v) (((v)&0x1fU) << 8U) #define pwr_pmu_falcon_icd_cmd_idx_f(v) ((U32(v) & 0x1fU) << 8U)
#define pwr_pmu_falcon_icd_rdata_r() (0x0010a20cU) #define pwr_pmu_falcon_icd_rdata_r() (0x0010a20cU)
#define pwr_falcon_dmemc_r(i)\ #define pwr_falcon_dmemc_r(i)\
(nvgpu_safe_add_u32(0x0010a1c0U, nvgpu_safe_mult_u32((i), 8U))) (nvgpu_safe_add_u32(0x0010a1c0U, nvgpu_safe_mult_u32((i), 8U)))
#define pwr_falcon_dmemc_offs_f(v) (((v)&0x3fU) << 2U) #define pwr_falcon_dmemc_offs_f(v) ((U32(v) & 0x3fU) << 2U)
#define pwr_falcon_dmemc_offs_m() (U32(0x3fU) << 2U) #define pwr_falcon_dmemc_offs_m() (U32(0x3fU) << 2U)
#define pwr_falcon_dmemc_blk_f(v) (((v)&0xffU) << 8U) #define pwr_falcon_dmemc_blk_f(v) ((U32(v) & 0xffU) << 8U)
#define pwr_falcon_dmemc_blk_m() (U32(0xffU) << 8U) #define pwr_falcon_dmemc_blk_m() (U32(0xffU) << 8U)
#define pwr_falcon_dmemc_aincw_f(v) (((v)&0x1U) << 24U) #define pwr_falcon_dmemc_aincw_f(v) ((U32(v) & 0x1U) << 24U)
#define pwr_falcon_dmemc_aincr_f(v) (((v)&0x1U) << 25U) #define pwr_falcon_dmemc_aincr_f(v) ((U32(v) & 0x1U) << 25U)
#define pwr_falcon_dmemd_r(i)\ #define pwr_falcon_dmemd_r(i)\
(nvgpu_safe_add_u32(0x0010a1c4U, nvgpu_safe_mult_u32((i), 8U))) (nvgpu_safe_add_u32(0x0010a1c4U, nvgpu_safe_mult_u32((i), 8U)))
#define pwr_pmu_new_instblk_r() (0x0010a480U) #define pwr_pmu_new_instblk_r() (0x0010a480U)
#define pwr_pmu_new_instblk_ptr_f(v) (((v)&0xfffffffU) << 0U) #define pwr_pmu_new_instblk_ptr_f(v) ((U32(v) & 0xfffffffU) << 0U)
#define pwr_pmu_new_instblk_target_fb_f() (0x0U) #define pwr_pmu_new_instblk_target_fb_f() (0x0U)
#define pwr_pmu_new_instblk_target_sys_coh_f() (0x20000000U) #define pwr_pmu_new_instblk_target_sys_coh_f() (0x20000000U)
#define pwr_pmu_new_instblk_target_sys_ncoh_f() (0x30000000U) #define pwr_pmu_new_instblk_target_sys_ncoh_f() (0x30000000U)
#define pwr_pmu_new_instblk_valid_f(v) (((v)&0x1U) << 30U) #define pwr_pmu_new_instblk_valid_f(v) ((U32(v) & 0x1U) << 30U)
#define pwr_pmu_mutex_id_r() (0x0010a488U) #define pwr_pmu_mutex_id_r() (0x0010a488U)
#define pwr_pmu_mutex_id_value_v(r) (((r) >> 0U) & 0xffU) #define pwr_pmu_mutex_id_value_v(r) (((r) >> 0U) & 0xffU)
#define pwr_pmu_mutex_id_value_init_v() (0x00000000U) #define pwr_pmu_mutex_id_value_init_v() (0x00000000U)
#define pwr_pmu_mutex_id_value_not_avail_v() (0x000000ffU) #define pwr_pmu_mutex_id_value_not_avail_v() (0x000000ffU)
#define pwr_pmu_mutex_id_release_r() (0x0010a48cU) #define pwr_pmu_mutex_id_release_r() (0x0010a48cU)
#define pwr_pmu_mutex_id_release_value_f(v) (((v)&0xffU) << 0U) #define pwr_pmu_mutex_id_release_value_f(v) ((U32(v) & 0xffU) << 0U)
#define pwr_pmu_mutex_id_release_value_m() (U32(0xffU) << 0U) #define pwr_pmu_mutex_id_release_value_m() (U32(0xffU) << 0U)
#define pwr_pmu_mutex_id_release_value_init_v() (0x00000000U) #define pwr_pmu_mutex_id_release_value_init_v() (0x00000000U)
#define pwr_pmu_mutex_id_release_value_init_f() (0x0U) #define pwr_pmu_mutex_id_release_value_init_f() (0x0U)
#define pwr_pmu_mutex_r(i)\ #define pwr_pmu_mutex_r(i)\
(nvgpu_safe_add_u32(0x0010a580U, nvgpu_safe_mult_u32((i), 4U))) (nvgpu_safe_add_u32(0x0010a580U, nvgpu_safe_mult_u32((i), 4U)))
#define pwr_pmu_mutex__size_1_v() (0x00000010U) #define pwr_pmu_mutex__size_1_v() (0x00000010U)
#define pwr_pmu_mutex_value_f(v) (((v)&0xffU) << 0U) #define pwr_pmu_mutex_value_f(v) ((U32(v) & 0xffU) << 0U)
#define pwr_pmu_mutex_value_v(r) (((r) >> 0U) & 0xffU) #define pwr_pmu_mutex_value_v(r) (((r) >> 0U) & 0xffU)
#define pwr_pmu_mutex_value_initial_lock_f() (0x0U) #define pwr_pmu_mutex_value_initial_lock_f() (0x0U)
#define pwr_pmu_queue_head_r(i)\ #define pwr_pmu_queue_head_r(i)\
(nvgpu_safe_add_u32(0x0010a4a0U, nvgpu_safe_mult_u32((i), 4U))) (nvgpu_safe_add_u32(0x0010a4a0U, nvgpu_safe_mult_u32((i), 4U)))
#define pwr_pmu_queue_head__size_1_v() (0x00000004U) #define pwr_pmu_queue_head__size_1_v() (0x00000004U)
#define pwr_pmu_queue_head_address_f(v) (((v)&0xffffffffU) << 0U) #define pwr_pmu_queue_head_address_f(v) ((U32(v) & 0xffffffffU) << 0U)
#define pwr_pmu_queue_head_address_v(r) (((r) >> 0U) & 0xffffffffU) #define pwr_pmu_queue_head_address_v(r) (((r) >> 0U) & 0xffffffffU)
#define pwr_pmu_queue_tail_r(i)\ #define pwr_pmu_queue_tail_r(i)\
(nvgpu_safe_add_u32(0x0010a4b0U, nvgpu_safe_mult_u32((i), 4U))) (nvgpu_safe_add_u32(0x0010a4b0U, nvgpu_safe_mult_u32((i), 4U)))
#define pwr_pmu_queue_tail__size_1_v() (0x00000004U) #define pwr_pmu_queue_tail__size_1_v() (0x00000004U)
#define pwr_pmu_queue_tail_address_f(v) (((v)&0xffffffffU) << 0U) #define pwr_pmu_queue_tail_address_f(v) ((U32(v) & 0xffffffffU) << 0U)
#define pwr_pmu_queue_tail_address_v(r) (((r) >> 0U) & 0xffffffffU) #define pwr_pmu_queue_tail_address_v(r) (((r) >> 0U) & 0xffffffffU)
#define pwr_pmu_msgq_head_r() (0x0010a4c8U) #define pwr_pmu_msgq_head_r() (0x0010a4c8U)
#define pwr_pmu_msgq_head_val_f(v) (((v)&0xffffffffU) << 0U) #define pwr_pmu_msgq_head_val_f(v) ((U32(v) & 0xffffffffU) << 0U)
#define pwr_pmu_msgq_head_val_v(r) (((r) >> 0U) & 0xffffffffU) #define pwr_pmu_msgq_head_val_v(r) (((r) >> 0U) & 0xffffffffU)
#define pwr_pmu_msgq_tail_r() (0x0010a4ccU) #define pwr_pmu_msgq_tail_r() (0x0010a4ccU)
#define pwr_pmu_msgq_tail_val_f(v) (((v)&0xffffffffU) << 0U) #define pwr_pmu_msgq_tail_val_f(v) ((U32(v) & 0xffffffffU) << 0U)
#define pwr_pmu_msgq_tail_val_v(r) (((r) >> 0U) & 0xffffffffU) #define pwr_pmu_msgq_tail_val_v(r) (((r) >> 0U) & 0xffffffffU)
#define pwr_pmu_idle_mask_r(i)\ #define pwr_pmu_idle_mask_r(i)\
(nvgpu_safe_add_u32(0x0010a504U, nvgpu_safe_mult_u32((i), 16U))) (nvgpu_safe_add_u32(0x0010a504U, nvgpu_safe_mult_u32((i), 16U)))
@@ -226,9 +226,9 @@
#define pwr_pmu_idle_mask_ce_2_enabled_f() (0x200000U) #define pwr_pmu_idle_mask_ce_2_enabled_f() (0x200000U)
#define pwr_pmu_idle_count_r(i)\ #define pwr_pmu_idle_count_r(i)\
(nvgpu_safe_add_u32(0x0010a508U, nvgpu_safe_mult_u32((i), 16U))) (nvgpu_safe_add_u32(0x0010a508U, nvgpu_safe_mult_u32((i), 16U)))
#define pwr_pmu_idle_count_value_f(v) (((v)&0x7fffffffU) << 0U) #define pwr_pmu_idle_count_value_f(v) ((U32(v) & 0x7fffffffU) << 0U)
#define pwr_pmu_idle_count_value_v(r) (((r) >> 0U) & 0x7fffffffU) #define pwr_pmu_idle_count_value_v(r) (((r) >> 0U) & 0x7fffffffU)
#define pwr_pmu_idle_count_reset_f(v) (((v)&0x1U) << 31U) #define pwr_pmu_idle_count_reset_f(v) ((U32(v) & 0x1U) << 31U)
#define pwr_pmu_idle_ctrl_r(i)\ #define pwr_pmu_idle_ctrl_r(i)\
(nvgpu_safe_add_u32(0x0010a50cU, nvgpu_safe_mult_u32((i), 16U))) (nvgpu_safe_add_u32(0x0010a50cU, nvgpu_safe_mult_u32((i), 16U)))
#define pwr_pmu_idle_ctrl_value_m() (U32(0x3U) << 0U) #define pwr_pmu_idle_ctrl_value_m() (U32(0x3U) << 0U)
@@ -238,13 +238,13 @@
#define pwr_pmu_idle_ctrl_filter_disabled_f() (0x0U) #define pwr_pmu_idle_ctrl_filter_disabled_f() (0x0U)
#define pwr_pmu_idle_threshold_r(i)\ #define pwr_pmu_idle_threshold_r(i)\
(nvgpu_safe_add_u32(0x0010a8a0U, nvgpu_safe_mult_u32((i), 4U))) (nvgpu_safe_add_u32(0x0010a8a0U, nvgpu_safe_mult_u32((i), 4U)))
#define pwr_pmu_idle_threshold_value_f(v) (((v)&0x7fffffffU) << 0U) #define pwr_pmu_idle_threshold_value_f(v) ((U32(v) & 0x7fffffffU) << 0U)
#define pwr_pmu_idle_intr_r() (0x0010a9e8U) #define pwr_pmu_idle_intr_r() (0x0010a9e8U)
#define pwr_pmu_idle_intr_en_f(v) (((v)&0x1U) << 0U) #define pwr_pmu_idle_intr_en_f(v) ((U32(v) & 0x1U) << 0U)
#define pwr_pmu_idle_intr_en_disabled_v() (0x00000000U) #define pwr_pmu_idle_intr_en_disabled_v() (0x00000000U)
#define pwr_pmu_idle_intr_en_enabled_v() (0x00000001U) #define pwr_pmu_idle_intr_en_enabled_v() (0x00000001U)
#define pwr_pmu_idle_intr_status_r() (0x0010a9ecU) #define pwr_pmu_idle_intr_status_r() (0x0010a9ecU)
#define pwr_pmu_idle_intr_status_intr_f(v) (((v)&0x1U) << 0U) #define pwr_pmu_idle_intr_status_intr_f(v) ((U32(v) & 0x1U) << 0U)
#define pwr_pmu_idle_intr_status_intr_m() (U32(0x1U) << 0U) #define pwr_pmu_idle_intr_status_intr_m() (U32(0x1U) << 0U)
#define pwr_pmu_idle_intr_status_intr_v(r) (((r) >> 0U) & 0x1U) #define pwr_pmu_idle_intr_status_intr_v(r) (((r) >> 0U) & 0x1U)
#define pwr_pmu_idle_intr_status_intr_pending_v() (0x00000001U) #define pwr_pmu_idle_intr_status_intr_pending_v() (0x00000001U)
@@ -288,7 +288,7 @@
#define pwr_fbif_transcfg_target_coherent_sysmem_f() (0x1U) #define pwr_fbif_transcfg_target_coherent_sysmem_f() (0x1U)
#define pwr_fbif_transcfg_target_noncoherent_sysmem_f() (0x2U) #define pwr_fbif_transcfg_target_noncoherent_sysmem_f() (0x2U)
#define pwr_fbif_transcfg_mem_type_s() (1U) #define pwr_fbif_transcfg_mem_type_s() (1U)
#define pwr_fbif_transcfg_mem_type_f(v) (((v)&0x1U) << 2U) #define pwr_fbif_transcfg_mem_type_f(v) ((U32(v) & 0x1U) << 2U)
#define pwr_fbif_transcfg_mem_type_m() (U32(0x1U) << 2U) #define pwr_fbif_transcfg_mem_type_m() (U32(0x1U) << 2U)
#define pwr_fbif_transcfg_mem_type_v(r) (((r) >> 2U) & 0x1U) #define pwr_fbif_transcfg_mem_type_v(r) (((r) >> 2U) & 0x1U)
#define pwr_fbif_transcfg_mem_type_virtual_f() (0x0U) #define pwr_fbif_transcfg_mem_type_virtual_f() (0x0U)

36
drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_ram_gp10b.h
View File

@@ -61,38 +61,38 @@
#define ram_in_ramfc_s() (4096U) #define ram_in_ramfc_s() (4096U)
#define ram_in_ramfc_w() (0U) #define ram_in_ramfc_w() (0U)
#define ram_in_page_dir_base_target_f(v) (((v)&0x3U) << 0U) #define ram_in_page_dir_base_target_f(v) ((U32(v) & 0x3U) << 0U)
#define ram_in_page_dir_base_target_w() (128U) #define ram_in_page_dir_base_target_w() (128U)
#define ram_in_page_dir_base_target_vid_mem_f() (0x0U) #define ram_in_page_dir_base_target_vid_mem_f() (0x0U)
#define ram_in_page_dir_base_target_sys_mem_coh_f() (0x2U) #define ram_in_page_dir_base_target_sys_mem_coh_f() (0x2U)
#define ram_in_page_dir_base_target_sys_mem_ncoh_f() (0x3U) #define ram_in_page_dir_base_target_sys_mem_ncoh_f() (0x3U)
#define ram_in_page_dir_base_vol_w() (128U) #define ram_in_page_dir_base_vol_w() (128U)
#define ram_in_page_dir_base_vol_true_f() (0x4U) #define ram_in_page_dir_base_vol_true_f() (0x4U)
#define ram_in_page_dir_base_fault_replay_tex_f(v) (((v)&0x1U) << 4U) #define ram_in_page_dir_base_fault_replay_tex_f(v) ((U32(v) & 0x1U) << 4U)
#define ram_in_page_dir_base_fault_replay_tex_m() (U32(0x1U) << 4U) #define ram_in_page_dir_base_fault_replay_tex_m() (U32(0x1U) << 4U)
#define ram_in_page_dir_base_fault_replay_tex_w() (128U) #define ram_in_page_dir_base_fault_replay_tex_w() (128U)
#define ram_in_page_dir_base_fault_replay_tex_true_f() (0x10U) #define ram_in_page_dir_base_fault_replay_tex_true_f() (0x10U)
#define ram_in_page_dir_base_fault_replay_gcc_f(v) (((v)&0x1U) << 5U) #define ram_in_page_dir_base_fault_replay_gcc_f(v) ((U32(v) & 0x1U) << 5U)
#define ram_in_page_dir_base_fault_replay_gcc_m() (U32(0x1U) << 5U) #define ram_in_page_dir_base_fault_replay_gcc_m() (U32(0x1U) << 5U)
#define ram_in_page_dir_base_fault_replay_gcc_w() (128U) #define ram_in_page_dir_base_fault_replay_gcc_w() (128U)
#define ram_in_page_dir_base_fault_replay_gcc_true_f() (0x20U) #define ram_in_page_dir_base_fault_replay_gcc_true_f() (0x20U)
#define ram_in_use_ver2_pt_format_f(v) (((v)&0x1U) << 10U) #define ram_in_use_ver2_pt_format_f(v) ((U32(v) & 0x1U) << 10U)
#define ram_in_use_ver2_pt_format_m() (U32(0x1U) << 10U) #define ram_in_use_ver2_pt_format_m() (U32(0x1U) << 10U)
#define ram_in_use_ver2_pt_format_w() (128U) #define ram_in_use_ver2_pt_format_w() (128U)
#define ram_in_use_ver2_pt_format_true_f() (0x400U) #define ram_in_use_ver2_pt_format_true_f() (0x400U)
#define ram_in_use_ver2_pt_format_false_f() (0x0U) #define ram_in_use_ver2_pt_format_false_f() (0x0U)
#define ram_in_big_page_size_f(v) (((v)&0x1U) << 11U) #define ram_in_big_page_size_f(v) ((U32(v) & 0x1U) << 11U)
#define ram_in_big_page_size_m() (U32(0x1U) << 11U) #define ram_in_big_page_size_m() (U32(0x1U) << 11U)
#define ram_in_big_page_size_w() (128U) #define ram_in_big_page_size_w() (128U)
#define ram_in_big_page_size_128kb_f() (0x0U) #define ram_in_big_page_size_128kb_f() (0x0U)
#define ram_in_big_page_size_64kb_f() (0x800U) #define ram_in_big_page_size_64kb_f() (0x800U)
#define ram_in_page_dir_base_lo_f(v) (((v)&0xfffffU) << 12U) #define ram_in_page_dir_base_lo_f(v) ((U32(v) & 0xfffffU) << 12U)
#define ram_in_page_dir_base_lo_w() (128U) #define ram_in_page_dir_base_lo_w() (128U)
#define ram_in_page_dir_base_hi_f(v) (((v)&0xffU) << 0U) #define ram_in_page_dir_base_hi_f(v) ((U32(v) & 0xffU) << 0U)
#define ram_in_page_dir_base_hi_w() (129U) #define ram_in_page_dir_base_hi_w() (129U)
#define ram_in_adr_limit_lo_f(v) (((v)&0xfffffU) << 12U) #define ram_in_adr_limit_lo_f(v) ((U32(v) & 0xfffffU) << 12U)
#define ram_in_adr_limit_lo_w() (130U) #define ram_in_adr_limit_lo_w() (130U)
#define ram_in_adr_limit_hi_f(v) (((v)&0xffffffffU) << 0U) #define ram_in_adr_limit_hi_f(v) ((U32(v) & 0xffffffffU) << 0U)
#define ram_in_adr_limit_hi_w() (131U) #define ram_in_adr_limit_hi_w() (131U)
#define ram_in_engine_cs_w() (132U) #define ram_in_engine_cs_w() (132U)
#define ram_in_engine_cs_wfi_v() (0x00000000U) #define ram_in_engine_cs_wfi_v() (0x00000000U)
@@ -107,9 +107,9 @@
#define ram_in_gr_wfi_mode_physical_f() (0x0U) #define ram_in_gr_wfi_mode_physical_f() (0x0U)
#define ram_in_gr_wfi_mode_virtual_v() (0x00000001U) #define ram_in_gr_wfi_mode_virtual_v() (0x00000001U)
#define ram_in_gr_wfi_mode_virtual_f() (0x4U) #define ram_in_gr_wfi_mode_virtual_f() (0x4U)
#define ram_in_gr_wfi_ptr_lo_f(v) (((v)&0xfffffU) << 12U) #define ram_in_gr_wfi_ptr_lo_f(v) ((U32(v) & 0xfffffU) << 12U)
#define ram_in_gr_wfi_ptr_lo_w() (132U) #define ram_in_gr_wfi_ptr_lo_w() (132U)
#define ram_in_gr_wfi_ptr_hi_f(v) (((v)&0xffU) << 0U) #define ram_in_gr_wfi_ptr_hi_f(v) ((U32(v) & 0xffU) << 0U)
#define ram_in_gr_wfi_ptr_hi_w() (133U) #define ram_in_gr_wfi_ptr_hi_w() (133U)
#define ram_in_base_shift_v() (0x0000000cU) #define ram_in_base_shift_v() (0x0000000cU)
#define ram_in_alloc_size_v() (0x00001000U) #define ram_in_alloc_size_v() (0x00001000U)
@@ -145,7 +145,7 @@
#define ram_fc_target_w() (43U) #define ram_fc_target_w() (43U)
#define ram_fc_hce_ctrl_w() (57U) #define ram_fc_hce_ctrl_w() (57U)
#define ram_fc_chid_w() (58U) #define ram_fc_chid_w() (58U)
#define ram_fc_chid_id_f(v) (((v)&0xfffU) << 0U) #define ram_fc_chid_id_f(v) ((U32(v) & 0xfffU) << 0U)
#define ram_fc_chid_id_w() (0U) #define ram_fc_chid_id_w() (0U)
#define ram_fc_config_w() (61U) #define ram_fc_config_w() (61U)
#define ram_fc_runlist_timeslice_w() (62U) #define ram_fc_runlist_timeslice_w() (62U)
@@ -163,16 +163,16 @@
#define ram_userd_gp_top_level_get_w() (22U) #define ram_userd_gp_top_level_get_w() (22U)
#define ram_userd_gp_top_level_get_hi_w() (23U) #define ram_userd_gp_top_level_get_hi_w() (23U)
#define ram_rl_entry_size_v() (0x00000008U) #define ram_rl_entry_size_v() (0x00000008U)
#define ram_rl_entry_chid_f(v) (((v)&0xfffU) << 0U) #define ram_rl_entry_chid_f(v) ((U32(v) & 0xfffU) << 0U)
#define ram_rl_entry_id_f(v) (((v)&0xfffU) << 0U) #define ram_rl_entry_id_f(v) ((U32(v) & 0xfffU) << 0U)
#define ram_rl_entry_type_f(v) (((v)&0x1U) << 13U) #define ram_rl_entry_type_f(v) ((U32(v) & 0x1U) << 13U)
#define ram_rl_entry_type_chid_f() (0x0U) #define ram_rl_entry_type_chid_f() (0x0U)
#define ram_rl_entry_type_tsg_f() (0x2000U) #define ram_rl_entry_type_tsg_f() (0x2000U)
#define ram_rl_entry_timeslice_scale_f(v) (((v)&0xfU) << 14U) #define ram_rl_entry_timeslice_scale_f(v) ((U32(v) & 0xfU) << 14U)
#define ram_rl_entry_timeslice_scale_v(r) (((r) >> 14U) & 0xfU) #define ram_rl_entry_timeslice_scale_v(r) (((r) >> 14U) & 0xfU)
#define ram_rl_entry_timeslice_scale_3_f() (0xc000U) #define ram_rl_entry_timeslice_scale_3_f() (0xc000U)
#define ram_rl_entry_timeslice_timeout_f(v) (((v)&0xffU) << 18U) #define ram_rl_entry_timeslice_timeout_f(v) ((U32(v) & 0xffU) << 18U)
#define ram_rl_entry_timeslice_timeout_v(r) (((r) >> 18U) & 0xffU) #define ram_rl_entry_timeslice_timeout_v(r) (((r) >> 18U) & 0xffU)
#define ram_rl_entry_timeslice_timeout_128_f() (0x2000000U) #define ram_rl_entry_timeslice_timeout_128_f() (0x2000000U)
#define ram_rl_entry_tsg_length_f(v) (((v)&0x3fU) << 26U) #define ram_rl_entry_tsg_length_f(v) ((U32(v) & 0x3fU) << 26U)
#endif #endif

45
drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_therm_gp10b.h
View File

@@ -64,25 +64,25 @@
#define therm_use_a_ext_therm_1_enable_f() (0x2U) #define therm_use_a_ext_therm_1_enable_f() (0x2U)
#define therm_use_a_ext_therm_2_enable_f() (0x4U) #define therm_use_a_ext_therm_2_enable_f() (0x4U)
#define therm_evt_ext_therm_0_r() (0x00020700U) #define therm_evt_ext_therm_0_r() (0x00020700U)
#define therm_evt_ext_therm_0_slow_factor_f(v) (((v)&0x3fU) << 24U) #define therm_evt_ext_therm_0_slow_factor_f(v) ((U32(v) & 0x3fU) << 24U)
#define therm_evt_ext_therm_0_slow_factor_init_v() (0x00000001U) #define therm_evt_ext_therm_0_slow_factor_init_v() (0x00000001U)
#define therm_evt_ext_therm_0_mode_f(v) (((v)&0x3U) << 30U) #define therm_evt_ext_therm_0_mode_f(v) ((U32(v) & 0x3U) << 30U)
#define therm_evt_ext_therm_0_mode_normal_v() (0x00000000U) #define therm_evt_ext_therm_0_mode_normal_v() (0x00000000U)
#define therm_evt_ext_therm_0_mode_inverted_v() (0x00000001U) #define therm_evt_ext_therm_0_mode_inverted_v() (0x00000001U)
#define therm_evt_ext_therm_0_mode_forced_v() (0x00000002U) #define therm_evt_ext_therm_0_mode_forced_v() (0x00000002U)
#define therm_evt_ext_therm_0_mode_cleared_v() (0x00000003U) #define therm_evt_ext_therm_0_mode_cleared_v() (0x00000003U)
#define therm_evt_ext_therm_1_r() (0x00020704U) #define therm_evt_ext_therm_1_r() (0x00020704U)
#define therm_evt_ext_therm_1_slow_factor_f(v) (((v)&0x3fU) << 24U) #define therm_evt_ext_therm_1_slow_factor_f(v) ((U32(v) & 0x3fU) << 24U)
#define therm_evt_ext_therm_1_slow_factor_init_v() (0x00000002U) #define therm_evt_ext_therm_1_slow_factor_init_v() (0x00000002U)
#define therm_evt_ext_therm_1_mode_f(v) (((v)&0x3U) << 30U) #define therm_evt_ext_therm_1_mode_f(v) ((U32(v) & 0x3U) << 30U)
#define therm_evt_ext_therm_1_mode_normal_v() (0x00000000U) #define therm_evt_ext_therm_1_mode_normal_v() (0x00000000U)
#define therm_evt_ext_therm_1_mode_inverted_v() (0x00000001U) #define therm_evt_ext_therm_1_mode_inverted_v() (0x00000001U)
#define therm_evt_ext_therm_1_mode_forced_v() (0x00000002U) #define therm_evt_ext_therm_1_mode_forced_v() (0x00000002U)
#define therm_evt_ext_therm_1_mode_cleared_v() (0x00000003U) #define therm_evt_ext_therm_1_mode_cleared_v() (0x00000003U)
#define therm_evt_ext_therm_2_r() (0x00020708U) #define therm_evt_ext_therm_2_r() (0x00020708U)
#define therm_evt_ext_therm_2_slow_factor_f(v) (((v)&0x3fU) << 24U) #define therm_evt_ext_therm_2_slow_factor_f(v) ((U32(v) & 0x3fU) << 24U)
#define therm_evt_ext_therm_2_slow_factor_init_v() (0x00000003U) #define therm_evt_ext_therm_2_slow_factor_init_v() (0x00000003U)
#define therm_evt_ext_therm_2_mode_f(v) (((v)&0x3U) << 30U) #define therm_evt_ext_therm_2_mode_f(v) ((U32(v) & 0x3U) << 30U)
#define therm_evt_ext_therm_2_mode_normal_v() (0x00000000U) #define therm_evt_ext_therm_2_mode_normal_v() (0x00000000U)
#define therm_evt_ext_therm_2_mode_inverted_v() (0x00000001U) #define therm_evt_ext_therm_2_mode_inverted_v() (0x00000001U)
#define therm_evt_ext_therm_2_mode_forced_v() (0x00000002U) #define therm_evt_ext_therm_2_mode_forced_v() (0x00000002U)
@@ -90,8 +90,8 @@
#define therm_weight_1_r() (0x00020024U) #define therm_weight_1_r() (0x00020024U)
#define therm_config1_r() (0x00020050U) #define therm_config1_r() (0x00020050U)
#define therm_config2_r() (0x00020130U) #define therm_config2_r() (0x00020130U)
#define therm_config2_slowdown_factor_extended_f(v) (((v)&0x1U) << 24U) #define therm_config2_slowdown_factor_extended_f(v) ((U32(v) & 0x1U) << 24U)
#define therm_config2_grad_enable_f(v) (((v)&0x1U) << 31U) #define therm_config2_grad_enable_f(v) ((U32(v) & 0x1U) << 31U)
#define therm_gate_ctrl_r(i)\ #define therm_gate_ctrl_r(i)\
(nvgpu_safe_add_u32(0x00020200U, nvgpu_safe_mult_u32((i), 4U))) (nvgpu_safe_add_u32(0x00020200U, nvgpu_safe_mult_u32((i), 4U)))
#define therm_gate_ctrl_eng_clk_m() (U32(0x3U) << 0U) #define therm_gate_ctrl_eng_clk_m() (U32(0x3U) << 0U)
@@ -105,13 +105,13 @@
#define therm_gate_ctrl_eng_pwr_auto_f() (0x10U) #define therm_gate_ctrl_eng_pwr_auto_f() (0x10U)
#define therm_gate_ctrl_eng_pwr_off_v() (0x00000002U) #define therm_gate_ctrl_eng_pwr_off_v() (0x00000002U)
#define therm_gate_ctrl_eng_pwr_off_f() (0x20U) #define therm_gate_ctrl_eng_pwr_off_f() (0x20U)
#define therm_gate_ctrl_eng_idle_filt_exp_f(v) (((v)&0x1fU) << 8U) #define therm_gate_ctrl_eng_idle_filt_exp_f(v) ((U32(v) & 0x1fU) << 8U)
#define therm_gate_ctrl_eng_idle_filt_exp_m() (U32(0x1fU) << 8U) #define therm_gate_ctrl_eng_idle_filt_exp_m() (U32(0x1fU) << 8U)
#define therm_gate_ctrl_eng_idle_filt_mant_f(v) (((v)&0x7U) << 13U) #define therm_gate_ctrl_eng_idle_filt_mant_f(v) ((U32(v) & 0x7U) << 13U)
#define therm_gate_ctrl_eng_idle_filt_mant_m() (U32(0x7U) << 13U) #define therm_gate_ctrl_eng_idle_filt_mant_m() (U32(0x7U) << 13U)
#define therm_gate_ctrl_eng_delay_before_f(v) (((v)&0xfU) << 16U) #define therm_gate_ctrl_eng_delay_before_f(v) ((U32(v) & 0xfU) << 16U)
#define therm_gate_ctrl_eng_delay_before_m() (U32(0xfU) << 16U) #define therm_gate_ctrl_eng_delay_before_m() (U32(0xfU) << 16U)
#define therm_gate_ctrl_eng_delay_after_f(v) (((v)&0xfU) << 20U) #define therm_gate_ctrl_eng_delay_after_f(v) ((U32(v) & 0xfU) << 20U)
#define therm_gate_ctrl_eng_delay_after_m() (U32(0xfU) << 20U) #define therm_gate_ctrl_eng_delay_after_m() (U32(0xfU) << 20U)
#define therm_fecs_idle_filter_r() (0x00020288U) #define therm_fecs_idle_filter_r() (0x00020288U)
#define therm_fecs_idle_filter_value_m() (U32(0xffffffffU) << 0U) #define therm_fecs_idle_filter_value_m() (U32(0xffffffffU) << 0U)
@@ -119,37 +119,40 @@
#define therm_hubmmu_idle_filter_value_m() (U32(0xffffffffU) << 0U) #define therm_hubmmu_idle_filter_value_m() (U32(0xffffffffU) << 0U)
#define therm_clk_slowdown_r(i)\ #define therm_clk_slowdown_r(i)\
(nvgpu_safe_add_u32(0x00020160U, nvgpu_safe_mult_u32((i), 4U))) (nvgpu_safe_add_u32(0x00020160U, nvgpu_safe_mult_u32((i), 4U)))
#define therm_clk_slowdown_idle_factor_f(v) (((v)&0x3fU) << 16U) #define therm_clk_slowdown_idle_factor_f(v) ((U32(v) & 0x3fU) << 16U)
#define therm_clk_slowdown_idle_factor_m() (U32(0x3fU) << 16U) #define therm_clk_slowdown_idle_factor_m() (U32(0x3fU) << 16U)
#define therm_clk_slowdown_idle_factor_v(r) (((r) >> 16U) & 0x3fU) #define therm_clk_slowdown_idle_factor_v(r) (((r) >> 16U) & 0x3fU)
#define therm_clk_slowdown_idle_factor_disabled_f() (0x0U) #define therm_clk_slowdown_idle_factor_disabled_f() (0x0U)
#define therm_grad_stepping_table_r(i)\ #define therm_grad_stepping_table_r(i)\
(nvgpu_safe_add_u32(0x000202c8U, nvgpu_safe_mult_u32((i), 4U))) (nvgpu_safe_add_u32(0x000202c8U, nvgpu_safe_mult_u32((i), 4U)))
#define therm_grad_stepping_table_slowdown_factor0_f(v) (((v)&0x3fU) << 0U) #define therm_grad_stepping_table_slowdown_factor0_f(v) ((U32(v) & 0x3fU) << 0U)
#define therm_grad_stepping_table_slowdown_factor0_m() (U32(0x3fU) << 0U) #define therm_grad_stepping_table_slowdown_factor0_m() (U32(0x3fU) << 0U)
#define therm_grad_stepping_table_slowdown_factor0_fpdiv_by1p5_f() (0x1U) #define therm_grad_stepping_table_slowdown_factor0_fpdiv_by1p5_f() (0x1U)
#define therm_grad_stepping_table_slowdown_factor0_fpdiv_by2_f() (0x2U) #define therm_grad_stepping_table_slowdown_factor0_fpdiv_by2_f() (0x2U)
#define therm_grad_stepping_table_slowdown_factor0_fpdiv_by4_f() (0x6U) #define therm_grad_stepping_table_slowdown_factor0_fpdiv_by4_f() (0x6U)
#define therm_grad_stepping_table_slowdown_factor0_fpdiv_by8_f() (0xeU) #define therm_grad_stepping_table_slowdown_factor0_fpdiv_by8_f() (0xeU)
#define therm_grad_stepping_table_slowdown_factor1_f(v) (((v)&0x3fU) << 6U) #define therm_grad_stepping_table_slowdown_factor1_f(v) ((U32(v) & 0x3fU) << 6U)
#define therm_grad_stepping_table_slowdown_factor1_m() (U32(0x3fU) << 6U) #define therm_grad_stepping_table_slowdown_factor1_m() (U32(0x3fU) << 6U)
#define therm_grad_stepping_table_slowdown_factor2_f(v) (((v)&0x3fU) << 12U) #define therm_grad_stepping_table_slowdown_factor2_f(v)\
((U32(v) & 0x3fU) << 12U)
#define therm_grad_stepping_table_slowdown_factor2_m() (U32(0x3fU) << 12U) #define therm_grad_stepping_table_slowdown_factor2_m() (U32(0x3fU) << 12U)
#define therm_grad_stepping_table_slowdown_factor3_f(v) (((v)&0x3fU) << 18U) #define therm_grad_stepping_table_slowdown_factor3_f(v)\
((U32(v) & 0x3fU) << 18U)
#define therm_grad_stepping_table_slowdown_factor3_m() (U32(0x3fU) << 18U) #define therm_grad_stepping_table_slowdown_factor3_m() (U32(0x3fU) << 18U)
#define therm_grad_stepping_table_slowdown_factor4_f(v) (((v)&0x3fU) << 24U) #define therm_grad_stepping_table_slowdown_factor4_f(v)\
((U32(v) & 0x3fU) << 24U)
#define therm_grad_stepping_table_slowdown_factor4_m() (U32(0x3fU) << 24U) #define therm_grad_stepping_table_slowdown_factor4_m() (U32(0x3fU) << 24U)
#define therm_grad_stepping0_r() (0x000202c0U) #define therm_grad_stepping0_r() (0x000202c0U)
#define therm_grad_stepping0_feature_s() (1U) #define therm_grad_stepping0_feature_s() (1U)
#define therm_grad_stepping0_feature_f(v) (((v)&0x1U) << 0U) #define therm_grad_stepping0_feature_f(v) ((U32(v) & 0x1U) << 0U)
#define therm_grad_stepping0_feature_m() (U32(0x1U) << 0U) #define therm_grad_stepping0_feature_m() (U32(0x1U) << 0U)
#define therm_grad_stepping0_feature_v(r) (((r) >> 0U) & 0x1U) #define therm_grad_stepping0_feature_v(r) (((r) >> 0U) & 0x1U)
#define therm_grad_stepping0_feature_enable_f() (0x1U) #define therm_grad_stepping0_feature_enable_f() (0x1U)
#define therm_grad_stepping1_r() (0x000202c4U) #define therm_grad_stepping1_r() (0x000202c4U)
#define therm_grad_stepping1_pdiv_duration_f(v) (((v)&0x1ffffU) << 0U) #define therm_grad_stepping1_pdiv_duration_f(v) ((U32(v) & 0x1ffffU) << 0U)
#define therm_clk_timing_r(i)\ #define therm_clk_timing_r(i)\
(nvgpu_safe_add_u32(0x000203c0U, nvgpu_safe_mult_u32((i), 4U))) (nvgpu_safe_add_u32(0x000203c0U, nvgpu_safe_mult_u32((i), 4U)))
#define therm_clk_timing_grad_slowdown_f(v) (((v)&0x1U) << 16U) #define therm_clk_timing_grad_slowdown_f(v) ((U32(v) & 0x1U) << 16U)
#define therm_clk_timing_grad_slowdown_m() (U32(0x1U) << 16U) #define therm_clk_timing_grad_slowdown_m() (U32(0x1U) << 16U)
#define therm_clk_timing_grad_slowdown_enabled_f() (0x10000U) #define therm_clk_timing_grad_slowdown_enabled_f() (0x10000U)
#endif #endif

4
drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_timer_gp10b.h
View File

@@ -60,10 +60,10 @@
#include <nvgpu/safe_ops.h> #include <nvgpu/safe_ops.h>
#define timer_pri_timeout_r() (0x00009080U) #define timer_pri_timeout_r() (0x00009080U)
#define timer_pri_timeout_period_f(v) (((v)&0xffffffU) << 0U) #define timer_pri_timeout_period_f(v) ((U32(v) & 0xffffffU) << 0U)
#define timer_pri_timeout_period_m() (U32(0xffffffU) << 0U) #define timer_pri_timeout_period_m() (U32(0xffffffU) << 0U)
#define timer_pri_timeout_period_v(r) (((r) >> 0U) & 0xffffffU) #define timer_pri_timeout_period_v(r) (((r) >> 0U) & 0xffffffU)
#define timer_pri_timeout_en_f(v) (((v)&0x1U) << 31U) #define timer_pri_timeout_en_f(v) ((U32(v) & 0x1U) << 31U)
#define timer_pri_timeout_en_m() (U32(0x1U) << 31U) #define timer_pri_timeout_en_m() (U32(0x1U) << 31U)
#define timer_pri_timeout_en_v(r) (((r) >> 31U) & 0x1U) #define timer_pri_timeout_en_v(r) (((r) >> 31U) & 0x1U)
#define timer_pri_timeout_en_en_enabled_f() (0x80000000U) #define timer_pri_timeout_en_en_enabled_f() (0x80000000U)

6
drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_bus_gv100.h
View File

@@ -62,19 +62,19 @@
#define bus_sw_scratch_r(i)\ #define bus_sw_scratch_r(i)\
(nvgpu_safe_add_u32(0x00001580U, nvgpu_safe_mult_u32((i), 4U))) (nvgpu_safe_add_u32(0x00001580U, nvgpu_safe_mult_u32((i), 4U)))
#define bus_bar0_window_r() (0x00001700U) #define bus_bar0_window_r() (0x00001700U)
#define bus_bar0_window_base_f(v) (((v)&0xffffffU) << 0U) #define bus_bar0_window_base_f(v) ((U32(v) & 0xffffffU) << 0U)
#define bus_bar0_window_target_vid_mem_f() (0x0U) #define bus_bar0_window_target_vid_mem_f() (0x0U)
#define bus_bar0_window_target_sys_mem_coherent_f() (0x2000000U) #define bus_bar0_window_target_sys_mem_coherent_f() (0x2000000U)
#define bus_bar0_window_target_sys_mem_noncoherent_f() (0x3000000U) #define bus_bar0_window_target_sys_mem_noncoherent_f() (0x3000000U)
#define bus_bar0_window_target_bar0_window_base_shift_v() (0x00000010U) #define bus_bar0_window_target_bar0_window_base_shift_v() (0x00000010U)
#define bus_bar1_block_r() (0x00001704U) #define bus_bar1_block_r() (0x00001704U)
#define bus_bar1_block_ptr_f(v) (((v)&0xfffffffU) << 0U) #define bus_bar1_block_ptr_f(v) ((U32(v) & 0xfffffffU) << 0U)
#define bus_bar1_block_target_vid_mem_f() (0x0U) #define bus_bar1_block_target_vid_mem_f() (0x0U)
#define bus_bar1_block_target_sys_mem_coh_f() (0x20000000U) #define bus_bar1_block_target_sys_mem_coh_f() (0x20000000U)
#define bus_bar1_block_target_sys_mem_ncoh_f() (0x30000000U) #define bus_bar1_block_target_sys_mem_ncoh_f() (0x30000000U)
#define bus_bar1_block_mode_virtual_f() (0x80000000U) #define bus_bar1_block_mode_virtual_f() (0x80000000U)
#define bus_bar2_block_r() (0x00001714U) #define bus_bar2_block_r() (0x00001714U)
#define bus_bar2_block_ptr_f(v) (((v)&0xfffffffU) << 0U) #define bus_bar2_block_ptr_f(v) ((U32(v) & 0xfffffffU) << 0U)
#define bus_bar2_block_target_vid_mem_f() (0x0U) #define bus_bar2_block_target_vid_mem_f() (0x0U)
#define bus_bar2_block_target_sys_mem_coh_f() (0x20000000U) #define bus_bar2_block_target_sys_mem_coh_f() (0x20000000U)
#define bus_bar2_block_target_sys_mem_ncoh_f() (0x30000000U) #define bus_bar2_block_target_sys_mem_ncoh_f() (0x30000000U)

8
drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_ccsr_gv100.h
View File

@@ -62,7 +62,7 @@
#define ccsr_channel_inst_r(i)\ #define ccsr_channel_inst_r(i)\
(nvgpu_safe_add_u32(0x00800000U, nvgpu_safe_mult_u32((i), 8U))) (nvgpu_safe_add_u32(0x00800000U, nvgpu_safe_mult_u32((i), 8U)))
#define ccsr_channel_inst__size_1_v() (0x00001000U) #define ccsr_channel_inst__size_1_v() (0x00001000U)
#define ccsr_channel_inst_ptr_f(v) (((v)&0xfffffffU) << 0U) #define ccsr_channel_inst_ptr_f(v) ((U32(v) & 0xfffffffU) << 0U)
#define ccsr_channel_inst_target_vid_mem_f() (0x0U) #define ccsr_channel_inst_target_vid_mem_f() (0x0U)
#define ccsr_channel_inst_target_sys_mem_coh_f() (0x20000000U) #define ccsr_channel_inst_target_sys_mem_coh_f() (0x20000000U)
#define ccsr_channel_inst_target_sys_mem_ncoh_f() (0x30000000U) #define ccsr_channel_inst_target_sys_mem_ncoh_f() (0x30000000U)
@@ -73,7 +73,7 @@
#define ccsr_channel__size_1_v() (0x00001000U) #define ccsr_channel__size_1_v() (0x00001000U)
#define ccsr_channel_enable_v(r) (((r) >> 0U) & 0x1U) #define ccsr_channel_enable_v(r) (((r) >> 0U) & 0x1U)
#define ccsr_channel_enable_in_use_v() (0x00000001U) #define ccsr_channel_enable_in_use_v() (0x00000001U)
#define ccsr_channel_enable_set_f(v) (((v)&0x1U) << 10U) #define ccsr_channel_enable_set_f(v) ((U32(v) & 0x1U) << 10U)
#define ccsr_channel_enable_set_true_f() (0x400U) #define ccsr_channel_enable_set_true_f() (0x400U)
#define ccsr_channel_enable_clr_true_f() (0x800U) #define ccsr_channel_enable_clr_true_f() (0x800U)
#define ccsr_channel_status_v(r) (((r) >> 24U) & 0xfU) #define ccsr_channel_status_v(r) (((r) >> 24U) & 0xfU)
@@ -95,9 +95,9 @@
#define ccsr_channel_next_v(r) (((r) >> 1U) & 0x1U) #define ccsr_channel_next_v(r) (((r) >> 1U) & 0x1U)
#define ccsr_channel_next_true_v() (0x00000001U) #define ccsr_channel_next_true_v() (0x00000001U)
#define ccsr_channel_force_ctx_reload_true_f() (0x100U) #define ccsr_channel_force_ctx_reload_true_f() (0x100U)
#define ccsr_channel_pbdma_faulted_f(v) (((v)&0x1U) << 22U) #define ccsr_channel_pbdma_faulted_f(v) ((U32(v) & 0x1U) << 22U)
#define ccsr_channel_pbdma_faulted_reset_f() (0x400000U) #define ccsr_channel_pbdma_faulted_reset_f() (0x400000U)
#define ccsr_channel_eng_faulted_f(v) (((v)&0x1U) << 23U) #define ccsr_channel_eng_faulted_f(v) ((U32(v) & 0x1U) << 23U)
#define ccsr_channel_eng_faulted_v(r) (((r) >> 23U) & 0x1U) #define ccsr_channel_eng_faulted_v(r) (((r) >> 23U) & 0x1U)
#define ccsr_channel_eng_faulted_reset_f() (0x800000U) #define ccsr_channel_eng_faulted_reset_f() (0x800000U)
#define ccsr_channel_eng_faulted_true_v() (0x00000001U) #define ccsr_channel_eng_faulted_true_v() (0x00000001U)

42
drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_ctxsw_prog_gv100.h
View File

@@ -63,7 +63,7 @@
#define ctxsw_prog_gpccs_header_stride_v() (0x00000100U) #define ctxsw_prog_gpccs_header_stride_v() (0x00000100U)
#define ctxsw_prog_main_image_num_gpcs_o() (0x00000008U) #define ctxsw_prog_main_image_num_gpcs_o() (0x00000008U)
#define ctxsw_prog_main_image_ctl_o() (0x0000000cU) #define ctxsw_prog_main_image_ctl_o() (0x0000000cU)
#define ctxsw_prog_main_image_ctl_type_f(v) (((v)&0x3fU) << 0U) #define ctxsw_prog_main_image_ctl_type_f(v) ((U32(v) & 0x3fU) << 0U)
#define ctxsw_prog_main_image_ctl_type_undefined_v() (0x00000000U) #define ctxsw_prog_main_image_ctl_type_undefined_v() (0x00000000U)
#define ctxsw_prog_main_image_ctl_type_opengl_v() (0x00000008U) #define ctxsw_prog_main_image_ctl_type_opengl_v() (0x00000008U)
#define ctxsw_prog_main_image_ctl_type_dx9_v() (0x00000010U) #define ctxsw_prog_main_image_ctl_type_dx9_v() (0x00000010U)
@@ -95,50 +95,54 @@
#define ctxsw_prog_main_image_num_cilp_save_ops_o() (0x000000dcU) #define ctxsw_prog_main_image_num_cilp_save_ops_o() (0x000000dcU)
#define ctxsw_prog_main_image_num_restore_ops_o() (0x000000f8U) #define ctxsw_prog_main_image_num_restore_ops_o() (0x000000f8U)
#define ctxsw_prog_main_image_zcull_ptr_hi_o() (0x00000060U) #define ctxsw_prog_main_image_zcull_ptr_hi_o() (0x00000060U)
#define ctxsw_prog_main_image_zcull_ptr_hi_v_f(v) (((v)&0x1ffffU) << 0U) #define ctxsw_prog_main_image_zcull_ptr_hi_v_f(v) ((U32(v) & 0x1ffffU) << 0U)
#define ctxsw_prog_main_image_pm_ptr_hi_o() (0x00000094U) #define ctxsw_prog_main_image_pm_ptr_hi_o() (0x00000094U)
#define ctxsw_prog_main_image_full_preemption_ptr_hi_o() (0x00000064U) #define ctxsw_prog_main_image_full_preemption_ptr_hi_o() (0x00000064U)
#define ctxsw_prog_main_image_full_preemption_ptr_hi_v_f(v)\ #define ctxsw_prog_main_image_full_preemption_ptr_hi_v_f(v)\
(((v)&0x1ffffU) << 0U) ((U32(v) & 0x1ffffU) << 0U)
#define ctxsw_prog_main_image_full_preemption_ptr_o() (0x00000068U) #define ctxsw_prog_main_image_full_preemption_ptr_o() (0x00000068U)
#define ctxsw_prog_main_image_full_preemption_ptr_v_f(v)\ #define ctxsw_prog_main_image_full_preemption_ptr_v_f(v)\
(((v)&0xffffffffU) << 0U) ((U32(v) & 0xffffffffU) << 0U)
#define ctxsw_prog_main_image_full_preemption_ptr_veid0_hi_o() (0x00000070U) #define ctxsw_prog_main_image_full_preemption_ptr_veid0_hi_o() (0x00000070U)
#define ctxsw_prog_main_image_full_preemption_ptr_veid0_hi_v_f(v)\ #define ctxsw_prog_main_image_full_preemption_ptr_veid0_hi_v_f(v)\
(((v)&0x1ffffU) << 0U) ((U32(v) & 0x1ffffU) << 0U)
#define ctxsw_prog_main_image_full_preemption_ptr_veid0_o() (0x00000074U) #define ctxsw_prog_main_image_full_preemption_ptr_veid0_o() (0x00000074U)
#define ctxsw_prog_main_image_full_preemption_ptr_veid0_v_f(v)\ #define ctxsw_prog_main_image_full_preemption_ptr_veid0_v_f(v)\
(((v)&0xffffffffU) << 0U) ((U32(v) & 0xffffffffU) << 0U)
#define ctxsw_prog_main_image_context_buffer_ptr_hi_o() (0x00000078U) #define ctxsw_prog_main_image_context_buffer_ptr_hi_o() (0x00000078U)
#define ctxsw_prog_main_image_context_buffer_ptr_hi_v_f(v)\ #define ctxsw_prog_main_image_context_buffer_ptr_hi_v_f(v)\
(((v)&0x1ffffU) << 0U) ((U32(v) & 0x1ffffU) << 0U)
#define ctxsw_prog_main_image_context_buffer_ptr_o() (0x0000007cU) #define ctxsw_prog_main_image_context_buffer_ptr_o() (0x0000007cU)
#define ctxsw_prog_main_image_context_buffer_ptr_v_f(v)\ #define ctxsw_prog_main_image_context_buffer_ptr_v_f(v)\
(((v)&0xffffffffU) << 0U) ((U32(v) & 0xffffffffU) << 0U)
#define ctxsw_prog_main_image_magic_value_o() (0x000000fcU) #define ctxsw_prog_main_image_magic_value_o() (0x000000fcU)
#define ctxsw_prog_main_image_magic_value_v_value_v() (0x600dc0deU) #define ctxsw_prog_main_image_magic_value_v_value_v() (0x600dc0deU)
#define ctxsw_prog_local_priv_register_ctl_o() (0x0000000cU) #define ctxsw_prog_local_priv_register_ctl_o() (0x0000000cU)
#define ctxsw_prog_local_priv_register_ctl_offset_v(r) (((r) >> 0U) & 0xffffU) #define ctxsw_prog_local_priv_register_ctl_offset_v(r) (((r) >> 0U) & 0xffffU)
#define ctxsw_prog_main_image_global_cb_ptr_o() (0x000000b8U) #define ctxsw_prog_main_image_global_cb_ptr_o() (0x000000b8U)
#define ctxsw_prog_main_image_global_cb_ptr_v_f(v) (((v)&0xffffffffU) << 0U) #define ctxsw_prog_main_image_global_cb_ptr_v_f(v)\
((U32(v) & 0xffffffffU) << 0U)
#define ctxsw_prog_main_image_global_cb_ptr_hi_o() (0x000000bcU) #define ctxsw_prog_main_image_global_cb_ptr_hi_o() (0x000000bcU)
#define ctxsw_prog_main_image_global_cb_ptr_hi_v_f(v) (((v)&0x1ffffU) << 0U) #define ctxsw_prog_main_image_global_cb_ptr_hi_v_f(v)\
((U32(v) & 0x1ffffU) << 0U)
#define ctxsw_prog_main_image_global_pagepool_ptr_o() (0x000000c0U) #define ctxsw_prog_main_image_global_pagepool_ptr_o() (0x000000c0U)
#define ctxsw_prog_main_image_global_pagepool_ptr_v_f(v)\ #define ctxsw_prog_main_image_global_pagepool_ptr_v_f(v)\
(((v)&0xffffffffU) << 0U) ((U32(v) & 0xffffffffU) << 0U)
#define ctxsw_prog_main_image_global_pagepool_ptr_hi_o() (0x000000c4U) #define ctxsw_prog_main_image_global_pagepool_ptr_hi_o() (0x000000c4U)
#define ctxsw_prog_main_image_global_pagepool_ptr_hi_v_f(v)\ #define ctxsw_prog_main_image_global_pagepool_ptr_hi_v_f(v)\
(((v)&0x1ffffU) << 0U) ((U32(v) & 0x1ffffU) << 0U)
#define ctxsw_prog_main_image_control_block_ptr_o() (0x000000c8U) #define ctxsw_prog_main_image_control_block_ptr_o() (0x000000c8U)
#define ctxsw_prog_main_image_control_block_ptr_v_f(v) (((v)&0xffffffffU) << 0U) #define ctxsw_prog_main_image_control_block_ptr_v_f(v)\
((U32(v) & 0xffffffffU) << 0U)
#define ctxsw_prog_main_image_control_block_ptr_hi_o() (0x000000ccU) #define ctxsw_prog_main_image_control_block_ptr_hi_o() (0x000000ccU)
#define ctxsw_prog_main_image_control_block_ptr_hi_v_f(v) (((v)&0x1ffffU) << 0U) #define ctxsw_prog_main_image_control_block_ptr_hi_v_f(v)\
((U32(v) & 0x1ffffU) << 0U)
#define ctxsw_prog_main_image_context_ramchain_buffer_addr_lo_o() (0x000000e0U) #define ctxsw_prog_main_image_context_ramchain_buffer_addr_lo_o() (0x000000e0U)
#define ctxsw_prog_main_image_context_ramchain_buffer_addr_lo_v_f(v)\ #define ctxsw_prog_main_image_context_ramchain_buffer_addr_lo_v_f(v)\
(((v)&0xffffffffU) << 0U) ((U32(v) & 0xffffffffU) << 0U)
#define ctxsw_prog_main_image_context_ramchain_buffer_addr_hi_o() (0x000000e4U) #define ctxsw_prog_main_image_context_ramchain_buffer_addr_hi_o() (0x000000e4U)
#define ctxsw_prog_main_image_context_ramchain_buffer_addr_hi_v_f(v)\ #define ctxsw_prog_main_image_context_ramchain_buffer_addr_hi_v_f(v)\
(((v)&0x1ffffU) << 0U) ((U32(v) & 0x1ffffU) << 0U)
#define ctxsw_prog_local_image_ppc_info_o() (0x000000f4U) #define ctxsw_prog_local_image_ppc_info_o() (0x000000f4U)
#define ctxsw_prog_local_image_ppc_info_num_ppcs_v(r) (((r) >> 0U) & 0xffffU) #define ctxsw_prog_local_image_ppc_info_num_ppcs_v(r) (((r) >> 0U) & 0xffffU)
#define ctxsw_prog_local_image_ppc_info_ppc_mask_v(r) (((r) >> 16U) & 0xffffU) #define ctxsw_prog_local_image_ppc_info_ppc_mask_v(r) (((r) >> 16U) & 0xffffU)
@@ -157,7 +161,7 @@
#define ctxsw_prog_main_image_priv_access_map_config_o() (0x000000a0U) #define ctxsw_prog_main_image_priv_access_map_config_o() (0x000000a0U)
#define ctxsw_prog_main_image_priv_access_map_config_mode_s() (2U) #define ctxsw_prog_main_image_priv_access_map_config_mode_s() (2U)
#define ctxsw_prog_main_image_priv_access_map_config_mode_f(v)\ #define ctxsw_prog_main_image_priv_access_map_config_mode_f(v)\
(((v)&0x3U) << 0U) ((U32(v) & 0x3U) << 0U)
#define ctxsw_prog_main_image_priv_access_map_config_mode_m() (U32(0x3U) << 0U) #define ctxsw_prog_main_image_priv_access_map_config_mode_m() (U32(0x3U) << 0U)
#define ctxsw_prog_main_image_priv_access_map_config_mode_v(r)\ #define ctxsw_prog_main_image_priv_access_map_config_mode_v(r)\
(((r) >> 0U) & 0x3U) (((r) >> 0U) & 0x3U)
@@ -170,12 +174,12 @@
#define ctxsw_prog_main_image_misc_options_verif_features_disabled_f() (0x0U) #define ctxsw_prog_main_image_misc_options_verif_features_disabled_f() (0x0U)
#define ctxsw_prog_main_image_graphics_preemption_options_o() (0x00000080U) #define ctxsw_prog_main_image_graphics_preemption_options_o() (0x00000080U)
#define ctxsw_prog_main_image_graphics_preemption_options_control_f(v)\ #define ctxsw_prog_main_image_graphics_preemption_options_control_f(v)\
(((v)&0x3U) << 0U) ((U32(v) & 0x3U) << 0U)
#define ctxsw_prog_main_image_graphics_preemption_options_control_gfxp_f()\ #define ctxsw_prog_main_image_graphics_preemption_options_control_gfxp_f()\
(0x1U) (0x1U)
#define ctxsw_prog_main_image_compute_preemption_options_o() (0x00000084U) #define ctxsw_prog_main_image_compute_preemption_options_o() (0x00000084U)
#define ctxsw_prog_main_image_compute_preemption_options_control_f(v)\ #define ctxsw_prog_main_image_compute_preemption_options_control_f(v)\
(((v)&0x3U) << 0U) ((U32(v) & 0x3U) << 0U)
#define ctxsw_prog_main_image_compute_preemption_options_control_cta_f() (0x1U) #define ctxsw_prog_main_image_compute_preemption_options_control_cta_f() (0x1U)
#define ctxsw_prog_main_image_compute_preemption_options_control_cilp_f() (0x2U) #define ctxsw_prog_main_image_compute_preemption_options_control_cilp_f() (0x2U)
#endif #endif

122
drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_falcon_gv100.h
View File

@@ -68,44 +68,44 @@
#define falcon_falcon_irqstat_swgen0_true_f() (0x40U) #define falcon_falcon_irqstat_swgen0_true_f() (0x40U)
#define falcon_falcon_irqmode_r() (0x0000000cU) #define falcon_falcon_irqmode_r() (0x0000000cU)
#define falcon_falcon_irqmset_r() (0x00000010U) #define falcon_falcon_irqmset_r() (0x00000010U)
#define falcon_falcon_irqmset_gptmr_f(v) (((v)&0x1U) << 0U) #define falcon_falcon_irqmset_gptmr_f(v) ((U32(v) & 0x1U) << 0U)
#define falcon_falcon_irqmset_wdtmr_f(v) (((v)&0x1U) << 1U) #define falcon_falcon_irqmset_wdtmr_f(v) ((U32(v) & 0x1U) << 1U)
#define falcon_falcon_irqmset_mthd_f(v) (((v)&0x1U) << 2U) #define falcon_falcon_irqmset_mthd_f(v) ((U32(v) & 0x1U) << 2U)
#define falcon_falcon_irqmset_ctxsw_f(v) (((v)&0x1U) << 3U) #define falcon_falcon_irqmset_ctxsw_f(v) ((U32(v) & 0x1U) << 3U)
#define falcon_falcon_irqmset_halt_f(v) (((v)&0x1U) << 4U) #define falcon_falcon_irqmset_halt_f(v) ((U32(v) & 0x1U) << 4U)
#define falcon_falcon_irqmset_exterr_f(v) (((v)&0x1U) << 5U) #define falcon_falcon_irqmset_exterr_f(v) ((U32(v) & 0x1U) << 5U)
#define falcon_falcon_irqmset_swgen0_f(v) (((v)&0x1U) << 6U) #define falcon_falcon_irqmset_swgen0_f(v) ((U32(v) & 0x1U) << 6U)
#define falcon_falcon_irqmset_swgen1_f(v) (((v)&0x1U) << 7U) #define falcon_falcon_irqmset_swgen1_f(v) ((U32(v) & 0x1U) << 7U)
#define falcon_falcon_irqmclr_r() (0x00000014U) #define falcon_falcon_irqmclr_r() (0x00000014U)
#define falcon_falcon_irqmclr_gptmr_f(v) (((v)&0x1U) << 0U) #define falcon_falcon_irqmclr_gptmr_f(v) ((U32(v) & 0x1U) << 0U)
#define falcon_falcon_irqmclr_wdtmr_f(v) (((v)&0x1U) << 1U) #define falcon_falcon_irqmclr_wdtmr_f(v) ((U32(v) & 0x1U) << 1U)
#define falcon_falcon_irqmclr_mthd_f(v) (((v)&0x1U) << 2U) #define falcon_falcon_irqmclr_mthd_f(v) ((U32(v) & 0x1U) << 2U)
#define falcon_falcon_irqmclr_ctxsw_f(v) (((v)&0x1U) << 3U) #define falcon_falcon_irqmclr_ctxsw_f(v) ((U32(v) & 0x1U) << 3U)
#define falcon_falcon_irqmclr_halt_f(v) (((v)&0x1U) << 4U) #define falcon_falcon_irqmclr_halt_f(v) ((U32(v) & 0x1U) << 4U)
#define falcon_falcon_irqmclr_exterr_f(v) (((v)&0x1U) << 5U) #define falcon_falcon_irqmclr_exterr_f(v) ((U32(v) & 0x1U) << 5U)
#define falcon_falcon_irqmclr_swgen0_f(v) (((v)&0x1U) << 6U) #define falcon_falcon_irqmclr_swgen0_f(v) ((U32(v) & 0x1U) << 6U)
#define falcon_falcon_irqmclr_swgen1_f(v) (((v)&0x1U) << 7U) #define falcon_falcon_irqmclr_swgen1_f(v) ((U32(v) & 0x1U) << 7U)
#define falcon_falcon_irqmclr_ext_f(v) (((v)&0xffU) << 8U) #define falcon_falcon_irqmclr_ext_f(v) ((U32(v) & 0xffU) << 8U)
#define falcon_falcon_irqmask_r() (0x00000018U) #define falcon_falcon_irqmask_r() (0x00000018U)
#define falcon_falcon_irqdest_r() (0x0000001cU) #define falcon_falcon_irqdest_r() (0x0000001cU)
#define falcon_falcon_irqdest_host_gptmr_f(v) (((v)&0x1U) << 0U) #define falcon_falcon_irqdest_host_gptmr_f(v) ((U32(v) & 0x1U) << 0U)
#define falcon_falcon_irqdest_host_wdtmr_f(v) (((v)&0x1U) << 1U) #define falcon_falcon_irqdest_host_wdtmr_f(v) ((U32(v) & 0x1U) << 1U)
#define falcon_falcon_irqdest_host_mthd_f(v) (((v)&0x1U) << 2U) #define falcon_falcon_irqdest_host_mthd_f(v) ((U32(v) & 0x1U) << 2U)
#define falcon_falcon_irqdest_host_ctxsw_f(v) (((v)&0x1U) << 3U) #define falcon_falcon_irqdest_host_ctxsw_f(v) ((U32(v) & 0x1U) << 3U)
#define falcon_falcon_irqdest_host_halt_f(v) (((v)&0x1U) << 4U) #define falcon_falcon_irqdest_host_halt_f(v) ((U32(v) & 0x1U) << 4U)
#define falcon_falcon_irqdest_host_exterr_f(v) (((v)&0x1U) << 5U) #define falcon_falcon_irqdest_host_exterr_f(v) ((U32(v) & 0x1U) << 5U)
#define falcon_falcon_irqdest_host_swgen0_f(v) (((v)&0x1U) << 6U) #define falcon_falcon_irqdest_host_swgen0_f(v) ((U32(v) & 0x1U) << 6U)
#define falcon_falcon_irqdest_host_swgen1_f(v) (((v)&0x1U) << 7U) #define falcon_falcon_irqdest_host_swgen1_f(v) ((U32(v) & 0x1U) << 7U)
#define falcon_falcon_irqdest_host_ext_f(v) (((v)&0xffU) << 8U) #define falcon_falcon_irqdest_host_ext_f(v) ((U32(v) & 0xffU) << 8U)
#define falcon_falcon_irqdest_target_gptmr_f(v) (((v)&0x1U) << 16U) #define falcon_falcon_irqdest_target_gptmr_f(v) ((U32(v) & 0x1U) << 16U)
#define falcon_falcon_irqdest_target_wdtmr_f(v) (((v)&0x1U) << 17U) #define falcon_falcon_irqdest_target_wdtmr_f(v) ((U32(v) & 0x1U) << 17U)
#define falcon_falcon_irqdest_target_mthd_f(v) (((v)&0x1U) << 18U) #define falcon_falcon_irqdest_target_mthd_f(v) ((U32(v) & 0x1U) << 18U)
#define falcon_falcon_irqdest_target_ctxsw_f(v) (((v)&0x1U) << 19U) #define falcon_falcon_irqdest_target_ctxsw_f(v) ((U32(v) & 0x1U) << 19U)
#define falcon_falcon_irqdest_target_halt_f(v) (((v)&0x1U) << 20U) #define falcon_falcon_irqdest_target_halt_f(v) ((U32(v) & 0x1U) << 20U)
#define falcon_falcon_irqdest_target_exterr_f(v) (((v)&0x1U) << 21U) #define falcon_falcon_irqdest_target_exterr_f(v) ((U32(v) & 0x1U) << 21U)
#define falcon_falcon_irqdest_target_swgen0_f(v) (((v)&0x1U) << 22U) #define falcon_falcon_irqdest_target_swgen0_f(v) ((U32(v) & 0x1U) << 22U)
#define falcon_falcon_irqdest_target_swgen1_f(v) (((v)&0x1U) << 23U) #define falcon_falcon_irqdest_target_swgen1_f(v) ((U32(v) & 0x1U) << 23U)
#define falcon_falcon_irqdest_target_ext_f(v) (((v)&0xffU) << 24U) #define falcon_falcon_irqdest_target_ext_f(v) ((U32(v) & 0xffU) << 24U)
#define falcon_falcon_curctx_r() (0x00000050U) #define falcon_falcon_curctx_r() (0x00000050U)
#define falcon_falcon_nxtctx_r() (0x00000054U) #define falcon_falcon_nxtctx_r() (0x00000054U)
#define falcon_falcon_mailbox0_r() (0x00000040U) #define falcon_falcon_mailbox0_r() (0x00000040U)
@@ -118,24 +118,24 @@
#define falcon_falcon_os_r() (0x00000080U) #define falcon_falcon_os_r() (0x00000080U)
#define falcon_falcon_engctl_r() (0x000000a4U) #define falcon_falcon_engctl_r() (0x000000a4U)
#define falcon_falcon_cpuctl_r() (0x00000100U) #define falcon_falcon_cpuctl_r() (0x00000100U)
#define falcon_falcon_cpuctl_startcpu_f(v) (((v)&0x1U) << 1U) #define falcon_falcon_cpuctl_startcpu_f(v) ((U32(v) & 0x1U) << 1U)
#define falcon_falcon_cpuctl_sreset_f(v) (((v)&0x1U) << 2U) #define falcon_falcon_cpuctl_sreset_f(v) ((U32(v) & 0x1U) << 2U)
#define falcon_falcon_cpuctl_hreset_f(v) (((v)&0x1U) << 3U) #define falcon_falcon_cpuctl_hreset_f(v) ((U32(v) & 0x1U) << 3U)
#define falcon_falcon_cpuctl_halt_intr_f(v) (((v)&0x1U) << 4U) #define falcon_falcon_cpuctl_halt_intr_f(v) ((U32(v) & 0x1U) << 4U)
#define falcon_falcon_cpuctl_halt_intr_m() (U32(0x1U) << 4U) #define falcon_falcon_cpuctl_halt_intr_m() (U32(0x1U) << 4U)
#define falcon_falcon_cpuctl_halt_intr_v(r) (((r) >> 4U) & 0x1U) #define falcon_falcon_cpuctl_halt_intr_v(r) (((r) >> 4U) & 0x1U)
#define falcon_falcon_cpuctl_stopped_m() (U32(0x1U) << 5U) #define falcon_falcon_cpuctl_stopped_m() (U32(0x1U) << 5U)
#define falcon_falcon_cpuctl_cpuctl_alias_en_f(v) (((v)&0x1U) << 6U) #define falcon_falcon_cpuctl_cpuctl_alias_en_f(v) ((U32(v) & 0x1U) << 6U)
#define falcon_falcon_cpuctl_cpuctl_alias_en_m() (U32(0x1U) << 6U) #define falcon_falcon_cpuctl_cpuctl_alias_en_m() (U32(0x1U) << 6U)
#define falcon_falcon_cpuctl_cpuctl_alias_en_v(r) (((r) >> 6U) & 0x1U) #define falcon_falcon_cpuctl_cpuctl_alias_en_v(r) (((r) >> 6U) & 0x1U)
#define falcon_falcon_cpuctl_alias_r() (0x00000130U) #define falcon_falcon_cpuctl_alias_r() (0x00000130U)
#define falcon_falcon_cpuctl_alias_startcpu_f(v) (((v)&0x1U) << 1U) #define falcon_falcon_cpuctl_alias_startcpu_f(v) ((U32(v) & 0x1U) << 1U)
#define falcon_falcon_imemc_r(i)\ #define falcon_falcon_imemc_r(i)\
(nvgpu_safe_add_u32(0x00000180U, nvgpu_safe_mult_u32((i), 16U))) (nvgpu_safe_add_u32(0x00000180U, nvgpu_safe_mult_u32((i), 16U)))
#define falcon_falcon_imemc_offs_f(v) (((v)&0x3fU) << 2U) #define falcon_falcon_imemc_offs_f(v) ((U32(v) & 0x3fU) << 2U)
#define falcon_falcon_imemc_blk_f(v) (((v)&0xffU) << 8U) #define falcon_falcon_imemc_blk_f(v) ((U32(v) & 0xffU) << 8U)
#define falcon_falcon_imemc_aincw_f(v) (((v)&0x1U) << 24U) #define falcon_falcon_imemc_aincw_f(v) ((U32(v) & 0x1U) << 24U)
#define falcon_falcon_imemc_secure_f(v) (((v)&0x1U) << 28U) #define falcon_falcon_imemc_secure_f(v) ((U32(v) & 0x1U) << 28U)
#define falcon_falcon_imemd_r(i)\ #define falcon_falcon_imemd_r(i)\
(nvgpu_safe_add_u32(0x00000184U, nvgpu_safe_mult_u32((i), 16U))) (nvgpu_safe_add_u32(0x00000184U, nvgpu_safe_mult_u32((i), 16U)))
#define falcon_falcon_imemt_r(i)\ #define falcon_falcon_imemt_r(i)\
@@ -143,11 +143,11 @@
#define falcon_falcon_sctl_r() (0x00000240U) #define falcon_falcon_sctl_r() (0x00000240U)
#define falcon_falcon_mmu_phys_sec_r() (0x00100ce4U) #define falcon_falcon_mmu_phys_sec_r() (0x00100ce4U)
#define falcon_falcon_bootvec_r() (0x00000104U) #define falcon_falcon_bootvec_r() (0x00000104U)
#define falcon_falcon_bootvec_vec_f(v) (((v)&0xffffffffU) << 0U) #define falcon_falcon_bootvec_vec_f(v) ((U32(v) & 0xffffffffU) << 0U)
#define falcon_falcon_dmactl_r() (0x0000010cU) #define falcon_falcon_dmactl_r() (0x0000010cU)
#define falcon_falcon_dmactl_dmem_scrubbing_m() (U32(0x1U) << 1U) #define falcon_falcon_dmactl_dmem_scrubbing_m() (U32(0x1U) << 1U)
#define falcon_falcon_dmactl_imem_scrubbing_m() (U32(0x1U) << 2U) #define falcon_falcon_dmactl_imem_scrubbing_m() (U32(0x1U) << 2U)
#define falcon_falcon_dmactl_require_ctx_f(v) (((v)&0x1U) << 0U) #define falcon_falcon_dmactl_require_ctx_f(v) ((U32(v) & 0x1U) << 0U)
#define falcon_falcon_hwcfg_r() (0x00000108U) #define falcon_falcon_hwcfg_r() (0x00000108U)
#define falcon_falcon_hwcfg_imem_size_v(r) (((r) >> 0U) & 0x1ffU) #define falcon_falcon_hwcfg_imem_size_v(r) (((r) >> 0U) & 0x1ffU)
#define falcon_falcon_hwcfg_dmem_size_v(r) (((r) >> 9U) & 0x1ffU) #define falcon_falcon_hwcfg_dmem_size_v(r) (((r) >> 9U) & 0x1ffU)
@@ -155,18 +155,18 @@
#define falcon_falcon_dmatrfbase1_r() (0x00000128U) #define falcon_falcon_dmatrfbase1_r() (0x00000128U)
#define falcon_falcon_dmatrfmoffs_r() (0x00000114U) #define falcon_falcon_dmatrfmoffs_r() (0x00000114U)
#define falcon_falcon_dmatrfcmd_r() (0x00000118U) #define falcon_falcon_dmatrfcmd_r() (0x00000118U)
#define falcon_falcon_dmatrfcmd_imem_f(v) (((v)&0x1U) << 4U) #define falcon_falcon_dmatrfcmd_imem_f(v) ((U32(v) & 0x1U) << 4U)
#define falcon_falcon_dmatrfcmd_write_f(v) (((v)&0x1U) << 5U) #define falcon_falcon_dmatrfcmd_write_f(v) ((U32(v) & 0x1U) << 5U)
#define falcon_falcon_dmatrfcmd_size_f(v) (((v)&0x7U) << 8U) #define falcon_falcon_dmatrfcmd_size_f(v) ((U32(v) & 0x7U) << 8U)
#define falcon_falcon_dmatrfcmd_ctxdma_f(v) (((v)&0x7U) << 12U) #define falcon_falcon_dmatrfcmd_ctxdma_f(v) ((U32(v) & 0x7U) << 12U)
#define falcon_falcon_dmatrffboffs_r() (0x0000011cU) #define falcon_falcon_dmatrffboffs_r() (0x0000011cU)
#define falcon_falcon_imctl_debug_r() (0x0000015cU) #define falcon_falcon_imctl_debug_r() (0x0000015cU)
#define falcon_falcon_imctl_debug_addr_blk_f(v) (((v)&0xffffffU) << 0U) #define falcon_falcon_imctl_debug_addr_blk_f(v) ((U32(v) & 0xffffffU) << 0U)
#define falcon_falcon_imctl_debug_cmd_f(v) (((v)&0x7U) << 24U) #define falcon_falcon_imctl_debug_cmd_f(v) ((U32(v) & 0x7U) << 24U)
#define falcon_falcon_imstat_r() (0x00000144U) #define falcon_falcon_imstat_r() (0x00000144U)
#define falcon_falcon_traceidx_r() (0x00000148U) #define falcon_falcon_traceidx_r() (0x00000148U)
#define falcon_falcon_traceidx_maxidx_v(r) (((r) >> 16U) & 0xffU) #define falcon_falcon_traceidx_maxidx_v(r) (((r) >> 16U) & 0xffU)
#define falcon_falcon_traceidx_idx_f(v) (((v)&0xffU) << 0U) #define falcon_falcon_traceidx_idx_f(v) ((U32(v) & 0xffU) << 0U)
#define falcon_falcon_tracepc_r() (0x0000014cU) #define falcon_falcon_tracepc_r() (0x0000014cU)
#define falcon_falcon_tracepc_pc_v(r) (((r) >> 0U) & 0xffffffU) #define falcon_falcon_tracepc_pc_v(r) (((r) >> 0U) & 0xffffffU)
#define falcon_falcon_exterraddr_r() (0x0010a168U) #define falcon_falcon_exterraddr_r() (0x0010a168U)
@@ -176,26 +176,26 @@
#define falcon_falcon_exterrstat_valid_true_v() (0x00000001U) #define falcon_falcon_exterrstat_valid_true_v() (0x00000001U)
#define falcon_falcon_icd_cmd_r() (0x00000200U) #define falcon_falcon_icd_cmd_r() (0x00000200U)
#define falcon_falcon_icd_cmd_opc_s() (4U) #define falcon_falcon_icd_cmd_opc_s() (4U)
#define falcon_falcon_icd_cmd_opc_f(v) (((v)&0xfU) << 0U) #define falcon_falcon_icd_cmd_opc_f(v) ((U32(v) & 0xfU) << 0U)
#define falcon_falcon_icd_cmd_opc_m() (U32(0xfU) << 0U) #define falcon_falcon_icd_cmd_opc_m() (U32(0xfU) << 0U)
#define falcon_falcon_icd_cmd_opc_v(r) (((r) >> 0U) & 0xfU) #define falcon_falcon_icd_cmd_opc_v(r) (((r) >> 0U) & 0xfU)
#define falcon_falcon_icd_cmd_opc_rreg_f() (0x8U) #define falcon_falcon_icd_cmd_opc_rreg_f() (0x8U)
#define falcon_falcon_icd_cmd_opc_rstat_f() (0xeU) #define falcon_falcon_icd_cmd_opc_rstat_f() (0xeU)
#define falcon_falcon_icd_cmd_idx_f(v) (((v)&0x1fU) << 8U) #define falcon_falcon_icd_cmd_idx_f(v) ((U32(v) & 0x1fU) << 8U)
#define falcon_falcon_icd_rdata_r() (0x0000020cU) #define falcon_falcon_icd_rdata_r() (0x0000020cU)
#define falcon_falcon_dmemc_r(i)\ #define falcon_falcon_dmemc_r(i)\
(nvgpu_safe_add_u32(0x000001c0U, nvgpu_safe_mult_u32((i), 8U))) (nvgpu_safe_add_u32(0x000001c0U, nvgpu_safe_mult_u32((i), 8U)))
#define falcon_falcon_dmemc_offs_f(v) (((v)&0x3fU) << 2U) #define falcon_falcon_dmemc_offs_f(v) ((U32(v) & 0x3fU) << 2U)
#define falcon_falcon_dmemc_offs_m() (U32(0x3fU) << 2U) #define falcon_falcon_dmemc_offs_m() (U32(0x3fU) << 2U)
#define falcon_falcon_dmemc_blk_f(v) (((v)&0xffU) << 8U) #define falcon_falcon_dmemc_blk_f(v) ((U32(v) & 0xffU) << 8U)
#define falcon_falcon_dmemc_blk_m() (U32(0xffU) << 8U) #define falcon_falcon_dmemc_blk_m() (U32(0xffU) << 8U)
#define falcon_falcon_dmemc_aincw_f(v) (((v)&0x1U) << 24U) #define falcon_falcon_dmemc_aincw_f(v) ((U32(v) & 0x1U) << 24U)
#define falcon_falcon_dmemc_aincr_f(v) (((v)&0x1U) << 25U) #define falcon_falcon_dmemc_aincr_f(v) ((U32(v) & 0x1U) << 25U)
#define falcon_falcon_dmemd_r(i)\ #define falcon_falcon_dmemd_r(i)\
(nvgpu_safe_add_u32(0x000001c4U, nvgpu_safe_mult_u32((i), 8U))) (nvgpu_safe_add_u32(0x000001c4U, nvgpu_safe_mult_u32((i), 8U)))
#define falcon_falcon_debug1_r() (0x00000090U) #define falcon_falcon_debug1_r() (0x00000090U)
#define falcon_falcon_debug1_ctxsw_mode_s() (1U) #define falcon_falcon_debug1_ctxsw_mode_s() (1U)
#define falcon_falcon_debug1_ctxsw_mode_f(v) (((v)&0x1U) << 16U) #define falcon_falcon_debug1_ctxsw_mode_f(v) ((U32(v) & 0x1U) << 16U)
#define falcon_falcon_debug1_ctxsw_mode_m() (U32(0x1U) << 16U) #define falcon_falcon_debug1_ctxsw_mode_m() (U32(0x1U) << 16U)
#define falcon_falcon_debug1_ctxsw_mode_v(r) (((r) >> 16U) & 0x1U) #define falcon_falcon_debug1_ctxsw_mode_v(r) (((r) >> 16U) & 0x1U)
#define falcon_falcon_debug1_ctxsw_mode_init_f() (0x0U) #define falcon_falcon_debug1_ctxsw_mode_init_f() (0x0U)

142
drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_fb_gv100.h
View File

@@ -60,11 +60,11 @@
#include <nvgpu/safe_ops.h> #include <nvgpu/safe_ops.h>
#define fb_fbhub_num_active_ltcs_r() (0x00100800U) #define fb_fbhub_num_active_ltcs_r() (0x00100800U)
#define fb_fbhub_num_active_ltcs_use_nvlink_f(v) (((v)&0xffU) << 16U) #define fb_fbhub_num_active_ltcs_use_nvlink_f(v) ((U32(v) & 0xffU) << 16U)
#define fb_fbhub_num_active_ltcs_use_nvlink_m() (U32(0xffU) << 16U) #define fb_fbhub_num_active_ltcs_use_nvlink_m() (U32(0xffU) << 16U)
#define fb_fbhub_num_active_ltcs_use_nvlink_v(r) (((r) >> 16U) & 0xffU) #define fb_fbhub_num_active_ltcs_use_nvlink_v(r) (((r) >> 16U) & 0xffU)
#define fb_fbhub_num_active_ltcs_use_nvlink_peer_f(v, i)\ #define fb_fbhub_num_active_ltcs_use_nvlink_peer_f(v, i)\
(((v) & 0x1) << (16U + i*1U)) ((U32(v) & 0x1U) << (16U + (i)*1U))
#define fb_fbhub_num_active_ltcs_use_nvlink_peer_m(i)\ #define fb_fbhub_num_active_ltcs_use_nvlink_peer_m(i)\
(U32(0x1U) << (16U + (i)*1U)) (U32(0x1U) << (16U + (i)*1U))
#define fb_fbhub_num_active_ltcs_use_nvlink_peer_v(r, i)\ #define fb_fbhub_num_active_ltcs_use_nvlink_peer_v(r, i)\
@@ -78,7 +78,8 @@
#define fb_fbhub_num_active_ltcs_use_nvlink_peer_disabled_v() (0x00000000U) #define fb_fbhub_num_active_ltcs_use_nvlink_peer_disabled_v() (0x00000000U)
#define fb_fbhub_num_active_ltcs_use_nvlink_peer_disabled_f(i)\ #define fb_fbhub_num_active_ltcs_use_nvlink_peer_disabled_f(i)\
((0x0U << (32U +((i)*1U)))) ((0x0U << (32U +((i)*1U))))
#define fb_fbhub_num_active_ltcs_hub_sys_atomic_mode_f(v) (((v)&0x1U) << 25U) #define fb_fbhub_num_active_ltcs_hub_sys_atomic_mode_f(v)\
((U32(v) & 0x1U) << 25U)
#define fb_fbhub_num_active_ltcs_hub_sys_atomic_mode_m() (U32(0x1U) << 25U) #define fb_fbhub_num_active_ltcs_hub_sys_atomic_mode_m() (U32(0x1U) << 25U)
#define fb_fbhub_num_active_ltcs_hub_sys_atomic_mode_v(r) (((r) >> 25U) & 0x1U) #define fb_fbhub_num_active_ltcs_hub_sys_atomic_mode_v(r) (((r) >> 25U) & 0x1U)
#define fb_fbhub_num_active_ltcs_hub_sys_atomic_mode_use_read_v() (0x00000000U) #define fb_fbhub_num_active_ltcs_hub_sys_atomic_mode_use_read_v() (0x00000000U)
@@ -89,7 +90,7 @@
#define fb_mmu_ctrl_pri_fifo_empty_v(r) (((r) >> 15U) & 0x1U) #define fb_mmu_ctrl_pri_fifo_empty_v(r) (((r) >> 15U) & 0x1U)
#define fb_mmu_ctrl_pri_fifo_empty_false_f() (0x0U) #define fb_mmu_ctrl_pri_fifo_empty_false_f() (0x0U)
#define fb_mmu_ctrl_pri_fifo_space_v(r) (((r) >> 16U) & 0xffU) #define fb_mmu_ctrl_pri_fifo_space_v(r) (((r) >> 16U) & 0xffU)
#define fb_mmu_ctrl_atomic_capability_mode_f(v) (((v)&0x3U) << 24U) #define fb_mmu_ctrl_atomic_capability_mode_f(v) ((U32(v) & 0x3U) << 24U)
#define fb_mmu_ctrl_atomic_capability_mode_m() (U32(0x3U) << 24U) #define fb_mmu_ctrl_atomic_capability_mode_m() (U32(0x3U) << 24U)
#define fb_mmu_ctrl_atomic_capability_mode_v(r) (((r) >> 24U) & 0x3U) #define fb_mmu_ctrl_atomic_capability_mode_v(r) (((r) >> 24U) & 0x3U)
#define fb_mmu_ctrl_atomic_capability_mode_l2_v() (0x00000000U) #define fb_mmu_ctrl_atomic_capability_mode_l2_v() (0x00000000U)
@@ -101,7 +102,8 @@
#define fb_mmu_ctrl_atomic_capability_mode_power_v() (0x00000003U) #define fb_mmu_ctrl_atomic_capability_mode_power_v() (0x00000003U)
#define fb_mmu_ctrl_atomic_capability_mode_power_f() (0x3000000U) #define fb_mmu_ctrl_atomic_capability_mode_power_f() (0x3000000U)
#define fb_hsmmu_pri_mmu_ctrl_r() (0x001fac80U) #define fb_hsmmu_pri_mmu_ctrl_r() (0x001fac80U)
#define fb_hsmmu_pri_mmu_ctrl_atomic_capability_mode_f(v) (((v)&0x3U) << 24U) #define fb_hsmmu_pri_mmu_ctrl_atomic_capability_mode_f(v)\
((U32(v) & 0x3U) << 24U)
#define fb_hsmmu_pri_mmu_ctrl_atomic_capability_mode_m() (U32(0x3U) << 24U) #define fb_hsmmu_pri_mmu_ctrl_atomic_capability_mode_m() (U32(0x3U) << 24U)
#define fb_hsmmu_pri_mmu_ctrl_atomic_capability_mode_v(r) (((r) >> 24U) & 0x3U) #define fb_hsmmu_pri_mmu_ctrl_atomic_capability_mode_v(r) (((r) >> 24U) & 0x3U)
#define fb_hsmmu_pri_mmu_ctrl_atomic_capability_mode_l2_v() (0x00000000U) #define fb_hsmmu_pri_mmu_ctrl_atomic_capability_mode_l2_v() (0x00000000U)
@@ -113,11 +115,11 @@
#define fb_hsmmu_pri_mmu_ctrl_atomic_capability_mode_power_v() (0x00000003U) #define fb_hsmmu_pri_mmu_ctrl_atomic_capability_mode_power_v() (0x00000003U)
#define fb_hsmmu_pri_mmu_ctrl_atomic_capability_mode_power_f() (0x3000000U) #define fb_hsmmu_pri_mmu_ctrl_atomic_capability_mode_power_f() (0x3000000U)
#define fb_hshub_num_active_ltcs_r() (0x001fbc20U) #define fb_hshub_num_active_ltcs_r() (0x001fbc20U)
#define fb_hshub_num_active_ltcs_use_nvlink_f(v) (((v)&0xffU) << 16U) #define fb_hshub_num_active_ltcs_use_nvlink_f(v) ((U32(v) & 0xffU) << 16U)
#define fb_hshub_num_active_ltcs_use_nvlink_m() (U32(0xffU) << 16U) #define fb_hshub_num_active_ltcs_use_nvlink_m() (U32(0xffU) << 16U)
#define fb_hshub_num_active_ltcs_use_nvlink_v(r) (((r) >> 16U) & 0xffU) #define fb_hshub_num_active_ltcs_use_nvlink_v(r) (((r) >> 16U) & 0xffU)
#define fb_hshub_num_active_ltcs_use_nvlink_peer_f(v, i)\ #define fb_hshub_num_active_ltcs_use_nvlink_peer_f(v, i)\
(((v) & 0x1) << (16U + i*1U)) ((U32(v) & 0x1U) << (16U + (i)*1U))
#define fb_hshub_num_active_ltcs_use_nvlink_peer_m(i)\ #define fb_hshub_num_active_ltcs_use_nvlink_peer_m(i)\
(U32(0x1U) << (16U + (i)*1U)) (U32(0x1U) << (16U + (i)*1U))
#define fb_hshub_num_active_ltcs_use_nvlink_peer_v(r, i)\ #define fb_hshub_num_active_ltcs_use_nvlink_peer_v(r, i)\
@@ -131,7 +133,8 @@
#define fb_hshub_num_active_ltcs_use_nvlink_peer_disabled_v() (0x00000000U) #define fb_hshub_num_active_ltcs_use_nvlink_peer_disabled_v() (0x00000000U)
#define fb_hshub_num_active_ltcs_use_nvlink_peer_disabled_f(i)\ #define fb_hshub_num_active_ltcs_use_nvlink_peer_disabled_f(i)\
((0x0U << (32U +((i)*1U)))) ((0x0U << (32U +((i)*1U))))
#define fb_hshub_num_active_ltcs_hub_sys_atomic_mode_f(v) (((v)&0x1U) << 25U) #define fb_hshub_num_active_ltcs_hub_sys_atomic_mode_f(v)\
((U32(v) & 0x1U) << 25U)
#define fb_hshub_num_active_ltcs_hub_sys_atomic_mode_m() (U32(0x1U) << 25U) #define fb_hshub_num_active_ltcs_hub_sys_atomic_mode_m() (U32(0x1U) << 25U)
#define fb_hshub_num_active_ltcs_hub_sys_atomic_mode_v(r) (((r) >> 25U) & 0x1U) #define fb_hshub_num_active_ltcs_hub_sys_atomic_mode_v(r) (((r) >> 25U) & 0x1U)
#define fb_hshub_num_active_ltcs_hub_sys_atomic_mode_use_read_v() (0x00000000U) #define fb_hshub_num_active_ltcs_hub_sys_atomic_mode_use_read_v() (0x00000000U)
@@ -142,17 +145,17 @@
#define fb_mmu_invalidate_pdb_r() (0x00100cb8U) #define fb_mmu_invalidate_pdb_r() (0x00100cb8U)
#define fb_mmu_invalidate_pdb_aperture_vid_mem_f() (0x0U) #define fb_mmu_invalidate_pdb_aperture_vid_mem_f() (0x0U)
#define fb_mmu_invalidate_pdb_aperture_sys_mem_f() (0x2U) #define fb_mmu_invalidate_pdb_aperture_sys_mem_f() (0x2U)
#define fb_mmu_invalidate_pdb_addr_f(v) (((v)&0xfffffffU) << 4U) #define fb_mmu_invalidate_pdb_addr_f(v) ((U32(v) & 0xfffffffU) << 4U)
#define fb_mmu_invalidate_r() (0x00100cbcU) #define fb_mmu_invalidate_r() (0x00100cbcU)
#define fb_mmu_invalidate_all_va_true_f() (0x1U) #define fb_mmu_invalidate_all_va_true_f() (0x1U)
#define fb_mmu_invalidate_all_pdb_true_f() (0x2U) #define fb_mmu_invalidate_all_pdb_true_f() (0x2U)
#define fb_mmu_invalidate_hubtlb_only_s() (1U) #define fb_mmu_invalidate_hubtlb_only_s() (1U)
#define fb_mmu_invalidate_hubtlb_only_f(v) (((v)&0x1U) << 2U) #define fb_mmu_invalidate_hubtlb_only_f(v) ((U32(v) & 0x1U) << 2U)
#define fb_mmu_invalidate_hubtlb_only_m() (U32(0x1U) << 2U) #define fb_mmu_invalidate_hubtlb_only_m() (U32(0x1U) << 2U)
#define fb_mmu_invalidate_hubtlb_only_v(r) (((r) >> 2U) & 0x1U) #define fb_mmu_invalidate_hubtlb_only_v(r) (((r) >> 2U) & 0x1U)
#define fb_mmu_invalidate_hubtlb_only_true_f() (0x4U) #define fb_mmu_invalidate_hubtlb_only_true_f() (0x4U)
#define fb_mmu_invalidate_replay_s() (3U) #define fb_mmu_invalidate_replay_s() (3U)
#define fb_mmu_invalidate_replay_f(v) (((v)&0x7U) << 3U) #define fb_mmu_invalidate_replay_f(v) ((U32(v) & 0x7U) << 3U)
#define fb_mmu_invalidate_replay_m() (U32(0x7U) << 3U) #define fb_mmu_invalidate_replay_m() (U32(0x7U) << 3U)
#define fb_mmu_invalidate_replay_v(r) (((r) >> 3U) & 0x7U) #define fb_mmu_invalidate_replay_v(r) (((r) >> 3U) & 0x7U)
#define fb_mmu_invalidate_replay_none_f() (0x0U) #define fb_mmu_invalidate_replay_none_f() (0x0U)
@@ -160,33 +163,33 @@
#define fb_mmu_invalidate_replay_start_ack_all_f() (0x10U) #define fb_mmu_invalidate_replay_start_ack_all_f() (0x10U)
#define fb_mmu_invalidate_replay_cancel_global_f() (0x20U) #define fb_mmu_invalidate_replay_cancel_global_f() (0x20U)
#define fb_mmu_invalidate_sys_membar_s() (1U) #define fb_mmu_invalidate_sys_membar_s() (1U)
#define fb_mmu_invalidate_sys_membar_f(v) (((v)&0x1U) << 6U) #define fb_mmu_invalidate_sys_membar_f(v) ((U32(v) & 0x1U) << 6U)
#define fb_mmu_invalidate_sys_membar_m() (U32(0x1U) << 6U) #define fb_mmu_invalidate_sys_membar_m() (U32(0x1U) << 6U)
#define fb_mmu_invalidate_sys_membar_v(r) (((r) >> 6U) & 0x1U) #define fb_mmu_invalidate_sys_membar_v(r) (((r) >> 6U) & 0x1U)
#define fb_mmu_invalidate_sys_membar_true_f() (0x40U) #define fb_mmu_invalidate_sys_membar_true_f() (0x40U)
#define fb_mmu_invalidate_ack_s() (2U) #define fb_mmu_invalidate_ack_s() (2U)
#define fb_mmu_invalidate_ack_f(v) (((v)&0x3U) << 7U) #define fb_mmu_invalidate_ack_f(v) ((U32(v) & 0x3U) << 7U)
#define fb_mmu_invalidate_ack_m() (U32(0x3U) << 7U) #define fb_mmu_invalidate_ack_m() (U32(0x3U) << 7U)
#define fb_mmu_invalidate_ack_v(r) (((r) >> 7U) & 0x3U) #define fb_mmu_invalidate_ack_v(r) (((r) >> 7U) & 0x3U)
#define fb_mmu_invalidate_ack_ack_none_required_f() (0x0U) #define fb_mmu_invalidate_ack_ack_none_required_f() (0x0U)
#define fb_mmu_invalidate_ack_ack_intranode_f() (0x100U) #define fb_mmu_invalidate_ack_ack_intranode_f() (0x100U)
#define fb_mmu_invalidate_ack_ack_globally_f() (0x80U) #define fb_mmu_invalidate_ack_ack_globally_f() (0x80U)
#define fb_mmu_invalidate_cancel_client_id_s() (6U) #define fb_mmu_invalidate_cancel_client_id_s() (6U)
#define fb_mmu_invalidate_cancel_client_id_f(v) (((v)&0x3fU) << 9U) #define fb_mmu_invalidate_cancel_client_id_f(v) ((U32(v) & 0x3fU) << 9U)
#define fb_mmu_invalidate_cancel_client_id_m() (U32(0x3fU) << 9U) #define fb_mmu_invalidate_cancel_client_id_m() (U32(0x3fU) << 9U)
#define fb_mmu_invalidate_cancel_client_id_v(r) (((r) >> 9U) & 0x3fU) #define fb_mmu_invalidate_cancel_client_id_v(r) (((r) >> 9U) & 0x3fU)
#define fb_mmu_invalidate_cancel_gpc_id_s() (5U) #define fb_mmu_invalidate_cancel_gpc_id_s() (5U)
#define fb_mmu_invalidate_cancel_gpc_id_f(v) (((v)&0x1fU) << 15U) #define fb_mmu_invalidate_cancel_gpc_id_f(v) ((U32(v) & 0x1fU) << 15U)
#define fb_mmu_invalidate_cancel_gpc_id_m() (U32(0x1fU) << 15U) #define fb_mmu_invalidate_cancel_gpc_id_m() (U32(0x1fU) << 15U)
#define fb_mmu_invalidate_cancel_gpc_id_v(r) (((r) >> 15U) & 0x1fU) #define fb_mmu_invalidate_cancel_gpc_id_v(r) (((r) >> 15U) & 0x1fU)
#define fb_mmu_invalidate_cancel_client_type_s() (1U) #define fb_mmu_invalidate_cancel_client_type_s() (1U)
#define fb_mmu_invalidate_cancel_client_type_f(v) (((v)&0x1U) << 20U) #define fb_mmu_invalidate_cancel_client_type_f(v) ((U32(v) & 0x1U) << 20U)
#define fb_mmu_invalidate_cancel_client_type_m() (U32(0x1U) << 20U) #define fb_mmu_invalidate_cancel_client_type_m() (U32(0x1U) << 20U)
#define fb_mmu_invalidate_cancel_client_type_v(r) (((r) >> 20U) & 0x1U) #define fb_mmu_invalidate_cancel_client_type_v(r) (((r) >> 20U) & 0x1U)
#define fb_mmu_invalidate_cancel_client_type_gpc_f() (0x0U) #define fb_mmu_invalidate_cancel_client_type_gpc_f() (0x0U)
#define fb_mmu_invalidate_cancel_client_type_hub_f() (0x100000U) #define fb_mmu_invalidate_cancel_client_type_hub_f() (0x100000U)
#define fb_mmu_invalidate_cancel_cache_level_s() (3U) #define fb_mmu_invalidate_cancel_cache_level_s() (3U)
#define fb_mmu_invalidate_cancel_cache_level_f(v) (((v)&0x7U) << 24U) #define fb_mmu_invalidate_cancel_cache_level_f(v) ((U32(v) & 0x7U) << 24U)
#define fb_mmu_invalidate_cancel_cache_level_m() (U32(0x7U) << 24U) #define fb_mmu_invalidate_cancel_cache_level_m() (U32(0x7U) << 24U)
#define fb_mmu_invalidate_cancel_cache_level_v(r) (((r) >> 24U) & 0x7U) #define fb_mmu_invalidate_cancel_cache_level_v(r) (((r) >> 24U) & 0x7U)
#define fb_mmu_invalidate_cancel_cache_level_all_f() (0x0U) #define fb_mmu_invalidate_cancel_cache_level_all_f() (0x0U)
@@ -198,13 +201,13 @@
#define fb_mmu_invalidate_cancel_cache_level_up_to_pde4_f() (0x6000000U) #define fb_mmu_invalidate_cancel_cache_level_up_to_pde4_f() (0x6000000U)
#define fb_mmu_invalidate_cancel_cache_level_up_to_pde5_f() (0x7000000U) #define fb_mmu_invalidate_cancel_cache_level_up_to_pde5_f() (0x7000000U)
#define fb_mmu_invalidate_trigger_s() (1U) #define fb_mmu_invalidate_trigger_s() (1U)
#define fb_mmu_invalidate_trigger_f(v) (((v)&0x1U) << 31U) #define fb_mmu_invalidate_trigger_f(v) ((U32(v) & 0x1U) << 31U)
#define fb_mmu_invalidate_trigger_m() (U32(0x1U) << 31U) #define fb_mmu_invalidate_trigger_m() (U32(0x1U) << 31U)
#define fb_mmu_invalidate_trigger_v(r) (((r) >> 31U) & 0x1U) #define fb_mmu_invalidate_trigger_v(r) (((r) >> 31U) & 0x1U)
#define fb_mmu_invalidate_trigger_true_f() (0x80000000U) #define fb_mmu_invalidate_trigger_true_f() (0x80000000U)
#define fb_mmu_debug_wr_r() (0x00100cc8U) #define fb_mmu_debug_wr_r() (0x00100cc8U)
#define fb_mmu_debug_wr_aperture_s() (2U) #define fb_mmu_debug_wr_aperture_s() (2U)
#define fb_mmu_debug_wr_aperture_f(v) (((v)&0x3U) << 0U) #define fb_mmu_debug_wr_aperture_f(v) ((U32(v) & 0x3U) << 0U)
#define fb_mmu_debug_wr_aperture_m() (U32(0x3U) << 0U) #define fb_mmu_debug_wr_aperture_m() (U32(0x3U) << 0U)
#define fb_mmu_debug_wr_aperture_v(r) (((r) >> 0U) & 0x3U) #define fb_mmu_debug_wr_aperture_v(r) (((r) >> 0U) & 0x3U)
#define fb_mmu_debug_wr_aperture_vid_mem_f() (0x0U) #define fb_mmu_debug_wr_aperture_vid_mem_f() (0x0U)
@@ -213,14 +216,14 @@
#define fb_mmu_debug_wr_vol_false_f() (0x0U) #define fb_mmu_debug_wr_vol_false_f() (0x0U)
#define fb_mmu_debug_wr_vol_true_v() (0x00000001U) #define fb_mmu_debug_wr_vol_true_v() (0x00000001U)
#define fb_mmu_debug_wr_vol_true_f() (0x4U) #define fb_mmu_debug_wr_vol_true_f() (0x4U)
#define fb_mmu_debug_wr_addr_f(v) (((v)&0xfffffffU) << 4U) #define fb_mmu_debug_wr_addr_f(v) ((U32(v) & 0xfffffffU) << 4U)
#define fb_mmu_debug_wr_addr_alignment_v() (0x0000000cU) #define fb_mmu_debug_wr_addr_alignment_v() (0x0000000cU)
#define fb_mmu_debug_rd_r() (0x00100cccU) #define fb_mmu_debug_rd_r() (0x00100cccU)
#define fb_mmu_debug_rd_aperture_vid_mem_f() (0x0U) #define fb_mmu_debug_rd_aperture_vid_mem_f() (0x0U)
#define fb_mmu_debug_rd_aperture_sys_mem_coh_f() (0x2U) #define fb_mmu_debug_rd_aperture_sys_mem_coh_f() (0x2U)
#define fb_mmu_debug_rd_aperture_sys_mem_ncoh_f() (0x3U) #define fb_mmu_debug_rd_aperture_sys_mem_ncoh_f() (0x3U)
#define fb_mmu_debug_rd_vol_false_f() (0x0U) #define fb_mmu_debug_rd_vol_false_f() (0x0U)
#define fb_mmu_debug_rd_addr_f(v) (((v)&0xfffffffU) << 4U) #define fb_mmu_debug_rd_addr_f(v) ((U32(v) & 0xfffffffU) << 4U)
#define fb_mmu_debug_rd_addr_alignment_v() (0x0000000cU) #define fb_mmu_debug_rd_addr_alignment_v() (0x0000000cU)
#define fb_mmu_debug_ctrl_r() (0x00100cc4U) #define fb_mmu_debug_ctrl_r() (0x00100cc4U)
#define fb_mmu_debug_ctrl_debug_v(r) (((r) >> 16U) & 0x1U) #define fb_mmu_debug_ctrl_debug_v(r) (((r) >> 16U) & 0x1U)
@@ -228,7 +231,7 @@
#define fb_mmu_debug_ctrl_debug_enabled_v() (0x00000001U) #define fb_mmu_debug_ctrl_debug_enabled_v() (0x00000001U)
#define fb_mmu_debug_ctrl_debug_disabled_v() (0x00000000U) #define fb_mmu_debug_ctrl_debug_disabled_v() (0x00000000U)
#define fb_niso_cfg1_r() (0x00100c14U) #define fb_niso_cfg1_r() (0x00100c14U)
#define fb_niso_cfg1_sysmem_nvlink_f(v) (((v)&0x1U) << 17U) #define fb_niso_cfg1_sysmem_nvlink_f(v) ((U32(v) & 0x1U) << 17U)
#define fb_niso_cfg1_sysmem_nvlink_m() (U32(0x1U) << 17U) #define fb_niso_cfg1_sysmem_nvlink_m() (U32(0x1U) << 17U)
#define fb_niso_cfg1_sysmem_nvlink_v(r) (((r) >> 17U) & 0x1U) #define fb_niso_cfg1_sysmem_nvlink_v(r) (((r) >> 17U) & 0x1U)
#define fb_niso_cfg1_sysmem_nvlink_enabled_v() (0x00000001U) #define fb_niso_cfg1_sysmem_nvlink_enabled_v() (0x00000001U)
@@ -252,21 +255,24 @@
#define fb_niso_intr_en_r(i)\ #define fb_niso_intr_en_r(i)\
(nvgpu_safe_add_u32(0x00100a24U, nvgpu_safe_mult_u32((i), 4U))) (nvgpu_safe_add_u32(0x00100a24U, nvgpu_safe_mult_u32((i), 4U)))
#define fb_niso_intr_en__size_1_v() (0x00000002U) #define fb_niso_intr_en__size_1_v() (0x00000002U)
#define fb_niso_intr_en_hub_access_counter_notify_f(v) (((v)&0x1U) << 0U) #define fb_niso_intr_en_hub_access_counter_notify_f(v) ((U32(v) & 0x1U) << 0U)
#define fb_niso_intr_en_hub_access_counter_notify_enabled_f() (0x1U) #define fb_niso_intr_en_hub_access_counter_notify_enabled_f() (0x1U)
#define fb_niso_intr_en_hub_access_counter_error_f(v) (((v)&0x1U) << 1U) #define fb_niso_intr_en_hub_access_counter_error_f(v) ((U32(v) & 0x1U) << 1U)
#define fb_niso_intr_en_hub_access_counter_error_enabled_f() (0x2U) #define fb_niso_intr_en_hub_access_counter_error_enabled_f() (0x2U)
#define fb_niso_intr_en_mmu_replayable_fault_notify_f(v) (((v)&0x1U) << 27U) #define fb_niso_intr_en_mmu_replayable_fault_notify_f(v)\
((U32(v) & 0x1U) << 27U)
#define fb_niso_intr_en_mmu_replayable_fault_notify_enabled_f() (0x8000000U) #define fb_niso_intr_en_mmu_replayable_fault_notify_enabled_f() (0x8000000U)
#define fb_niso_intr_en_mmu_replayable_fault_overflow_f(v) (((v)&0x1U) << 28U) #define fb_niso_intr_en_mmu_replayable_fault_overflow_f(v)\
((U32(v) & 0x1U) << 28U)
#define fb_niso_intr_en_mmu_replayable_fault_overflow_enabled_f() (0x10000000U) #define fb_niso_intr_en_mmu_replayable_fault_overflow_enabled_f() (0x10000000U)
#define fb_niso_intr_en_mmu_nonreplayable_fault_notify_f(v) (((v)&0x1U) << 29U) #define fb_niso_intr_en_mmu_nonreplayable_fault_notify_f(v)\
((U32(v) & 0x1U) << 29U)
#define fb_niso_intr_en_mmu_nonreplayable_fault_notify_enabled_f() (0x20000000U) #define fb_niso_intr_en_mmu_nonreplayable_fault_notify_enabled_f() (0x20000000U)
#define fb_niso_intr_en_mmu_nonreplayable_fault_overflow_f(v)\ #define fb_niso_intr_en_mmu_nonreplayable_fault_overflow_f(v)\
(((v)&0x1U) << 30U) ((U32(v) & 0x1U) << 30U)
#define fb_niso_intr_en_mmu_nonreplayable_fault_overflow_enabled_f()\ #define fb_niso_intr_en_mmu_nonreplayable_fault_overflow_enabled_f()\
(0x40000000U) (0x40000000U)
#define fb_niso_intr_en_mmu_other_fault_notify_f(v) (((v)&0x1U) << 31U) #define fb_niso_intr_en_mmu_other_fault_notify_f(v) ((U32(v) & 0x1U) << 31U)
#define fb_niso_intr_en_mmu_other_fault_notify_enabled_f() (0x80000000U) #define fb_niso_intr_en_mmu_other_fault_notify_enabled_f() (0x80000000U)
#define fb_niso_intr_en_set_r(i)\ #define fb_niso_intr_en_set_r(i)\
(nvgpu_safe_add_u32(0x00100a2cU, nvgpu_safe_mult_u32((i), 4U))) (nvgpu_safe_add_u32(0x00100a2cU, nvgpu_safe_mult_u32((i), 4U)))
@@ -313,92 +319,92 @@
#define fb_mmu_fault_buffer_lo_r(i)\ #define fb_mmu_fault_buffer_lo_r(i)\
(nvgpu_safe_add_u32(0x00100e24U, nvgpu_safe_mult_u32((i), 20U))) (nvgpu_safe_add_u32(0x00100e24U, nvgpu_safe_mult_u32((i), 20U)))
#define fb_mmu_fault_buffer_lo__size_1_v() (0x00000002U) #define fb_mmu_fault_buffer_lo__size_1_v() (0x00000002U)
#define fb_mmu_fault_buffer_lo_addr_mode_f(v) (((v)&0x1U) << 0U) #define fb_mmu_fault_buffer_lo_addr_mode_f(v) ((U32(v) & 0x1U) << 0U)
#define fb_mmu_fault_buffer_lo_addr_mode_v(r) (((r) >> 0U) & 0x1U) #define fb_mmu_fault_buffer_lo_addr_mode_v(r) (((r) >> 0U) & 0x1U)
#define fb_mmu_fault_buffer_lo_addr_mode_virtual_v() (0x00000000U) #define fb_mmu_fault_buffer_lo_addr_mode_virtual_v() (0x00000000U)
#define fb_mmu_fault_buffer_lo_addr_mode_virtual_f() (0x0U) #define fb_mmu_fault_buffer_lo_addr_mode_virtual_f() (0x0U)
#define fb_mmu_fault_buffer_lo_addr_mode_physical_v() (0x00000001U) #define fb_mmu_fault_buffer_lo_addr_mode_physical_v() (0x00000001U)
#define fb_mmu_fault_buffer_lo_addr_mode_physical_f() (0x1U) #define fb_mmu_fault_buffer_lo_addr_mode_physical_f() (0x1U)
#define fb_mmu_fault_buffer_lo_phys_aperture_f(v) (((v)&0x3U) << 1U) #define fb_mmu_fault_buffer_lo_phys_aperture_f(v) ((U32(v) & 0x3U) << 1U)
#define fb_mmu_fault_buffer_lo_phys_aperture_v(r) (((r) >> 1U) & 0x3U) #define fb_mmu_fault_buffer_lo_phys_aperture_v(r) (((r) >> 1U) & 0x3U)
#define fb_mmu_fault_buffer_lo_phys_aperture_sys_coh_v() (0x00000002U) #define fb_mmu_fault_buffer_lo_phys_aperture_sys_coh_v() (0x00000002U)
#define fb_mmu_fault_buffer_lo_phys_aperture_sys_coh_f() (0x4U) #define fb_mmu_fault_buffer_lo_phys_aperture_sys_coh_f() (0x4U)
#define fb_mmu_fault_buffer_lo_phys_aperture_sys_nocoh_v() (0x00000003U) #define fb_mmu_fault_buffer_lo_phys_aperture_sys_nocoh_v() (0x00000003U)
#define fb_mmu_fault_buffer_lo_phys_aperture_sys_nocoh_f() (0x6U) #define fb_mmu_fault_buffer_lo_phys_aperture_sys_nocoh_f() (0x6U)
#define fb_mmu_fault_buffer_lo_phys_vol_f(v) (((v)&0x1U) << 3U) #define fb_mmu_fault_buffer_lo_phys_vol_f(v) ((U32(v) & 0x1U) << 3U)
#define fb_mmu_fault_buffer_lo_phys_vol_v(r) (((r) >> 3U) & 0x1U) #define fb_mmu_fault_buffer_lo_phys_vol_v(r) (((r) >> 3U) & 0x1U)
#define fb_mmu_fault_buffer_lo_addr_f(v) (((v)&0xfffffU) << 12U) #define fb_mmu_fault_buffer_lo_addr_f(v) ((U32(v) & 0xfffffU) << 12U)
#define fb_mmu_fault_buffer_lo_addr_v(r) (((r) >> 12U) & 0xfffffU) #define fb_mmu_fault_buffer_lo_addr_v(r) (((r) >> 12U) & 0xfffffU)
#define fb_mmu_fault_buffer_hi_r(i)\ #define fb_mmu_fault_buffer_hi_r(i)\
(nvgpu_safe_add_u32(0x00100e28U, nvgpu_safe_mult_u32((i), 20U))) (nvgpu_safe_add_u32(0x00100e28U, nvgpu_safe_mult_u32((i), 20U)))
#define fb_mmu_fault_buffer_hi__size_1_v() (0x00000002U) #define fb_mmu_fault_buffer_hi__size_1_v() (0x00000002U)
#define fb_mmu_fault_buffer_hi_addr_f(v) (((v)&0xffffffffU) << 0U) #define fb_mmu_fault_buffer_hi_addr_f(v) ((U32(v) & 0xffffffffU) << 0U)
#define fb_mmu_fault_buffer_hi_addr_v(r) (((r) >> 0U) & 0xffffffffU) #define fb_mmu_fault_buffer_hi_addr_v(r) (((r) >> 0U) & 0xffffffffU)
#define fb_mmu_fault_buffer_get_r(i)\ #define fb_mmu_fault_buffer_get_r(i)\
(nvgpu_safe_add_u32(0x00100e2cU, nvgpu_safe_mult_u32((i), 20U))) (nvgpu_safe_add_u32(0x00100e2cU, nvgpu_safe_mult_u32((i), 20U)))
#define fb_mmu_fault_buffer_get__size_1_v() (0x00000002U) #define fb_mmu_fault_buffer_get__size_1_v() (0x00000002U)
#define fb_mmu_fault_buffer_get_ptr_f(v) (((v)&0xfffffU) << 0U) #define fb_mmu_fault_buffer_get_ptr_f(v) ((U32(v) & 0xfffffU) << 0U)
#define fb_mmu_fault_buffer_get_ptr_m() (U32(0xfffffU) << 0U) #define fb_mmu_fault_buffer_get_ptr_m() (U32(0xfffffU) << 0U)
#define fb_mmu_fault_buffer_get_ptr_v(r) (((r) >> 0U) & 0xfffffU) #define fb_mmu_fault_buffer_get_ptr_v(r) (((r) >> 0U) & 0xfffffU)
#define fb_mmu_fault_buffer_get_getptr_corrupted_f(v) (((v)&0x1U) << 30U) #define fb_mmu_fault_buffer_get_getptr_corrupted_f(v) ((U32(v) & 0x1U) << 30U)
#define fb_mmu_fault_buffer_get_getptr_corrupted_m() (U32(0x1U) << 30U) #define fb_mmu_fault_buffer_get_getptr_corrupted_m() (U32(0x1U) << 30U)
#define fb_mmu_fault_buffer_get_getptr_corrupted_clear_v() (0x00000001U) #define fb_mmu_fault_buffer_get_getptr_corrupted_clear_v() (0x00000001U)
#define fb_mmu_fault_buffer_get_getptr_corrupted_clear_f() (0x40000000U) #define fb_mmu_fault_buffer_get_getptr_corrupted_clear_f() (0x40000000U)
#define fb_mmu_fault_buffer_get_overflow_f(v) (((v)&0x1U) << 31U) #define fb_mmu_fault_buffer_get_overflow_f(v) ((U32(v) & 0x1U) << 31U)
#define fb_mmu_fault_buffer_get_overflow_m() (U32(0x1U) << 31U) #define fb_mmu_fault_buffer_get_overflow_m() (U32(0x1U) << 31U)
#define fb_mmu_fault_buffer_get_overflow_clear_v() (0x00000001U) #define fb_mmu_fault_buffer_get_overflow_clear_v() (0x00000001U)
#define fb_mmu_fault_buffer_get_overflow_clear_f() (0x80000000U) #define fb_mmu_fault_buffer_get_overflow_clear_f() (0x80000000U)
#define fb_mmu_fault_buffer_put_r(i)\ #define fb_mmu_fault_buffer_put_r(i)\
(nvgpu_safe_add_u32(0x00100e30U, nvgpu_safe_mult_u32((i), 20U))) (nvgpu_safe_add_u32(0x00100e30U, nvgpu_safe_mult_u32((i), 20U)))
#define fb_mmu_fault_buffer_put__size_1_v() (0x00000002U) #define fb_mmu_fault_buffer_put__size_1_v() (0x00000002U)
#define fb_mmu_fault_buffer_put_ptr_f(v) (((v)&0xfffffU) << 0U) #define fb_mmu_fault_buffer_put_ptr_f(v) ((U32(v) & 0xfffffU) << 0U)
#define fb_mmu_fault_buffer_put_ptr_v(r) (((r) >> 0U) & 0xfffffU) #define fb_mmu_fault_buffer_put_ptr_v(r) (((r) >> 0U) & 0xfffffU)
#define fb_mmu_fault_buffer_put_getptr_corrupted_f(v) (((v)&0x1U) << 30U) #define fb_mmu_fault_buffer_put_getptr_corrupted_f(v) ((U32(v) & 0x1U) << 30U)
#define fb_mmu_fault_buffer_put_getptr_corrupted_v(r) (((r) >> 30U) & 0x1U) #define fb_mmu_fault_buffer_put_getptr_corrupted_v(r) (((r) >> 30U) & 0x1U)
#define fb_mmu_fault_buffer_put_getptr_corrupted_yes_v() (0x00000001U) #define fb_mmu_fault_buffer_put_getptr_corrupted_yes_v() (0x00000001U)
#define fb_mmu_fault_buffer_put_getptr_corrupted_yes_f() (0x40000000U) #define fb_mmu_fault_buffer_put_getptr_corrupted_yes_f() (0x40000000U)
#define fb_mmu_fault_buffer_put_getptr_corrupted_no_v() (0x00000000U) #define fb_mmu_fault_buffer_put_getptr_corrupted_no_v() (0x00000000U)
#define fb_mmu_fault_buffer_put_getptr_corrupted_no_f() (0x0U) #define fb_mmu_fault_buffer_put_getptr_corrupted_no_f() (0x0U)
#define fb_mmu_fault_buffer_put_overflow_f(v) (((v)&0x1U) << 31U) #define fb_mmu_fault_buffer_put_overflow_f(v) ((U32(v) & 0x1U) << 31U)
#define fb_mmu_fault_buffer_put_overflow_v(r) (((r) >> 31U) & 0x1U) #define fb_mmu_fault_buffer_put_overflow_v(r) (((r) >> 31U) & 0x1U)
#define fb_mmu_fault_buffer_put_overflow_yes_v() (0x00000001U) #define fb_mmu_fault_buffer_put_overflow_yes_v() (0x00000001U)
#define fb_mmu_fault_buffer_put_overflow_yes_f() (0x80000000U) #define fb_mmu_fault_buffer_put_overflow_yes_f() (0x80000000U)
#define fb_mmu_fault_buffer_size_r(i)\ #define fb_mmu_fault_buffer_size_r(i)\
(nvgpu_safe_add_u32(0x00100e34U, nvgpu_safe_mult_u32((i), 20U))) (nvgpu_safe_add_u32(0x00100e34U, nvgpu_safe_mult_u32((i), 20U)))
#define fb_mmu_fault_buffer_size__size_1_v() (0x00000002U) #define fb_mmu_fault_buffer_size__size_1_v() (0x00000002U)
#define fb_mmu_fault_buffer_size_val_f(v) (((v)&0xfffffU) << 0U) #define fb_mmu_fault_buffer_size_val_f(v) ((U32(v) & 0xfffffU) << 0U)
#define fb_mmu_fault_buffer_size_val_v(r) (((r) >> 0U) & 0xfffffU) #define fb_mmu_fault_buffer_size_val_v(r) (((r) >> 0U) & 0xfffffU)
#define fb_mmu_fault_buffer_size_overflow_intr_f(v) (((v)&0x1U) << 29U) #define fb_mmu_fault_buffer_size_overflow_intr_f(v) ((U32(v) & 0x1U) << 29U)
#define fb_mmu_fault_buffer_size_overflow_intr_v(r) (((r) >> 29U) & 0x1U) #define fb_mmu_fault_buffer_size_overflow_intr_v(r) (((r) >> 29U) & 0x1U)
#define fb_mmu_fault_buffer_size_overflow_intr_enable_v() (0x00000001U) #define fb_mmu_fault_buffer_size_overflow_intr_enable_v() (0x00000001U)
#define fb_mmu_fault_buffer_size_overflow_intr_enable_f() (0x20000000U) #define fb_mmu_fault_buffer_size_overflow_intr_enable_f() (0x20000000U)
#define fb_mmu_fault_buffer_size_set_default_f(v) (((v)&0x1U) << 30U) #define fb_mmu_fault_buffer_size_set_default_f(v) ((U32(v) & 0x1U) << 30U)
#define fb_mmu_fault_buffer_size_set_default_v(r) (((r) >> 30U) & 0x1U) #define fb_mmu_fault_buffer_size_set_default_v(r) (((r) >> 30U) & 0x1U)
#define fb_mmu_fault_buffer_size_set_default_yes_v() (0x00000001U) #define fb_mmu_fault_buffer_size_set_default_yes_v() (0x00000001U)
#define fb_mmu_fault_buffer_size_set_default_yes_f() (0x40000000U) #define fb_mmu_fault_buffer_size_set_default_yes_f() (0x40000000U)
#define fb_mmu_fault_buffer_size_enable_f(v) (((v)&0x1U) << 31U) #define fb_mmu_fault_buffer_size_enable_f(v) ((U32(v) & 0x1U) << 31U)
#define fb_mmu_fault_buffer_size_enable_m() (U32(0x1U) << 31U) #define fb_mmu_fault_buffer_size_enable_m() (U32(0x1U) << 31U)
#define fb_mmu_fault_buffer_size_enable_v(r) (((r) >> 31U) & 0x1U) #define fb_mmu_fault_buffer_size_enable_v(r) (((r) >> 31U) & 0x1U)
#define fb_mmu_fault_buffer_size_enable_true_v() (0x00000001U) #define fb_mmu_fault_buffer_size_enable_true_v() (0x00000001U)
#define fb_mmu_fault_buffer_size_enable_true_f() (0x80000000U) #define fb_mmu_fault_buffer_size_enable_true_f() (0x80000000U)
#define fb_mmu_fault_addr_lo_r() (0x00100e4cU) #define fb_mmu_fault_addr_lo_r() (0x00100e4cU)
#define fb_mmu_fault_addr_lo_phys_aperture_f(v) (((v)&0x3U) << 0U) #define fb_mmu_fault_addr_lo_phys_aperture_f(v) ((U32(v) & 0x3U) << 0U)
#define fb_mmu_fault_addr_lo_phys_aperture_v(r) (((r) >> 0U) & 0x3U) #define fb_mmu_fault_addr_lo_phys_aperture_v(r) (((r) >> 0U) & 0x3U)
#define fb_mmu_fault_addr_lo_phys_aperture_sys_coh_v() (0x00000002U) #define fb_mmu_fault_addr_lo_phys_aperture_sys_coh_v() (0x00000002U)
#define fb_mmu_fault_addr_lo_phys_aperture_sys_coh_f() (0x2U) #define fb_mmu_fault_addr_lo_phys_aperture_sys_coh_f() (0x2U)
#define fb_mmu_fault_addr_lo_phys_aperture_sys_nocoh_v() (0x00000003U) #define fb_mmu_fault_addr_lo_phys_aperture_sys_nocoh_v() (0x00000003U)
#define fb_mmu_fault_addr_lo_phys_aperture_sys_nocoh_f() (0x3U) #define fb_mmu_fault_addr_lo_phys_aperture_sys_nocoh_f() (0x3U)
#define fb_mmu_fault_addr_lo_addr_f(v) (((v)&0xfffffU) << 12U) #define fb_mmu_fault_addr_lo_addr_f(v) ((U32(v) & 0xfffffU) << 12U)
#define fb_mmu_fault_addr_lo_addr_v(r) (((r) >> 12U) & 0xfffffU) #define fb_mmu_fault_addr_lo_addr_v(r) (((r) >> 12U) & 0xfffffU)
#define fb_mmu_fault_addr_hi_r() (0x00100e50U) #define fb_mmu_fault_addr_hi_r() (0x00100e50U)
#define fb_mmu_fault_addr_hi_addr_f(v) (((v)&0xffffffffU) << 0U) #define fb_mmu_fault_addr_hi_addr_f(v) ((U32(v) & 0xffffffffU) << 0U)
#define fb_mmu_fault_addr_hi_addr_v(r) (((r) >> 0U) & 0xffffffffU) #define fb_mmu_fault_addr_hi_addr_v(r) (((r) >> 0U) & 0xffffffffU)
#define fb_mmu_fault_inst_lo_r() (0x00100e54U) #define fb_mmu_fault_inst_lo_r() (0x00100e54U)
#define fb_mmu_fault_inst_lo_engine_id_v(r) (((r) >> 0U) & 0x1ffU) #define fb_mmu_fault_inst_lo_engine_id_v(r) (((r) >> 0U) & 0x1ffU)
#define fb_mmu_fault_inst_lo_aperture_v(r) (((r) >> 10U) & 0x3U) #define fb_mmu_fault_inst_lo_aperture_v(r) (((r) >> 10U) & 0x3U)
#define fb_mmu_fault_inst_lo_aperture_sys_coh_v() (0x00000002U) #define fb_mmu_fault_inst_lo_aperture_sys_coh_v() (0x00000002U)
#define fb_mmu_fault_inst_lo_aperture_sys_nocoh_v() (0x00000003U) #define fb_mmu_fault_inst_lo_aperture_sys_nocoh_v() (0x00000003U)
#define fb_mmu_fault_inst_lo_addr_f(v) (((v)&0xfffffU) << 12U) #define fb_mmu_fault_inst_lo_addr_f(v) ((U32(v) & 0xfffffU) << 12U)
#define fb_mmu_fault_inst_lo_addr_v(r) (((r) >> 12U) & 0xfffffU) #define fb_mmu_fault_inst_lo_addr_v(r) (((r) >> 12U) & 0xfffffU)
#define fb_mmu_fault_inst_hi_r() (0x00100e58U) #define fb_mmu_fault_inst_hi_r() (0x00100e58U)
#define fb_mmu_fault_inst_hi_addr_v(r) (((r) >> 0U) & 0xffffffffU) #define fb_mmu_fault_inst_hi_addr_v(r) (((r) >> 0U) & 0xffffffffU)
@@ -500,70 +506,70 @@
#define fb_niso_scrub_status_r() (0x00100b20U) #define fb_niso_scrub_status_r() (0x00100b20U)
#define fb_niso_scrub_status_flag_v(r) (((r) >> 0U) & 0x1U) #define fb_niso_scrub_status_flag_v(r) (((r) >> 0U) & 0x1U)
#define fb_mmu_priv_level_mask_r() (0x00100cdcU) #define fb_mmu_priv_level_mask_r() (0x00100cdcU)
#define fb_mmu_priv_level_mask_write_violation_f(v) (((v)&0x1U) << 7U) #define fb_mmu_priv_level_mask_write_violation_f(v) ((U32(v) & 0x1U) << 7U)
#define fb_mmu_priv_level_mask_write_violation_m() (U32(0x1U) << 7U) #define fb_mmu_priv_level_mask_write_violation_m() (U32(0x1U) << 7U)
#define fb_mmu_priv_level_mask_write_violation_v(r) (((r) >> 7U) & 0x1U) #define fb_mmu_priv_level_mask_write_violation_v(r) (((r) >> 7U) & 0x1U)
#define fb_hshub_config0_r() (0x001fbc00U) #define fb_hshub_config0_r() (0x001fbc00U)
#define fb_hshub_config0_sysmem_nvlink_mask_f(v) (((v)&0xffffU) << 0U) #define fb_hshub_config0_sysmem_nvlink_mask_f(v) ((U32(v) & 0xffffU) << 0U)
#define fb_hshub_config0_sysmem_nvlink_mask_m() (U32(0xffffU) << 0U) #define fb_hshub_config0_sysmem_nvlink_mask_m() (U32(0xffffU) << 0U)
#define fb_hshub_config0_sysmem_nvlink_mask_v(r) (((r) >> 0U) & 0xffffU) #define fb_hshub_config0_sysmem_nvlink_mask_v(r) (((r) >> 0U) & 0xffffU)
#define fb_hshub_config0_peer_pcie_mask_f(v) (((v)&0xffffU) << 16U) #define fb_hshub_config0_peer_pcie_mask_f(v) ((U32(v) & 0xffffU) << 16U)
#define fb_hshub_config0_peer_pcie_mask_v(r) (((r) >> 16U) & 0xffffU) #define fb_hshub_config0_peer_pcie_mask_v(r) (((r) >> 16U) & 0xffffU)
#define fb_hshub_config1_r() (0x001fbc04U) #define fb_hshub_config1_r() (0x001fbc04U)
#define fb_hshub_config1_peer_0_nvlink_mask_f(v) (((v)&0xffU) << 0U) #define fb_hshub_config1_peer_0_nvlink_mask_f(v) ((U32(v) & 0xffU) << 0U)
#define fb_hshub_config1_peer_0_nvlink_mask_v(r) (((r) >> 0U) & 0xffU) #define fb_hshub_config1_peer_0_nvlink_mask_v(r) (((r) >> 0U) & 0xffU)
#define fb_hshub_config1_peer_1_nvlink_mask_f(v) (((v)&0xffU) << 8U) #define fb_hshub_config1_peer_1_nvlink_mask_f(v) ((U32(v) & 0xffU) << 8U)
#define fb_hshub_config1_peer_1_nvlink_mask_v(r) (((r) >> 8U) & 0xffU) #define fb_hshub_config1_peer_1_nvlink_mask_v(r) (((r) >> 8U) & 0xffU)
#define fb_hshub_config1_peer_2_nvlink_mask_f(v) (((v)&0xffU) << 16U) #define fb_hshub_config1_peer_2_nvlink_mask_f(v) ((U32(v) & 0xffU) << 16U)
#define fb_hshub_config1_peer_2_nvlink_mask_v(r) (((r) >> 16U) & 0xffU) #define fb_hshub_config1_peer_2_nvlink_mask_v(r) (((r) >> 16U) & 0xffU)
#define fb_hshub_config1_peer_3_nvlink_mask_f(v) (((v)&0xffU) << 24U) #define fb_hshub_config1_peer_3_nvlink_mask_f(v) ((U32(v) & 0xffU) << 24U)
#define fb_hshub_config1_peer_3_nvlink_mask_v(r) (((r) >> 24U) & 0xffU) #define fb_hshub_config1_peer_3_nvlink_mask_v(r) (((r) >> 24U) & 0xffU)
#define fb_hshub_config2_r() (0x001fbc08U) #define fb_hshub_config2_r() (0x001fbc08U)
#define fb_hshub_config2_peer_4_nvlink_mask_f(v) (((v)&0xffU) << 0U) #define fb_hshub_config2_peer_4_nvlink_mask_f(v) ((U32(v) & 0xffU) << 0U)
#define fb_hshub_config2_peer_4_nvlink_mask_v(r) (((r) >> 0U) & 0xffU) #define fb_hshub_config2_peer_4_nvlink_mask_v(r) (((r) >> 0U) & 0xffU)
#define fb_hshub_config2_peer_5_nvlink_mask_f(v) (((v)&0xffU) << 8U) #define fb_hshub_config2_peer_5_nvlink_mask_f(v) ((U32(v) & 0xffU) << 8U)
#define fb_hshub_config2_peer_5_nvlink_mask_v(r) (((r) >> 8U) & 0xffU) #define fb_hshub_config2_peer_5_nvlink_mask_v(r) (((r) >> 8U) & 0xffU)
#define fb_hshub_config2_peer_6_nvlink_mask_f(v) (((v)&0xffU) << 16U) #define fb_hshub_config2_peer_6_nvlink_mask_f(v) ((U32(v) & 0xffU) << 16U)
#define fb_hshub_config2_peer_6_nvlink_mask_v(r) (((r) >> 16U) & 0xffU) #define fb_hshub_config2_peer_6_nvlink_mask_v(r) (((r) >> 16U) & 0xffU)
#define fb_hshub_config2_peer_7_nvlink_mask_f(v) (((v)&0xffU) << 24U) #define fb_hshub_config2_peer_7_nvlink_mask_f(v) ((U32(v) & 0xffU) << 24U)
#define fb_hshub_config2_peer_7_nvlink_mask_v(r) (((r) >> 24U) & 0xffU) #define fb_hshub_config2_peer_7_nvlink_mask_v(r) (((r) >> 24U) & 0xffU)
#define fb_hshub_config6_r() (0x001fbc18U) #define fb_hshub_config6_r() (0x001fbc18U)
#define fb_hshub_config7_r() (0x001fbc1cU) #define fb_hshub_config7_r() (0x001fbc1cU)
#define fb_hshub_config7_nvlink_logical_0_physical_portmap_f(v)\ #define fb_hshub_config7_nvlink_logical_0_physical_portmap_f(v)\
(((v)&0xfU) << 0U) ((U32(v) & 0xfU) << 0U)
#define fb_hshub_config7_nvlink_logical_0_physical_portmap_v(r)\ #define fb_hshub_config7_nvlink_logical_0_physical_portmap_v(r)\
(((r) >> 0U) & 0xfU) (((r) >> 0U) & 0xfU)
#define fb_hshub_config7_nvlink_logical_1_physical_portmap_f(v)\ #define fb_hshub_config7_nvlink_logical_1_physical_portmap_f(v)\
(((v)&0xfU) << 4U) ((U32(v) & 0xfU) << 4U)
#define fb_hshub_config7_nvlink_logical_1_physical_portmap_v(r)\ #define fb_hshub_config7_nvlink_logical_1_physical_portmap_v(r)\
(((r) >> 4U) & 0xfU) (((r) >> 4U) & 0xfU)
#define fb_hshub_config7_nvlink_logical_2_physical_portmap_f(v)\ #define fb_hshub_config7_nvlink_logical_2_physical_portmap_f(v)\
(((v)&0xfU) << 8U) ((U32(v) & 0xfU) << 8U)
#define fb_hshub_config7_nvlink_logical_2_physical_portmap_v(r)\ #define fb_hshub_config7_nvlink_logical_2_physical_portmap_v(r)\
(((r) >> 8U) & 0xfU) (((r) >> 8U) & 0xfU)
#define fb_hshub_config7_nvlink_logical_3_physical_portmap_f(v)\ #define fb_hshub_config7_nvlink_logical_3_physical_portmap_f(v)\
(((v)&0xfU) << 12U) ((U32(v) & 0xfU) << 12U)
#define fb_hshub_config7_nvlink_logical_3_physical_portmap_v(r)\ #define fb_hshub_config7_nvlink_logical_3_physical_portmap_v(r)\
(((r) >> 12U) & 0xfU) (((r) >> 12U) & 0xfU)
#define fb_hshub_config7_nvlink_logical_4_physical_portmap_f(v)\ #define fb_hshub_config7_nvlink_logical_4_physical_portmap_f(v)\
(((v)&0xfU) << 16U) ((U32(v) & 0xfU) << 16U)
#define fb_hshub_config7_nvlink_logical_4_physical_portmap_v(r)\ #define fb_hshub_config7_nvlink_logical_4_physical_portmap_v(r)\
(((r) >> 16U) & 0xfU) (((r) >> 16U) & 0xfU)
#define fb_hshub_config7_nvlink_logical_5_physical_portmap_f(v)\ #define fb_hshub_config7_nvlink_logical_5_physical_portmap_f(v)\
(((v)&0xfU) << 20U) ((U32(v) & 0xfU) << 20U)
#define fb_hshub_config7_nvlink_logical_5_physical_portmap_v(r)\ #define fb_hshub_config7_nvlink_logical_5_physical_portmap_v(r)\
(((r) >> 20U) & 0xfU) (((r) >> 20U) & 0xfU)
#define fb_hshub_config7_nvlink_logical_6_physical_portmap_f(v)\ #define fb_hshub_config7_nvlink_logical_6_physical_portmap_f(v)\
(((v)&0xfU) << 24U) ((U32(v) & 0xfU) << 24U)
#define fb_hshub_config7_nvlink_logical_6_physical_portmap_v(r)\ #define fb_hshub_config7_nvlink_logical_6_physical_portmap_v(r)\
(((r) >> 24U) & 0xfU) (((r) >> 24U) & 0xfU)
#define fb_hshub_config7_nvlink_logical_7_physical_portmap_f(v)\ #define fb_hshub_config7_nvlink_logical_7_physical_portmap_f(v)\
(((v)&0xfU) << 28U) ((U32(v) & 0xfU) << 28U)
#define fb_hshub_config7_nvlink_logical_7_physical_portmap_v(r)\ #define fb_hshub_config7_nvlink_logical_7_physical_portmap_v(r)\
(((r) >> 28U) & 0xfU) (((r) >> 28U) & 0xfU)
#define fb_hshub_nvl_cfg_priv_level_mask_r() (0x001fbc50U) #define fb_hshub_nvl_cfg_priv_level_mask_r() (0x001fbc50U)
#define fb_hshub_nvl_cfg_priv_level_mask_write_protection_f(v)\ #define fb_hshub_nvl_cfg_priv_level_mask_write_protection_f(v)\
(((v)&0x7U) << 4U) ((U32(v) & 0x7U) << 4U)
#define fb_hshub_nvl_cfg_priv_level_mask_write_protection_v(r)\ #define fb_hshub_nvl_cfg_priv_level_mask_write_protection_v(r)\
(((r) >> 4U) & 0x7U) (((r) >> 4U) & 0x7U)
#endif #endif

24
drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_fifo_gv100.h
View File

@@ -60,26 +60,26 @@
#include <nvgpu/safe_ops.h> #include <nvgpu/safe_ops.h>
#define fifo_userd_writeback_r() (0x0000225cU) #define fifo_userd_writeback_r() (0x0000225cU)
#define fifo_userd_writeback_timer_f(v) (((v)&0xffU) << 0U) #define fifo_userd_writeback_timer_f(v) ((U32(v) & 0xffU) << 0U)
#define fifo_userd_writeback_timer_disabled_v() (0x00000000U) #define fifo_userd_writeback_timer_disabled_v() (0x00000000U)
#define fifo_userd_writeback_timer_shorter_v() (0x00000003U) #define fifo_userd_writeback_timer_shorter_v() (0x00000003U)
#define fifo_userd_writeback_timer_100us_v() (0x00000064U) #define fifo_userd_writeback_timer_100us_v() (0x00000064U)
#define fifo_userd_writeback_timescale_f(v) (((v)&0xfU) << 12U) #define fifo_userd_writeback_timescale_f(v) ((U32(v) & 0xfU) << 12U)
#define fifo_userd_writeback_timescale_0_v() (0x00000000U) #define fifo_userd_writeback_timescale_0_v() (0x00000000U)
#define fifo_runlist_base_r() (0x00002270U) #define fifo_runlist_base_r() (0x00002270U)
#define fifo_runlist_base_ptr_f(v) (((v)&0xfffffffU) << 0U) #define fifo_runlist_base_ptr_f(v) ((U32(v) & 0xfffffffU) << 0U)
#define fifo_runlist_base_target_vid_mem_f() (0x0U) #define fifo_runlist_base_target_vid_mem_f() (0x0U)
#define fifo_runlist_base_target_sys_mem_coh_f() (0x20000000U) #define fifo_runlist_base_target_sys_mem_coh_f() (0x20000000U)
#define fifo_runlist_base_target_sys_mem_ncoh_f() (0x30000000U) #define fifo_runlist_base_target_sys_mem_ncoh_f() (0x30000000U)
#define fifo_runlist_r() (0x00002274U) #define fifo_runlist_r() (0x00002274U)
#define fifo_runlist_engine_f(v) (((v)&0xfU) << 20U) #define fifo_runlist_engine_f(v) ((U32(v) & 0xfU) << 20U)
#define fifo_eng_runlist_base_r(i)\ #define fifo_eng_runlist_base_r(i)\
(nvgpu_safe_add_u32(0x00002280U, nvgpu_safe_mult_u32((i), 8U))) (nvgpu_safe_add_u32(0x00002280U, nvgpu_safe_mult_u32((i), 8U)))
#define fifo_eng_runlist_base__size_1_v() (0x0000000dU) #define fifo_eng_runlist_base__size_1_v() (0x0000000dU)
#define fifo_eng_runlist_r(i)\ #define fifo_eng_runlist_r(i)\
(nvgpu_safe_add_u32(0x00002284U, nvgpu_safe_mult_u32((i), 8U))) (nvgpu_safe_add_u32(0x00002284U, nvgpu_safe_mult_u32((i), 8U)))
#define fifo_eng_runlist__size_1_v() (0x0000000dU) #define fifo_eng_runlist__size_1_v() (0x0000000dU)
#define fifo_eng_runlist_length_f(v) (((v)&0xffffU) << 0U) #define fifo_eng_runlist_length_f(v) ((U32(v) & 0xffffU) << 0U)
#define fifo_eng_runlist_length_max_v() (0x0000ffffU) #define fifo_eng_runlist_length_max_v() (0x0000ffffU)
#define fifo_eng_runlist_pending_true_f() (0x100000U) #define fifo_eng_runlist_pending_true_f() (0x100000U)
#define fifo_pb_timeslice_r(i)\ #define fifo_pb_timeslice_r(i)\
@@ -104,16 +104,16 @@
#define fifo_intr_0_runlist_event_pending_f() (0x40000000U) #define fifo_intr_0_runlist_event_pending_f() (0x40000000U)
#define fifo_intr_0_channel_intr_pending_f() (0x80000000U) #define fifo_intr_0_channel_intr_pending_f() (0x80000000U)
#define fifo_intr_en_0_r() (0x00002140U) #define fifo_intr_en_0_r() (0x00002140U)
#define fifo_intr_en_0_sched_error_f(v) (((v)&0x1U) << 8U) #define fifo_intr_en_0_sched_error_f(v) ((U32(v) & 0x1U) << 8U)
#define fifo_intr_en_0_sched_error_m() (U32(0x1U) << 8U) #define fifo_intr_en_0_sched_error_m() (U32(0x1U) << 8U)
#define fifo_intr_en_1_r() (0x00002528U) #define fifo_intr_en_1_r() (0x00002528U)
#define fifo_intr_bind_error_r() (0x0000252cU) #define fifo_intr_bind_error_r() (0x0000252cU)
#define fifo_intr_sched_error_r() (0x0000254cU) #define fifo_intr_sched_error_r() (0x0000254cU)
#define fifo_intr_sched_error_code_f(v) (((v)&0xffU) << 0U) #define fifo_intr_sched_error_code_f(v) ((U32(v) & 0xffU) << 0U)
#define fifo_intr_chsw_error_r() (0x0000256cU) #define fifo_intr_chsw_error_r() (0x0000256cU)
#define fifo_intr_pbdma_id_r() (0x000025a0U) #define fifo_intr_pbdma_id_r() (0x000025a0U)
#define fifo_intr_pbdma_id_status_f(v, i)\ #define fifo_intr_pbdma_id_status_f(v, i)\
(((v) & 0x1) << (0U + i*1U)) ((U32(v) & 0x1U) << (0U + (i)*1U))
#define fifo_intr_pbdma_id_status_v(r, i)\ #define fifo_intr_pbdma_id_status_v(r, i)\
(((r) >> (0U + i*1U)) & 0x1U) (((r) >> (0U + i*1U)) & 0x1U)
#define fifo_intr_pbdma_id_status__size_1_v() (0x0000000eU) #define fifo_intr_pbdma_id_status__size_1_v() (0x0000000eU)
@@ -124,13 +124,13 @@
#define fifo_fb_timeout_period_init_f() (0x3c00U) #define fifo_fb_timeout_period_init_f() (0x3c00U)
#define fifo_sched_disable_r() (0x00002630U) #define fifo_sched_disable_r() (0x00002630U)
#define fifo_sched_disable_runlist_f(v, i)\ #define fifo_sched_disable_runlist_f(v, i)\
(((v) & 0x1) << (0U + i*1U)) ((U32(v) & 0x1U) << (0U + (i)*1U))
#define fifo_sched_disable_runlist_m(i)\ #define fifo_sched_disable_runlist_m(i)\
(U32(0x1U) << (0U + (i)*1U)) (U32(0x1U) << (0U + (i)*1U))
#define fifo_sched_disable_true_v() (0x00000001U) #define fifo_sched_disable_true_v() (0x00000001U)
#define fifo_runlist_preempt_r() (0x00002638U) #define fifo_runlist_preempt_r() (0x00002638U)
#define fifo_runlist_preempt_runlist_f(v, i)\ #define fifo_runlist_preempt_runlist_f(v, i)\
(((v) & 0x1) << (0U + i*1U)) ((U32(v) & 0x1U) << (0U + (i)*1U))
#define fifo_runlist_preempt_runlist_m(i)\ #define fifo_runlist_preempt_runlist_m(i)\
(U32(0x1U) << (0U + (i)*1U)) (U32(0x1U) << (0U + (i)*1U))
#define fifo_runlist_preempt_runlist_pending_v() (0x00000001U) #define fifo_runlist_preempt_runlist_pending_v() (0x00000001U)
@@ -138,8 +138,8 @@
#define fifo_preempt_pending_true_f() (0x100000U) #define fifo_preempt_pending_true_f() (0x100000U)
#define fifo_preempt_type_channel_f() (0x0U) #define fifo_preempt_type_channel_f() (0x0U)
#define fifo_preempt_type_tsg_f() (0x1000000U) #define fifo_preempt_type_tsg_f() (0x1000000U)
#define fifo_preempt_chid_f(v) (((v)&0xfffU) << 0U) #define fifo_preempt_chid_f(v) ((U32(v) & 0xfffU) << 0U)
#define fifo_preempt_id_f(v) (((v)&0xfffU) << 0U) #define fifo_preempt_id_f(v) ((U32(v) & 0xfffU) << 0U)
#define fifo_engine_status_r(i)\ #define fifo_engine_status_r(i)\
(nvgpu_safe_add_u32(0x00002640U, nvgpu_safe_mult_u32((i), 8U))) (nvgpu_safe_add_u32(0x00002640U, nvgpu_safe_mult_u32((i), 8U)))
#define fifo_engine_status__size_1_v() (0x0000000fU) #define fifo_engine_status__size_1_v() (0x0000000fU)

6
drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_fuse_gv100.h
View File

@@ -65,17 +65,17 @@
#define fuse_ctrl_opt_tpc_gpc_r(i)\ #define fuse_ctrl_opt_tpc_gpc_r(i)\
(nvgpu_safe_add_u32(0x00021838U, nvgpu_safe_mult_u32((i), 4U))) (nvgpu_safe_add_u32(0x00021838U, nvgpu_safe_mult_u32((i), 4U)))
#define fuse_ctrl_opt_ram_svop_pdp_r() (0x00021944U) #define fuse_ctrl_opt_ram_svop_pdp_r() (0x00021944U)
#define fuse_ctrl_opt_ram_svop_pdp_data_f(v) (((v)&0xffU) << 0U) #define fuse_ctrl_opt_ram_svop_pdp_data_f(v) ((U32(v) & 0xffU) << 0U)
#define fuse_ctrl_opt_ram_svop_pdp_data_m() (U32(0xffU) << 0U) #define fuse_ctrl_opt_ram_svop_pdp_data_m() (U32(0xffU) << 0U)
#define fuse_ctrl_opt_ram_svop_pdp_data_v(r) (((r) >> 0U) & 0xffU) #define fuse_ctrl_opt_ram_svop_pdp_data_v(r) (((r) >> 0U) & 0xffU)
#define fuse_ctrl_opt_ram_svop_pdp_override_r() (0x00021948U) #define fuse_ctrl_opt_ram_svop_pdp_override_r() (0x00021948U)
#define fuse_ctrl_opt_ram_svop_pdp_override_data_f(v) (((v)&0x1U) << 0U) #define fuse_ctrl_opt_ram_svop_pdp_override_data_f(v) ((U32(v) & 0x1U) << 0U)
#define fuse_ctrl_opt_ram_svop_pdp_override_data_m() (U32(0x1U) << 0U) #define fuse_ctrl_opt_ram_svop_pdp_override_data_m() (U32(0x1U) << 0U)
#define fuse_ctrl_opt_ram_svop_pdp_override_data_v(r) (((r) >> 0U) & 0x1U) #define fuse_ctrl_opt_ram_svop_pdp_override_data_v(r) (((r) >> 0U) & 0x1U)
#define fuse_ctrl_opt_ram_svop_pdp_override_data_yes_f() (0x1U) #define fuse_ctrl_opt_ram_svop_pdp_override_data_yes_f() (0x1U)
#define fuse_ctrl_opt_ram_svop_pdp_override_data_no_f() (0x0U) #define fuse_ctrl_opt_ram_svop_pdp_override_data_no_f() (0x0U)
#define fuse_status_opt_fbio_r() (0x00021c14U) #define fuse_status_opt_fbio_r() (0x00021c14U)
#define fuse_status_opt_fbio_data_f(v) (((v)&0xffffU) << 0U) #define fuse_status_opt_fbio_data_f(v) ((U32(v) & 0xffffU) << 0U)
#define fuse_status_opt_fbio_data_m() (U32(0xffffU) << 0U) #define fuse_status_opt_fbio_data_m() (U32(0xffffU) << 0U)
#define fuse_status_opt_fbio_data_v(r) (((r) >> 0U) & 0xffffU) #define fuse_status_opt_fbio_data_v(r) (((r) >> 0U) & 0xffffU)
#define fuse_status_opt_rop_l2_fbp_r(i)\ #define fuse_status_opt_rop_l2_fbp_r(i)\

16
drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_gmmu_gv100.h
View File

@@ -66,7 +66,7 @@
#define gmmu_new_pde_aperture_video_memory_f() (0x2U) #define gmmu_new_pde_aperture_video_memory_f() (0x2U)
#define gmmu_new_pde_aperture_sys_mem_coh_f() (0x4U) #define gmmu_new_pde_aperture_sys_mem_coh_f() (0x4U)
#define gmmu_new_pde_aperture_sys_mem_ncoh_f() (0x6U) #define gmmu_new_pde_aperture_sys_mem_ncoh_f() (0x6U)
#define gmmu_new_pde_address_sys_f(v) (((v)&0xffffffU) << 8U) #define gmmu_new_pde_address_sys_f(v) ((U32(v) & 0xffffffU) << 8U)
#define gmmu_new_pde_address_sys_w() (0U) #define gmmu_new_pde_address_sys_w() (0U)
#define gmmu_new_pde_vol_w() (0U) #define gmmu_new_pde_vol_w() (0U)
#define gmmu_new_pde_vol_true_f() (0x8U) #define gmmu_new_pde_vol_true_f() (0x8U)
@@ -80,7 +80,7 @@
#define gmmu_new_dual_pde_aperture_big_video_memory_f() (0x2U) #define gmmu_new_dual_pde_aperture_big_video_memory_f() (0x2U)
#define gmmu_new_dual_pde_aperture_big_sys_mem_coh_f() (0x4U) #define gmmu_new_dual_pde_aperture_big_sys_mem_coh_f() (0x4U)
#define gmmu_new_dual_pde_aperture_big_sys_mem_ncoh_f() (0x6U) #define gmmu_new_dual_pde_aperture_big_sys_mem_ncoh_f() (0x6U)
#define gmmu_new_dual_pde_address_big_sys_f(v) (((v)&0xfffffffU) << 4U) #define gmmu_new_dual_pde_address_big_sys_f(v) ((U32(v) & 0xfffffffU) << 4U)
#define gmmu_new_dual_pde_address_big_sys_w() (0U) #define gmmu_new_dual_pde_address_big_sys_w() (0U)
#define gmmu_new_dual_pde_aperture_small_w() (2U) #define gmmu_new_dual_pde_aperture_small_w() (2U)
#define gmmu_new_dual_pde_aperture_small_invalid_f() (0x0U) #define gmmu_new_dual_pde_aperture_small_invalid_f() (0x0U)
@@ -93,7 +93,7 @@
#define gmmu_new_dual_pde_vol_big_w() (0U) #define gmmu_new_dual_pde_vol_big_w() (0U)
#define gmmu_new_dual_pde_vol_big_true_f() (0x8U) #define gmmu_new_dual_pde_vol_big_true_f() (0x8U)
#define gmmu_new_dual_pde_vol_big_false_f() (0x0U) #define gmmu_new_dual_pde_vol_big_false_f() (0x0U)
#define gmmu_new_dual_pde_address_small_sys_f(v) (((v)&0xffffffU) << 8U) #define gmmu_new_dual_pde_address_small_sys_f(v) ((U32(v) & 0xffffffU) << 8U)
#define gmmu_new_dual_pde_address_small_sys_w() (2U) #define gmmu_new_dual_pde_address_small_sys_w() (2U)
#define gmmu_new_dual_pde_address_shift_v() (0x0000000cU) #define gmmu_new_dual_pde_address_shift_v() (0x0000000cU)
#define gmmu_new_dual_pde_address_big_shift_v() (0x00000008U) #define gmmu_new_dual_pde_address_big_shift_v() (0x00000008U)
@@ -105,9 +105,9 @@
#define gmmu_new_pte_privilege_w() (0U) #define gmmu_new_pte_privilege_w() (0U)
#define gmmu_new_pte_privilege_true_f() (0x20U) #define gmmu_new_pte_privilege_true_f() (0x20U)
#define gmmu_new_pte_privilege_false_f() (0x0U) #define gmmu_new_pte_privilege_false_f() (0x0U)
#define gmmu_new_pte_address_sys_f(v) (((v)&0xffffffU) << 8U) #define gmmu_new_pte_address_sys_f(v) ((U32(v) & 0xffffffU) << 8U)
#define gmmu_new_pte_address_sys_w() (0U) #define gmmu_new_pte_address_sys_w() (0U)
#define gmmu_new_pte_address_vid_f(v) (((v)&0xffffffU) << 8U) #define gmmu_new_pte_address_vid_f(v) ((U32(v) & 0xffffffU) << 8U)
#define gmmu_new_pte_address_vid_w() (0U) #define gmmu_new_pte_address_vid_w() (0U)
#define gmmu_new_pte_vol_w() (0U) #define gmmu_new_pte_vol_w() (0U)
#define gmmu_new_pte_vol_true_f() (0x8U) #define gmmu_new_pte_vol_true_f() (0x8U)
@@ -118,12 +118,12 @@
#define gmmu_new_pte_aperture_sys_mem_ncoh_f() (0x6U) #define gmmu_new_pte_aperture_sys_mem_ncoh_f() (0x6U)
#define gmmu_new_pte_read_only_w() (0U) #define gmmu_new_pte_read_only_w() (0U)
#define gmmu_new_pte_read_only_true_f() (0x40U) #define gmmu_new_pte_read_only_true_f() (0x40U)
#define gmmu_new_pte_comptagline_f(v) (((v)&0x3ffffU) << 4U) #define gmmu_new_pte_comptagline_f(v) ((U32(v) & 0x3ffffU) << 4U)
#define gmmu_new_pte_comptagline_w() (1U) #define gmmu_new_pte_comptagline_w() (1U)
#define gmmu_new_pte_kind_f(v) (((v)&0xffU) << 24U) #define gmmu_new_pte_kind_f(v) ((U32(v) & 0xffU) << 24U)
#define gmmu_new_pte_kind_w() (1U) #define gmmu_new_pte_kind_w() (1U)
#define gmmu_new_pte_address_shift_v() (0x0000000cU) #define gmmu_new_pte_address_shift_v() (0x0000000cU)
#define gmmu_pte_kind_f(v) (((v)&0xffU) << 4U) #define gmmu_pte_kind_f(v) ((U32(v) & 0xffU) << 4U)
#define gmmu_pte_kind_w() (1U) #define gmmu_pte_kind_w() (1U)
#define gmmu_pte_kind_invalid_v() (0x000000ffU) #define gmmu_pte_kind_invalid_v() (0x000000ffU)
#define gmmu_pte_kind_pitch_v() (0x00000000U) #define gmmu_pte_kind_pitch_v() (0x00000000U)

372
drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_gr_gv100.h
View File

@@ -68,7 +68,7 @@
#define gr_intr_illegal_method_reset_f() (0x10U) #define gr_intr_illegal_method_reset_f() (0x10U)
#define gr_intr_illegal_notify_pending_f() (0x40U) #define gr_intr_illegal_notify_pending_f() (0x40U)
#define gr_intr_illegal_notify_reset_f() (0x40U) #define gr_intr_illegal_notify_reset_f() (0x40U)
#define gr_intr_firmware_method_f(v) (((v)&0x1U) << 8U) #define gr_intr_firmware_method_f(v) ((U32(v) & 0x1U) << 8U)
#define gr_intr_firmware_method_pending_f() (0x100U) #define gr_intr_firmware_method_pending_f() (0x100U)
#define gr_intr_firmware_method_reset_f() (0x100U) #define gr_intr_firmware_method_reset_f() (0x100U)
#define gr_intr_illegal_class_pending_f() (0x20U) #define gr_intr_illegal_class_pending_f() (0x20U)
@@ -120,10 +120,10 @@
#define gr_exception1_en_r() (0x00400130U) #define gr_exception1_en_r() (0x00400130U)
#define gr_exception2_en_r() (0x00400134U) #define gr_exception2_en_r() (0x00400134U)
#define gr_gpfifo_ctl_r() (0x00400500U) #define gr_gpfifo_ctl_r() (0x00400500U)
#define gr_gpfifo_ctl_access_f(v) (((v)&0x1U) << 0U) #define gr_gpfifo_ctl_access_f(v) ((U32(v) & 0x1U) << 0U)
#define gr_gpfifo_ctl_access_disabled_f() (0x0U) #define gr_gpfifo_ctl_access_disabled_f() (0x0U)
#define gr_gpfifo_ctl_access_enabled_f() (0x1U) #define gr_gpfifo_ctl_access_enabled_f() (0x1U)
#define gr_gpfifo_ctl_semaphore_access_f(v) (((v)&0x1U) << 16U) #define gr_gpfifo_ctl_semaphore_access_f(v) ((U32(v) & 0x1U) << 16U)
#define gr_gpfifo_ctl_semaphore_access_enabled_v() (0x00000001U) #define gr_gpfifo_ctl_semaphore_access_enabled_v() (0x00000001U)
#define gr_gpfifo_ctl_semaphore_access_enabled_f() (0x10000U) #define gr_gpfifo_ctl_semaphore_access_enabled_f() (0x10000U)
#define gr_gpfifo_status_r() (0x00400504U) #define gr_gpfifo_status_r() (0x00400504U)
@@ -159,7 +159,7 @@
#define gr_activity_2_r() (0x00400388U) #define gr_activity_2_r() (0x00400388U)
#define gr_activity_4_r() (0x00400390U) #define gr_activity_4_r() (0x00400390U)
#define gr_activity_4_gpc0_s() (3U) #define gr_activity_4_gpc0_s() (3U)
#define gr_activity_4_gpc0_f(v) (((v)&0x7U) << 0U) #define gr_activity_4_gpc0_f(v) ((U32(v) & 0x7U) << 0U)
#define gr_activity_4_gpc0_m() (U32(0x7U) << 0U) #define gr_activity_4_gpc0_m() (U32(0x7U) << 0U)
#define gr_activity_4_gpc0_v(r) (((r) >> 0U) & 0x7U) #define gr_activity_4_gpc0_v(r) (((r) >> 0U) & 0x7U)
#define gr_activity_4_gpc0_empty_v() (0x00000000U) #define gr_activity_4_gpc0_empty_v() (0x00000000U)
@@ -303,7 +303,7 @@
#define gr_pri_bes_zrop_status2_r() (0x0040884cU) #define gr_pri_bes_zrop_status2_r() (0x0040884cU)
#define gr_pipe_bundle_address_r() (0x00400200U) #define gr_pipe_bundle_address_r() (0x00400200U)
#define gr_pipe_bundle_address_value_v(r) (((r) >> 0U) & 0xffffU) #define gr_pipe_bundle_address_value_v(r) (((r) >> 0U) & 0xffffU)
#define gr_pipe_bundle_address_veid_f(v) (((v)&0x3fU) << 20U) #define gr_pipe_bundle_address_veid_f(v) ((U32(v) & 0x3fU) << 20U)
#define gr_pipe_bundle_address_veid_w() (0U) #define gr_pipe_bundle_address_veid_w() (0U)
#define gr_pipe_bundle_data_r() (0x00400204U) #define gr_pipe_bundle_data_r() (0x00400204U)
#define gr_pipe_bundle_config_r() (0x00400208U) #define gr_pipe_bundle_config_r() (0x00400208U)
@@ -338,7 +338,7 @@
#define gr_gpc0_tpc0_sm0_hww_global_esr_error_in_trap_m() (U32(0x1U) << 8U) #define gr_gpc0_tpc0_sm0_hww_global_esr_error_in_trap_m() (U32(0x1U) << 8U)
#define gr_gpc0_tpc0_sm0_hww_global_esr_error_in_trap_pending_f() (0x100U) #define gr_gpc0_tpc0_sm0_hww_global_esr_error_in_trap_pending_f() (0x100U)
#define gr_fe_go_idle_timeout_r() (0x00404154U) #define gr_fe_go_idle_timeout_r() (0x00404154U)
#define gr_fe_go_idle_timeout_count_f(v) (((v)&0xffffffffU) << 0U) #define gr_fe_go_idle_timeout_count_f(v) ((U32(v) & 0xffffffffU) << 0U)
#define gr_fe_go_idle_timeout_count_disabled_f() (0x0U) #define gr_fe_go_idle_timeout_count_disabled_f() (0x0U)
#define gr_fe_go_idle_timeout_count_prod_f() (0x1800U) #define gr_fe_go_idle_timeout_count_prod_f() (0x1800U)
#define gr_fe_object_table_r(i)\ #define gr_fe_object_table_r(i)\
@@ -357,11 +357,11 @@
#define gr_memfmt_hww_esr_reset_active_f() (0x40000000U) #define gr_memfmt_hww_esr_reset_active_f() (0x40000000U)
#define gr_memfmt_hww_esr_en_enable_f() (0x80000000U) #define gr_memfmt_hww_esr_en_enable_f() (0x80000000U)
#define gr_fecs_cpuctl_r() (0x00409100U) #define gr_fecs_cpuctl_r() (0x00409100U)
#define gr_fecs_cpuctl_startcpu_f(v) (((v)&0x1U) << 1U) #define gr_fecs_cpuctl_startcpu_f(v) ((U32(v) & 0x1U) << 1U)
#define gr_fecs_cpuctl_alias_r() (0x00409130U) #define gr_fecs_cpuctl_alias_r() (0x00409130U)
#define gr_fecs_cpuctl_alias_startcpu_f(v) (((v)&0x1U) << 1U) #define gr_fecs_cpuctl_alias_startcpu_f(v) ((U32(v) & 0x1U) << 1U)
#define gr_fecs_dmactl_r() (0x0040910cU) #define gr_fecs_dmactl_r() (0x0040910cU)
#define gr_fecs_dmactl_require_ctx_f(v) (((v)&0x1U) << 0U) #define gr_fecs_dmactl_require_ctx_f(v) ((U32(v) & 0x1U) << 0U)
#define gr_fecs_dmactl_dmem_scrubbing_m() (U32(0x1U) << 1U) #define gr_fecs_dmactl_dmem_scrubbing_m() (U32(0x1U) << 1U)
#define gr_fecs_dmactl_imem_scrubbing_m() (U32(0x1U) << 2U) #define gr_fecs_dmactl_imem_scrubbing_m() (U32(0x1U) << 2U)
#define gr_fecs_os_r() (0x00409080U) #define gr_fecs_os_r() (0x00409080U)
@@ -379,66 +379,66 @@
#define gr_fecs_debuginfo_r() (0x00409094U) #define gr_fecs_debuginfo_r() (0x00409094U)
#define gr_fecs_icd_cmd_r() (0x00409200U) #define gr_fecs_icd_cmd_r() (0x00409200U)
#define gr_fecs_icd_cmd_opc_s() (4U) #define gr_fecs_icd_cmd_opc_s() (4U)
#define gr_fecs_icd_cmd_opc_f(v) (((v)&0xfU) << 0U) #define gr_fecs_icd_cmd_opc_f(v) ((U32(v) & 0xfU) << 0U)
#define gr_fecs_icd_cmd_opc_m() (U32(0xfU) << 0U) #define gr_fecs_icd_cmd_opc_m() (U32(0xfU) << 0U)
#define gr_fecs_icd_cmd_opc_v(r) (((r) >> 0U) & 0xfU) #define gr_fecs_icd_cmd_opc_v(r) (((r) >> 0U) & 0xfU)
#define gr_fecs_icd_cmd_opc_rreg_f() (0x8U) #define gr_fecs_icd_cmd_opc_rreg_f() (0x8U)
#define gr_fecs_icd_cmd_opc_rstat_f() (0xeU) #define gr_fecs_icd_cmd_opc_rstat_f() (0xeU)
#define gr_fecs_icd_cmd_idx_f(v) (((v)&0x1fU) << 8U) #define gr_fecs_icd_cmd_idx_f(v) ((U32(v) & 0x1fU) << 8U)
#define gr_fecs_icd_rdata_r() (0x0040920cU) #define gr_fecs_icd_rdata_r() (0x0040920cU)
#define gr_fecs_imemc_r(i)\ #define gr_fecs_imemc_r(i)\
(nvgpu_safe_add_u32(0x00409180U, nvgpu_safe_mult_u32((i), 16U))) (nvgpu_safe_add_u32(0x00409180U, nvgpu_safe_mult_u32((i), 16U)))
#define gr_fecs_imemc_offs_f(v) (((v)&0x3fU) << 2U) #define gr_fecs_imemc_offs_f(v) ((U32(v) & 0x3fU) << 2U)
#define gr_fecs_imemc_blk_f(v) (((v)&0xffU) << 8U) #define gr_fecs_imemc_blk_f(v) ((U32(v) & 0xffU) << 8U)
#define gr_fecs_imemc_aincw_f(v) (((v)&0x1U) << 24U) #define gr_fecs_imemc_aincw_f(v) ((U32(v) & 0x1U) << 24U)
#define gr_fecs_imemd_r(i)\ #define gr_fecs_imemd_r(i)\
(nvgpu_safe_add_u32(0x00409184U, nvgpu_safe_mult_u32((i), 16U))) (nvgpu_safe_add_u32(0x00409184U, nvgpu_safe_mult_u32((i), 16U)))
#define gr_fecs_imemt_r(i)\ #define gr_fecs_imemt_r(i)\
(nvgpu_safe_add_u32(0x00409188U, nvgpu_safe_mult_u32((i), 16U))) (nvgpu_safe_add_u32(0x00409188U, nvgpu_safe_mult_u32((i), 16U)))
#define gr_fecs_imemt_tag_f(v) (((v)&0xffffU) << 0U) #define gr_fecs_imemt_tag_f(v) ((U32(v) & 0xffffU) << 0U)
#define gr_fecs_dmemc_r(i)\ #define gr_fecs_dmemc_r(i)\
(nvgpu_safe_add_u32(0x004091c0U, nvgpu_safe_mult_u32((i), 8U))) (nvgpu_safe_add_u32(0x004091c0U, nvgpu_safe_mult_u32((i), 8U)))
#define gr_fecs_dmemc_offs_s() (6U) #define gr_fecs_dmemc_offs_s() (6U)
#define gr_fecs_dmemc_offs_f(v) (((v)&0x3fU) << 2U) #define gr_fecs_dmemc_offs_f(v) ((U32(v) & 0x3fU) << 2U)
#define gr_fecs_dmemc_offs_m() (U32(0x3fU) << 2U) #define gr_fecs_dmemc_offs_m() (U32(0x3fU) << 2U)
#define gr_fecs_dmemc_offs_v(r) (((r) >> 2U) & 0x3fU) #define gr_fecs_dmemc_offs_v(r) (((r) >> 2U) & 0x3fU)
#define gr_fecs_dmemc_blk_f(v) (((v)&0xffU) << 8U) #define gr_fecs_dmemc_blk_f(v) ((U32(v) & 0xffU) << 8U)
#define gr_fecs_dmemc_aincw_f(v) (((v)&0x1U) << 24U) #define gr_fecs_dmemc_aincw_f(v) ((U32(v) & 0x1U) << 24U)
#define gr_fecs_dmemd_r(i)\ #define gr_fecs_dmemd_r(i)\
(nvgpu_safe_add_u32(0x004091c4U, nvgpu_safe_mult_u32((i), 8U))) (nvgpu_safe_add_u32(0x004091c4U, nvgpu_safe_mult_u32((i), 8U)))
#define gr_fecs_dmatrfbase_r() (0x00409110U) #define gr_fecs_dmatrfbase_r() (0x00409110U)
#define gr_fecs_dmatrfmoffs_r() (0x00409114U) #define gr_fecs_dmatrfmoffs_r() (0x00409114U)
#define gr_fecs_dmatrffboffs_r() (0x0040911cU) #define gr_fecs_dmatrffboffs_r() (0x0040911cU)
#define gr_fecs_dmatrfcmd_r() (0x00409118U) #define gr_fecs_dmatrfcmd_r() (0x00409118U)
#define gr_fecs_dmatrfcmd_imem_f(v) (((v)&0x1U) << 4U) #define gr_fecs_dmatrfcmd_imem_f(v) ((U32(v) & 0x1U) << 4U)
#define gr_fecs_dmatrfcmd_write_f(v) (((v)&0x1U) << 5U) #define gr_fecs_dmatrfcmd_write_f(v) ((U32(v) & 0x1U) << 5U)
#define gr_fecs_dmatrfcmd_size_f(v) (((v)&0x7U) << 8U) #define gr_fecs_dmatrfcmd_size_f(v) ((U32(v) & 0x7U) << 8U)
#define gr_fecs_dmatrfcmd_ctxdma_f(v) (((v)&0x7U) << 12U) #define gr_fecs_dmatrfcmd_ctxdma_f(v) ((U32(v) & 0x7U) << 12U)
#define gr_fecs_bootvec_r() (0x00409104U) #define gr_fecs_bootvec_r() (0x00409104U)
#define gr_fecs_bootvec_vec_f(v) (((v)&0xffffffffU) << 0U) #define gr_fecs_bootvec_vec_f(v) ((U32(v) & 0xffffffffU) << 0U)
#define gr_fecs_irqsset_r() (0x00409000U) #define gr_fecs_irqsset_r() (0x00409000U)
#define gr_fecs_falcon_hwcfg_r() (0x00409108U) #define gr_fecs_falcon_hwcfg_r() (0x00409108U)
#define gr_gpcs_gpccs_irqsset_r() (0x0041a000U) #define gr_gpcs_gpccs_irqsset_r() (0x0041a000U)
#define gr_gpcs_gpccs_falcon_hwcfg_r() (0x0041a108U) #define gr_gpcs_gpccs_falcon_hwcfg_r() (0x0041a108U)
#define gr_fecs_falcon_rm_r() (0x00409084U) #define gr_fecs_falcon_rm_r() (0x00409084U)
#define gr_fecs_current_ctx_r() (0x00409b00U) #define gr_fecs_current_ctx_r() (0x00409b00U)
#define gr_fecs_current_ctx_ptr_f(v) (((v)&0xfffffffU) << 0U) #define gr_fecs_current_ctx_ptr_f(v) ((U32(v) & 0xfffffffU) << 0U)
#define gr_fecs_current_ctx_ptr_v(r) (((r) >> 0U) & 0xfffffffU) #define gr_fecs_current_ctx_ptr_v(r) (((r) >> 0U) & 0xfffffffU)
#define gr_fecs_current_ctx_target_s() (2U) #define gr_fecs_current_ctx_target_s() (2U)
#define gr_fecs_current_ctx_target_f(v) (((v)&0x3U) << 28U) #define gr_fecs_current_ctx_target_f(v) ((U32(v) & 0x3U) << 28U)
#define gr_fecs_current_ctx_target_m() (U32(0x3U) << 28U) #define gr_fecs_current_ctx_target_m() (U32(0x3U) << 28U)
#define gr_fecs_current_ctx_target_v(r) (((r) >> 28U) & 0x3U) #define gr_fecs_current_ctx_target_v(r) (((r) >> 28U) & 0x3U)
#define gr_fecs_current_ctx_target_vid_mem_f() (0x0U) #define gr_fecs_current_ctx_target_vid_mem_f() (0x0U)
#define gr_fecs_current_ctx_target_sys_mem_coh_f() (0x20000000U) #define gr_fecs_current_ctx_target_sys_mem_coh_f() (0x20000000U)
#define gr_fecs_current_ctx_target_sys_mem_ncoh_f() (0x30000000U) #define gr_fecs_current_ctx_target_sys_mem_ncoh_f() (0x30000000U)
#define gr_fecs_current_ctx_valid_s() (1U) #define gr_fecs_current_ctx_valid_s() (1U)
#define gr_fecs_current_ctx_valid_f(v) (((v)&0x1U) << 31U) #define gr_fecs_current_ctx_valid_f(v) ((U32(v) & 0x1U) << 31U)
#define gr_fecs_current_ctx_valid_m() (U32(0x1U) << 31U) #define gr_fecs_current_ctx_valid_m() (U32(0x1U) << 31U)
#define gr_fecs_current_ctx_valid_v(r) (((r) >> 31U) & 0x1U) #define gr_fecs_current_ctx_valid_v(r) (((r) >> 31U) & 0x1U)
#define gr_fecs_current_ctx_valid_false_f() (0x0U) #define gr_fecs_current_ctx_valid_false_f() (0x0U)
#define gr_fecs_method_data_r() (0x00409500U) #define gr_fecs_method_data_r() (0x00409500U)
#define gr_fecs_method_push_r() (0x00409504U) #define gr_fecs_method_push_r() (0x00409504U)
#define gr_fecs_method_push_adr_f(v) (((v)&0xfffU) << 0U) #define gr_fecs_method_push_adr_f(v) ((U32(v) & 0xfffU) << 0U)
#define gr_fecs_method_push_adr_bind_pointer_v() (0x00000003U) #define gr_fecs_method_push_adr_bind_pointer_v() (0x00000003U)
#define gr_fecs_method_push_adr_bind_pointer_f() (0x3U) #define gr_fecs_method_push_adr_bind_pointer_f() (0x3U)
#define gr_fecs_method_push_adr_discover_image_size_v() (0x00000010U) #define gr_fecs_method_push_adr_discover_image_size_v() (0x00000010U)
@@ -457,12 +457,14 @@
#define gr_fecs_method_push_adr_configure_interrupt_completion_option_v()\ #define gr_fecs_method_push_adr_configure_interrupt_completion_option_v()\
(0x0000003aU) (0x0000003aU)
#define gr_fecs_host_int_status_r() (0x00409c18U) #define gr_fecs_host_int_status_r() (0x00409c18U)
#define gr_fecs_host_int_status_fault_during_ctxsw_f(v) (((v)&0x1U) << 16U) #define gr_fecs_host_int_status_fault_during_ctxsw_f(v) ((U32(v) & 0x1U) << 16U)
#define gr_fecs_host_int_status_umimp_firmware_method_f(v) (((v)&0x1U) << 17U) #define gr_fecs_host_int_status_umimp_firmware_method_f(v)\
#define gr_fecs_host_int_status_umimp_illegal_method_f(v) (((v)&0x1U) << 18U) ((U32(v) & 0x1U) << 17U)
#define gr_fecs_host_int_status_ctxsw_intr_f(v) (((v)&0xffffU) << 0U) #define gr_fecs_host_int_status_umimp_illegal_method_f(v)\
((U32(v) & 0x1U) << 18U)
#define gr_fecs_host_int_status_ctxsw_intr_f(v) ((U32(v) & 0xffffU) << 0U)
#define gr_fecs_host_int_clear_r() (0x00409c20U) #define gr_fecs_host_int_clear_r() (0x00409c20U)
#define gr_fecs_host_int_clear_ctxsw_intr1_f(v) (((v)&0x1U) << 1U) #define gr_fecs_host_int_clear_ctxsw_intr1_f(v) ((U32(v) & 0x1U) << 1U)
#define gr_fecs_host_int_clear_ctxsw_intr1_clear_f() (0x2U) #define gr_fecs_host_int_clear_ctxsw_intr1_clear_f() (0x2U)
#define gr_fecs_host_int_enable_r() (0x00409c24U) #define gr_fecs_host_int_enable_r() (0x00409c24U)
#define gr_fecs_host_int_enable_ctxsw_intr1_enable_f() (0x2U) #define gr_fecs_host_int_enable_ctxsw_intr1_enable_f() (0x2U)
@@ -482,7 +484,7 @@
#define gr_fecs_ctxsw_reset_ctl_gpc_context_reset_enabled_f() (0x0U) #define gr_fecs_ctxsw_reset_ctl_gpc_context_reset_enabled_f() (0x0U)
#define gr_fecs_ctxsw_reset_ctl_gpc_context_reset_disabled_f() (0x200U) #define gr_fecs_ctxsw_reset_ctl_gpc_context_reset_disabled_f() (0x200U)
#define gr_fecs_ctxsw_reset_ctl_be_context_reset_s() (1U) #define gr_fecs_ctxsw_reset_ctl_be_context_reset_s() (1U)
#define gr_fecs_ctxsw_reset_ctl_be_context_reset_f(v) (((v)&0x1U) << 10U) #define gr_fecs_ctxsw_reset_ctl_be_context_reset_f(v) ((U32(v) & 0x1U) << 10U)
#define gr_fecs_ctxsw_reset_ctl_be_context_reset_m() (U32(0x1U) << 10U) #define gr_fecs_ctxsw_reset_ctl_be_context_reset_m() (U32(0x1U) << 10U)
#define gr_fecs_ctxsw_reset_ctl_be_context_reset_v(r) (((r) >> 10U) & 0x1U) #define gr_fecs_ctxsw_reset_ctl_be_context_reset_v(r) (((r) >> 10U) & 0x1U)
#define gr_fecs_ctxsw_reset_ctl_be_context_reset_enabled_f() (0x0U) #define gr_fecs_ctxsw_reset_ctl_be_context_reset_enabled_f() (0x0U)
@@ -491,62 +493,62 @@
#define gr_fecs_ctxsw_mailbox_r(i)\ #define gr_fecs_ctxsw_mailbox_r(i)\
(nvgpu_safe_add_u32(0x00409800U, nvgpu_safe_mult_u32((i), 4U))) (nvgpu_safe_add_u32(0x00409800U, nvgpu_safe_mult_u32((i), 4U)))
#define gr_fecs_ctxsw_mailbox__size_1_v() (0x00000010U) #define gr_fecs_ctxsw_mailbox__size_1_v() (0x00000010U)
#define gr_fecs_ctxsw_mailbox_value_f(v) (((v)&0xffffffffU) << 0U) #define gr_fecs_ctxsw_mailbox_value_f(v) ((U32(v) & 0xffffffffU) << 0U)
#define gr_fecs_ctxsw_mailbox_value_pass_v() (0x00000001U) #define gr_fecs_ctxsw_mailbox_value_pass_v() (0x00000001U)
#define gr_fecs_ctxsw_mailbox_value_fail_v() (0x00000002U) #define gr_fecs_ctxsw_mailbox_value_fail_v() (0x00000002U)
#define gr_fecs_ctxsw_mailbox_set_r(i)\ #define gr_fecs_ctxsw_mailbox_set_r(i)\
(nvgpu_safe_add_u32(0x004098c0U, nvgpu_safe_mult_u32((i), 4U))) (nvgpu_safe_add_u32(0x004098c0U, nvgpu_safe_mult_u32((i), 4U)))
#define gr_fecs_ctxsw_mailbox_set_value_f(v) (((v)&0xffffffffU) << 0U) #define gr_fecs_ctxsw_mailbox_set_value_f(v) ((U32(v) & 0xffffffffU) << 0U)
#define gr_fecs_ctxsw_mailbox_clear_r(i)\ #define gr_fecs_ctxsw_mailbox_clear_r(i)\
(nvgpu_safe_add_u32(0x00409840U, nvgpu_safe_mult_u32((i), 4U))) (nvgpu_safe_add_u32(0x00409840U, nvgpu_safe_mult_u32((i), 4U)))
#define gr_fecs_ctxsw_mailbox_clear_value_f(v) (((v)&0xffffffffU) << 0U) #define gr_fecs_ctxsw_mailbox_clear_value_f(v) ((U32(v) & 0xffffffffU) << 0U)
#define gr_fecs_fs_r() (0x00409604U) #define gr_fecs_fs_r() (0x00409604U)
#define gr_fecs_fs_num_available_gpcs_s() (5U) #define gr_fecs_fs_num_available_gpcs_s() (5U)
#define gr_fecs_fs_num_available_gpcs_f(v) (((v)&0x1fU) << 0U) #define gr_fecs_fs_num_available_gpcs_f(v) ((U32(v) & 0x1fU) << 0U)
#define gr_fecs_fs_num_available_gpcs_m() (U32(0x1fU) << 0U) #define gr_fecs_fs_num_available_gpcs_m() (U32(0x1fU) << 0U)
#define gr_fecs_fs_num_available_gpcs_v(r) (((r) >> 0U) & 0x1fU) #define gr_fecs_fs_num_available_gpcs_v(r) (((r) >> 0U) & 0x1fU)
#define gr_fecs_fs_num_available_fbps_s() (5U) #define gr_fecs_fs_num_available_fbps_s() (5U)
#define gr_fecs_fs_num_available_fbps_f(v) (((v)&0x1fU) << 16U) #define gr_fecs_fs_num_available_fbps_f(v) ((U32(v) & 0x1fU) << 16U)
#define gr_fecs_fs_num_available_fbps_m() (U32(0x1fU) << 16U) #define gr_fecs_fs_num_available_fbps_m() (U32(0x1fU) << 16U)
#define gr_fecs_fs_num_available_fbps_v(r) (((r) >> 16U) & 0x1fU) #define gr_fecs_fs_num_available_fbps_v(r) (((r) >> 16U) & 0x1fU)
#define gr_fecs_cfg_r() (0x00409620U) #define gr_fecs_cfg_r() (0x00409620U)
#define gr_fecs_cfg_imem_sz_v(r) (((r) >> 0U) & 0xffU) #define gr_fecs_cfg_imem_sz_v(r) (((r) >> 0U) & 0xffU)
#define gr_fecs_rc_lanes_r() (0x00409880U) #define gr_fecs_rc_lanes_r() (0x00409880U)
#define gr_fecs_rc_lanes_num_chains_s() (6U) #define gr_fecs_rc_lanes_num_chains_s() (6U)
#define gr_fecs_rc_lanes_num_chains_f(v) (((v)&0x3fU) << 0U) #define gr_fecs_rc_lanes_num_chains_f(v) ((U32(v) & 0x3fU) << 0U)
#define gr_fecs_rc_lanes_num_chains_m() (U32(0x3fU) << 0U) #define gr_fecs_rc_lanes_num_chains_m() (U32(0x3fU) << 0U)
#define gr_fecs_rc_lanes_num_chains_v(r) (((r) >> 0U) & 0x3fU) #define gr_fecs_rc_lanes_num_chains_v(r) (((r) >> 0U) & 0x3fU)
#define gr_fecs_ctxsw_status_1_r() (0x00409400U) #define gr_fecs_ctxsw_status_1_r() (0x00409400U)
#define gr_fecs_ctxsw_status_1_arb_busy_s() (1U) #define gr_fecs_ctxsw_status_1_arb_busy_s() (1U)
#define gr_fecs_ctxsw_status_1_arb_busy_f(v) (((v)&0x1U) << 12U) #define gr_fecs_ctxsw_status_1_arb_busy_f(v) ((U32(v) & 0x1U) << 12U)
#define gr_fecs_ctxsw_status_1_arb_busy_m() (U32(0x1U) << 12U) #define gr_fecs_ctxsw_status_1_arb_busy_m() (U32(0x1U) << 12U)
#define gr_fecs_ctxsw_status_1_arb_busy_v(r) (((r) >> 12U) & 0x1U) #define gr_fecs_ctxsw_status_1_arb_busy_v(r) (((r) >> 12U) & 0x1U)
#define gr_fecs_arb_ctx_adr_r() (0x00409a24U) #define gr_fecs_arb_ctx_adr_r() (0x00409a24U)
#define gr_fecs_new_ctx_r() (0x00409b04U) #define gr_fecs_new_ctx_r() (0x00409b04U)
#define gr_fecs_new_ctx_ptr_s() (28U) #define gr_fecs_new_ctx_ptr_s() (28U)
#define gr_fecs_new_ctx_ptr_f(v) (((v)&0xfffffffU) << 0U) #define gr_fecs_new_ctx_ptr_f(v) ((U32(v) & 0xfffffffU) << 0U)
#define gr_fecs_new_ctx_ptr_m() (U32(0xfffffffU) << 0U) #define gr_fecs_new_ctx_ptr_m() (U32(0xfffffffU) << 0U)
#define gr_fecs_new_ctx_ptr_v(r) (((r) >> 0U) & 0xfffffffU) #define gr_fecs_new_ctx_ptr_v(r) (((r) >> 0U) & 0xfffffffU)
#define gr_fecs_new_ctx_target_s() (2U) #define gr_fecs_new_ctx_target_s() (2U)
#define gr_fecs_new_ctx_target_f(v) (((v)&0x3U) << 28U) #define gr_fecs_new_ctx_target_f(v) ((U32(v) & 0x3U) << 28U)
#define gr_fecs_new_ctx_target_m() (U32(0x3U) << 28U) #define gr_fecs_new_ctx_target_m() (U32(0x3U) << 28U)
#define gr_fecs_new_ctx_target_v(r) (((r) >> 28U) & 0x3U) #define gr_fecs_new_ctx_target_v(r) (((r) >> 28U) & 0x3U)
#define gr_fecs_new_ctx_valid_s() (1U) #define gr_fecs_new_ctx_valid_s() (1U)
#define gr_fecs_new_ctx_valid_f(v) (((v)&0x1U) << 31U) #define gr_fecs_new_ctx_valid_f(v) ((U32(v) & 0x1U) << 31U)
#define gr_fecs_new_ctx_valid_m() (U32(0x1U) << 31U) #define gr_fecs_new_ctx_valid_m() (U32(0x1U) << 31U)
#define gr_fecs_new_ctx_valid_v(r) (((r) >> 31U) & 0x1U) #define gr_fecs_new_ctx_valid_v(r) (((r) >> 31U) & 0x1U)
#define gr_fecs_arb_ctx_ptr_r() (0x00409a0cU) #define gr_fecs_arb_ctx_ptr_r() (0x00409a0cU)
#define gr_fecs_arb_ctx_ptr_ptr_s() (28U) #define gr_fecs_arb_ctx_ptr_ptr_s() (28U)
#define gr_fecs_arb_ctx_ptr_ptr_f(v) (((v)&0xfffffffU) << 0U) #define gr_fecs_arb_ctx_ptr_ptr_f(v) ((U32(v) & 0xfffffffU) << 0U)
#define gr_fecs_arb_ctx_ptr_ptr_m() (U32(0xfffffffU) << 0U) #define gr_fecs_arb_ctx_ptr_ptr_m() (U32(0xfffffffU) << 0U)
#define gr_fecs_arb_ctx_ptr_ptr_v(r) (((r) >> 0U) & 0xfffffffU) #define gr_fecs_arb_ctx_ptr_ptr_v(r) (((r) >> 0U) & 0xfffffffU)
#define gr_fecs_arb_ctx_ptr_target_s() (2U) #define gr_fecs_arb_ctx_ptr_target_s() (2U)
#define gr_fecs_arb_ctx_ptr_target_f(v) (((v)&0x3U) << 28U) #define gr_fecs_arb_ctx_ptr_target_f(v) ((U32(v) & 0x3U) << 28U)
#define gr_fecs_arb_ctx_ptr_target_m() (U32(0x3U) << 28U) #define gr_fecs_arb_ctx_ptr_target_m() (U32(0x3U) << 28U)
#define gr_fecs_arb_ctx_ptr_target_v(r) (((r) >> 28U) & 0x3U) #define gr_fecs_arb_ctx_ptr_target_v(r) (((r) >> 28U) & 0x3U)
#define gr_fecs_arb_ctx_cmd_r() (0x00409a10U) #define gr_fecs_arb_ctx_cmd_r() (0x00409a10U)
#define gr_fecs_arb_ctx_cmd_cmd_s() (5U) #define gr_fecs_arb_ctx_cmd_cmd_s() (5U)
#define gr_fecs_arb_ctx_cmd_cmd_f(v) (((v)&0x1fU) << 0U) #define gr_fecs_arb_ctx_cmd_cmd_f(v) ((U32(v) & 0x1fU) << 0U)
#define gr_fecs_arb_ctx_cmd_cmd_m() (U32(0x1fU) << 0U) #define gr_fecs_arb_ctx_cmd_cmd_m() (U32(0x1fU) << 0U)
#define gr_fecs_arb_ctx_cmd_cmd_v(r) (((r) >> 0U) & 0x1fU) #define gr_fecs_arb_ctx_cmd_cmd_v(r) (((r) >> 0U) & 0x1fU)
#define gr_fecs_ctxsw_status_fe_0_r() (0x00409c00U) #define gr_fecs_ctxsw_status_fe_0_r() (0x00409c00U)
@@ -562,55 +564,55 @@
#define gr_rstr2d_gpc_map_r(i)\ #define gr_rstr2d_gpc_map_r(i)\
(nvgpu_safe_add_u32(0x0040780cU, nvgpu_safe_mult_u32((i), 4U))) (nvgpu_safe_add_u32(0x0040780cU, nvgpu_safe_mult_u32((i), 4U)))
#define gr_rstr2d_map_table_cfg_r() (0x004078bcU) #define gr_rstr2d_map_table_cfg_r() (0x004078bcU)
#define gr_rstr2d_map_table_cfg_row_offset_f(v) (((v)&0xffU) << 0U) #define gr_rstr2d_map_table_cfg_row_offset_f(v) ((U32(v) & 0xffU) << 0U)
#define gr_rstr2d_map_table_cfg_num_entries_f(v) (((v)&0xffU) << 8U) #define gr_rstr2d_map_table_cfg_num_entries_f(v) ((U32(v) & 0xffU) << 8U)
#define gr_pd_hww_esr_r() (0x00406018U) #define gr_pd_hww_esr_r() (0x00406018U)
#define gr_pd_hww_esr_reset_active_f() (0x40000000U) #define gr_pd_hww_esr_reset_active_f() (0x40000000U)
#define gr_pd_hww_esr_en_enable_f() (0x80000000U) #define gr_pd_hww_esr_en_enable_f() (0x80000000U)
#define gr_pd_num_tpc_per_gpc_r(i)\ #define gr_pd_num_tpc_per_gpc_r(i)\
(nvgpu_safe_add_u32(0x00406028U, nvgpu_safe_mult_u32((i), 4U))) (nvgpu_safe_add_u32(0x00406028U, nvgpu_safe_mult_u32((i), 4U)))
#define gr_pd_num_tpc_per_gpc__size_1_v() (0x00000004U) #define gr_pd_num_tpc_per_gpc__size_1_v() (0x00000004U)
#define gr_pd_num_tpc_per_gpc_count0_f(v) (((v)&0xfU) << 0U) #define gr_pd_num_tpc_per_gpc_count0_f(v) ((U32(v) & 0xfU) << 0U)
#define gr_pd_num_tpc_per_gpc_count1_f(v) (((v)&0xfU) << 4U) #define gr_pd_num_tpc_per_gpc_count1_f(v) ((U32(v) & 0xfU) << 4U)
#define gr_pd_num_tpc_per_gpc_count2_f(v) (((v)&0xfU) << 8U) #define gr_pd_num_tpc_per_gpc_count2_f(v) ((U32(v) & 0xfU) << 8U)
#define gr_pd_num_tpc_per_gpc_count3_f(v) (((v)&0xfU) << 12U) #define gr_pd_num_tpc_per_gpc_count3_f(v) ((U32(v) & 0xfU) << 12U)
#define gr_pd_num_tpc_per_gpc_count4_f(v) (((v)&0xfU) << 16U) #define gr_pd_num_tpc_per_gpc_count4_f(v) ((U32(v) & 0xfU) << 16U)
#define gr_pd_num_tpc_per_gpc_count5_f(v) (((v)&0xfU) << 20U) #define gr_pd_num_tpc_per_gpc_count5_f(v) ((U32(v) & 0xfU) << 20U)
#define gr_pd_num_tpc_per_gpc_count6_f(v) (((v)&0xfU) << 24U) #define gr_pd_num_tpc_per_gpc_count6_f(v) ((U32(v) & 0xfU) << 24U)
#define gr_pd_num_tpc_per_gpc_count7_f(v) (((v)&0xfU) << 28U) #define gr_pd_num_tpc_per_gpc_count7_f(v) ((U32(v) & 0xfU) << 28U)
#define gr_pd_ab_dist_cfg0_r() (0x004064c0U) #define gr_pd_ab_dist_cfg0_r() (0x004064c0U)
#define gr_pd_ab_dist_cfg0_timeslice_enable_en_f() (0x80000000U) #define gr_pd_ab_dist_cfg0_timeslice_enable_en_f() (0x80000000U)
#define gr_pd_ab_dist_cfg0_timeslice_enable_dis_f() (0x0U) #define gr_pd_ab_dist_cfg0_timeslice_enable_dis_f() (0x0U)
#define gr_pd_ab_dist_cfg1_r() (0x004064c4U) #define gr_pd_ab_dist_cfg1_r() (0x004064c4U)
#define gr_pd_ab_dist_cfg1_max_batches_init_f() (0xffffU) #define gr_pd_ab_dist_cfg1_max_batches_init_f() (0xffffU)
#define gr_pd_ab_dist_cfg1_max_output_f(v) (((v)&0xffffU) << 16U) #define gr_pd_ab_dist_cfg1_max_output_f(v) ((U32(v) & 0xffffU) << 16U)
#define gr_pd_ab_dist_cfg1_max_output_granularity_v() (0x00000080U) #define gr_pd_ab_dist_cfg1_max_output_granularity_v() (0x00000080U)
#define gr_pd_ab_dist_cfg2_r() (0x004064c8U) #define gr_pd_ab_dist_cfg2_r() (0x004064c8U)
#define gr_pd_ab_dist_cfg2_token_limit_f(v) (((v)&0x1fffU) << 0U) #define gr_pd_ab_dist_cfg2_token_limit_f(v) ((U32(v) & 0x1fffU) << 0U)
#define gr_pd_ab_dist_cfg2_token_limit_init_v() (0x00001680U) #define gr_pd_ab_dist_cfg2_token_limit_init_v() (0x00001680U)
#define gr_pd_ab_dist_cfg2_state_limit_f(v) (((v)&0x1fffU) << 16U) #define gr_pd_ab_dist_cfg2_state_limit_f(v) ((U32(v) & 0x1fffU) << 16U)
#define gr_pd_ab_dist_cfg2_state_limit_scc_bundle_granularity_v() (0x00000020U) #define gr_pd_ab_dist_cfg2_state_limit_scc_bundle_granularity_v() (0x00000020U)
#define gr_pd_ab_dist_cfg2_state_limit_min_gpm_fifo_depths_v() (0x00001680U) #define gr_pd_ab_dist_cfg2_state_limit_min_gpm_fifo_depths_v() (0x00001680U)
#define gr_pd_dist_skip_table_r(i)\ #define gr_pd_dist_skip_table_r(i)\
(nvgpu_safe_add_u32(0x004064d0U, nvgpu_safe_mult_u32((i), 4U))) (nvgpu_safe_add_u32(0x004064d0U, nvgpu_safe_mult_u32((i), 4U)))
#define gr_pd_dist_skip_table__size_1_v() (0x00000008U) #define gr_pd_dist_skip_table__size_1_v() (0x00000008U)
#define gr_pd_dist_skip_table_gpc_4n0_mask_f(v) (((v)&0xffU) << 0U) #define gr_pd_dist_skip_table_gpc_4n0_mask_f(v) ((U32(v) & 0xffU) << 0U)
#define gr_pd_dist_skip_table_gpc_4n1_mask_f(v) (((v)&0xffU) << 8U) #define gr_pd_dist_skip_table_gpc_4n1_mask_f(v) ((U32(v) & 0xffU) << 8U)
#define gr_pd_dist_skip_table_gpc_4n2_mask_f(v) (((v)&0xffU) << 16U) #define gr_pd_dist_skip_table_gpc_4n2_mask_f(v) ((U32(v) & 0xffU) << 16U)
#define gr_pd_dist_skip_table_gpc_4n3_mask_f(v) (((v)&0xffU) << 24U) #define gr_pd_dist_skip_table_gpc_4n3_mask_f(v) ((U32(v) & 0xffU) << 24U)
#define gr_ds_debug_r() (0x00405800U) #define gr_ds_debug_r() (0x00405800U)
#define gr_ds_debug_timeslice_mode_disable_f() (0x0U) #define gr_ds_debug_timeslice_mode_disable_f() (0x0U)
#define gr_ds_debug_timeslice_mode_enable_f() (0x8000000U) #define gr_ds_debug_timeslice_mode_enable_f() (0x8000000U)
#define gr_ds_zbc_color_r_r() (0x00405804U) #define gr_ds_zbc_color_r_r() (0x00405804U)
#define gr_ds_zbc_color_r_val_f(v) (((v)&0xffffffffU) << 0U) #define gr_ds_zbc_color_r_val_f(v) ((U32(v) & 0xffffffffU) << 0U)
#define gr_ds_zbc_color_g_r() (0x00405808U) #define gr_ds_zbc_color_g_r() (0x00405808U)
#define gr_ds_zbc_color_g_val_f(v) (((v)&0xffffffffU) << 0U) #define gr_ds_zbc_color_g_val_f(v) ((U32(v) & 0xffffffffU) << 0U)
#define gr_ds_zbc_color_b_r() (0x0040580cU) #define gr_ds_zbc_color_b_r() (0x0040580cU)
#define gr_ds_zbc_color_b_val_f(v) (((v)&0xffffffffU) << 0U) #define gr_ds_zbc_color_b_val_f(v) ((U32(v) & 0xffffffffU) << 0U)
#define gr_ds_zbc_color_a_r() (0x00405810U) #define gr_ds_zbc_color_a_r() (0x00405810U)
#define gr_ds_zbc_color_a_val_f(v) (((v)&0xffffffffU) << 0U) #define gr_ds_zbc_color_a_val_f(v) ((U32(v) & 0xffffffffU) << 0U)
#define gr_ds_zbc_color_fmt_r() (0x00405814U) #define gr_ds_zbc_color_fmt_r() (0x00405814U)
#define gr_ds_zbc_color_fmt_val_f(v) (((v)&0x7fU) << 0U) #define gr_ds_zbc_color_fmt_val_f(v) ((U32(v) & 0x7fU) << 0U)
#define gr_ds_zbc_color_fmt_val_invalid_f() (0x0U) #define gr_ds_zbc_color_fmt_val_invalid_f() (0x0U)
#define gr_ds_zbc_color_fmt_val_zero_v() (0x00000001U) #define gr_ds_zbc_color_fmt_val_zero_v() (0x00000001U)
#define gr_ds_zbc_color_fmt_val_unorm_one_v() (0x00000002U) #define gr_ds_zbc_color_fmt_val_unorm_one_v() (0x00000002U)
@@ -618,29 +620,29 @@
#define gr_ds_zbc_color_fmt_val_a8_b8_g8_r8_v() (0x00000028U) #define gr_ds_zbc_color_fmt_val_a8_b8_g8_r8_v() (0x00000028U)
#define gr_ds_zbc_z_r() (0x00405818U) #define gr_ds_zbc_z_r() (0x00405818U)
#define gr_ds_zbc_z_val_s() (32U) #define gr_ds_zbc_z_val_s() (32U)
#define gr_ds_zbc_z_val_f(v) (((v)&0xffffffffU) << 0U) #define gr_ds_zbc_z_val_f(v) ((U32(v) & 0xffffffffU) << 0U)
#define gr_ds_zbc_z_val_m() (U32(0xffffffffU) << 0U) #define gr_ds_zbc_z_val_m() (U32(0xffffffffU) << 0U)
#define gr_ds_zbc_z_val_v(r) (((r) >> 0U) & 0xffffffffU) #define gr_ds_zbc_z_val_v(r) (((r) >> 0U) & 0xffffffffU)
#define gr_ds_zbc_z_val__init_v() (0x00000000U) #define gr_ds_zbc_z_val__init_v() (0x00000000U)
#define gr_ds_zbc_z_val__init_f() (0x0U) #define gr_ds_zbc_z_val__init_f() (0x0U)
#define gr_ds_zbc_z_fmt_r() (0x0040581cU) #define gr_ds_zbc_z_fmt_r() (0x0040581cU)
#define gr_ds_zbc_z_fmt_val_f(v) (((v)&0x1U) << 0U) #define gr_ds_zbc_z_fmt_val_f(v) ((U32(v) & 0x1U) << 0U)
#define gr_ds_zbc_z_fmt_val_invalid_f() (0x0U) #define gr_ds_zbc_z_fmt_val_invalid_f() (0x0U)
#define gr_ds_zbc_z_fmt_val_fp32_v() (0x00000001U) #define gr_ds_zbc_z_fmt_val_fp32_v() (0x00000001U)
#define gr_ds_zbc_tbl_index_r() (0x00405820U) #define gr_ds_zbc_tbl_index_r() (0x00405820U)
#define gr_ds_zbc_tbl_index_val_f(v) (((v)&0xfU) << 0U) #define gr_ds_zbc_tbl_index_val_f(v) ((U32(v) & 0xfU) << 0U)
#define gr_ds_zbc_tbl_ld_r() (0x00405824U) #define gr_ds_zbc_tbl_ld_r() (0x00405824U)
#define gr_ds_zbc_tbl_ld_select_c_f() (0x0U) #define gr_ds_zbc_tbl_ld_select_c_f() (0x0U)
#define gr_ds_zbc_tbl_ld_select_z_f() (0x1U) #define gr_ds_zbc_tbl_ld_select_z_f() (0x1U)
#define gr_ds_zbc_tbl_ld_action_write_f() (0x0U) #define gr_ds_zbc_tbl_ld_action_write_f() (0x0U)
#define gr_ds_zbc_tbl_ld_trigger_active_f() (0x4U) #define gr_ds_zbc_tbl_ld_trigger_active_f() (0x4U)
#define gr_ds_tga_constraintlogic_beta_r() (0x00405830U) #define gr_ds_tga_constraintlogic_beta_r() (0x00405830U)
#define gr_ds_tga_constraintlogic_beta_cbsize_f(v) (((v)&0x3fffffU) << 0U) #define gr_ds_tga_constraintlogic_beta_cbsize_f(v) ((U32(v) & 0x3fffffU) << 0U)
#define gr_ds_tga_constraintlogic_alpha_r() (0x0040585cU) #define gr_ds_tga_constraintlogic_alpha_r() (0x0040585cU)
#define gr_ds_tga_constraintlogic_alpha_cbsize_f(v) (((v)&0xffffU) << 0U) #define gr_ds_tga_constraintlogic_alpha_cbsize_f(v) ((U32(v) & 0xffffU) << 0U)
#define gr_ds_hww_esr_r() (0x00405840U) #define gr_ds_hww_esr_r() (0x00405840U)
#define gr_ds_hww_esr_reset_s() (1U) #define gr_ds_hww_esr_reset_s() (1U)
#define gr_ds_hww_esr_reset_f(v) (((v)&0x1U) << 30U) #define gr_ds_hww_esr_reset_f(v) ((U32(v) & 0x1U) << 30U)
#define gr_ds_hww_esr_reset_m() (U32(0x1U) << 30U) #define gr_ds_hww_esr_reset_m() (U32(0x1U) << 30U)
#define gr_ds_hww_esr_reset_v(r) (((r) >> 30U) & 0x1U) #define gr_ds_hww_esr_reset_v(r) (((r) >> 30U) & 0x1U)
#define gr_ds_hww_esr_reset_task_v() (0x00000001U) #define gr_ds_hww_esr_reset_task_v() (0x00000001U)
@@ -648,7 +650,7 @@
#define gr_ds_hww_esr_en_enabled_f() (0x80000000U) #define gr_ds_hww_esr_en_enabled_f() (0x80000000U)
#define gr_ds_hww_esr_2_r() (0x00405848U) #define gr_ds_hww_esr_2_r() (0x00405848U)
#define gr_ds_hww_esr_2_reset_s() (1U) #define gr_ds_hww_esr_2_reset_s() (1U)
#define gr_ds_hww_esr_2_reset_f(v) (((v)&0x1U) << 30U) #define gr_ds_hww_esr_2_reset_f(v) ((U32(v) & 0x1U) << 30U)
#define gr_ds_hww_esr_2_reset_m() (U32(0x1U) << 30U) #define gr_ds_hww_esr_2_reset_m() (U32(0x1U) << 30U)
#define gr_ds_hww_esr_2_reset_v(r) (((r) >> 30U) & 0x1U) #define gr_ds_hww_esr_2_reset_v(r) (((r) >> 30U) & 0x1U)
#define gr_ds_hww_esr_2_reset_task_v() (0x00000001U) #define gr_ds_hww_esr_2_reset_task_v() (0x00000001U)
@@ -684,25 +686,25 @@
#define gr_ds_num_tpc_per_gpc_r(i)\ #define gr_ds_num_tpc_per_gpc_r(i)\
(nvgpu_safe_add_u32(0x00405870U, nvgpu_safe_mult_u32((i), 4U))) (nvgpu_safe_add_u32(0x00405870U, nvgpu_safe_mult_u32((i), 4U)))
#define gr_scc_bundle_cb_base_r() (0x00408004U) #define gr_scc_bundle_cb_base_r() (0x00408004U)
#define gr_scc_bundle_cb_base_addr_39_8_f(v) (((v)&0xffffffffU) << 0U) #define gr_scc_bundle_cb_base_addr_39_8_f(v) ((U32(v) & 0xffffffffU) << 0U)
#define gr_scc_bundle_cb_base_addr_39_8_align_bits_v() (0x00000008U) #define gr_scc_bundle_cb_base_addr_39_8_align_bits_v() (0x00000008U)
#define gr_scc_bundle_cb_size_r() (0x00408008U) #define gr_scc_bundle_cb_size_r() (0x00408008U)
#define gr_scc_bundle_cb_size_div_256b_f(v) (((v)&0x7ffU) << 0U) #define gr_scc_bundle_cb_size_div_256b_f(v) ((U32(v) & 0x7ffU) << 0U)
#define gr_scc_bundle_cb_size_div_256b__prod_v() (0x00000030U) #define gr_scc_bundle_cb_size_div_256b__prod_v() (0x00000030U)
#define gr_scc_bundle_cb_size_div_256b_byte_granularity_v() (0x00000100U) #define gr_scc_bundle_cb_size_div_256b_byte_granularity_v() (0x00000100U)
#define gr_scc_bundle_cb_size_valid_false_v() (0x00000000U) #define gr_scc_bundle_cb_size_valid_false_v() (0x00000000U)
#define gr_scc_bundle_cb_size_valid_false_f() (0x0U) #define gr_scc_bundle_cb_size_valid_false_f() (0x0U)
#define gr_scc_bundle_cb_size_valid_true_f() (0x80000000U) #define gr_scc_bundle_cb_size_valid_true_f() (0x80000000U)
#define gr_scc_pagepool_base_r() (0x0040800cU) #define gr_scc_pagepool_base_r() (0x0040800cU)
#define gr_scc_pagepool_base_addr_39_8_f(v) (((v)&0xffffffffU) << 0U) #define gr_scc_pagepool_base_addr_39_8_f(v) ((U32(v) & 0xffffffffU) << 0U)
#define gr_scc_pagepool_base_addr_39_8_align_bits_v() (0x00000008U) #define gr_scc_pagepool_base_addr_39_8_align_bits_v() (0x00000008U)
#define gr_scc_pagepool_r() (0x00408010U) #define gr_scc_pagepool_r() (0x00408010U)
#define gr_scc_pagepool_total_pages_f(v) (((v)&0x3ffU) << 0U) #define gr_scc_pagepool_total_pages_f(v) ((U32(v) & 0x3ffU) << 0U)
#define gr_scc_pagepool_total_pages_hwmax_v() (0x00000000U) #define gr_scc_pagepool_total_pages_hwmax_v() (0x00000000U)
#define gr_scc_pagepool_total_pages_hwmax_value_v() (0x00000200U) #define gr_scc_pagepool_total_pages_hwmax_value_v() (0x00000200U)
#define gr_scc_pagepool_total_pages_byte_granularity_v() (0x00000100U) #define gr_scc_pagepool_total_pages_byte_granularity_v() (0x00000100U)
#define gr_scc_pagepool_max_valid_pages_s() (10U) #define gr_scc_pagepool_max_valid_pages_s() (10U)
#define gr_scc_pagepool_max_valid_pages_f(v) (((v)&0x3ffU) << 10U) #define gr_scc_pagepool_max_valid_pages_f(v) ((U32(v) & 0x3ffU) << 10U)
#define gr_scc_pagepool_max_valid_pages_m() (U32(0x3ffU) << 10U) #define gr_scc_pagepool_max_valid_pages_m() (U32(0x3ffU) << 10U)
#define gr_scc_pagepool_max_valid_pages_v(r) (((r) >> 10U) & 0x3ffU) #define gr_scc_pagepool_max_valid_pages_v(r) (((r) >> 10U) & 0x3ffU)
#define gr_scc_pagepool_valid_true_f() (0x80000000U) #define gr_scc_pagepool_valid_true_f() (0x80000000U)
@@ -721,20 +723,20 @@
#define gr_sked_hww_esr_en_skedcheck18_l1_config_too_small_enabled_f()\ #define gr_sked_hww_esr_en_skedcheck18_l1_config_too_small_enabled_f()\
(0x2000000U) (0x2000000U)
#define gr_cwd_fs_r() (0x00405b00U) #define gr_cwd_fs_r() (0x00405b00U)
#define gr_cwd_fs_num_gpcs_f(v) (((v)&0xffU) << 0U) #define gr_cwd_fs_num_gpcs_f(v) ((U32(v) & 0xffU) << 0U)
#define gr_cwd_fs_num_tpcs_f(v) (((v)&0xffU) << 8U) #define gr_cwd_fs_num_tpcs_f(v) ((U32(v) & 0xffU) << 8U)
#define gr_cwd_gpc_tpc_id_r(i)\ #define gr_cwd_gpc_tpc_id_r(i)\
(nvgpu_safe_add_u32(0x00405b60U, nvgpu_safe_mult_u32((i), 4U))) (nvgpu_safe_add_u32(0x00405b60U, nvgpu_safe_mult_u32((i), 4U)))
#define gr_cwd_gpc_tpc_id_tpc0_s() (4U) #define gr_cwd_gpc_tpc_id_tpc0_s() (4U)
#define gr_cwd_gpc_tpc_id_tpc0_f(v) (((v)&0xfU) << 0U) #define gr_cwd_gpc_tpc_id_tpc0_f(v) ((U32(v) & 0xfU) << 0U)
#define gr_cwd_gpc_tpc_id_gpc0_s() (4U) #define gr_cwd_gpc_tpc_id_gpc0_s() (4U)
#define gr_cwd_gpc_tpc_id_gpc0_f(v) (((v)&0xfU) << 4U) #define gr_cwd_gpc_tpc_id_gpc0_f(v) ((U32(v) & 0xfU) << 4U)
#define gr_cwd_gpc_tpc_id_tpc1_f(v) (((v)&0xfU) << 8U) #define gr_cwd_gpc_tpc_id_tpc1_f(v) ((U32(v) & 0xfU) << 8U)
#define gr_cwd_sm_id_r(i)\ #define gr_cwd_sm_id_r(i)\
(nvgpu_safe_add_u32(0x00405ba0U, nvgpu_safe_mult_u32((i), 4U))) (nvgpu_safe_add_u32(0x00405ba0U, nvgpu_safe_mult_u32((i), 4U)))
#define gr_cwd_sm_id__size_1_v() (0x00000010U) #define gr_cwd_sm_id__size_1_v() (0x00000010U)
#define gr_cwd_sm_id_tpc0_f(v) (((v)&0xffU) << 0U) #define gr_cwd_sm_id_tpc0_f(v) ((U32(v) & 0xffU) << 0U)
#define gr_cwd_sm_id_tpc1_f(v) (((v)&0xffU) << 8U) #define gr_cwd_sm_id_tpc1_f(v) ((U32(v) & 0xffU) << 8U)
#define gr_gpc0_fs_gpc_r() (0x00502608U) #define gr_gpc0_fs_gpc_r() (0x00502608U)
#define gr_gpc0_fs_gpc_num_available_tpcs_v(r) (((r) >> 0U) & 0x1fU) #define gr_gpc0_fs_gpc_num_available_tpcs_v(r) (((r) >> 0U) & 0x1fU)
#define gr_gpc0_fs_gpc_num_available_zculls_v(r) (((r) >> 16U) & 0x1fU) #define gr_gpc0_fs_gpc_num_available_zculls_v(r) (((r) >> 16U) & 0x1fU)
@@ -742,42 +744,43 @@
#define gr_gpc0_cfg_imem_sz_v(r) (((r) >> 0U) & 0xffU) #define gr_gpc0_cfg_imem_sz_v(r) (((r) >> 0U) & 0xffU)
#define gr_gpccs_rc_lanes_r() (0x00502880U) #define gr_gpccs_rc_lanes_r() (0x00502880U)
#define gr_gpccs_rc_lanes_num_chains_s() (6U) #define gr_gpccs_rc_lanes_num_chains_s() (6U)
#define gr_gpccs_rc_lanes_num_chains_f(v) (((v)&0x3fU) << 0U) #define gr_gpccs_rc_lanes_num_chains_f(v) ((U32(v) & 0x3fU) << 0U)
#define gr_gpccs_rc_lanes_num_chains_m() (U32(0x3fU) << 0U) #define gr_gpccs_rc_lanes_num_chains_m() (U32(0x3fU) << 0U)
#define gr_gpccs_rc_lanes_num_chains_v(r) (((r) >> 0U) & 0x3fU) #define gr_gpccs_rc_lanes_num_chains_v(r) (((r) >> 0U) & 0x3fU)
#define gr_gpccs_rc_lane_size_r() (0x00502910U) #define gr_gpccs_rc_lane_size_r() (0x00502910U)
#define gr_gpccs_rc_lane_size_v_s() (24U) #define gr_gpccs_rc_lane_size_v_s() (24U)
#define gr_gpccs_rc_lane_size_v_f(v) (((v)&0xffffffU) << 0U) #define gr_gpccs_rc_lane_size_v_f(v) ((U32(v) & 0xffffffU) << 0U)
#define gr_gpccs_rc_lane_size_v_m() (U32(0xffffffU) << 0U) #define gr_gpccs_rc_lane_size_v_m() (U32(0xffffffU) << 0U)
#define gr_gpccs_rc_lane_size_v_v(r) (((r) >> 0U) & 0xffffffU) #define gr_gpccs_rc_lane_size_v_v(r) (((r) >> 0U) & 0xffffffU)
#define gr_gpccs_rc_lane_size_v_0_v() (0x00000000U) #define gr_gpccs_rc_lane_size_v_0_v() (0x00000000U)
#define gr_gpccs_rc_lane_size_v_0_f() (0x0U) #define gr_gpccs_rc_lane_size_v_0_f() (0x0U)
#define gr_gpc0_zcull_fs_r() (0x00500910U) #define gr_gpc0_zcull_fs_r() (0x00500910U)
#define gr_gpc0_zcull_fs_num_sms_f(v) (((v)&0x1ffU) << 0U) #define gr_gpc0_zcull_fs_num_sms_f(v) ((U32(v) & 0x1ffU) << 0U)
#define gr_gpc0_zcull_fs_num_active_banks_f(v) (((v)&0xfU) << 16U) #define gr_gpc0_zcull_fs_num_active_banks_f(v) ((U32(v) & 0xfU) << 16U)
#define gr_gpc0_zcull_ram_addr_r() (0x00500914U) #define gr_gpc0_zcull_ram_addr_r() (0x00500914U)
#define gr_gpc0_zcull_ram_addr_tiles_per_hypertile_row_per_gpc_f(v)\ #define gr_gpc0_zcull_ram_addr_tiles_per_hypertile_row_per_gpc_f(v)\
(((v)&0xfU) << 0U) ((U32(v) & 0xfU) << 0U)
#define gr_gpc0_zcull_ram_addr_row_offset_f(v) (((v)&0xfU) << 8U) #define gr_gpc0_zcull_ram_addr_row_offset_f(v) ((U32(v) & 0xfU) << 8U)
#define gr_gpc0_zcull_sm_num_rcp_r() (0x00500918U) #define gr_gpc0_zcull_sm_num_rcp_r() (0x00500918U)
#define gr_gpc0_zcull_sm_num_rcp_conservative_f(v) (((v)&0xffffffU) << 0U) #define gr_gpc0_zcull_sm_num_rcp_conservative_f(v) ((U32(v) & 0xffffffU) << 0U)
#define gr_gpc0_zcull_sm_num_rcp_conservative__max_v() (0x00800000U) #define gr_gpc0_zcull_sm_num_rcp_conservative__max_v() (0x00800000U)
#define gr_gpc0_zcull_total_ram_size_r() (0x00500920U) #define gr_gpc0_zcull_total_ram_size_r() (0x00500920U)
#define gr_gpc0_zcull_total_ram_size_num_aliquots_f(v) (((v)&0xffffU) << 0U) #define gr_gpc0_zcull_total_ram_size_num_aliquots_f(v)\
((U32(v) & 0xffffU) << 0U)
#define gr_gpc0_zcull_zcsize_r(i)\ #define gr_gpc0_zcull_zcsize_r(i)\
(nvgpu_safe_add_u32(0x00500a04U, nvgpu_safe_mult_u32((i), 32U))) (nvgpu_safe_add_u32(0x00500a04U, nvgpu_safe_mult_u32((i), 32U)))
#define gr_gpc0_zcull_zcsize_height_subregion__multiple_v() (0x00000040U) #define gr_gpc0_zcull_zcsize_height_subregion__multiple_v() (0x00000040U)
#define gr_gpc0_zcull_zcsize_width_subregion__multiple_v() (0x00000010U) #define gr_gpc0_zcull_zcsize_width_subregion__multiple_v() (0x00000010U)
#define gr_gpc0_gpm_pd_sm_id_r(i)\ #define gr_gpc0_gpm_pd_sm_id_r(i)\
(nvgpu_safe_add_u32(0x00500c10U, nvgpu_safe_mult_u32((i), 4U))) (nvgpu_safe_add_u32(0x00500c10U, nvgpu_safe_mult_u32((i), 4U)))
#define gr_gpc0_gpm_pd_sm_id_id_f(v) (((v)&0xffU) << 0U) #define gr_gpc0_gpm_pd_sm_id_id_f(v) ((U32(v) & 0xffU) << 0U)
#define gr_gpc0_gpm_pd_pes_tpc_id_mask_r(i)\ #define gr_gpc0_gpm_pd_pes_tpc_id_mask_r(i)\
(nvgpu_safe_add_u32(0x00500c30U, nvgpu_safe_mult_u32((i), 4U))) (nvgpu_safe_add_u32(0x00500c30U, nvgpu_safe_mult_u32((i), 4U)))
#define gr_gpc0_gpm_pd_pes_tpc_id_mask_mask_v(r) (((r) >> 0U) & 0xffU) #define gr_gpc0_gpm_pd_pes_tpc_id_mask_mask_v(r) (((r) >> 0U) & 0xffU)
#define gr_gpc0_tpc0_pe_cfg_smid_r() (0x00504088U) #define gr_gpc0_tpc0_pe_cfg_smid_r() (0x00504088U)
#define gr_gpc0_tpc0_pe_cfg_smid_value_f(v) (((v)&0xffffU) << 0U) #define gr_gpc0_tpc0_pe_cfg_smid_value_f(v) ((U32(v) & 0xffffU) << 0U)
#define gr_gpc0_tpc0_sm_cfg_r() (0x00504608U) #define gr_gpc0_tpc0_sm_cfg_r() (0x00504608U)
#define gr_gpc0_tpc0_sm_cfg_tpc_id_f(v) (((v)&0xffffU) << 0U) #define gr_gpc0_tpc0_sm_cfg_tpc_id_f(v) ((U32(v) & 0xffffU) << 0U)
#define gr_gpc0_tpc0_sm_cfg_tpc_id_v(r) (((r) >> 0U) & 0xffffU) #define gr_gpc0_tpc0_sm_cfg_tpc_id_v(r) (((r) >> 0U) & 0xffffU)
#define gr_gpc0_tpc0_sm_arch_r() (0x00504330U) #define gr_gpc0_tpc0_sm_arch_r() (0x00504330U)
#define gr_gpc0_tpc0_sm_arch_warp_count_v(r) (((r) >> 0U) & 0xffU) #define gr_gpc0_tpc0_sm_arch_warp_count_v(r) (((r) >> 0U) & 0xffU)
@@ -787,95 +790,97 @@
#define gr_gpc0_ppc0_pes_vsc_strem_master_pe_m() (U32(0x1U) << 0U) #define gr_gpc0_ppc0_pes_vsc_strem_master_pe_m() (U32(0x1U) << 0U)
#define gr_gpc0_ppc0_pes_vsc_strem_master_pe_true_f() (0x1U) #define gr_gpc0_ppc0_pes_vsc_strem_master_pe_true_f() (0x1U)
#define gr_gpc0_ppc0_cbm_beta_cb_size_r() (0x005030c0U) #define gr_gpc0_ppc0_cbm_beta_cb_size_r() (0x005030c0U)
#define gr_gpc0_ppc0_cbm_beta_cb_size_v_f(v) (((v)&0x3fffffU) << 0U) #define gr_gpc0_ppc0_cbm_beta_cb_size_v_f(v) ((U32(v) & 0x3fffffU) << 0U)
#define gr_gpc0_ppc0_cbm_beta_cb_size_v_m() (U32(0x3fffffU) << 0U) #define gr_gpc0_ppc0_cbm_beta_cb_size_v_m() (U32(0x3fffffU) << 0U)
#define gr_gpc0_ppc0_cbm_beta_cb_size_v_default_v() (0x00000480U) #define gr_gpc0_ppc0_cbm_beta_cb_size_v_default_v() (0x00000480U)
#define gr_gpc0_ppc0_cbm_beta_cb_size_v_gfxp_v() (0x00000d10U) #define gr_gpc0_ppc0_cbm_beta_cb_size_v_gfxp_v() (0x00000d10U)
#define gr_gpc0_ppc0_cbm_beta_cb_size_v_granularity_v() (0x00000020U) #define gr_gpc0_ppc0_cbm_beta_cb_size_v_granularity_v() (0x00000020U)
#define gr_gpc0_ppc0_cbm_beta_cb_offset_r() (0x005030f4U) #define gr_gpc0_ppc0_cbm_beta_cb_offset_r() (0x005030f4U)
#define gr_gpc0_ppc0_cbm_alpha_cb_size_r() (0x005030e4U) #define gr_gpc0_ppc0_cbm_alpha_cb_size_r() (0x005030e4U)
#define gr_gpc0_ppc0_cbm_alpha_cb_size_v_f(v) (((v)&0xffffU) << 0U) #define gr_gpc0_ppc0_cbm_alpha_cb_size_v_f(v) ((U32(v) & 0xffffU) << 0U)
#define gr_gpc0_ppc0_cbm_alpha_cb_size_v_m() (U32(0xffffU) << 0U) #define gr_gpc0_ppc0_cbm_alpha_cb_size_v_m() (U32(0xffffU) << 0U)
#define gr_gpc0_ppc0_cbm_alpha_cb_size_v_default_v() (0x00000800U) #define gr_gpc0_ppc0_cbm_alpha_cb_size_v_default_v() (0x00000800U)
#define gr_gpc0_ppc0_cbm_alpha_cb_size_v_granularity_v() (0x00000020U) #define gr_gpc0_ppc0_cbm_alpha_cb_size_v_granularity_v() (0x00000020U)
#define gr_gpc0_ppc0_cbm_alpha_cb_offset_r() (0x005030f8U) #define gr_gpc0_ppc0_cbm_alpha_cb_offset_r() (0x005030f8U)
#define gr_gpc0_ppc0_cbm_beta_steady_state_cb_size_r() (0x005030f0U) #define gr_gpc0_ppc0_cbm_beta_steady_state_cb_size_r() (0x005030f0U)
#define gr_gpc0_ppc0_cbm_beta_steady_state_cb_size_v_f(v)\ #define gr_gpc0_ppc0_cbm_beta_steady_state_cb_size_v_f(v)\
(((v)&0x3fffffU) << 0U) ((U32(v) & 0x3fffffU) << 0U)
#define gr_gpc0_ppc0_cbm_beta_steady_state_cb_size_v_default_v() (0x00000480U) #define gr_gpc0_ppc0_cbm_beta_steady_state_cb_size_v_default_v() (0x00000480U)
#define gr_gpcs_tpcs_tex_rm_cb_0_r() (0x00419e00U) #define gr_gpcs_tpcs_tex_rm_cb_0_r() (0x00419e00U)
#define gr_gpcs_tpcs_tex_rm_cb_0_base_addr_43_12_f(v) (((v)&0xffffffffU) << 0U) #define gr_gpcs_tpcs_tex_rm_cb_0_base_addr_43_12_f(v)\
((U32(v) & 0xffffffffU) << 0U)
#define gr_gpcs_tpcs_tex_rm_cb_1_r() (0x00419e04U) #define gr_gpcs_tpcs_tex_rm_cb_1_r() (0x00419e04U)
#define gr_gpcs_tpcs_tex_rm_cb_1_size_div_128b_s() (21U) #define gr_gpcs_tpcs_tex_rm_cb_1_size_div_128b_s() (21U)
#define gr_gpcs_tpcs_tex_rm_cb_1_size_div_128b_f(v) (((v)&0x1fffffU) << 0U) #define gr_gpcs_tpcs_tex_rm_cb_1_size_div_128b_f(v) ((U32(v) & 0x1fffffU) << 0U)
#define gr_gpcs_tpcs_tex_rm_cb_1_size_div_128b_m() (U32(0x1fffffU) << 0U) #define gr_gpcs_tpcs_tex_rm_cb_1_size_div_128b_m() (U32(0x1fffffU) << 0U)
#define gr_gpcs_tpcs_tex_rm_cb_1_size_div_128b_v(r) (((r) >> 0U) & 0x1fffffU) #define gr_gpcs_tpcs_tex_rm_cb_1_size_div_128b_v(r) (((r) >> 0U) & 0x1fffffU)
#define gr_gpcs_tpcs_tex_rm_cb_1_size_div_128b_granularity_f() (0x80U) #define gr_gpcs_tpcs_tex_rm_cb_1_size_div_128b_granularity_f() (0x80U)
#define gr_gpcs_tpcs_tex_rm_cb_1_valid_s() (1U) #define gr_gpcs_tpcs_tex_rm_cb_1_valid_s() (1U)
#define gr_gpcs_tpcs_tex_rm_cb_1_valid_f(v) (((v)&0x1U) << 31U) #define gr_gpcs_tpcs_tex_rm_cb_1_valid_f(v) ((U32(v) & 0x1U) << 31U)
#define gr_gpcs_tpcs_tex_rm_cb_1_valid_m() (U32(0x1U) << 31U) #define gr_gpcs_tpcs_tex_rm_cb_1_valid_m() (U32(0x1U) << 31U)
#define gr_gpcs_tpcs_tex_rm_cb_1_valid_v(r) (((r) >> 31U) & 0x1U) #define gr_gpcs_tpcs_tex_rm_cb_1_valid_v(r) (((r) >> 31U) & 0x1U)
#define gr_gpcs_tpcs_tex_rm_cb_1_valid_true_f() (0x80000000U) #define gr_gpcs_tpcs_tex_rm_cb_1_valid_true_f() (0x80000000U)
#define gr_gpccs_falcon_addr_r() (0x0041a0acU) #define gr_gpccs_falcon_addr_r() (0x0041a0acU)
#define gr_gpccs_falcon_addr_lsb_s() (6U) #define gr_gpccs_falcon_addr_lsb_s() (6U)
#define gr_gpccs_falcon_addr_lsb_f(v) (((v)&0x3fU) << 0U) #define gr_gpccs_falcon_addr_lsb_f(v) ((U32(v) & 0x3fU) << 0U)
#define gr_gpccs_falcon_addr_lsb_m() (U32(0x3fU) << 0U) #define gr_gpccs_falcon_addr_lsb_m() (U32(0x3fU) << 0U)
#define gr_gpccs_falcon_addr_lsb_v(r) (((r) >> 0U) & 0x3fU) #define gr_gpccs_falcon_addr_lsb_v(r) (((r) >> 0U) & 0x3fU)
#define gr_gpccs_falcon_addr_lsb_init_v() (0x00000000U) #define gr_gpccs_falcon_addr_lsb_init_v() (0x00000000U)
#define gr_gpccs_falcon_addr_lsb_init_f() (0x0U) #define gr_gpccs_falcon_addr_lsb_init_f() (0x0U)
#define gr_gpccs_falcon_addr_msb_s() (6U) #define gr_gpccs_falcon_addr_msb_s() (6U)
#define gr_gpccs_falcon_addr_msb_f(v) (((v)&0x3fU) << 6U) #define gr_gpccs_falcon_addr_msb_f(v) ((U32(v) & 0x3fU) << 6U)
#define gr_gpccs_falcon_addr_msb_m() (U32(0x3fU) << 6U) #define gr_gpccs_falcon_addr_msb_m() (U32(0x3fU) << 6U)
#define gr_gpccs_falcon_addr_msb_v(r) (((r) >> 6U) & 0x3fU) #define gr_gpccs_falcon_addr_msb_v(r) (((r) >> 6U) & 0x3fU)
#define gr_gpccs_falcon_addr_msb_init_v() (0x00000000U) #define gr_gpccs_falcon_addr_msb_init_v() (0x00000000U)
#define gr_gpccs_falcon_addr_msb_init_f() (0x0U) #define gr_gpccs_falcon_addr_msb_init_f() (0x0U)
#define gr_gpccs_falcon_addr_ext_s() (12U) #define gr_gpccs_falcon_addr_ext_s() (12U)
#define gr_gpccs_falcon_addr_ext_f(v) (((v)&0xfffU) << 0U) #define gr_gpccs_falcon_addr_ext_f(v) ((U32(v) & 0xfffU) << 0U)
#define gr_gpccs_falcon_addr_ext_m() (U32(0xfffU) << 0U) #define gr_gpccs_falcon_addr_ext_m() (U32(0xfffU) << 0U)
#define gr_gpccs_falcon_addr_ext_v(r) (((r) >> 0U) & 0xfffU) #define gr_gpccs_falcon_addr_ext_v(r) (((r) >> 0U) & 0xfffU)
#define gr_gpccs_cpuctl_r() (0x0041a100U) #define gr_gpccs_cpuctl_r() (0x0041a100U)
#define gr_gpccs_cpuctl_startcpu_f(v) (((v)&0x1U) << 1U) #define gr_gpccs_cpuctl_startcpu_f(v) ((U32(v) & 0x1U) << 1U)
#define gr_gpccs_dmactl_r() (0x0041a10cU) #define gr_gpccs_dmactl_r() (0x0041a10cU)
#define gr_gpccs_dmactl_require_ctx_f(v) (((v)&0x1U) << 0U) #define gr_gpccs_dmactl_require_ctx_f(v) ((U32(v) & 0x1U) << 0U)
#define gr_gpccs_dmactl_dmem_scrubbing_m() (U32(0x1U) << 1U) #define gr_gpccs_dmactl_dmem_scrubbing_m() (U32(0x1U) << 1U)
#define gr_gpccs_dmactl_imem_scrubbing_m() (U32(0x1U) << 2U) #define gr_gpccs_dmactl_imem_scrubbing_m() (U32(0x1U) << 2U)
#define gr_gpccs_imemc_r(i)\ #define gr_gpccs_imemc_r(i)\
(nvgpu_safe_add_u32(0x0041a180U, nvgpu_safe_mult_u32((i), 16U))) (nvgpu_safe_add_u32(0x0041a180U, nvgpu_safe_mult_u32((i), 16U)))
#define gr_gpccs_imemc_offs_f(v) (((v)&0x3fU) << 2U) #define gr_gpccs_imemc_offs_f(v) ((U32(v) & 0x3fU) << 2U)
#define gr_gpccs_imemc_blk_f(v) (((v)&0xffU) << 8U) #define gr_gpccs_imemc_blk_f(v) ((U32(v) & 0xffU) << 8U)
#define gr_gpccs_imemc_aincw_f(v) (((v)&0x1U) << 24U) #define gr_gpccs_imemc_aincw_f(v) ((U32(v) & 0x1U) << 24U)
#define gr_gpccs_imemd_r(i)\ #define gr_gpccs_imemd_r(i)\
(nvgpu_safe_add_u32(0x0041a184U, nvgpu_safe_mult_u32((i), 16U))) (nvgpu_safe_add_u32(0x0041a184U, nvgpu_safe_mult_u32((i), 16U)))
#define gr_gpccs_imemt_r(i)\ #define gr_gpccs_imemt_r(i)\
(nvgpu_safe_add_u32(0x0041a188U, nvgpu_safe_mult_u32((i), 16U))) (nvgpu_safe_add_u32(0x0041a188U, nvgpu_safe_mult_u32((i), 16U)))
#define gr_gpccs_imemt__size_1_v() (0x00000004U) #define gr_gpccs_imemt__size_1_v() (0x00000004U)
#define gr_gpccs_imemt_tag_f(v) (((v)&0xffffU) << 0U) #define gr_gpccs_imemt_tag_f(v) ((U32(v) & 0xffffU) << 0U)
#define gr_gpccs_dmemc_r(i)\ #define gr_gpccs_dmemc_r(i)\
(nvgpu_safe_add_u32(0x0041a1c0U, nvgpu_safe_mult_u32((i), 8U))) (nvgpu_safe_add_u32(0x0041a1c0U, nvgpu_safe_mult_u32((i), 8U)))
#define gr_gpccs_dmemc_offs_f(v) (((v)&0x3fU) << 2U) #define gr_gpccs_dmemc_offs_f(v) ((U32(v) & 0x3fU) << 2U)
#define gr_gpccs_dmemc_blk_f(v) (((v)&0xffU) << 8U) #define gr_gpccs_dmemc_blk_f(v) ((U32(v) & 0xffU) << 8U)
#define gr_gpccs_dmemc_aincw_f(v) (((v)&0x1U) << 24U) #define gr_gpccs_dmemc_aincw_f(v) ((U32(v) & 0x1U) << 24U)
#define gr_gpccs_dmemd_r(i)\ #define gr_gpccs_dmemd_r(i)\
(nvgpu_safe_add_u32(0x0041a1c4U, nvgpu_safe_mult_u32((i), 8U))) (nvgpu_safe_add_u32(0x0041a1c4U, nvgpu_safe_mult_u32((i), 8U)))
#define gr_gpccs_ctxsw_mailbox_r(i)\ #define gr_gpccs_ctxsw_mailbox_r(i)\
(nvgpu_safe_add_u32(0x0041a800U, nvgpu_safe_mult_u32((i), 4U))) (nvgpu_safe_add_u32(0x0041a800U, nvgpu_safe_mult_u32((i), 4U)))
#define gr_gpccs_ctxsw_mailbox_value_f(v) (((v)&0xffffffffU) << 0U) #define gr_gpccs_ctxsw_mailbox_value_f(v) ((U32(v) & 0xffffffffU) << 0U)
#define gr_gpcs_swdx_bundle_cb_base_r() (0x00418e24U) #define gr_gpcs_swdx_bundle_cb_base_r() (0x00418e24U)
#define gr_gpcs_swdx_bundle_cb_base_addr_39_8_s() (32U) #define gr_gpcs_swdx_bundle_cb_base_addr_39_8_s() (32U)
#define gr_gpcs_swdx_bundle_cb_base_addr_39_8_f(v) (((v)&0xffffffffU) << 0U) #define gr_gpcs_swdx_bundle_cb_base_addr_39_8_f(v)\
((U32(v) & 0xffffffffU) << 0U)
#define gr_gpcs_swdx_bundle_cb_base_addr_39_8_m() (U32(0xffffffffU) << 0U) #define gr_gpcs_swdx_bundle_cb_base_addr_39_8_m() (U32(0xffffffffU) << 0U)
#define gr_gpcs_swdx_bundle_cb_base_addr_39_8_v(r) (((r) >> 0U) & 0xffffffffU) #define gr_gpcs_swdx_bundle_cb_base_addr_39_8_v(r) (((r) >> 0U) & 0xffffffffU)
#define gr_gpcs_swdx_bundle_cb_base_addr_39_8_init_v() (0x00000000U) #define gr_gpcs_swdx_bundle_cb_base_addr_39_8_init_v() (0x00000000U)
#define gr_gpcs_swdx_bundle_cb_base_addr_39_8_init_f() (0x0U) #define gr_gpcs_swdx_bundle_cb_base_addr_39_8_init_f() (0x0U)
#define gr_gpcs_swdx_bundle_cb_size_r() (0x00418e28U) #define gr_gpcs_swdx_bundle_cb_size_r() (0x00418e28U)
#define gr_gpcs_swdx_bundle_cb_size_div_256b_s() (11U) #define gr_gpcs_swdx_bundle_cb_size_div_256b_s() (11U)
#define gr_gpcs_swdx_bundle_cb_size_div_256b_f(v) (((v)&0x7ffU) << 0U) #define gr_gpcs_swdx_bundle_cb_size_div_256b_f(v) ((U32(v) & 0x7ffU) << 0U)
#define gr_gpcs_swdx_bundle_cb_size_div_256b_m() (U32(0x7ffU) << 0U) #define gr_gpcs_swdx_bundle_cb_size_div_256b_m() (U32(0x7ffU) << 0U)
#define gr_gpcs_swdx_bundle_cb_size_div_256b_v(r) (((r) >> 0U) & 0x7ffU) #define gr_gpcs_swdx_bundle_cb_size_div_256b_v(r) (((r) >> 0U) & 0x7ffU)
#define gr_gpcs_swdx_bundle_cb_size_div_256b_init_v() (0x00000030U) #define gr_gpcs_swdx_bundle_cb_size_div_256b_init_v() (0x00000030U)
#define gr_gpcs_swdx_bundle_cb_size_div_256b_init_f() (0x30U) #define gr_gpcs_swdx_bundle_cb_size_div_256b_init_f() (0x30U)
#define gr_gpcs_swdx_bundle_cb_size_valid_s() (1U) #define gr_gpcs_swdx_bundle_cb_size_valid_s() (1U)
#define gr_gpcs_swdx_bundle_cb_size_valid_f(v) (((v)&0x1U) << 31U) #define gr_gpcs_swdx_bundle_cb_size_valid_f(v) ((U32(v) & 0x1U) << 31U)
#define gr_gpcs_swdx_bundle_cb_size_valid_m() (U32(0x1U) << 31U) #define gr_gpcs_swdx_bundle_cb_size_valid_m() (U32(0x1U) << 31U)
#define gr_gpcs_swdx_bundle_cb_size_valid_v(r) (((r) >> 31U) & 0x1U) #define gr_gpcs_swdx_bundle_cb_size_valid_v(r) (((r) >> 31U) & 0x1U)
#define gr_gpcs_swdx_bundle_cb_size_valid_false_v() (0x00000000U) #define gr_gpcs_swdx_bundle_cb_size_valid_false_v() (0x00000000U)
@@ -883,85 +888,92 @@
#define gr_gpcs_swdx_bundle_cb_size_valid_true_v() (0x00000001U) #define gr_gpcs_swdx_bundle_cb_size_valid_true_v() (0x00000001U)
#define gr_gpcs_swdx_bundle_cb_size_valid_true_f() (0x80000000U) #define gr_gpcs_swdx_bundle_cb_size_valid_true_f() (0x80000000U)
#define gr_gpc0_swdx_rm_spill_buffer_size_r() (0x005001dcU) #define gr_gpc0_swdx_rm_spill_buffer_size_r() (0x005001dcU)
#define gr_gpc0_swdx_rm_spill_buffer_size_256b_f(v) (((v)&0xffffU) << 0U) #define gr_gpc0_swdx_rm_spill_buffer_size_256b_f(v) ((U32(v) & 0xffffU) << 0U)
#define gr_gpc0_swdx_rm_spill_buffer_size_256b_default_v() (0x000004b0U) #define gr_gpc0_swdx_rm_spill_buffer_size_256b_default_v() (0x000004b0U)
#define gr_gpc0_swdx_rm_spill_buffer_size_256b_byte_granularity_v()\ #define gr_gpc0_swdx_rm_spill_buffer_size_256b_byte_granularity_v()\
(0x00000100U) (0x00000100U)
#define gr_gpc0_swdx_rm_spill_buffer_addr_r() (0x005001d8U) #define gr_gpc0_swdx_rm_spill_buffer_addr_r() (0x005001d8U)
#define gr_gpc0_swdx_rm_spill_buffer_addr_39_8_f(v) (((v)&0xffffffffU) << 0U) #define gr_gpc0_swdx_rm_spill_buffer_addr_39_8_f(v)\
((U32(v) & 0xffffffffU) << 0U)
#define gr_gpc0_swdx_rm_spill_buffer_addr_39_8_align_bits_v() (0x00000008U) #define gr_gpc0_swdx_rm_spill_buffer_addr_39_8_align_bits_v() (0x00000008U)
#define gr_gpcs_swdx_beta_cb_ctrl_r() (0x004181e4U) #define gr_gpcs_swdx_beta_cb_ctrl_r() (0x004181e4U)
#define gr_gpcs_swdx_beta_cb_ctrl_cbes_reserve_f(v) (((v)&0xfffU) << 0U) #define gr_gpcs_swdx_beta_cb_ctrl_cbes_reserve_f(v) ((U32(v) & 0xfffU) << 0U)
#define gr_gpcs_swdx_beta_cb_ctrl_cbes_reserve_gfxp_v() (0x00000100U) #define gr_gpcs_swdx_beta_cb_ctrl_cbes_reserve_gfxp_v() (0x00000100U)
#define gr_gpcs_ppcs_cbm_beta_cb_ctrl_r() (0x0041befcU) #define gr_gpcs_ppcs_cbm_beta_cb_ctrl_r() (0x0041befcU)
#define gr_gpcs_ppcs_cbm_beta_cb_ctrl_cbes_reserve_f(v) (((v)&0xfffU) << 0U) #define gr_gpcs_ppcs_cbm_beta_cb_ctrl_cbes_reserve_f(v)\
((U32(v) & 0xfffU) << 0U)
#define gr_gpcs_swdx_tc_beta_cb_size_r(i)\ #define gr_gpcs_swdx_tc_beta_cb_size_r(i)\
(nvgpu_safe_add_u32(0x00418ea0U, nvgpu_safe_mult_u32((i), 4U))) (nvgpu_safe_add_u32(0x00418ea0U, nvgpu_safe_mult_u32((i), 4U)))
#define gr_gpcs_swdx_tc_beta_cb_size_v_f(v) (((v)&0x3fffffU) << 0U) #define gr_gpcs_swdx_tc_beta_cb_size_v_f(v) ((U32(v) & 0x3fffffU) << 0U)
#define gr_gpcs_swdx_tc_beta_cb_size_v_m() (U32(0x3fffffU) << 0U) #define gr_gpcs_swdx_tc_beta_cb_size_v_m() (U32(0x3fffffU) << 0U)
#define gr_gpcs_swdx_dss_zbc_color_r_r(i)\ #define gr_gpcs_swdx_dss_zbc_color_r_r(i)\
(nvgpu_safe_add_u32(0x00418010U, nvgpu_safe_mult_u32((i), 4U))) (nvgpu_safe_add_u32(0x00418010U, nvgpu_safe_mult_u32((i), 4U)))
#define gr_gpcs_swdx_dss_zbc_color_r_val_f(v) (((v)&0xffffffffU) << 0U) #define gr_gpcs_swdx_dss_zbc_color_r_val_f(v) ((U32(v) & 0xffffffffU) << 0U)
#define gr_gpcs_swdx_dss_zbc_color_g_r(i)\ #define gr_gpcs_swdx_dss_zbc_color_g_r(i)\
(nvgpu_safe_add_u32(0x0041804cU, nvgpu_safe_mult_u32((i), 4U))) (nvgpu_safe_add_u32(0x0041804cU, nvgpu_safe_mult_u32((i), 4U)))
#define gr_gpcs_swdx_dss_zbc_color_g_val_f(v) (((v)&0xffffffffU) << 0U) #define gr_gpcs_swdx_dss_zbc_color_g_val_f(v) ((U32(v) & 0xffffffffU) << 0U)
#define gr_gpcs_swdx_dss_zbc_color_b_r(i)\ #define gr_gpcs_swdx_dss_zbc_color_b_r(i)\
(nvgpu_safe_add_u32(0x00418088U, nvgpu_safe_mult_u32((i), 4U))) (nvgpu_safe_add_u32(0x00418088U, nvgpu_safe_mult_u32((i), 4U)))
#define gr_gpcs_swdx_dss_zbc_color_b_val_f(v) (((v)&0xffffffffU) << 0U) #define gr_gpcs_swdx_dss_zbc_color_b_val_f(v) ((U32(v) & 0xffffffffU) << 0U)
#define gr_gpcs_swdx_dss_zbc_color_a_r(i)\ #define gr_gpcs_swdx_dss_zbc_color_a_r(i)\
(nvgpu_safe_add_u32(0x004180c4U, nvgpu_safe_mult_u32((i), 4U))) (nvgpu_safe_add_u32(0x004180c4U, nvgpu_safe_mult_u32((i), 4U)))
#define gr_gpcs_swdx_dss_zbc_color_a_val_f(v) (((v)&0xffffffffU) << 0U) #define gr_gpcs_swdx_dss_zbc_color_a_val_f(v) ((U32(v) & 0xffffffffU) << 0U)
#define gr_gpcs_swdx_dss_zbc_c_01_to_04_format_r() (0x00418100U) #define gr_gpcs_swdx_dss_zbc_c_01_to_04_format_r() (0x00418100U)
#define gr_gpcs_swdx_dss_zbc_z_r(i)\ #define gr_gpcs_swdx_dss_zbc_z_r(i)\
(nvgpu_safe_add_u32(0x00418110U, nvgpu_safe_mult_u32((i), 4U))) (nvgpu_safe_add_u32(0x00418110U, nvgpu_safe_mult_u32((i), 4U)))
#define gr_gpcs_swdx_dss_zbc_z_val_f(v) (((v)&0xffffffffU) << 0U) #define gr_gpcs_swdx_dss_zbc_z_val_f(v) ((U32(v) & 0xffffffffU) << 0U)
#define gr_gpcs_swdx_dss_zbc_z_01_to_04_format_r() (0x0041814cU) #define gr_gpcs_swdx_dss_zbc_z_01_to_04_format_r() (0x0041814cU)
#define gr_gpcs_swdx_dss_zbc_s_r(i)\ #define gr_gpcs_swdx_dss_zbc_s_r(i)\
(nvgpu_safe_add_u32(0x0041815cU, nvgpu_safe_mult_u32((i), 4U))) (nvgpu_safe_add_u32(0x0041815cU, nvgpu_safe_mult_u32((i), 4U)))
#define gr_gpcs_swdx_dss_zbc_s_val_f(v) (((v)&0xffU) << 0U) #define gr_gpcs_swdx_dss_zbc_s_val_f(v) ((U32(v) & 0xffU) << 0U)
#define gr_gpcs_swdx_dss_zbc_s_01_to_04_format_r() (0x00418198U) #define gr_gpcs_swdx_dss_zbc_s_01_to_04_format_r() (0x00418198U)
#define gr_gpcs_setup_attrib_cb_base_r() (0x00418810U) #define gr_gpcs_setup_attrib_cb_base_r() (0x00418810U)
#define gr_gpcs_setup_attrib_cb_base_addr_39_12_f(v) (((v)&0xfffffffU) << 0U) #define gr_gpcs_setup_attrib_cb_base_addr_39_12_f(v)\
((U32(v) & 0xfffffffU) << 0U)
#define gr_gpcs_setup_attrib_cb_base_addr_39_12_align_bits_v() (0x0000000cU) #define gr_gpcs_setup_attrib_cb_base_addr_39_12_align_bits_v() (0x0000000cU)
#define gr_gpcs_setup_attrib_cb_base_valid_true_f() (0x80000000U) #define gr_gpcs_setup_attrib_cb_base_valid_true_f() (0x80000000U)
#define gr_crstr_gpc_map_r(i)\ #define gr_crstr_gpc_map_r(i)\
(nvgpu_safe_add_u32(0x00418b08U, nvgpu_safe_mult_u32((i), 4U))) (nvgpu_safe_add_u32(0x00418b08U, nvgpu_safe_mult_u32((i), 4U)))
#define gr_crstr_gpc_map_tile0_f(v) (((v)&0x1fU) << 0U) #define gr_crstr_gpc_map_tile0_f(v) ((U32(v) & 0x1fU) << 0U)
#define gr_crstr_gpc_map_tile1_f(v) (((v)&0x1fU) << 5U) #define gr_crstr_gpc_map_tile1_f(v) ((U32(v) & 0x1fU) << 5U)
#define gr_crstr_gpc_map_tile2_f(v) (((v)&0x1fU) << 10U) #define gr_crstr_gpc_map_tile2_f(v) ((U32(v) & 0x1fU) << 10U)
#define gr_crstr_gpc_map_tile3_f(v) (((v)&0x1fU) << 15U) #define gr_crstr_gpc_map_tile3_f(v) ((U32(v) & 0x1fU) << 15U)
#define gr_crstr_gpc_map_tile4_f(v) (((v)&0x1fU) << 20U) #define gr_crstr_gpc_map_tile4_f(v) ((U32(v) & 0x1fU) << 20U)
#define gr_crstr_gpc_map_tile5_f(v) (((v)&0x1fU) << 25U) #define gr_crstr_gpc_map_tile5_f(v) ((U32(v) & 0x1fU) << 25U)
#define gr_crstr_map_table_cfg_r() (0x00418bb8U) #define gr_crstr_map_table_cfg_r() (0x00418bb8U)
#define gr_crstr_map_table_cfg_row_offset_f(v) (((v)&0xffU) << 0U) #define gr_crstr_map_table_cfg_row_offset_f(v) ((U32(v) & 0xffU) << 0U)
#define gr_crstr_map_table_cfg_num_entries_f(v) (((v)&0xffU) << 8U) #define gr_crstr_map_table_cfg_num_entries_f(v) ((U32(v) & 0xffU) << 8U)
#define gr_gpcs_zcull_sm_in_gpc_number_map_r(i)\ #define gr_gpcs_zcull_sm_in_gpc_number_map_r(i)\
(nvgpu_safe_add_u32(0x00418980U, nvgpu_safe_mult_u32((i), 4U))) (nvgpu_safe_add_u32(0x00418980U, nvgpu_safe_mult_u32((i), 4U)))
#define gr_gpcs_zcull_sm_in_gpc_number_map_tile_0_f(v) (((v)&0x7U) << 0U) #define gr_gpcs_zcull_sm_in_gpc_number_map_tile_0_f(v) ((U32(v) & 0x7U) << 0U)
#define gr_gpcs_zcull_sm_in_gpc_number_map_tile_1_f(v) (((v)&0x7U) << 4U) #define gr_gpcs_zcull_sm_in_gpc_number_map_tile_1_f(v) ((U32(v) & 0x7U) << 4U)
#define gr_gpcs_zcull_sm_in_gpc_number_map_tile_2_f(v) (((v)&0x7U) << 8U) #define gr_gpcs_zcull_sm_in_gpc_number_map_tile_2_f(v) ((U32(v) & 0x7U) << 8U)
#define gr_gpcs_zcull_sm_in_gpc_number_map_tile_3_f(v) (((v)&0x7U) << 12U) #define gr_gpcs_zcull_sm_in_gpc_number_map_tile_3_f(v) ((U32(v) & 0x7U) << 12U)
#define gr_gpcs_zcull_sm_in_gpc_number_map_tile_4_f(v) (((v)&0x7U) << 16U) #define gr_gpcs_zcull_sm_in_gpc_number_map_tile_4_f(v) ((U32(v) & 0x7U) << 16U)
#define gr_gpcs_zcull_sm_in_gpc_number_map_tile_5_f(v) (((v)&0x7U) << 20U) #define gr_gpcs_zcull_sm_in_gpc_number_map_tile_5_f(v) ((U32(v) & 0x7U) << 20U)
#define gr_gpcs_zcull_sm_in_gpc_number_map_tile_6_f(v) (((v)&0x7U) << 24U) #define gr_gpcs_zcull_sm_in_gpc_number_map_tile_6_f(v) ((U32(v) & 0x7U) << 24U)
#define gr_gpcs_zcull_sm_in_gpc_number_map_tile_7_f(v) (((v)&0x7U) << 28U) #define gr_gpcs_zcull_sm_in_gpc_number_map_tile_7_f(v) ((U32(v) & 0x7U) << 28U)
#define gr_gpcs_gpm_pd_cfg_r() (0x00418c6cU) #define gr_gpcs_gpm_pd_cfg_r() (0x00418c6cU)
#define gr_gpcs_gcc_pagepool_base_r() (0x00419004U) #define gr_gpcs_gcc_pagepool_base_r() (0x00419004U)
#define gr_gpcs_gcc_pagepool_base_addr_39_8_f(v) (((v)&0xffffffffU) << 0U) #define gr_gpcs_gcc_pagepool_base_addr_39_8_f(v) ((U32(v) & 0xffffffffU) << 0U)
#define gr_gpcs_gcc_pagepool_r() (0x00419008U) #define gr_gpcs_gcc_pagepool_r() (0x00419008U)
#define gr_gpcs_gcc_pagepool_total_pages_f(v) (((v)&0x3ffU) << 0U) #define gr_gpcs_gcc_pagepool_total_pages_f(v) ((U32(v) & 0x3ffU) << 0U)
#define gr_gpcs_tpcs_pe_vaf_r() (0x0041980cU) #define gr_gpcs_tpcs_pe_vaf_r() (0x0041980cU)
#define gr_gpcs_tpcs_pe_vaf_fast_mode_switch_true_f() (0x10U) #define gr_gpcs_tpcs_pe_vaf_fast_mode_switch_true_f() (0x10U)
#define gr_gpcs_tpcs_pe_pin_cb_global_base_addr_r() (0x00419848U) #define gr_gpcs_tpcs_pe_pin_cb_global_base_addr_r() (0x00419848U)
#define gr_gpcs_tpcs_pe_pin_cb_global_base_addr_v_f(v) (((v)&0xfffffffU) << 0U) #define gr_gpcs_tpcs_pe_pin_cb_global_base_addr_v_f(v)\
#define gr_gpcs_tpcs_pe_pin_cb_global_base_addr_valid_f(v) (((v)&0x1U) << 28U) ((U32(v) & 0xfffffffU) << 0U)
#define gr_gpcs_tpcs_pe_pin_cb_global_base_addr_valid_f(v)\
((U32(v) & 0x1U) << 28U)
#define gr_gpcs_tpcs_pe_pin_cb_global_base_addr_valid_true_f() (0x10000000U) #define gr_gpcs_tpcs_pe_pin_cb_global_base_addr_valid_true_f() (0x10000000U)
#define gr_gpcs_tpcs_mpc_vtg_debug_r() (0x00419c00U) #define gr_gpcs_tpcs_mpc_vtg_debug_r() (0x00419c00U)
#define gr_gpcs_tpcs_mpc_vtg_debug_timeslice_mode_disabled_f() (0x0U) #define gr_gpcs_tpcs_mpc_vtg_debug_timeslice_mode_disabled_f() (0x0U)
#define gr_gpcs_tpcs_mpc_vtg_debug_timeslice_mode_enabled_f() (0x8U) #define gr_gpcs_tpcs_mpc_vtg_debug_timeslice_mode_enabled_f() (0x8U)
#define gr_gpcs_tpcs_mpc_vtg_cb_global_base_addr_r() (0x00419c2cU) #define gr_gpcs_tpcs_mpc_vtg_cb_global_base_addr_r() (0x00419c2cU)
#define gr_gpcs_tpcs_mpc_vtg_cb_global_base_addr_v_f(v) (((v)&0xfffffffU) << 0U) #define gr_gpcs_tpcs_mpc_vtg_cb_global_base_addr_v_f(v)\
#define gr_gpcs_tpcs_mpc_vtg_cb_global_base_addr_valid_f(v) (((v)&0x1U) << 28U) ((U32(v) & 0xfffffffU) << 0U)
#define gr_gpcs_tpcs_mpc_vtg_cb_global_base_addr_valid_f(v)\
((U32(v) & 0x1U) << 28U)
#define gr_gpcs_tpcs_mpc_vtg_cb_global_base_addr_valid_true_f() (0x10000000U) #define gr_gpcs_tpcs_mpc_vtg_cb_global_base_addr_valid_true_f() (0x10000000U)
#define gr_gpcs_tpcs_sms_hww_warp_esr_report_mask_r() (0x00419ea8U) #define gr_gpcs_tpcs_sms_hww_warp_esr_report_mask_r() (0x00419ea8U)
#define gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_r() (0x00504728U) #define gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_r() (0x00504728U)
@@ -1001,8 +1013,8 @@
#define gr_gpc0_tpc0_tpccs_tpc_exception_en_sm_enabled_f() (0x2U) #define gr_gpc0_tpc0_tpccs_tpc_exception_en_sm_enabled_f() (0x2U)
#define gr_gpc0_tpc0_tpccs_tpc_exception_en_mpc_enabled_f() (0x10U) #define gr_gpc0_tpc0_tpccs_tpc_exception_en_mpc_enabled_f() (0x10U)
#define gr_gpcs_gpccs_gpc_exception_en_r() (0x0041ac94U) #define gr_gpcs_gpccs_gpc_exception_en_r() (0x0041ac94U)
#define gr_gpcs_gpccs_gpc_exception_en_gcc_f(v) (((v)&0x1U) << 2U) #define gr_gpcs_gpccs_gpc_exception_en_gcc_f(v) ((U32(v) & 0x1U) << 2U)
#define gr_gpcs_gpccs_gpc_exception_en_tpc_f(v) (((v)&0xffU) << 16U) #define gr_gpcs_gpccs_gpc_exception_en_tpc_f(v) ((U32(v) & 0xffU) << 16U)
#define gr_gpc0_gpccs_gpc_exception_r() (0x00502c90U) #define gr_gpc0_gpccs_gpc_exception_r() (0x00502c90U)
#define gr_gpc0_gpccs_gpc_exception_gcc_v(r) (((r) >> 2U) & 0x1U) #define gr_gpc0_gpccs_gpc_exception_gcc_v(r) (((r) >> 2U) & 0x1U)
#define gr_gpc0_gpccs_gpc_exception_tpc_v(r) (((r) >> 16U) & 0xffU) #define gr_gpc0_gpccs_gpc_exception_tpc_v(r) (((r) >> 16U) & 0xffU)
@@ -1074,33 +1086,40 @@
#define gr_gpc0_tpc0_sm_halfctl_ctrl_r() (0x005043a0U) #define gr_gpc0_tpc0_sm_halfctl_ctrl_r() (0x005043a0U)
#define gr_gpcs_tpcs_sm_halfctl_ctrl_r() (0x00419ba0U) #define gr_gpcs_tpcs_sm_halfctl_ctrl_r() (0x00419ba0U)
#define gr_gpcs_tpcs_sm_halfctl_ctrl_sctl_read_quad_ctl_m() (U32(0x1U) << 4U) #define gr_gpcs_tpcs_sm_halfctl_ctrl_sctl_read_quad_ctl_m() (U32(0x1U) << 4U)
#define gr_gpcs_tpcs_sm_halfctl_ctrl_sctl_read_quad_ctl_f(v) (((v)&0x1U) << 4U) #define gr_gpcs_tpcs_sm_halfctl_ctrl_sctl_read_quad_ctl_f(v)\
((U32(v) & 0x1U) << 4U)
#define gr_gpc0_tpc0_sm_debug_sfe_control_r() (0x005043b0U) #define gr_gpc0_tpc0_sm_debug_sfe_control_r() (0x005043b0U)
#define gr_gpcs_tpcs_sm_debug_sfe_control_r() (0x00419bb0U) #define gr_gpcs_tpcs_sm_debug_sfe_control_r() (0x00419bb0U)
#define gr_gpcs_tpcs_sm_debug_sfe_control_read_half_ctl_m() (U32(0x1U) << 0U) #define gr_gpcs_tpcs_sm_debug_sfe_control_read_half_ctl_m() (U32(0x1U) << 0U)
#define gr_gpcs_tpcs_sm_debug_sfe_control_read_half_ctl_f(v) (((v)&0x1U) << 0U) #define gr_gpcs_tpcs_sm_debug_sfe_control_read_half_ctl_f(v)\
((U32(v) & 0x1U) << 0U)
#define gr_gpcs_tpcs_pes_vsc_vpc_r() (0x0041be08U) #define gr_gpcs_tpcs_pes_vsc_vpc_r() (0x0041be08U)
#define gr_gpcs_tpcs_pes_vsc_vpc_fast_mode_switch_true_f() (0x4U) #define gr_gpcs_tpcs_pes_vsc_vpc_fast_mode_switch_true_f() (0x4U)
#define gr_ppcs_wwdx_map_gpc_map_r(i)\ #define gr_ppcs_wwdx_map_gpc_map_r(i)\
(nvgpu_safe_add_u32(0x0041bf00U, nvgpu_safe_mult_u32((i), 4U))) (nvgpu_safe_add_u32(0x0041bf00U, nvgpu_safe_mult_u32((i), 4U)))
#define gr_ppcs_wwdx_map_table_cfg_r() (0x0041bfd0U) #define gr_ppcs_wwdx_map_table_cfg_r() (0x0041bfd0U)
#define gr_ppcs_wwdx_map_table_cfg_row_offset_f(v) (((v)&0xffU) << 0U) #define gr_ppcs_wwdx_map_table_cfg_row_offset_f(v) ((U32(v) & 0xffU) << 0U)
#define gr_ppcs_wwdx_map_table_cfg_num_entries_f(v) (((v)&0xffU) << 8U) #define gr_ppcs_wwdx_map_table_cfg_num_entries_f(v) ((U32(v) & 0xffU) << 8U)
#define gr_ppcs_wwdx_map_table_cfg_normalized_num_entries_f(v)\ #define gr_ppcs_wwdx_map_table_cfg_normalized_num_entries_f(v)\
(((v)&0x1fU) << 16U) ((U32(v) & 0x1fU) << 16U)
#define gr_ppcs_wwdx_map_table_cfg_normalized_shift_value_f(v)\ #define gr_ppcs_wwdx_map_table_cfg_normalized_shift_value_f(v)\
(((v)&0x7U) << 21U) ((U32(v) & 0x7U) << 21U)
#define gr_gpcs_ppcs_wwdx_sm_num_rcp_r() (0x0041bfd4U) #define gr_gpcs_ppcs_wwdx_sm_num_rcp_r() (0x0041bfd4U)
#define gr_gpcs_ppcs_wwdx_sm_num_rcp_conservative_f(v) (((v)&0xffffffU) << 0U) #define gr_gpcs_ppcs_wwdx_sm_num_rcp_conservative_f(v)\
((U32(v) & 0xffffffU) << 0U)
#define gr_ppcs_wwdx_map_table_cfg_coeff_r(i)\ #define gr_ppcs_wwdx_map_table_cfg_coeff_r(i)\
(nvgpu_safe_add_u32(0x0041bfb0U, nvgpu_safe_mult_u32((i), 4U))) (nvgpu_safe_add_u32(0x0041bfb0U, nvgpu_safe_mult_u32((i), 4U)))
#define gr_ppcs_wwdx_map_table_cfg_coeff__size_1_v() (0x00000005U) #define gr_ppcs_wwdx_map_table_cfg_coeff__size_1_v() (0x00000005U)
#define gr_ppcs_wwdx_map_table_cfg_coeff_0_mod_value_f(v) (((v)&0xffU) << 0U) #define gr_ppcs_wwdx_map_table_cfg_coeff_0_mod_value_f(v)\
#define gr_ppcs_wwdx_map_table_cfg_coeff_1_mod_value_f(v) (((v)&0xffU) << 8U) ((U32(v) & 0xffU) << 0U)
#define gr_ppcs_wwdx_map_table_cfg_coeff_2_mod_value_f(v) (((v)&0xffU) << 16U) #define gr_ppcs_wwdx_map_table_cfg_coeff_1_mod_value_f(v)\
#define gr_ppcs_wwdx_map_table_cfg_coeff_3_mod_value_f(v) (((v)&0xffU) << 24U) ((U32(v) & 0xffU) << 8U)
#define gr_ppcs_wwdx_map_table_cfg_coeff_2_mod_value_f(v)\
((U32(v) & 0xffU) << 16U)
#define gr_ppcs_wwdx_map_table_cfg_coeff_3_mod_value_f(v)\
((U32(v) & 0xffU) << 24U)
#define gr_bes_zrop_settings_r() (0x00408850U) #define gr_bes_zrop_settings_r() (0x00408850U)
#define gr_bes_zrop_settings_num_active_ltcs_f(v) (((v)&0xfU) << 0U) #define gr_bes_zrop_settings_num_active_ltcs_f(v) ((U32(v) & 0xfU) << 0U)
#define gr_be0_crop_debug3_r() (0x00410108U) #define gr_be0_crop_debug3_r() (0x00410108U)
#define gr_bes_crop_debug3_r() (0x00408908U) #define gr_bes_crop_debug3_r() (0x00408908U)
#define gr_bes_crop_debug3_comp_vdc_4to2_disable_m() (U32(0x1U) << 31U) #define gr_bes_crop_debug3_comp_vdc_4to2_disable_m() (U32(0x1U) << 31U)
@@ -1115,18 +1134,20 @@
#define gr_bes_crop_debug4_clamp_fp_blend_to_inf_f() (0x0U) #define gr_bes_crop_debug4_clamp_fp_blend_to_inf_f() (0x0U)
#define gr_bes_crop_debug4_clamp_fp_blend_to_maxval_f() (0x40000U) #define gr_bes_crop_debug4_clamp_fp_blend_to_maxval_f() (0x40000U)
#define gr_bes_crop_settings_r() (0x00408958U) #define gr_bes_crop_settings_r() (0x00408958U)
#define gr_bes_crop_settings_num_active_ltcs_f(v) (((v)&0xfU) << 0U) #define gr_bes_crop_settings_num_active_ltcs_f(v) ((U32(v) & 0xfU) << 0U)
#define gr_zcull_bytes_per_aliquot_per_gpu_v() (0x00000020U) #define gr_zcull_bytes_per_aliquot_per_gpu_v() (0x00000020U)
#define gr_zcull_save_restore_header_bytes_per_gpc_v() (0x00000020U) #define gr_zcull_save_restore_header_bytes_per_gpc_v() (0x00000020U)
#define gr_zcull_save_restore_subregion_header_bytes_per_gpc_v() (0x000000c0U) #define gr_zcull_save_restore_subregion_header_bytes_per_gpc_v() (0x000000c0U)
#define gr_zcull_subregion_qty_v() (0x00000010U) #define gr_zcull_subregion_qty_v() (0x00000010U)
#define gr_gpcs_tpcs_tex_in_dbg_r() (0x00419a00U) #define gr_gpcs_tpcs_tex_in_dbg_r() (0x00419a00U)
#define gr_gpcs_tpcs_tex_in_dbg_tsl1_rvch_invalidate_f(v) (((v)&0x1U) << 19U) #define gr_gpcs_tpcs_tex_in_dbg_tsl1_rvch_invalidate_f(v)\
((U32(v) & 0x1U) << 19U)
#define gr_gpcs_tpcs_tex_in_dbg_tsl1_rvch_invalidate_m() (U32(0x1U) << 19U) #define gr_gpcs_tpcs_tex_in_dbg_tsl1_rvch_invalidate_m() (U32(0x1U) << 19U)
#define gr_gpcs_tpcs_sm_l1tag_ctrl_r() (0x00419bf0U) #define gr_gpcs_tpcs_sm_l1tag_ctrl_r() (0x00419bf0U)
#define gr_gpcs_tpcs_sm_l1tag_ctrl_cache_surface_ld_f(v) (((v)&0x1U) << 5U) #define gr_gpcs_tpcs_sm_l1tag_ctrl_cache_surface_ld_f(v) ((U32(v) & 0x1U) << 5U)
#define gr_gpcs_tpcs_sm_l1tag_ctrl_cache_surface_ld_m() (U32(0x1U) << 5U) #define gr_gpcs_tpcs_sm_l1tag_ctrl_cache_surface_ld_m() (U32(0x1U) << 5U)
#define gr_gpcs_tpcs_sm_l1tag_ctrl_cache_surface_st_f(v) (((v)&0x1U) << 10U) #define gr_gpcs_tpcs_sm_l1tag_ctrl_cache_surface_st_f(v)\
((U32(v) & 0x1U) << 10U)
#define gr_gpcs_tpcs_sm_l1tag_ctrl_cache_surface_st_m() (U32(0x1U) << 10U) #define gr_gpcs_tpcs_sm_l1tag_ctrl_cache_surface_st_m() (U32(0x1U) << 10U)
#define gr_gpcs_tpcs_sm_l1tag_ctrl_always_cut_collector_m() (U32(0x1U) << 28U) #define gr_gpcs_tpcs_sm_l1tag_ctrl_always_cut_collector_m() (U32(0x1U) << 28U)
#define gr_gpcs_tpcs_sm_l1tag_ctrl_always_cut_collector_disable_f() (0x0U) #define gr_gpcs_tpcs_sm_l1tag_ctrl_always_cut_collector_disable_f() (0x0U)
@@ -1159,11 +1180,11 @@
#define gr_gpcs_mmu_num_active_ltcs_r() (0x004188acU) #define gr_gpcs_mmu_num_active_ltcs_r() (0x004188acU)
#define gr_gpcs_tpcs_sms_dbgr_control0_r() (0x00419e84U) #define gr_gpcs_tpcs_sms_dbgr_control0_r() (0x00419e84U)
#define gr_fe_gfxp_wfi_timeout_r() (0x004041c0U) #define gr_fe_gfxp_wfi_timeout_r() (0x004041c0U)
#define gr_fe_gfxp_wfi_timeout_count_f(v) (((v)&0xffffffffU) << 0U) #define gr_fe_gfxp_wfi_timeout_count_f(v) ((U32(v) & 0xffffffffU) << 0U)
#define gr_fe_gfxp_wfi_timeout_count_disabled_f() (0x0U) #define gr_fe_gfxp_wfi_timeout_count_disabled_f() (0x0U)
#define gr_gpcs_tpcs_sm_texio_control_r() (0x00419bd8U) #define gr_gpcs_tpcs_sm_texio_control_r() (0x00419bd8U)
#define gr_gpcs_tpcs_sm_texio_control_oor_addr_check_mode_f(v)\ #define gr_gpcs_tpcs_sm_texio_control_oor_addr_check_mode_f(v)\
(((v)&0x7U) << 8U) ((U32(v) & 0x7U) << 8U)
#define gr_gpcs_tpcs_sm_texio_control_oor_addr_check_mode_m() (U32(0x7U) << 8U) #define gr_gpcs_tpcs_sm_texio_control_oor_addr_check_mode_m() (U32(0x7U) << 8U)
#define gr_gpcs_tpcs_sm_texio_control_oor_addr_check_mode_arm_63_48_match_f()\ #define gr_gpcs_tpcs_sm_texio_control_oor_addr_check_mode_arm_63_48_match_f()\
(0x100U) (0x100U)
@@ -1171,6 +1192,7 @@
#define gr_gpcs_tpcs_sm_disp_ctrl_re_suppress_m() (U32(0x3U) << 11U) #define gr_gpcs_tpcs_sm_disp_ctrl_re_suppress_m() (U32(0x3U) << 11U)
#define gr_gpcs_tpcs_sm_disp_ctrl_re_suppress_disable_f() (0x1000U) #define gr_gpcs_tpcs_sm_disp_ctrl_re_suppress_disable_f() (0x1000U)
#define gr_gpcs_tc_debug0_r() (0x00418708U) #define gr_gpcs_tc_debug0_r() (0x00418708U)
#define gr_gpcs_tc_debug0_limit_coalesce_buffer_size_f(v) (((v)&0x1ffU) << 0U) #define gr_gpcs_tc_debug0_limit_coalesce_buffer_size_f(v)\
((U32(v) & 0x1ffU) << 0U)
#define gr_gpcs_tc_debug0_limit_coalesce_buffer_size_m() (U32(0x1ffU) << 0U) #define gr_gpcs_tc_debug0_limit_coalesce_buffer_size_m() (U32(0x1ffU) << 0U)
#endif #endif

52
drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_ioctrl_gv100.h
View File

@@ -61,73 +61,73 @@
#define ioctrl_reset_r() (0x00000140U) #define ioctrl_reset_r() (0x00000140U)
#define ioctrl_reset_sw_post_reset_delay_microseconds_v() (0x00000008U) #define ioctrl_reset_sw_post_reset_delay_microseconds_v() (0x00000008U)
#define ioctrl_reset_linkreset_f(v) (((v)&0x3fU) << 8U) #define ioctrl_reset_linkreset_f(v) ((U32(v) & 0x3fU) << 8U)
#define ioctrl_reset_linkreset_m() (U32(0x3fU) << 8U) #define ioctrl_reset_linkreset_m() (U32(0x3fU) << 8U)
#define ioctrl_reset_linkreset_v(r) (((r) >> 8U) & 0x3fU) #define ioctrl_reset_linkreset_v(r) (((r) >> 8U) & 0x3fU)
#define ioctrl_debug_reset_r() (0x00000144U) #define ioctrl_debug_reset_r() (0x00000144U)
#define ioctrl_debug_reset_link_f(v) (((v)&0x3fU) << 0U) #define ioctrl_debug_reset_link_f(v) ((U32(v) & 0x3fU) << 0U)
#define ioctrl_debug_reset_link_m() (U32(0x3fU) << 0U) #define ioctrl_debug_reset_link_m() (U32(0x3fU) << 0U)
#define ioctrl_debug_reset_link_v(r) (((r) >> 0U) & 0x3fU) #define ioctrl_debug_reset_link_v(r) (((r) >> 0U) & 0x3fU)
#define ioctrl_debug_reset_common_f(v) (((v)&0x1U) << 31U) #define ioctrl_debug_reset_common_f(v) ((U32(v) & 0x1U) << 31U)
#define ioctrl_debug_reset_common_m() (U32(0x1U) << 31U) #define ioctrl_debug_reset_common_m() (U32(0x1U) << 31U)
#define ioctrl_debug_reset_common_v(r) (((r) >> 31U) & 0x1U) #define ioctrl_debug_reset_common_v(r) (((r) >> 31U) & 0x1U)
#define ioctrl_clock_control_r(i)\ #define ioctrl_clock_control_r(i)\
(nvgpu_safe_add_u32(0x00000180U, nvgpu_safe_mult_u32((i), 4U))) (nvgpu_safe_add_u32(0x00000180U, nvgpu_safe_mult_u32((i), 4U)))
#define ioctrl_clock_control__size_1_v() (0x00000006U) #define ioctrl_clock_control__size_1_v() (0x00000006U)
#define ioctrl_clock_control_clkdis_f(v) (((v)&0x1U) << 0U) #define ioctrl_clock_control_clkdis_f(v) ((U32(v) & 0x1U) << 0U)
#define ioctrl_clock_control_clkdis_m() (U32(0x1U) << 0U) #define ioctrl_clock_control_clkdis_m() (U32(0x1U) << 0U)
#define ioctrl_clock_control_clkdis_v(r) (((r) >> 0U) & 0x1U) #define ioctrl_clock_control_clkdis_v(r) (((r) >> 0U) & 0x1U)
#define ioctrl_top_intr_0_status_r() (0x00000200U) #define ioctrl_top_intr_0_status_r() (0x00000200U)
#define ioctrl_top_intr_0_status_link_f(v) (((v)&0x3fU) << 0U) #define ioctrl_top_intr_0_status_link_f(v) ((U32(v) & 0x3fU) << 0U)
#define ioctrl_top_intr_0_status_link_m() (U32(0x3fU) << 0U) #define ioctrl_top_intr_0_status_link_m() (U32(0x3fU) << 0U)
#define ioctrl_top_intr_0_status_link_v(r) (((r) >> 0U) & 0x3fU) #define ioctrl_top_intr_0_status_link_v(r) (((r) >> 0U) & 0x3fU)
#define ioctrl_top_intr_0_status_common_f(v) (((v)&0x1U) << 31U) #define ioctrl_top_intr_0_status_common_f(v) ((U32(v) & 0x1U) << 31U)
#define ioctrl_top_intr_0_status_common_m() (U32(0x1U) << 31U) #define ioctrl_top_intr_0_status_common_m() (U32(0x1U) << 31U)
#define ioctrl_top_intr_0_status_common_v(r) (((r) >> 31U) & 0x1U) #define ioctrl_top_intr_0_status_common_v(r) (((r) >> 31U) & 0x1U)
#define ioctrl_common_intr_0_mask_r() (0x00000220U) #define ioctrl_common_intr_0_mask_r() (0x00000220U)
#define ioctrl_common_intr_0_mask_fatal_f(v) (((v)&0x1U) << 0U) #define ioctrl_common_intr_0_mask_fatal_f(v) ((U32(v) & 0x1U) << 0U)
#define ioctrl_common_intr_0_mask_fatal_v(r) (((r) >> 0U) & 0x1U) #define ioctrl_common_intr_0_mask_fatal_v(r) (((r) >> 0U) & 0x1U)
#define ioctrl_common_intr_0_mask_nonfatal_f(v) (((v)&0x1U) << 1U) #define ioctrl_common_intr_0_mask_nonfatal_f(v) ((U32(v) & 0x1U) << 1U)
#define ioctrl_common_intr_0_mask_nonfatal_v(r) (((r) >> 1U) & 0x1U) #define ioctrl_common_intr_0_mask_nonfatal_v(r) (((r) >> 1U) & 0x1U)
#define ioctrl_common_intr_0_mask_correctable_f(v) (((v)&0x1U) << 2U) #define ioctrl_common_intr_0_mask_correctable_f(v) ((U32(v) & 0x1U) << 2U)
#define ioctrl_common_intr_0_mask_correctable_v(r) (((r) >> 2U) & 0x1U) #define ioctrl_common_intr_0_mask_correctable_v(r) (((r) >> 2U) & 0x1U)
#define ioctrl_common_intr_0_mask_intra_f(v) (((v)&0x1U) << 3U) #define ioctrl_common_intr_0_mask_intra_f(v) ((U32(v) & 0x1U) << 3U)
#define ioctrl_common_intr_0_mask_intra_v(r) (((r) >> 3U) & 0x1U) #define ioctrl_common_intr_0_mask_intra_v(r) (((r) >> 3U) & 0x1U)
#define ioctrl_common_intr_0_mask_intrb_f(v) (((v)&0x1U) << 4U) #define ioctrl_common_intr_0_mask_intrb_f(v) ((U32(v) & 0x1U) << 4U)
#define ioctrl_common_intr_0_mask_intrb_v(r) (((r) >> 4U) & 0x1U) #define ioctrl_common_intr_0_mask_intrb_v(r) (((r) >> 4U) & 0x1U)
#define ioctrl_common_intr_0_status_r() (0x00000224U) #define ioctrl_common_intr_0_status_r() (0x00000224U)
#define ioctrl_common_intr_0_status_fatal_f(v) (((v)&0x1U) << 0U) #define ioctrl_common_intr_0_status_fatal_f(v) ((U32(v) & 0x1U) << 0U)
#define ioctrl_common_intr_0_status_fatal_v(r) (((r) >> 0U) & 0x1U) #define ioctrl_common_intr_0_status_fatal_v(r) (((r) >> 0U) & 0x1U)
#define ioctrl_common_intr_0_status_nonfatal_f(v) (((v)&0x1U) << 1U) #define ioctrl_common_intr_0_status_nonfatal_f(v) ((U32(v) & 0x1U) << 1U)
#define ioctrl_common_intr_0_status_nonfatal_v(r) (((r) >> 1U) & 0x1U) #define ioctrl_common_intr_0_status_nonfatal_v(r) (((r) >> 1U) & 0x1U)
#define ioctrl_common_intr_0_status_correctable_f(v) (((v)&0x1U) << 2U) #define ioctrl_common_intr_0_status_correctable_f(v) ((U32(v) & 0x1U) << 2U)
#define ioctrl_common_intr_0_status_correctable_v(r) (((r) >> 2U) & 0x1U) #define ioctrl_common_intr_0_status_correctable_v(r) (((r) >> 2U) & 0x1U)
#define ioctrl_common_intr_0_status_intra_f(v) (((v)&0x1U) << 3U) #define ioctrl_common_intr_0_status_intra_f(v) ((U32(v) & 0x1U) << 3U)
#define ioctrl_common_intr_0_status_intra_v(r) (((r) >> 3U) & 0x1U) #define ioctrl_common_intr_0_status_intra_v(r) (((r) >> 3U) & 0x1U)
#define ioctrl_common_intr_0_status_intrb_f(v) (((v)&0x1U) << 4U) #define ioctrl_common_intr_0_status_intrb_f(v) ((U32(v) & 0x1U) << 4U)
#define ioctrl_common_intr_0_status_intrb_v(r) (((r) >> 4U) & 0x1U) #define ioctrl_common_intr_0_status_intrb_v(r) (((r) >> 4U) & 0x1U)
#define ioctrl_link_intr_0_mask_r(i)\ #define ioctrl_link_intr_0_mask_r(i)\
(nvgpu_safe_add_u32(0x00000240U, nvgpu_safe_mult_u32((i), 20U))) (nvgpu_safe_add_u32(0x00000240U, nvgpu_safe_mult_u32((i), 20U)))
#define ioctrl_link_intr_0_mask_fatal_f(v) (((v)&0x1U) << 0U) #define ioctrl_link_intr_0_mask_fatal_f(v) ((U32(v) & 0x1U) << 0U)
#define ioctrl_link_intr_0_mask_fatal_v(r) (((r) >> 0U) & 0x1U) #define ioctrl_link_intr_0_mask_fatal_v(r) (((r) >> 0U) & 0x1U)
#define ioctrl_link_intr_0_mask_nonfatal_f(v) (((v)&0x1U) << 1U) #define ioctrl_link_intr_0_mask_nonfatal_f(v) ((U32(v) & 0x1U) << 1U)
#define ioctrl_link_intr_0_mask_nonfatal_v(r) (((r) >> 1U) & 0x1U) #define ioctrl_link_intr_0_mask_nonfatal_v(r) (((r) >> 1U) & 0x1U)
#define ioctrl_link_intr_0_mask_correctable_f(v) (((v)&0x1U) << 2U) #define ioctrl_link_intr_0_mask_correctable_f(v) ((U32(v) & 0x1U) << 2U)
#define ioctrl_link_intr_0_mask_correctable_v(r) (((r) >> 2U) & 0x1U) #define ioctrl_link_intr_0_mask_correctable_v(r) (((r) >> 2U) & 0x1U)
#define ioctrl_link_intr_0_mask_intra_f(v) (((v)&0x1U) << 3U) #define ioctrl_link_intr_0_mask_intra_f(v) ((U32(v) & 0x1U) << 3U)
#define ioctrl_link_intr_0_mask_intra_v(r) (((r) >> 3U) & 0x1U) #define ioctrl_link_intr_0_mask_intra_v(r) (((r) >> 3U) & 0x1U)
#define ioctrl_link_intr_0_mask_intrb_f(v) (((v)&0x1U) << 4U) #define ioctrl_link_intr_0_mask_intrb_f(v) ((U32(v) & 0x1U) << 4U)
#define ioctrl_link_intr_0_mask_intrb_v(r) (((r) >> 4U) & 0x1U) #define ioctrl_link_intr_0_mask_intrb_v(r) (((r) >> 4U) & 0x1U)
#define ioctrl_link_intr_0_status_r(i)\ #define ioctrl_link_intr_0_status_r(i)\
(nvgpu_safe_add_u32(0x00000244U, nvgpu_safe_mult_u32((i), 20U))) (nvgpu_safe_add_u32(0x00000244U, nvgpu_safe_mult_u32((i), 20U)))
#define ioctrl_link_intr_0_status_fatal_f(v) (((v)&0x1U) << 0U) #define ioctrl_link_intr_0_status_fatal_f(v) ((U32(v) & 0x1U) << 0U)
#define ioctrl_link_intr_0_status_fatal_v(r) (((r) >> 0U) & 0x1U) #define ioctrl_link_intr_0_status_fatal_v(r) (((r) >> 0U) & 0x1U)
#define ioctrl_link_intr_0_status_nonfatal_f(v) (((v)&0x1U) << 1U) #define ioctrl_link_intr_0_status_nonfatal_f(v) ((U32(v) & 0x1U) << 1U)
#define ioctrl_link_intr_0_status_nonfatal_v(r) (((r) >> 1U) & 0x1U) #define ioctrl_link_intr_0_status_nonfatal_v(r) (((r) >> 1U) & 0x1U)
#define ioctrl_link_intr_0_status_correctable_f(v) (((v)&0x1U) << 2U) #define ioctrl_link_intr_0_status_correctable_f(v) ((U32(v) & 0x1U) << 2U)
#define ioctrl_link_intr_0_status_correctable_v(r) (((r) >> 2U) & 0x1U) #define ioctrl_link_intr_0_status_correctable_v(r) (((r) >> 2U) & 0x1U)
#define ioctrl_link_intr_0_status_intra_f(v) (((v)&0x1U) << 3U) #define ioctrl_link_intr_0_status_intra_f(v) ((U32(v) & 0x1U) << 3U)
#define ioctrl_link_intr_0_status_intra_v(r) (((r) >> 3U) & 0x1U) #define ioctrl_link_intr_0_status_intra_v(r) (((r) >> 3U) & 0x1U)
#define ioctrl_link_intr_0_status_intrb_f(v) (((v)&0x1U) << 4U) #define ioctrl_link_intr_0_status_intrb_f(v) ((U32(v) & 0x1U) << 4U)
#define ioctrl_link_intr_0_status_intrb_v(r) (((r) >> 4U) & 0x1U) #define ioctrl_link_intr_0_status_intrb_v(r) (((r) >> 4U) & 0x1U)
#endif #endif

44
drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_ioctrlmif_gv100.h
View File

@@ -60,74 +60,86 @@
#include <nvgpu/safe_ops.h> #include <nvgpu/safe_ops.h>
#define ioctrlmif_rx_err_contain_en_0_r() (0x00000e0cU) #define ioctrlmif_rx_err_contain_en_0_r() (0x00000e0cU)
#define ioctrlmif_rx_err_contain_en_0_rxramdataparityerr_f(v) (((v)&0x1U) << 3U) #define ioctrlmif_rx_err_contain_en_0_rxramdataparityerr_f(v)\
((U32(v) & 0x1U) << 3U)
#define ioctrlmif_rx_err_contain_en_0_rxramdataparityerr_m() (U32(0x1U) << 3U) #define ioctrlmif_rx_err_contain_en_0_rxramdataparityerr_m() (U32(0x1U) << 3U)
#define ioctrlmif_rx_err_contain_en_0_rxramdataparityerr_v(r)\ #define ioctrlmif_rx_err_contain_en_0_rxramdataparityerr_v(r)\
(((r) >> 3U) & 0x1U) (((r) >> 3U) & 0x1U)
#define ioctrlmif_rx_err_contain_en_0_rxramdataparityerr__prod_v() (0x00000001U) #define ioctrlmif_rx_err_contain_en_0_rxramdataparityerr__prod_v() (0x00000001U)
#define ioctrlmif_rx_err_contain_en_0_rxramdataparityerr__prod_f() (0x8U) #define ioctrlmif_rx_err_contain_en_0_rxramdataparityerr__prod_f() (0x8U)
#define ioctrlmif_rx_err_contain_en_0_rxramhdrparityerr_f(v) (((v)&0x1U) << 4U) #define ioctrlmif_rx_err_contain_en_0_rxramhdrparityerr_f(v)\
((U32(v) & 0x1U) << 4U)
#define ioctrlmif_rx_err_contain_en_0_rxramhdrparityerr_m() (U32(0x1U) << 4U) #define ioctrlmif_rx_err_contain_en_0_rxramhdrparityerr_m() (U32(0x1U) << 4U)
#define ioctrlmif_rx_err_contain_en_0_rxramhdrparityerr_v(r)\ #define ioctrlmif_rx_err_contain_en_0_rxramhdrparityerr_v(r)\
(((r) >> 4U) & 0x1U) (((r) >> 4U) & 0x1U)
#define ioctrlmif_rx_err_contain_en_0_rxramhdrparityerr__prod_v() (0x00000001U) #define ioctrlmif_rx_err_contain_en_0_rxramhdrparityerr__prod_v() (0x00000001U)
#define ioctrlmif_rx_err_contain_en_0_rxramhdrparityerr__prod_f() (0x10U) #define ioctrlmif_rx_err_contain_en_0_rxramhdrparityerr__prod_f() (0x10U)
#define ioctrlmif_rx_err_log_en_0_r() (0x00000e04U) #define ioctrlmif_rx_err_log_en_0_r() (0x00000e04U)
#define ioctrlmif_rx_err_log_en_0_rxramdataparityerr_f(v) (((v)&0x1U) << 3U) #define ioctrlmif_rx_err_log_en_0_rxramdataparityerr_f(v)\
((U32(v) & 0x1U) << 3U)
#define ioctrlmif_rx_err_log_en_0_rxramdataparityerr_m() (U32(0x1U) << 3U) #define ioctrlmif_rx_err_log_en_0_rxramdataparityerr_m() (U32(0x1U) << 3U)
#define ioctrlmif_rx_err_log_en_0_rxramdataparityerr_v(r) (((r) >> 3U) & 0x1U) #define ioctrlmif_rx_err_log_en_0_rxramdataparityerr_v(r) (((r) >> 3U) & 0x1U)
#define ioctrlmif_rx_err_log_en_0_rxramhdrparityerr_f(v) (((v)&0x1U) << 4U) #define ioctrlmif_rx_err_log_en_0_rxramhdrparityerr_f(v) ((U32(v) & 0x1U) << 4U)
#define ioctrlmif_rx_err_log_en_0_rxramhdrparityerr_m() (U32(0x1U) << 4U) #define ioctrlmif_rx_err_log_en_0_rxramhdrparityerr_m() (U32(0x1U) << 4U)
#define ioctrlmif_rx_err_log_en_0_rxramhdrparityerr_v(r) (((r) >> 4U) & 0x1U) #define ioctrlmif_rx_err_log_en_0_rxramhdrparityerr_v(r) (((r) >> 4U) & 0x1U)
#define ioctrlmif_rx_err_report_en_0_r() (0x00000e08U) #define ioctrlmif_rx_err_report_en_0_r() (0x00000e08U)
#define ioctrlmif_rx_err_report_en_0_rxramdataparityerr_f(v) (((v)&0x1U) << 3U) #define ioctrlmif_rx_err_report_en_0_rxramdataparityerr_f(v)\
((U32(v) & 0x1U) << 3U)
#define ioctrlmif_rx_err_report_en_0_rxramdataparityerr_m() (U32(0x1U) << 3U) #define ioctrlmif_rx_err_report_en_0_rxramdataparityerr_m() (U32(0x1U) << 3U)
#define ioctrlmif_rx_err_report_en_0_rxramdataparityerr_v(r)\ #define ioctrlmif_rx_err_report_en_0_rxramdataparityerr_v(r)\
(((r) >> 3U) & 0x1U) (((r) >> 3U) & 0x1U)
#define ioctrlmif_rx_err_report_en_0_rxramhdrparityerr_f(v) (((v)&0x1U) << 4U) #define ioctrlmif_rx_err_report_en_0_rxramhdrparityerr_f(v)\
((U32(v) & 0x1U) << 4U)
#define ioctrlmif_rx_err_report_en_0_rxramhdrparityerr_m() (U32(0x1U) << 4U) #define ioctrlmif_rx_err_report_en_0_rxramhdrparityerr_m() (U32(0x1U) << 4U)
#define ioctrlmif_rx_err_report_en_0_rxramhdrparityerr_v(r) (((r) >> 4U) & 0x1U) #define ioctrlmif_rx_err_report_en_0_rxramhdrparityerr_v(r) (((r) >> 4U) & 0x1U)
#define ioctrlmif_rx_err_status_0_r() (0x00000e00U) #define ioctrlmif_rx_err_status_0_r() (0x00000e00U)
#define ioctrlmif_rx_err_status_0_rxramdataparityerr_f(v) (((v)&0x1U) << 3U) #define ioctrlmif_rx_err_status_0_rxramdataparityerr_f(v)\
((U32(v) & 0x1U) << 3U)
#define ioctrlmif_rx_err_status_0_rxramdataparityerr_m() (U32(0x1U) << 3U) #define ioctrlmif_rx_err_status_0_rxramdataparityerr_m() (U32(0x1U) << 3U)
#define ioctrlmif_rx_err_status_0_rxramdataparityerr_v(r) (((r) >> 3U) & 0x1U) #define ioctrlmif_rx_err_status_0_rxramdataparityerr_v(r) (((r) >> 3U) & 0x1U)
#define ioctrlmif_rx_err_status_0_rxramhdrparityerr_f(v) (((v)&0x1U) << 4U) #define ioctrlmif_rx_err_status_0_rxramhdrparityerr_f(v) ((U32(v) & 0x1U) << 4U)
#define ioctrlmif_rx_err_status_0_rxramhdrparityerr_m() (U32(0x1U) << 4U) #define ioctrlmif_rx_err_status_0_rxramhdrparityerr_m() (U32(0x1U) << 4U)
#define ioctrlmif_rx_err_status_0_rxramhdrparityerr_v(r) (((r) >> 4U) & 0x1U) #define ioctrlmif_rx_err_status_0_rxramhdrparityerr_v(r) (((r) >> 4U) & 0x1U)
#define ioctrlmif_rx_err_first_0_r() (0x00000e14U) #define ioctrlmif_rx_err_first_0_r() (0x00000e14U)
#define ioctrlmif_tx_err_contain_en_0_r() (0x00000a90U) #define ioctrlmif_tx_err_contain_en_0_r() (0x00000a90U)
#define ioctrlmif_tx_err_contain_en_0_txramdataparityerr_f(v) (((v)&0x1U) << 0U) #define ioctrlmif_tx_err_contain_en_0_txramdataparityerr_f(v)\
((U32(v) & 0x1U) << 0U)
#define ioctrlmif_tx_err_contain_en_0_txramdataparityerr_m() (U32(0x1U) << 0U) #define ioctrlmif_tx_err_contain_en_0_txramdataparityerr_m() (U32(0x1U) << 0U)
#define ioctrlmif_tx_err_contain_en_0_txramdataparityerr_v(r)\ #define ioctrlmif_tx_err_contain_en_0_txramdataparityerr_v(r)\
(((r) >> 0U) & 0x1U) (((r) >> 0U) & 0x1U)
#define ioctrlmif_tx_err_contain_en_0_txramdataparityerr__prod_v() (0x00000001U) #define ioctrlmif_tx_err_contain_en_0_txramdataparityerr__prod_v() (0x00000001U)
#define ioctrlmif_tx_err_contain_en_0_txramdataparityerr__prod_f() (0x1U) #define ioctrlmif_tx_err_contain_en_0_txramdataparityerr__prod_f() (0x1U)
#define ioctrlmif_tx_err_contain_en_0_txramhdrparityerr_f(v) (((v)&0x1U) << 1U) #define ioctrlmif_tx_err_contain_en_0_txramhdrparityerr_f(v)\
((U32(v) & 0x1U) << 1U)
#define ioctrlmif_tx_err_contain_en_0_txramhdrparityerr_m() (U32(0x1U) << 1U) #define ioctrlmif_tx_err_contain_en_0_txramhdrparityerr_m() (U32(0x1U) << 1U)
#define ioctrlmif_tx_err_contain_en_0_txramhdrparityerr_v(r)\ #define ioctrlmif_tx_err_contain_en_0_txramhdrparityerr_v(r)\
(((r) >> 1U) & 0x1U) (((r) >> 1U) & 0x1U)
#define ioctrlmif_tx_err_contain_en_0_txramhdrparityerr__prod_v() (0x00000001U) #define ioctrlmif_tx_err_contain_en_0_txramhdrparityerr__prod_v() (0x00000001U)
#define ioctrlmif_tx_err_contain_en_0_txramhdrparityerr__prod_f() (0x2U) #define ioctrlmif_tx_err_contain_en_0_txramhdrparityerr__prod_f() (0x2U)
#define ioctrlmif_tx_err_log_en_0_r() (0x00000a88U) #define ioctrlmif_tx_err_log_en_0_r() (0x00000a88U)
#define ioctrlmif_tx_err_log_en_0_txramdataparityerr_f(v) (((v)&0x1U) << 0U) #define ioctrlmif_tx_err_log_en_0_txramdataparityerr_f(v)\
((U32(v) & 0x1U) << 0U)
#define ioctrlmif_tx_err_log_en_0_txramdataparityerr_m() (U32(0x1U) << 0U) #define ioctrlmif_tx_err_log_en_0_txramdataparityerr_m() (U32(0x1U) << 0U)
#define ioctrlmif_tx_err_log_en_0_txramdataparityerr_v(r) (((r) >> 0U) & 0x1U) #define ioctrlmif_tx_err_log_en_0_txramdataparityerr_v(r) (((r) >> 0U) & 0x1U)
#define ioctrlmif_tx_err_log_en_0_txramhdrparityerr_f(v) (((v)&0x1U) << 1U) #define ioctrlmif_tx_err_log_en_0_txramhdrparityerr_f(v) ((U32(v) & 0x1U) << 1U)
#define ioctrlmif_tx_err_log_en_0_txramhdrparityerr_m() (U32(0x1U) << 1U) #define ioctrlmif_tx_err_log_en_0_txramhdrparityerr_m() (U32(0x1U) << 1U)
#define ioctrlmif_tx_err_log_en_0_txramhdrparityerr_v(r) (((r) >> 1U) & 0x1U) #define ioctrlmif_tx_err_log_en_0_txramhdrparityerr_v(r) (((r) >> 1U) & 0x1U)
#define ioctrlmif_tx_err_report_en_0_r() (0x00000e08U) #define ioctrlmif_tx_err_report_en_0_r() (0x00000e08U)
#define ioctrlmif_tx_err_report_en_0_txramdataparityerr_f(v) (((v)&0x1U) << 0U) #define ioctrlmif_tx_err_report_en_0_txramdataparityerr_f(v)\
((U32(v) & 0x1U) << 0U)
#define ioctrlmif_tx_err_report_en_0_txramdataparityerr_m() (U32(0x1U) << 0U) #define ioctrlmif_tx_err_report_en_0_txramdataparityerr_m() (U32(0x1U) << 0U)
#define ioctrlmif_tx_err_report_en_0_txramdataparityerr_v(r)\ #define ioctrlmif_tx_err_report_en_0_txramdataparityerr_v(r)\
(((r) >> 0U) & 0x1U) (((r) >> 0U) & 0x1U)
#define ioctrlmif_tx_err_report_en_0_txramhdrparityerr_f(v) (((v)&0x1U) << 1U) #define ioctrlmif_tx_err_report_en_0_txramhdrparityerr_f(v)\
((U32(v) & 0x1U) << 1U)
#define ioctrlmif_tx_err_report_en_0_txramhdrparityerr_m() (U32(0x1U) << 1U) #define ioctrlmif_tx_err_report_en_0_txramhdrparityerr_m() (U32(0x1U) << 1U)
#define ioctrlmif_tx_err_report_en_0_txramhdrparityerr_v(r) (((r) >> 1U) & 0x1U) #define ioctrlmif_tx_err_report_en_0_txramhdrparityerr_v(r) (((r) >> 1U) & 0x1U)
#define ioctrlmif_tx_err_status_0_r() (0x00000a84U) #define ioctrlmif_tx_err_status_0_r() (0x00000a84U)
#define ioctrlmif_tx_err_status_0_txramdataparityerr_f(v) (((v)&0x1U) << 0U) #define ioctrlmif_tx_err_status_0_txramdataparityerr_f(v)\
((U32(v) & 0x1U) << 0U)
#define ioctrlmif_tx_err_status_0_txramdataparityerr_m() (U32(0x1U) << 0U) #define ioctrlmif_tx_err_status_0_txramdataparityerr_m() (U32(0x1U) << 0U)
#define ioctrlmif_tx_err_status_0_txramdataparityerr_v(r) (((r) >> 0U) & 0x1U) #define ioctrlmif_tx_err_status_0_txramdataparityerr_v(r) (((r) >> 0U) & 0x1U)
#define ioctrlmif_tx_err_status_0_txramhdrparityerr_f(v) (((v)&0x1U) << 1U) #define ioctrlmif_tx_err_status_0_txramhdrparityerr_f(v) ((U32(v) & 0x1U) << 1U)
#define ioctrlmif_tx_err_status_0_txramhdrparityerr_m() (U32(0x1U) << 1U) #define ioctrlmif_tx_err_status_0_txramhdrparityerr_m() (U32(0x1U) << 1U)
#define ioctrlmif_tx_err_status_0_txramhdrparityerr_v(r) (((r) >> 1U) & 0x1U) #define ioctrlmif_tx_err_status_0_txramhdrparityerr_v(r) (((r) >> 1U) & 0x1U)
#define ioctrlmif_tx_err_first_0_r() (0x00000a98U) #define ioctrlmif_tx_err_first_0_r() (0x00000a98U)

19
drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_ltc_gv100.h
View File

@@ -82,9 +82,11 @@
#define ltc_ltcs_ltss_cbc_ctrl1_clear_active_f() (0x4U) #define ltc_ltcs_ltss_cbc_ctrl1_clear_active_f() (0x4U)
#define ltc_ltc0_lts0_cbc_ctrl1_r() (0x0014046cU) #define ltc_ltc0_lts0_cbc_ctrl1_r() (0x0014046cU)
#define ltc_ltcs_ltss_cbc_ctrl2_r() (0x0017e270U) #define ltc_ltcs_ltss_cbc_ctrl2_r() (0x0017e270U)
#define ltc_ltcs_ltss_cbc_ctrl2_clear_lower_bound_f(v) (((v)&0x3ffffU) << 0U) #define ltc_ltcs_ltss_cbc_ctrl2_clear_lower_bound_f(v)\
((U32(v) & 0x3ffffU) << 0U)
#define ltc_ltcs_ltss_cbc_ctrl3_r() (0x0017e274U) #define ltc_ltcs_ltss_cbc_ctrl3_r() (0x0017e274U)
#define ltc_ltcs_ltss_cbc_ctrl3_clear_upper_bound_f(v) (((v)&0x3ffffU) << 0U) #define ltc_ltcs_ltss_cbc_ctrl3_clear_upper_bound_f(v)\
((U32(v) & 0x3ffffU) << 0U)
#define ltc_ltcs_ltss_cbc_ctrl3_clear_upper_bound_init_v() (0x0003ffffU) #define ltc_ltcs_ltss_cbc_ctrl3_clear_upper_bound_init_v() (0x0003ffffU)
#define ltc_ltcs_ltss_cbc_base_r() (0x0017e278U) #define ltc_ltcs_ltss_cbc_base_r() (0x0017e278U)
#define ltc_ltcs_ltss_cbc_base_alignment_shift_v() (0x0000000bU) #define ltc_ltcs_ltss_cbc_base_alignment_shift_v() (0x0000000bU)
@@ -92,10 +94,11 @@
#define ltc_ltcs_ltss_cbc_num_active_ltcs_r() (0x0017e27cU) #define ltc_ltcs_ltss_cbc_num_active_ltcs_r() (0x0017e27cU)
#define ltc_ltcs_ltss_cbc_num_active_ltcs__v(r) (((r) >> 0U) & 0x1fU) #define ltc_ltcs_ltss_cbc_num_active_ltcs__v(r) (((r) >> 0U) & 0x1fU)
#define ltc_ltcs_ltss_cbc_num_active_ltcs_nvlink_peer_through_l2_f(v)\ #define ltc_ltcs_ltss_cbc_num_active_ltcs_nvlink_peer_through_l2_f(v)\
(((v)&0x1U) << 24U) ((U32(v) & 0x1U) << 24U)
#define ltc_ltcs_ltss_cbc_num_active_ltcs_nvlink_peer_through_l2_v(r)\ #define ltc_ltcs_ltss_cbc_num_active_ltcs_nvlink_peer_through_l2_v(r)\
(((r) >> 24U) & 0x1U) (((r) >> 24U) & 0x1U)
#define ltc_ltcs_ltss_cbc_num_active_ltcs_serialize_f(v) (((v)&0x1U) << 25U) #define ltc_ltcs_ltss_cbc_num_active_ltcs_serialize_f(v)\
((U32(v) & 0x1U) << 25U)
#define ltc_ltcs_ltss_cbc_num_active_ltcs_serialize_v(r) (((r) >> 25U) & 0x1U) #define ltc_ltcs_ltss_cbc_num_active_ltcs_serialize_v(r) (((r) >> 25U) & 0x1U)
#define ltc_ltcs_misc_ltc_num_active_ltcs_r() (0x0017e000U) #define ltc_ltcs_misc_ltc_num_active_ltcs_r() (0x0017e000U)
#define ltc_ltcs_ltss_cbc_param_r() (0x0017e280U) #define ltc_ltcs_ltss_cbc_param_r() (0x0017e280U)
@@ -108,16 +111,16 @@
(((r) >> 0U) & 0xffffU) (((r) >> 0U) & 0xffffU)
#define ltc_ltcs_ltss_tstg_set_mgmt_r() (0x0017e2acU) #define ltc_ltcs_ltss_tstg_set_mgmt_r() (0x0017e2acU)
#define ltc_ltcs_ltss_tstg_set_mgmt_max_ways_evict_last_f(v)\ #define ltc_ltcs_ltss_tstg_set_mgmt_max_ways_evict_last_f(v)\
(((v)&0x1fU) << 16U) ((U32(v) & 0x1fU) << 16U)
#define ltc_ltcs_ltss_dstg_zbc_index_r() (0x0017e338U) #define ltc_ltcs_ltss_dstg_zbc_index_r() (0x0017e338U)
#define ltc_ltcs_ltss_dstg_zbc_index_address_f(v) (((v)&0xfU) << 0U) #define ltc_ltcs_ltss_dstg_zbc_index_address_f(v) ((U32(v) & 0xfU) << 0U)
#define ltc_ltcs_ltss_dstg_zbc_color_clear_value_r(i)\ #define ltc_ltcs_ltss_dstg_zbc_color_clear_value_r(i)\
(nvgpu_safe_add_u32(0x0017e33cU, nvgpu_safe_mult_u32((i), 4U))) (nvgpu_safe_add_u32(0x0017e33cU, nvgpu_safe_mult_u32((i), 4U)))
#define ltc_ltcs_ltss_dstg_zbc_color_clear_value__size_1_v() (0x00000004U) #define ltc_ltcs_ltss_dstg_zbc_color_clear_value__size_1_v() (0x00000004U)
#define ltc_ltcs_ltss_dstg_zbc_depth_clear_value_r() (0x0017e34cU) #define ltc_ltcs_ltss_dstg_zbc_depth_clear_value_r() (0x0017e34cU)
#define ltc_ltcs_ltss_dstg_zbc_depth_clear_value_field_s() (32U) #define ltc_ltcs_ltss_dstg_zbc_depth_clear_value_field_s() (32U)
#define ltc_ltcs_ltss_dstg_zbc_depth_clear_value_field_f(v)\ #define ltc_ltcs_ltss_dstg_zbc_depth_clear_value_field_f(v)\
(((v)&0xffffffffU) << 0U) ((U32(v) & 0xffffffffU) << 0U)
#define ltc_ltcs_ltss_dstg_zbc_depth_clear_value_field_m()\ #define ltc_ltcs_ltss_dstg_zbc_depth_clear_value_field_m()\
(U32(0xffffffffU) << 0U) (U32(0xffffffffU) << 0U)
#define ltc_ltcs_ltss_dstg_zbc_depth_clear_value_field_v(r)\ #define ltc_ltcs_ltss_dstg_zbc_depth_clear_value_field_v(r)\
@@ -125,7 +128,7 @@
#define ltc_ltcs_ltss_dstg_zbc_stencil_clear_value_r() (0x0017e204U) #define ltc_ltcs_ltss_dstg_zbc_stencil_clear_value_r() (0x0017e204U)
#define ltc_ltcs_ltss_dstg_zbc_stencil_clear_value_field_s() (8U) #define ltc_ltcs_ltss_dstg_zbc_stencil_clear_value_field_s() (8U)
#define ltc_ltcs_ltss_dstg_zbc_stencil_clear_value_field_f(v)\ #define ltc_ltcs_ltss_dstg_zbc_stencil_clear_value_field_f(v)\
(((v)&0xffU) << 0U) ((U32(v) & 0xffU) << 0U)
#define ltc_ltcs_ltss_dstg_zbc_stencil_clear_value_field_m() (U32(0xffU) << 0U) #define ltc_ltcs_ltss_dstg_zbc_stencil_clear_value_field_m() (U32(0xffU) << 0U)
#define ltc_ltcs_ltss_dstg_zbc_stencil_clear_value_field_v(r)\ #define ltc_ltcs_ltss_dstg_zbc_stencil_clear_value_field_v(r)\
(((r) >> 0U) & 0xffU) (((r) >> 0U) & 0xffU)

6
drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_mc_gv100.h
View File

@@ -84,7 +84,7 @@
#define mc_enable_xbar_enabled_f() (0x4U) #define mc_enable_xbar_enabled_f() (0x4U)
#define mc_enable_l2_enabled_f() (0x8U) #define mc_enable_l2_enabled_f() (0x8U)
#define mc_enable_pmedia_s() (1U) #define mc_enable_pmedia_s() (1U)
#define mc_enable_pmedia_f(v) (((v)&0x1U) << 4U) #define mc_enable_pmedia_f(v) ((U32(v) & 0x1U) << 4U)
#define mc_enable_pmedia_m() (U32(0x1U) << 4U) #define mc_enable_pmedia_m() (U32(0x1U) << 4U)
#define mc_enable_pmedia_v(r) (((r) >> 4U) & 0x1U) #define mc_enable_pmedia_v(r) (((r) >> 4U) & 0x1U)
#define mc_enable_ce0_m() (U32(0x1U) << 6U) #define mc_enable_ce0_m() (U32(0x1U) << 6U)
@@ -108,10 +108,10 @@
#define mc_intr_ltc_r() (0x000001c0U) #define mc_intr_ltc_r() (0x000001c0U)
#define mc_enable_pb_r() (0x00000204U) #define mc_enable_pb_r() (0x00000204U)
#define mc_enable_pb_0_s() (1U) #define mc_enable_pb_0_s() (1U)
#define mc_enable_pb_0_f(v) (((v)&0x1U) << 0U) #define mc_enable_pb_0_f(v) ((U32(v) & 0x1U) << 0U)
#define mc_enable_pb_0_m() (U32(0x1U) << 0U) #define mc_enable_pb_0_m() (U32(0x1U) << 0U)
#define mc_enable_pb_0_v(r) (((r) >> 0U) & 0x1U) #define mc_enable_pb_0_v(r) (((r) >> 0U) & 0x1U)
#define mc_enable_pb_0_enabled_v() (0x00000001U) #define mc_enable_pb_0_enabled_v() (0x00000001U)
#define mc_enable_pb_sel_f(v, i)\ #define mc_enable_pb_sel_f(v, i)\
(((v) & 0x1) << (0U + i*1U)) ((U32(v) & 0x1U) << (0U + (i)*1U))
#endif #endif

72
drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_minion_gv100.h
View File

@@ -60,18 +60,18 @@
#include <nvgpu/safe_ops.h> #include <nvgpu/safe_ops.h>
#define minion_minion_status_r() (0x00000830U) #define minion_minion_status_r() (0x00000830U)
#define minion_minion_status_status_f(v) (((v)&0xffU) << 0U) #define minion_minion_status_status_f(v) ((U32(v) & 0xffU) << 0U)
#define minion_minion_status_status_m() (U32(0xffU) << 0U) #define minion_minion_status_status_m() (U32(0xffU) << 0U)
#define minion_minion_status_status_v(r) (((r) >> 0U) & 0xffU) #define minion_minion_status_status_v(r) (((r) >> 0U) & 0xffU)
#define minion_minion_status_status_boot_v() (0x00000001U) #define minion_minion_status_status_boot_v() (0x00000001U)
#define minion_minion_status_status_boot_f() (0x1U) #define minion_minion_status_status_boot_f() (0x1U)
#define minion_minion_status_intr_code_f(v) (((v)&0xffffffU) << 8U) #define minion_minion_status_intr_code_f(v) ((U32(v) & 0xffffffU) << 8U)
#define minion_minion_status_intr_code_m() (U32(0xffffffU) << 8U) #define minion_minion_status_intr_code_m() (U32(0xffffffU) << 8U)
#define minion_minion_status_intr_code_v(r) (((r) >> 8U) & 0xffffffU) #define minion_minion_status_intr_code_v(r) (((r) >> 8U) & 0xffffffU)
#define minion_falcon_irqstat_r() (0x00000008U) #define minion_falcon_irqstat_r() (0x00000008U)
#define minion_falcon_irqstat_halt_f(v) (((v)&0x1U) << 4U) #define minion_falcon_irqstat_halt_f(v) ((U32(v) & 0x1U) << 4U)
#define minion_falcon_irqstat_halt_v(r) (((r) >> 4U) & 0x1U) #define minion_falcon_irqstat_halt_v(r) (((r) >> 4U) & 0x1U)
#define minion_falcon_irqstat_exterr_f(v) (((v)&0x1U) << 5U) #define minion_falcon_irqstat_exterr_f(v) ((U32(v) & 0x1U) << 5U)
#define minion_falcon_irqstat_exterr_v(r) (((r) >> 5U) & 0x1U) #define minion_falcon_irqstat_exterr_v(r) (((r) >> 5U) & 0x1U)
#define minion_falcon_irqstat_exterr_true_v() (0x00000001U) #define minion_falcon_irqstat_exterr_true_v() (0x00000001U)
#define minion_falcon_irqstat_exterr_true_f() (0x20U) #define minion_falcon_irqstat_exterr_true_f() (0x20U)
@@ -79,78 +79,78 @@
#define minion_falcon_irqsclr_r() (0x00000004U) #define minion_falcon_irqsclr_r() (0x00000004U)
#define minion_falcon_irqsset_r() (0x00000000U) #define minion_falcon_irqsset_r() (0x00000000U)
#define minion_falcon_irqmset_r() (0x00000010U) #define minion_falcon_irqmset_r() (0x00000010U)
#define minion_falcon_irqmset_wdtmr_f(v) (((v)&0x1U) << 1U) #define minion_falcon_irqmset_wdtmr_f(v) ((U32(v) & 0x1U) << 1U)
#define minion_falcon_irqmset_wdtmr_m() (U32(0x1U) << 1U) #define minion_falcon_irqmset_wdtmr_m() (U32(0x1U) << 1U)
#define minion_falcon_irqmset_wdtmr_v(r) (((r) >> 1U) & 0x1U) #define minion_falcon_irqmset_wdtmr_v(r) (((r) >> 1U) & 0x1U)
#define minion_falcon_irqmset_wdtmr_set_v() (0x00000001U) #define minion_falcon_irqmset_wdtmr_set_v() (0x00000001U)
#define minion_falcon_irqmset_wdtmr_set_f() (0x2U) #define minion_falcon_irqmset_wdtmr_set_f() (0x2U)
#define minion_falcon_irqmset_halt_f(v) (((v)&0x1U) << 4U) #define minion_falcon_irqmset_halt_f(v) ((U32(v) & 0x1U) << 4U)
#define minion_falcon_irqmset_halt_m() (U32(0x1U) << 4U) #define minion_falcon_irqmset_halt_m() (U32(0x1U) << 4U)
#define minion_falcon_irqmset_halt_v(r) (((r) >> 4U) & 0x1U) #define minion_falcon_irqmset_halt_v(r) (((r) >> 4U) & 0x1U)
#define minion_falcon_irqmset_halt_set_v() (0x00000001U) #define minion_falcon_irqmset_halt_set_v() (0x00000001U)
#define minion_falcon_irqmset_halt_set_f() (0x10U) #define minion_falcon_irqmset_halt_set_f() (0x10U)
#define minion_falcon_irqmset_exterr_f(v) (((v)&0x1U) << 5U) #define minion_falcon_irqmset_exterr_f(v) ((U32(v) & 0x1U) << 5U)
#define minion_falcon_irqmset_exterr_m() (U32(0x1U) << 5U) #define minion_falcon_irqmset_exterr_m() (U32(0x1U) << 5U)
#define minion_falcon_irqmset_exterr_v(r) (((r) >> 5U) & 0x1U) #define minion_falcon_irqmset_exterr_v(r) (((r) >> 5U) & 0x1U)
#define minion_falcon_irqmset_exterr_set_v() (0x00000001U) #define minion_falcon_irqmset_exterr_set_v() (0x00000001U)
#define minion_falcon_irqmset_exterr_set_f() (0x20U) #define minion_falcon_irqmset_exterr_set_f() (0x20U)
#define minion_falcon_irqmset_swgen0_f(v) (((v)&0x1U) << 6U) #define minion_falcon_irqmset_swgen0_f(v) ((U32(v) & 0x1U) << 6U)
#define minion_falcon_irqmset_swgen0_m() (U32(0x1U) << 6U) #define minion_falcon_irqmset_swgen0_m() (U32(0x1U) << 6U)
#define minion_falcon_irqmset_swgen0_v(r) (((r) >> 6U) & 0x1U) #define minion_falcon_irqmset_swgen0_v(r) (((r) >> 6U) & 0x1U)
#define minion_falcon_irqmset_swgen0_set_v() (0x00000001U) #define minion_falcon_irqmset_swgen0_set_v() (0x00000001U)
#define minion_falcon_irqmset_swgen0_set_f() (0x40U) #define minion_falcon_irqmset_swgen0_set_f() (0x40U)
#define minion_falcon_irqmset_swgen1_f(v) (((v)&0x1U) << 7U) #define minion_falcon_irqmset_swgen1_f(v) ((U32(v) & 0x1U) << 7U)
#define minion_falcon_irqmset_swgen1_m() (U32(0x1U) << 7U) #define minion_falcon_irqmset_swgen1_m() (U32(0x1U) << 7U)
#define minion_falcon_irqmset_swgen1_v(r) (((r) >> 7U) & 0x1U) #define minion_falcon_irqmset_swgen1_v(r) (((r) >> 7U) & 0x1U)
#define minion_falcon_irqmset_swgen1_set_v() (0x00000001U) #define minion_falcon_irqmset_swgen1_set_v() (0x00000001U)
#define minion_falcon_irqmset_swgen1_set_f() (0x80U) #define minion_falcon_irqmset_swgen1_set_f() (0x80U)
#define minion_falcon_irqdest_r() (0x0000001cU) #define minion_falcon_irqdest_r() (0x0000001cU)
#define minion_falcon_irqdest_host_wdtmr_f(v) (((v)&0x1U) << 1U) #define minion_falcon_irqdest_host_wdtmr_f(v) ((U32(v) & 0x1U) << 1U)
#define minion_falcon_irqdest_host_wdtmr_m() (U32(0x1U) << 1U) #define minion_falcon_irqdest_host_wdtmr_m() (U32(0x1U) << 1U)
#define minion_falcon_irqdest_host_wdtmr_v(r) (((r) >> 1U) & 0x1U) #define minion_falcon_irqdest_host_wdtmr_v(r) (((r) >> 1U) & 0x1U)
#define minion_falcon_irqdest_host_wdtmr_host_v() (0x00000001U) #define minion_falcon_irqdest_host_wdtmr_host_v() (0x00000001U)
#define minion_falcon_irqdest_host_wdtmr_host_f() (0x2U) #define minion_falcon_irqdest_host_wdtmr_host_f() (0x2U)
#define minion_falcon_irqdest_host_halt_f(v) (((v)&0x1U) << 4U) #define minion_falcon_irqdest_host_halt_f(v) ((U32(v) & 0x1U) << 4U)
#define minion_falcon_irqdest_host_halt_m() (U32(0x1U) << 4U) #define minion_falcon_irqdest_host_halt_m() (U32(0x1U) << 4U)
#define minion_falcon_irqdest_host_halt_v(r) (((r) >> 4U) & 0x1U) #define minion_falcon_irqdest_host_halt_v(r) (((r) >> 4U) & 0x1U)
#define minion_falcon_irqdest_host_halt_host_v() (0x00000001U) #define minion_falcon_irqdest_host_halt_host_v() (0x00000001U)
#define minion_falcon_irqdest_host_halt_host_f() (0x10U) #define minion_falcon_irqdest_host_halt_host_f() (0x10U)
#define minion_falcon_irqdest_host_exterr_f(v) (((v)&0x1U) << 5U) #define minion_falcon_irqdest_host_exterr_f(v) ((U32(v) & 0x1U) << 5U)
#define minion_falcon_irqdest_host_exterr_m() (U32(0x1U) << 5U) #define minion_falcon_irqdest_host_exterr_m() (U32(0x1U) << 5U)
#define minion_falcon_irqdest_host_exterr_v(r) (((r) >> 5U) & 0x1U) #define minion_falcon_irqdest_host_exterr_v(r) (((r) >> 5U) & 0x1U)
#define minion_falcon_irqdest_host_exterr_host_v() (0x00000001U) #define minion_falcon_irqdest_host_exterr_host_v() (0x00000001U)
#define minion_falcon_irqdest_host_exterr_host_f() (0x20U) #define minion_falcon_irqdest_host_exterr_host_f() (0x20U)
#define minion_falcon_irqdest_host_swgen0_f(v) (((v)&0x1U) << 6U) #define minion_falcon_irqdest_host_swgen0_f(v) ((U32(v) & 0x1U) << 6U)
#define minion_falcon_irqdest_host_swgen0_m() (U32(0x1U) << 6U) #define minion_falcon_irqdest_host_swgen0_m() (U32(0x1U) << 6U)
#define minion_falcon_irqdest_host_swgen0_v(r) (((r) >> 6U) & 0x1U) #define minion_falcon_irqdest_host_swgen0_v(r) (((r) >> 6U) & 0x1U)
#define minion_falcon_irqdest_host_swgen0_host_v() (0x00000001U) #define minion_falcon_irqdest_host_swgen0_host_v() (0x00000001U)
#define minion_falcon_irqdest_host_swgen0_host_f() (0x40U) #define minion_falcon_irqdest_host_swgen0_host_f() (0x40U)
#define minion_falcon_irqdest_host_swgen1_f(v) (((v)&0x1U) << 7U) #define minion_falcon_irqdest_host_swgen1_f(v) ((U32(v) & 0x1U) << 7U)
#define minion_falcon_irqdest_host_swgen1_m() (U32(0x1U) << 7U) #define minion_falcon_irqdest_host_swgen1_m() (U32(0x1U) << 7U)
#define minion_falcon_irqdest_host_swgen1_v(r) (((r) >> 7U) & 0x1U) #define minion_falcon_irqdest_host_swgen1_v(r) (((r) >> 7U) & 0x1U)
#define minion_falcon_irqdest_host_swgen1_host_v() (0x00000001U) #define minion_falcon_irqdest_host_swgen1_host_v() (0x00000001U)
#define minion_falcon_irqdest_host_swgen1_host_f() (0x80U) #define minion_falcon_irqdest_host_swgen1_host_f() (0x80U)
#define minion_falcon_irqdest_target_wdtmr_f(v) (((v)&0x1U) << 17U) #define minion_falcon_irqdest_target_wdtmr_f(v) ((U32(v) & 0x1U) << 17U)
#define minion_falcon_irqdest_target_wdtmr_m() (U32(0x1U) << 17U) #define minion_falcon_irqdest_target_wdtmr_m() (U32(0x1U) << 17U)
#define minion_falcon_irqdest_target_wdtmr_v(r) (((r) >> 17U) & 0x1U) #define minion_falcon_irqdest_target_wdtmr_v(r) (((r) >> 17U) & 0x1U)
#define minion_falcon_irqdest_target_wdtmr_host_normal_v() (0x00000000U) #define minion_falcon_irqdest_target_wdtmr_host_normal_v() (0x00000000U)
#define minion_falcon_irqdest_target_wdtmr_host_normal_f() (0x0U) #define minion_falcon_irqdest_target_wdtmr_host_normal_f() (0x0U)
#define minion_falcon_irqdest_target_halt_f(v) (((v)&0x1U) << 20U) #define minion_falcon_irqdest_target_halt_f(v) ((U32(v) & 0x1U) << 20U)
#define minion_falcon_irqdest_target_halt_m() (U32(0x1U) << 20U) #define minion_falcon_irqdest_target_halt_m() (U32(0x1U) << 20U)
#define minion_falcon_irqdest_target_halt_v(r) (((r) >> 20U) & 0x1U) #define minion_falcon_irqdest_target_halt_v(r) (((r) >> 20U) & 0x1U)
#define minion_falcon_irqdest_target_halt_host_normal_v() (0x00000000U) #define minion_falcon_irqdest_target_halt_host_normal_v() (0x00000000U)
#define minion_falcon_irqdest_target_halt_host_normal_f() (0x0U) #define minion_falcon_irqdest_target_halt_host_normal_f() (0x0U)
#define minion_falcon_irqdest_target_exterr_f(v) (((v)&0x1U) << 21U) #define minion_falcon_irqdest_target_exterr_f(v) ((U32(v) & 0x1U) << 21U)
#define minion_falcon_irqdest_target_exterr_m() (U32(0x1U) << 21U) #define minion_falcon_irqdest_target_exterr_m() (U32(0x1U) << 21U)
#define minion_falcon_irqdest_target_exterr_v(r) (((r) >> 21U) & 0x1U) #define minion_falcon_irqdest_target_exterr_v(r) (((r) >> 21U) & 0x1U)
#define minion_falcon_irqdest_target_exterr_host_normal_v() (0x00000000U) #define minion_falcon_irqdest_target_exterr_host_normal_v() (0x00000000U)
#define minion_falcon_irqdest_target_exterr_host_normal_f() (0x0U) #define minion_falcon_irqdest_target_exterr_host_normal_f() (0x0U)
#define minion_falcon_irqdest_target_swgen0_f(v) (((v)&0x1U) << 22U) #define minion_falcon_irqdest_target_swgen0_f(v) ((U32(v) & 0x1U) << 22U)
#define minion_falcon_irqdest_target_swgen0_m() (U32(0x1U) << 22U) #define minion_falcon_irqdest_target_swgen0_m() (U32(0x1U) << 22U)
#define minion_falcon_irqdest_target_swgen0_v(r) (((r) >> 22U) & 0x1U) #define minion_falcon_irqdest_target_swgen0_v(r) (((r) >> 22U) & 0x1U)
#define minion_falcon_irqdest_target_swgen0_host_normal_v() (0x00000000U) #define minion_falcon_irqdest_target_swgen0_host_normal_v() (0x00000000U)
#define minion_falcon_irqdest_target_swgen0_host_normal_f() (0x0U) #define minion_falcon_irqdest_target_swgen0_host_normal_f() (0x0U)
#define minion_falcon_irqdest_target_swgen1_f(v) (((v)&0x1U) << 23U) #define minion_falcon_irqdest_target_swgen1_f(v) ((U32(v) & 0x1U) << 23U)
#define minion_falcon_irqdest_target_swgen1_m() (U32(0x1U) << 23U) #define minion_falcon_irqdest_target_swgen1_m() (U32(0x1U) << 23U)
#define minion_falcon_irqdest_target_swgen1_v(r) (((r) >> 23U) & 0x1U) #define minion_falcon_irqdest_target_swgen1_v(r) (((r) >> 23U) & 0x1U)
#define minion_falcon_irqdest_target_swgen1_host_normal_v() (0x00000000U) #define minion_falcon_irqdest_target_swgen1_host_normal_v() (0x00000000U)
@@ -158,58 +158,58 @@
#define minion_falcon_os_r() (0x00000080U) #define minion_falcon_os_r() (0x00000080U)
#define minion_falcon_mailbox1_r() (0x00000044U) #define minion_falcon_mailbox1_r() (0x00000044U)
#define minion_minion_intr_r() (0x00000810U) #define minion_minion_intr_r() (0x00000810U)
#define minion_minion_intr_fatal_f(v) (((v)&0x1U) << 0U) #define minion_minion_intr_fatal_f(v) ((U32(v) & 0x1U) << 0U)
#define minion_minion_intr_fatal_m() (U32(0x1U) << 0U) #define minion_minion_intr_fatal_m() (U32(0x1U) << 0U)
#define minion_minion_intr_fatal_v(r) (((r) >> 0U) & 0x1U) #define minion_minion_intr_fatal_v(r) (((r) >> 0U) & 0x1U)
#define minion_minion_intr_nonfatal_f(v) (((v)&0x1U) << 1U) #define minion_minion_intr_nonfatal_f(v) ((U32(v) & 0x1U) << 1U)
#define minion_minion_intr_nonfatal_m() (U32(0x1U) << 1U) #define minion_minion_intr_nonfatal_m() (U32(0x1U) << 1U)
#define minion_minion_intr_nonfatal_v(r) (((r) >> 1U) & 0x1U) #define minion_minion_intr_nonfatal_v(r) (((r) >> 1U) & 0x1U)
#define minion_minion_intr_falcon_stall_f(v) (((v)&0x1U) << 2U) #define minion_minion_intr_falcon_stall_f(v) ((U32(v) & 0x1U) << 2U)
#define minion_minion_intr_falcon_stall_m() (U32(0x1U) << 2U) #define minion_minion_intr_falcon_stall_m() (U32(0x1U) << 2U)
#define minion_minion_intr_falcon_stall_v(r) (((r) >> 2U) & 0x1U) #define minion_minion_intr_falcon_stall_v(r) (((r) >> 2U) & 0x1U)
#define minion_minion_intr_falcon_nostall_f(v) (((v)&0x1U) << 3U) #define minion_minion_intr_falcon_nostall_f(v) ((U32(v) & 0x1U) << 3U)
#define minion_minion_intr_falcon_nostall_m() (U32(0x1U) << 3U) #define minion_minion_intr_falcon_nostall_m() (U32(0x1U) << 3U)
#define minion_minion_intr_falcon_nostall_v(r) (((r) >> 3U) & 0x1U) #define minion_minion_intr_falcon_nostall_v(r) (((r) >> 3U) & 0x1U)
#define minion_minion_intr_link_f(v) (((v)&0xffffU) << 16U) #define minion_minion_intr_link_f(v) ((U32(v) & 0xffffU) << 16U)
#define minion_minion_intr_link_m() (U32(0xffffU) << 16U) #define minion_minion_intr_link_m() (U32(0xffffU) << 16U)
#define minion_minion_intr_link_v(r) (((r) >> 16U) & 0xffffU) #define minion_minion_intr_link_v(r) (((r) >> 16U) & 0xffffU)
#define minion_minion_intr_nonstall_en_r() (0x0000081cU) #define minion_minion_intr_nonstall_en_r() (0x0000081cU)
#define minion_minion_intr_stall_en_r() (0x00000818U) #define minion_minion_intr_stall_en_r() (0x00000818U)
#define minion_minion_intr_stall_en_fatal_f(v) (((v)&0x1U) << 0U) #define minion_minion_intr_stall_en_fatal_f(v) ((U32(v) & 0x1U) << 0U)
#define minion_minion_intr_stall_en_fatal_m() (U32(0x1U) << 0U) #define minion_minion_intr_stall_en_fatal_m() (U32(0x1U) << 0U)
#define minion_minion_intr_stall_en_fatal_v(r) (((r) >> 0U) & 0x1U) #define minion_minion_intr_stall_en_fatal_v(r) (((r) >> 0U) & 0x1U)
#define minion_minion_intr_stall_en_fatal_enable_v() (0x00000001U) #define minion_minion_intr_stall_en_fatal_enable_v() (0x00000001U)
#define minion_minion_intr_stall_en_fatal_enable_f() (0x1U) #define minion_minion_intr_stall_en_fatal_enable_f() (0x1U)
#define minion_minion_intr_stall_en_fatal_disable_v() (0x00000000U) #define minion_minion_intr_stall_en_fatal_disable_v() (0x00000000U)
#define minion_minion_intr_stall_en_fatal_disable_f() (0x0U) #define minion_minion_intr_stall_en_fatal_disable_f() (0x0U)
#define minion_minion_intr_stall_en_nonfatal_f(v) (((v)&0x1U) << 1U) #define minion_minion_intr_stall_en_nonfatal_f(v) ((U32(v) & 0x1U) << 1U)
#define minion_minion_intr_stall_en_nonfatal_m() (U32(0x1U) << 1U) #define minion_minion_intr_stall_en_nonfatal_m() (U32(0x1U) << 1U)
#define minion_minion_intr_stall_en_nonfatal_v(r) (((r) >> 1U) & 0x1U) #define minion_minion_intr_stall_en_nonfatal_v(r) (((r) >> 1U) & 0x1U)
#define minion_minion_intr_stall_en_nonfatal_enable_v() (0x00000001U) #define minion_minion_intr_stall_en_nonfatal_enable_v() (0x00000001U)
#define minion_minion_intr_stall_en_nonfatal_enable_f() (0x2U) #define minion_minion_intr_stall_en_nonfatal_enable_f() (0x2U)
#define minion_minion_intr_stall_en_nonfatal_disable_v() (0x00000000U) #define minion_minion_intr_stall_en_nonfatal_disable_v() (0x00000000U)
#define minion_minion_intr_stall_en_nonfatal_disable_f() (0x0U) #define minion_minion_intr_stall_en_nonfatal_disable_f() (0x0U)
#define minion_minion_intr_stall_en_falcon_stall_f(v) (((v)&0x1U) << 2U) #define minion_minion_intr_stall_en_falcon_stall_f(v) ((U32(v) & 0x1U) << 2U)
#define minion_minion_intr_stall_en_falcon_stall_m() (U32(0x1U) << 2U) #define minion_minion_intr_stall_en_falcon_stall_m() (U32(0x1U) << 2U)
#define minion_minion_intr_stall_en_falcon_stall_v(r) (((r) >> 2U) & 0x1U) #define minion_minion_intr_stall_en_falcon_stall_v(r) (((r) >> 2U) & 0x1U)
#define minion_minion_intr_stall_en_falcon_stall_enable_v() (0x00000001U) #define minion_minion_intr_stall_en_falcon_stall_enable_v() (0x00000001U)
#define minion_minion_intr_stall_en_falcon_stall_enable_f() (0x4U) #define minion_minion_intr_stall_en_falcon_stall_enable_f() (0x4U)
#define minion_minion_intr_stall_en_falcon_stall_disable_v() (0x00000000U) #define minion_minion_intr_stall_en_falcon_stall_disable_v() (0x00000000U)
#define minion_minion_intr_stall_en_falcon_stall_disable_f() (0x0U) #define minion_minion_intr_stall_en_falcon_stall_disable_f() (0x0U)
#define minion_minion_intr_stall_en_falcon_nostall_f(v) (((v)&0x1U) << 3U) #define minion_minion_intr_stall_en_falcon_nostall_f(v) ((U32(v) & 0x1U) << 3U)
#define minion_minion_intr_stall_en_falcon_nostall_m() (U32(0x1U) << 3U) #define minion_minion_intr_stall_en_falcon_nostall_m() (U32(0x1U) << 3U)
#define minion_minion_intr_stall_en_falcon_nostall_v(r) (((r) >> 3U) & 0x1U) #define minion_minion_intr_stall_en_falcon_nostall_v(r) (((r) >> 3U) & 0x1U)
#define minion_minion_intr_stall_en_falcon_nostall_enable_v() (0x00000001U) #define minion_minion_intr_stall_en_falcon_nostall_enable_v() (0x00000001U)
#define minion_minion_intr_stall_en_falcon_nostall_enable_f() (0x8U) #define minion_minion_intr_stall_en_falcon_nostall_enable_f() (0x8U)
#define minion_minion_intr_stall_en_falcon_nostall_disable_v() (0x00000000U) #define minion_minion_intr_stall_en_falcon_nostall_disable_v() (0x00000000U)
#define minion_minion_intr_stall_en_falcon_nostall_disable_f() (0x0U) #define minion_minion_intr_stall_en_falcon_nostall_disable_f() (0x0U)
#define minion_minion_intr_stall_en_link_f(v) (((v)&0xffffU) << 16U) #define minion_minion_intr_stall_en_link_f(v) ((U32(v) & 0xffffU) << 16U)
#define minion_minion_intr_stall_en_link_m() (U32(0xffffU) << 16U) #define minion_minion_intr_stall_en_link_m() (U32(0xffffU) << 16U)
#define minion_minion_intr_stall_en_link_v(r) (((r) >> 16U) & 0xffffU) #define minion_minion_intr_stall_en_link_v(r) (((r) >> 16U) & 0xffffU)
#define minion_nvlink_dl_cmd_r(i)\ #define minion_nvlink_dl_cmd_r(i)\
(nvgpu_safe_add_u32(0x00000900U, nvgpu_safe_mult_u32((i), 4U))) (nvgpu_safe_add_u32(0x00000900U, nvgpu_safe_mult_u32((i), 4U)))
#define minion_nvlink_dl_cmd___size_1_v() (0x00000006U) #define minion_nvlink_dl_cmd___size_1_v() (0x00000006U)
#define minion_nvlink_dl_cmd_command_f(v) (((v)&0xffU) << 0U) #define minion_nvlink_dl_cmd_command_f(v) ((U32(v) & 0xffU) << 0U)
#define minion_nvlink_dl_cmd_command_v(r) (((r) >> 0U) & 0xffU) #define minion_nvlink_dl_cmd_command_v(r) (((r) >> 0U) & 0xffU)
#define minion_nvlink_dl_cmd_command_configeom_v() (0x00000040U) #define minion_nvlink_dl_cmd_command_configeom_v() (0x00000040U)
#define minion_nvlink_dl_cmd_command_configeom_f() (0x40U) #define minion_nvlink_dl_cmd_command_configeom_f() (0x40U)
@@ -255,18 +255,18 @@
#define minion_nvlink_dl_cmd_command_initpll_6_f() (0x26U) #define minion_nvlink_dl_cmd_command_initpll_6_f() (0x26U)
#define minion_nvlink_dl_cmd_command_initpll_7_v() (0x00000027U) #define minion_nvlink_dl_cmd_command_initpll_7_v() (0x00000027U)
#define minion_nvlink_dl_cmd_command_initpll_7_f() (0x27U) #define minion_nvlink_dl_cmd_command_initpll_7_f() (0x27U)
#define minion_nvlink_dl_cmd_fault_f(v) (((v)&0x1U) << 30U) #define minion_nvlink_dl_cmd_fault_f(v) ((U32(v) & 0x1U) << 30U)
#define minion_nvlink_dl_cmd_fault_v(r) (((r) >> 30U) & 0x1U) #define minion_nvlink_dl_cmd_fault_v(r) (((r) >> 30U) & 0x1U)
#define minion_nvlink_dl_cmd_fault_fault_clear_v() (0x00000001U) #define minion_nvlink_dl_cmd_fault_fault_clear_v() (0x00000001U)
#define minion_nvlink_dl_cmd_ready_f(v) (((v)&0x1U) << 31U) #define minion_nvlink_dl_cmd_ready_f(v) ((U32(v) & 0x1U) << 31U)
#define minion_nvlink_dl_cmd_ready_v(r) (((r) >> 31U) & 0x1U) #define minion_nvlink_dl_cmd_ready_v(r) (((r) >> 31U) & 0x1U)
#define minion_misc_0_r() (0x000008b0U) #define minion_misc_0_r() (0x000008b0U)
#define minion_misc_0_scratch_swrw_0_f(v) (((v)&0xffffffffU) << 0U) #define minion_misc_0_scratch_swrw_0_f(v) ((U32(v) & 0xffffffffU) << 0U)
#define minion_misc_0_scratch_swrw_0_v(r) (((r) >> 0U) & 0xffffffffU) #define minion_misc_0_scratch_swrw_0_v(r) (((r) >> 0U) & 0xffffffffU)
#define minion_nvlink_link_intr_r(i)\ #define minion_nvlink_link_intr_r(i)\
(nvgpu_safe_add_u32(0x00000a00U, nvgpu_safe_mult_u32((i), 4U))) (nvgpu_safe_add_u32(0x00000a00U, nvgpu_safe_mult_u32((i), 4U)))
#define minion_nvlink_link_intr___size_1_v() (0x00000006U) #define minion_nvlink_link_intr___size_1_v() (0x00000006U)
#define minion_nvlink_link_intr_code_f(v) (((v)&0xffU) << 0U) #define minion_nvlink_link_intr_code_f(v) ((U32(v) & 0xffU) << 0U)
#define minion_nvlink_link_intr_code_m() (U32(0xffU) << 0U) #define minion_nvlink_link_intr_code_m() (U32(0xffU) << 0U)
#define minion_nvlink_link_intr_code_v(r) (((r) >> 0U) & 0xffU) #define minion_nvlink_link_intr_code_v(r) (((r) >> 0U) & 0xffU)
#define minion_nvlink_link_intr_code_na_v() (0x00000000U) #define minion_nvlink_link_intr_code_na_v() (0x00000000U)
@@ -277,10 +277,10 @@
#define minion_nvlink_link_intr_code_dlreq_f() (0x2U) #define minion_nvlink_link_intr_code_dlreq_f() (0x2U)
#define minion_nvlink_link_intr_code_pmdisabled_v() (0x00000003U) #define minion_nvlink_link_intr_code_pmdisabled_v() (0x00000003U)
#define minion_nvlink_link_intr_code_pmdisabled_f() (0x3U) #define minion_nvlink_link_intr_code_pmdisabled_f() (0x3U)
#define minion_nvlink_link_intr_subcode_f(v) (((v)&0xffU) << 8U) #define minion_nvlink_link_intr_subcode_f(v) ((U32(v) & 0xffU) << 8U)
#define minion_nvlink_link_intr_subcode_m() (U32(0xffU) << 8U) #define minion_nvlink_link_intr_subcode_m() (U32(0xffU) << 8U)
#define minion_nvlink_link_intr_subcode_v(r) (((r) >> 8U) & 0xffU) #define minion_nvlink_link_intr_subcode_v(r) (((r) >> 8U) & 0xffU)
#define minion_nvlink_link_intr_state_f(v) (((v)&0x1U) << 31U) #define minion_nvlink_link_intr_state_f(v) ((U32(v) & 0x1U) << 31U)
#define minion_nvlink_link_intr_state_m() (U32(0x1U) << 31U) #define minion_nvlink_link_intr_state_m() (U32(0x1U) << 31U)
#define minion_nvlink_link_intr_state_v(r) (((r) >> 31U) & 0x1U) #define minion_nvlink_link_intr_state_v(r) (((r) >> 31U) & 0x1U)
#define minion_falcon_csberrstat_r() (0x00000244U) #define minion_falcon_csberrstat_r() (0x00000244U)

158
drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_nvl_gv100.h
View File

@@ -60,7 +60,7 @@
#include <nvgpu/safe_ops.h> #include <nvgpu/safe_ops.h>
#define nvl_link_state_r() (0x00000000U) #define nvl_link_state_r() (0x00000000U)
#define nvl_link_state_state_f(v) (((v)&0xffU) << 0U) #define nvl_link_state_state_f(v) ((U32(v) & 0xffU) << 0U)
#define nvl_link_state_state_m() (U32(0xffU) << 0U) #define nvl_link_state_state_m() (U32(0xffU) << 0U)
#define nvl_link_state_state_v(r) (((r) >> 0U) & 0xffU) #define nvl_link_state_state_v(r) (((r) >> 0U) & 0xffU)
#define nvl_link_state_state_init_v() (0x00000000U) #define nvl_link_state_state_init_v() (0x00000000U)
@@ -79,45 +79,45 @@
#define nvl_link_state_state_rcvy_sw_f() (0x9U) #define nvl_link_state_state_rcvy_sw_f() (0x9U)
#define nvl_link_state_state_rcvy_rx_v() (0x0000000aU) #define nvl_link_state_state_rcvy_rx_v() (0x0000000aU)
#define nvl_link_state_state_rcvy_rx_f() (0xaU) #define nvl_link_state_state_rcvy_rx_f() (0xaU)
#define nvl_link_state_an0_busy_f(v) (((v)&0x1U) << 12U) #define nvl_link_state_an0_busy_f(v) ((U32(v) & 0x1U) << 12U)
#define nvl_link_state_an0_busy_m() (U32(0x1U) << 12U) #define nvl_link_state_an0_busy_m() (U32(0x1U) << 12U)
#define nvl_link_state_an0_busy_v(r) (((r) >> 12U) & 0x1U) #define nvl_link_state_an0_busy_v(r) (((r) >> 12U) & 0x1U)
#define nvl_link_state_tl_busy_f(v) (((v)&0x1U) << 13U) #define nvl_link_state_tl_busy_f(v) ((U32(v) & 0x1U) << 13U)
#define nvl_link_state_tl_busy_m() (U32(0x1U) << 13U) #define nvl_link_state_tl_busy_m() (U32(0x1U) << 13U)
#define nvl_link_state_tl_busy_v(r) (((r) >> 13U) & 0x1U) #define nvl_link_state_tl_busy_v(r) (((r) >> 13U) & 0x1U)
#define nvl_link_state_dbg_substate_f(v) (((v)&0xffffU) << 16U) #define nvl_link_state_dbg_substate_f(v) ((U32(v) & 0xffffU) << 16U)
#define nvl_link_state_dbg_substate_m() (U32(0xffffU) << 16U) #define nvl_link_state_dbg_substate_m() (U32(0xffffU) << 16U)
#define nvl_link_state_dbg_substate_v(r) (((r) >> 16U) & 0xffffU) #define nvl_link_state_dbg_substate_v(r) (((r) >> 16U) & 0xffffU)
#define nvl_link_activity_r() (0x0000000cU) #define nvl_link_activity_r() (0x0000000cU)
#define nvl_link_activity_blkact_f(v) (((v)&0x7U) << 0U) #define nvl_link_activity_blkact_f(v) ((U32(v) & 0x7U) << 0U)
#define nvl_link_activity_blkact_m() (U32(0x7U) << 0U) #define nvl_link_activity_blkact_m() (U32(0x7U) << 0U)
#define nvl_link_activity_blkact_v(r) (((r) >> 0U) & 0x7U) #define nvl_link_activity_blkact_v(r) (((r) >> 0U) & 0x7U)
#define nvl_sublink_activity_r(i)\ #define nvl_sublink_activity_r(i)\
(nvgpu_safe_add_u32(0x00000010U, nvgpu_safe_mult_u32((i), 4U))) (nvgpu_safe_add_u32(0x00000010U, nvgpu_safe_mult_u32((i), 4U)))
#define nvl_sublink_activity_blkact0_f(v) (((v)&0x7U) << 0U) #define nvl_sublink_activity_blkact0_f(v) ((U32(v) & 0x7U) << 0U)
#define nvl_sublink_activity_blkact0_m() (U32(0x7U) << 0U) #define nvl_sublink_activity_blkact0_m() (U32(0x7U) << 0U)
#define nvl_sublink_activity_blkact0_v(r) (((r) >> 0U) & 0x7U) #define nvl_sublink_activity_blkact0_v(r) (((r) >> 0U) & 0x7U)
#define nvl_sublink_activity_blkact1_f(v) (((v)&0x7U) << 8U) #define nvl_sublink_activity_blkact1_f(v) ((U32(v) & 0x7U) << 8U)
#define nvl_sublink_activity_blkact1_m() (U32(0x7U) << 8U) #define nvl_sublink_activity_blkact1_m() (U32(0x7U) << 8U)
#define nvl_sublink_activity_blkact1_v(r) (((r) >> 8U) & 0x7U) #define nvl_sublink_activity_blkact1_v(r) (((r) >> 8U) & 0x7U)
#define nvl_link_config_r() (0x00000018U) #define nvl_link_config_r() (0x00000018U)
#define nvl_link_config_ac_safe_en_f(v) (((v)&0x1U) << 30U) #define nvl_link_config_ac_safe_en_f(v) ((U32(v) & 0x1U) << 30U)
#define nvl_link_config_ac_safe_en_m() (U32(0x1U) << 30U) #define nvl_link_config_ac_safe_en_m() (U32(0x1U) << 30U)
#define nvl_link_config_ac_safe_en_v(r) (((r) >> 30U) & 0x1U) #define nvl_link_config_ac_safe_en_v(r) (((r) >> 30U) & 0x1U)
#define nvl_link_config_ac_safe_en_on_v() (0x00000001U) #define nvl_link_config_ac_safe_en_on_v() (0x00000001U)
#define nvl_link_config_ac_safe_en_on_f() (0x40000000U) #define nvl_link_config_ac_safe_en_on_f() (0x40000000U)
#define nvl_link_config_link_en_f(v) (((v)&0x1U) << 31U) #define nvl_link_config_link_en_f(v) ((U32(v) & 0x1U) << 31U)
#define nvl_link_config_link_en_m() (U32(0x1U) << 31U) #define nvl_link_config_link_en_m() (U32(0x1U) << 31U)
#define nvl_link_config_link_en_v(r) (((r) >> 31U) & 0x1U) #define nvl_link_config_link_en_v(r) (((r) >> 31U) & 0x1U)
#define nvl_link_config_link_en_on_v() (0x00000001U) #define nvl_link_config_link_en_on_v() (0x00000001U)
#define nvl_link_config_link_en_on_f() (0x80000000U) #define nvl_link_config_link_en_on_f() (0x80000000U)
#define nvl_link_change_r() (0x00000040U) #define nvl_link_change_r() (0x00000040U)
#define nvl_link_change_oldstate_mask_f(v) (((v)&0xfU) << 16U) #define nvl_link_change_oldstate_mask_f(v) ((U32(v) & 0xfU) << 16U)
#define nvl_link_change_oldstate_mask_m() (U32(0xfU) << 16U) #define nvl_link_change_oldstate_mask_m() (U32(0xfU) << 16U)
#define nvl_link_change_oldstate_mask_v(r) (((r) >> 16U) & 0xfU) #define nvl_link_change_oldstate_mask_v(r) (((r) >> 16U) & 0xfU)
#define nvl_link_change_oldstate_mask_dontcare_v() (0x0000000fU) #define nvl_link_change_oldstate_mask_dontcare_v() (0x0000000fU)
#define nvl_link_change_oldstate_mask_dontcare_f() (0xf0000U) #define nvl_link_change_oldstate_mask_dontcare_f() (0xf0000U)
#define nvl_link_change_newstate_f(v) (((v)&0xfU) << 4U) #define nvl_link_change_newstate_f(v) ((U32(v) & 0xfU) << 4U)
#define nvl_link_change_newstate_m() (U32(0xfU) << 4U) #define nvl_link_change_newstate_m() (U32(0xfU) << 4U)
#define nvl_link_change_newstate_v(r) (((r) >> 4U) & 0xfU) #define nvl_link_change_newstate_v(r) (((r) >> 4U) & 0xfU)
#define nvl_link_change_newstate_hwcfg_v() (0x00000001U) #define nvl_link_change_newstate_hwcfg_v() (0x00000001U)
@@ -126,12 +126,12 @@
#define nvl_link_change_newstate_swcfg_f() (0x20U) #define nvl_link_change_newstate_swcfg_f() (0x20U)
#define nvl_link_change_newstate_active_v() (0x00000003U) #define nvl_link_change_newstate_active_v() (0x00000003U)
#define nvl_link_change_newstate_active_f() (0x30U) #define nvl_link_change_newstate_active_f() (0x30U)
#define nvl_link_change_action_f(v) (((v)&0x3U) << 2U) #define nvl_link_change_action_f(v) ((U32(v) & 0x3U) << 2U)
#define nvl_link_change_action_m() (U32(0x3U) << 2U) #define nvl_link_change_action_m() (U32(0x3U) << 2U)
#define nvl_link_change_action_v(r) (((r) >> 2U) & 0x3U) #define nvl_link_change_action_v(r) (((r) >> 2U) & 0x3U)
#define nvl_link_change_action_ltssm_change_v() (0x00000001U) #define nvl_link_change_action_ltssm_change_v() (0x00000001U)
#define nvl_link_change_action_ltssm_change_f() (0x4U) #define nvl_link_change_action_ltssm_change_f() (0x4U)
#define nvl_link_change_status_f(v) (((v)&0x3U) << 0U) #define nvl_link_change_status_f(v) ((U32(v) & 0x3U) << 0U)
#define nvl_link_change_status_m() (U32(0x3U) << 0U) #define nvl_link_change_status_m() (U32(0x3U) << 0U)
#define nvl_link_change_status_v(r) (((r) >> 0U) & 0x3U) #define nvl_link_change_status_v(r) (((r) >> 0U) & 0x3U)
#define nvl_link_change_status_done_v() (0x00000000U) #define nvl_link_change_status_done_v() (0x00000000U)
@@ -141,22 +141,22 @@
#define nvl_link_change_status_fault_v() (0x00000002U) #define nvl_link_change_status_fault_v() (0x00000002U)
#define nvl_link_change_status_fault_f() (0x2U) #define nvl_link_change_status_fault_f() (0x2U)
#define nvl_sublink_change_r() (0x00000044U) #define nvl_sublink_change_r() (0x00000044U)
#define nvl_sublink_change_countdown_f(v) (((v)&0xfffU) << 20U) #define nvl_sublink_change_countdown_f(v) ((U32(v) & 0xfffU) << 20U)
#define nvl_sublink_change_countdown_m() (U32(0xfffU) << 20U) #define nvl_sublink_change_countdown_m() (U32(0xfffU) << 20U)
#define nvl_sublink_change_countdown_v(r) (((r) >> 20U) & 0xfffU) #define nvl_sublink_change_countdown_v(r) (((r) >> 20U) & 0xfffU)
#define nvl_sublink_change_oldstate_mask_f(v) (((v)&0xfU) << 16U) #define nvl_sublink_change_oldstate_mask_f(v) ((U32(v) & 0xfU) << 16U)
#define nvl_sublink_change_oldstate_mask_m() (U32(0xfU) << 16U) #define nvl_sublink_change_oldstate_mask_m() (U32(0xfU) << 16U)
#define nvl_sublink_change_oldstate_mask_v(r) (((r) >> 16U) & 0xfU) #define nvl_sublink_change_oldstate_mask_v(r) (((r) >> 16U) & 0xfU)
#define nvl_sublink_change_oldstate_mask_dontcare_v() (0x0000000fU) #define nvl_sublink_change_oldstate_mask_dontcare_v() (0x0000000fU)
#define nvl_sublink_change_oldstate_mask_dontcare_f() (0xf0000U) #define nvl_sublink_change_oldstate_mask_dontcare_f() (0xf0000U)
#define nvl_sublink_change_sublink_f(v) (((v)&0xfU) << 12U) #define nvl_sublink_change_sublink_f(v) ((U32(v) & 0xfU) << 12U)
#define nvl_sublink_change_sublink_m() (U32(0xfU) << 12U) #define nvl_sublink_change_sublink_m() (U32(0xfU) << 12U)
#define nvl_sublink_change_sublink_v(r) (((r) >> 12U) & 0xfU) #define nvl_sublink_change_sublink_v(r) (((r) >> 12U) & 0xfU)
#define nvl_sublink_change_sublink_tx_v() (0x00000000U) #define nvl_sublink_change_sublink_tx_v() (0x00000000U)
#define nvl_sublink_change_sublink_tx_f() (0x0U) #define nvl_sublink_change_sublink_tx_f() (0x0U)
#define nvl_sublink_change_sublink_rx_v() (0x00000001U) #define nvl_sublink_change_sublink_rx_v() (0x00000001U)
#define nvl_sublink_change_sublink_rx_f() (0x1000U) #define nvl_sublink_change_sublink_rx_f() (0x1000U)
#define nvl_sublink_change_newstate_f(v) (((v)&0xfU) << 4U) #define nvl_sublink_change_newstate_f(v) ((U32(v) & 0xfU) << 4U)
#define nvl_sublink_change_newstate_m() (U32(0xfU) << 4U) #define nvl_sublink_change_newstate_m() (U32(0xfU) << 4U)
#define nvl_sublink_change_newstate_v(r) (((r) >> 4U) & 0xfU) #define nvl_sublink_change_newstate_v(r) (((r) >> 4U) & 0xfU)
#define nvl_sublink_change_newstate_hs_v() (0x00000000U) #define nvl_sublink_change_newstate_hs_v() (0x00000000U)
@@ -169,12 +169,12 @@
#define nvl_sublink_change_newstate_safe_f() (0x60U) #define nvl_sublink_change_newstate_safe_f() (0x60U)
#define nvl_sublink_change_newstate_off_v() (0x00000007U) #define nvl_sublink_change_newstate_off_v() (0x00000007U)
#define nvl_sublink_change_newstate_off_f() (0x70U) #define nvl_sublink_change_newstate_off_f() (0x70U)
#define nvl_sublink_change_action_f(v) (((v)&0x3U) << 2U) #define nvl_sublink_change_action_f(v) ((U32(v) & 0x3U) << 2U)
#define nvl_sublink_change_action_m() (U32(0x3U) << 2U) #define nvl_sublink_change_action_m() (U32(0x3U) << 2U)
#define nvl_sublink_change_action_v(r) (((r) >> 2U) & 0x3U) #define nvl_sublink_change_action_v(r) (((r) >> 2U) & 0x3U)
#define nvl_sublink_change_action_slsm_change_v() (0x00000001U) #define nvl_sublink_change_action_slsm_change_v() (0x00000001U)
#define nvl_sublink_change_action_slsm_change_f() (0x4U) #define nvl_sublink_change_action_slsm_change_f() (0x4U)
#define nvl_sublink_change_status_f(v) (((v)&0x3U) << 0U) #define nvl_sublink_change_status_f(v) ((U32(v) & 0x3U) << 0U)
#define nvl_sublink_change_status_m() (U32(0x3U) << 0U) #define nvl_sublink_change_status_m() (U32(0x3U) << 0U)
#define nvl_sublink_change_status_v(r) (((r) >> 0U) & 0x3U) #define nvl_sublink_change_status_v(r) (((r) >> 0U) & 0x3U)
#define nvl_sublink_change_status_done_v() (0x00000000U) #define nvl_sublink_change_status_done_v() (0x00000000U)
@@ -184,26 +184,26 @@
#define nvl_sublink_change_status_fault_v() (0x00000002U) #define nvl_sublink_change_status_fault_v() (0x00000002U)
#define nvl_sublink_change_status_fault_f() (0x2U) #define nvl_sublink_change_status_fault_f() (0x2U)
#define nvl_link_test_r() (0x00000048U) #define nvl_link_test_r() (0x00000048U)
#define nvl_link_test_mode_f(v) (((v)&0x1U) << 0U) #define nvl_link_test_mode_f(v) ((U32(v) & 0x1U) << 0U)
#define nvl_link_test_mode_m() (U32(0x1U) << 0U) #define nvl_link_test_mode_m() (U32(0x1U) << 0U)
#define nvl_link_test_mode_v(r) (((r) >> 0U) & 0x1U) #define nvl_link_test_mode_v(r) (((r) >> 0U) & 0x1U)
#define nvl_link_test_mode_enable_v() (0x00000001U) #define nvl_link_test_mode_enable_v() (0x00000001U)
#define nvl_link_test_mode_enable_f() (0x1U) #define nvl_link_test_mode_enable_f() (0x1U)
#define nvl_link_test_auto_hwcfg_f(v) (((v)&0x1U) << 30U) #define nvl_link_test_auto_hwcfg_f(v) ((U32(v) & 0x1U) << 30U)
#define nvl_link_test_auto_hwcfg_m() (U32(0x1U) << 30U) #define nvl_link_test_auto_hwcfg_m() (U32(0x1U) << 30U)
#define nvl_link_test_auto_hwcfg_v(r) (((r) >> 30U) & 0x1U) #define nvl_link_test_auto_hwcfg_v(r) (((r) >> 30U) & 0x1U)
#define nvl_link_test_auto_hwcfg_enable_v() (0x00000001U) #define nvl_link_test_auto_hwcfg_enable_v() (0x00000001U)
#define nvl_link_test_auto_hwcfg_enable_f() (0x40000000U) #define nvl_link_test_auto_hwcfg_enable_f() (0x40000000U)
#define nvl_link_test_auto_nvhs_f(v) (((v)&0x1U) << 31U) #define nvl_link_test_auto_nvhs_f(v) ((U32(v) & 0x1U) << 31U)
#define nvl_link_test_auto_nvhs_m() (U32(0x1U) << 31U) #define nvl_link_test_auto_nvhs_m() (U32(0x1U) << 31U)
#define nvl_link_test_auto_nvhs_v(r) (((r) >> 31U) & 0x1U) #define nvl_link_test_auto_nvhs_v(r) (((r) >> 31U) & 0x1U)
#define nvl_link_test_auto_nvhs_enable_v() (0x00000001U) #define nvl_link_test_auto_nvhs_enable_v() (0x00000001U)
#define nvl_link_test_auto_nvhs_enable_f() (0x80000000U) #define nvl_link_test_auto_nvhs_enable_f() (0x80000000U)
#define nvl_sl0_slsm_status_tx_r() (0x00002024U) #define nvl_sl0_slsm_status_tx_r() (0x00002024U)
#define nvl_sl0_slsm_status_tx_substate_f(v) (((v)&0xfU) << 0U) #define nvl_sl0_slsm_status_tx_substate_f(v) ((U32(v) & 0xfU) << 0U)
#define nvl_sl0_slsm_status_tx_substate_m() (U32(0xfU) << 0U) #define nvl_sl0_slsm_status_tx_substate_m() (U32(0xfU) << 0U)
#define nvl_sl0_slsm_status_tx_substate_v(r) (((r) >> 0U) & 0xfU) #define nvl_sl0_slsm_status_tx_substate_v(r) (((r) >> 0U) & 0xfU)
#define nvl_sl0_slsm_status_tx_primary_state_f(v) (((v)&0xfU) << 4U) #define nvl_sl0_slsm_status_tx_primary_state_f(v) ((U32(v) & 0xfU) << 4U)
#define nvl_sl0_slsm_status_tx_primary_state_m() (U32(0xfU) << 4U) #define nvl_sl0_slsm_status_tx_primary_state_m() (U32(0xfU) << 4U)
#define nvl_sl0_slsm_status_tx_primary_state_v(r) (((r) >> 4U) & 0xfU) #define nvl_sl0_slsm_status_tx_primary_state_v(r) (((r) >> 4U) & 0xfU)
#define nvl_sl0_slsm_status_tx_primary_state_hs_v() (0x00000000U) #define nvl_sl0_slsm_status_tx_primary_state_hs_v() (0x00000000U)
@@ -217,10 +217,10 @@
#define nvl_sl0_slsm_status_tx_primary_state_safe_v() (0x00000006U) #define nvl_sl0_slsm_status_tx_primary_state_safe_v() (0x00000006U)
#define nvl_sl0_slsm_status_tx_primary_state_safe_f() (0x60U) #define nvl_sl0_slsm_status_tx_primary_state_safe_f() (0x60U)
#define nvl_sl1_slsm_status_rx_r() (0x00003014U) #define nvl_sl1_slsm_status_rx_r() (0x00003014U)
#define nvl_sl1_slsm_status_rx_substate_f(v) (((v)&0xfU) << 0U) #define nvl_sl1_slsm_status_rx_substate_f(v) ((U32(v) & 0xfU) << 0U)
#define nvl_sl1_slsm_status_rx_substate_m() (U32(0xfU) << 0U) #define nvl_sl1_slsm_status_rx_substate_m() (U32(0xfU) << 0U)
#define nvl_sl1_slsm_status_rx_substate_v(r) (((r) >> 0U) & 0xfU) #define nvl_sl1_slsm_status_rx_substate_v(r) (((r) >> 0U) & 0xfU)
#define nvl_sl1_slsm_status_rx_primary_state_f(v) (((v)&0xfU) << 4U) #define nvl_sl1_slsm_status_rx_primary_state_f(v) ((U32(v) & 0xfU) << 4U)
#define nvl_sl1_slsm_status_rx_primary_state_m() (U32(0xfU) << 4U) #define nvl_sl1_slsm_status_rx_primary_state_m() (U32(0xfU) << 4U)
#define nvl_sl1_slsm_status_rx_primary_state_v(r) (((r) >> 4U) & 0xfU) #define nvl_sl1_slsm_status_rx_primary_state_v(r) (((r) >> 4U) & 0xfU)
#define nvl_sl1_slsm_status_rx_primary_state_hs_v() (0x00000000U) #define nvl_sl1_slsm_status_rx_primary_state_hs_v() (0x00000000U)
@@ -234,208 +234,208 @@
#define nvl_sl1_slsm_status_rx_primary_state_safe_v() (0x00000006U) #define nvl_sl1_slsm_status_rx_primary_state_safe_v() (0x00000006U)
#define nvl_sl1_slsm_status_rx_primary_state_safe_f() (0x60U) #define nvl_sl1_slsm_status_rx_primary_state_safe_f() (0x60U)
#define nvl_sl0_safe_ctrl2_tx_r() (0x00002008U) #define nvl_sl0_safe_ctrl2_tx_r() (0x00002008U)
#define nvl_sl0_safe_ctrl2_tx_ctr_init_f(v) (((v)&0x7ffU) << 0U) #define nvl_sl0_safe_ctrl2_tx_ctr_init_f(v) ((U32(v) & 0x7ffU) << 0U)
#define nvl_sl0_safe_ctrl2_tx_ctr_init_m() (U32(0x7ffU) << 0U) #define nvl_sl0_safe_ctrl2_tx_ctr_init_m() (U32(0x7ffU) << 0U)
#define nvl_sl0_safe_ctrl2_tx_ctr_init_v(r) (((r) >> 0U) & 0x7ffU) #define nvl_sl0_safe_ctrl2_tx_ctr_init_v(r) (((r) >> 0U) & 0x7ffU)
#define nvl_sl0_safe_ctrl2_tx_ctr_init_init_v() (0x00000728U) #define nvl_sl0_safe_ctrl2_tx_ctr_init_init_v() (0x00000728U)
#define nvl_sl0_safe_ctrl2_tx_ctr_init_init_f() (0x728U) #define nvl_sl0_safe_ctrl2_tx_ctr_init_init_f() (0x728U)
#define nvl_sl0_safe_ctrl2_tx_ctr_initscl_f(v) (((v)&0x1fU) << 11U) #define nvl_sl0_safe_ctrl2_tx_ctr_initscl_f(v) ((U32(v) & 0x1fU) << 11U)
#define nvl_sl0_safe_ctrl2_tx_ctr_initscl_m() (U32(0x1fU) << 11U) #define nvl_sl0_safe_ctrl2_tx_ctr_initscl_m() (U32(0x1fU) << 11U)
#define nvl_sl0_safe_ctrl2_tx_ctr_initscl_v(r) (((r) >> 11U) & 0x1fU) #define nvl_sl0_safe_ctrl2_tx_ctr_initscl_v(r) (((r) >> 11U) & 0x1fU)
#define nvl_sl0_safe_ctrl2_tx_ctr_initscl_init_v() (0x0000000fU) #define nvl_sl0_safe_ctrl2_tx_ctr_initscl_init_v() (0x0000000fU)
#define nvl_sl0_safe_ctrl2_tx_ctr_initscl_init_f() (0x7800U) #define nvl_sl0_safe_ctrl2_tx_ctr_initscl_init_f() (0x7800U)
#define nvl_sl1_error_rate_ctrl_r() (0x00003284U) #define nvl_sl1_error_rate_ctrl_r() (0x00003284U)
#define nvl_sl1_error_rate_ctrl_short_threshold_man_f(v) (((v)&0x7U) << 0U) #define nvl_sl1_error_rate_ctrl_short_threshold_man_f(v) ((U32(v) & 0x7U) << 0U)
#define nvl_sl1_error_rate_ctrl_short_threshold_man_m() (U32(0x7U) << 0U) #define nvl_sl1_error_rate_ctrl_short_threshold_man_m() (U32(0x7U) << 0U)
#define nvl_sl1_error_rate_ctrl_short_threshold_man_v(r) (((r) >> 0U) & 0x7U) #define nvl_sl1_error_rate_ctrl_short_threshold_man_v(r) (((r) >> 0U) & 0x7U)
#define nvl_sl1_error_rate_ctrl_long_threshold_man_f(v) (((v)&0x7U) << 16U) #define nvl_sl1_error_rate_ctrl_long_threshold_man_f(v) ((U32(v) & 0x7U) << 16U)
#define nvl_sl1_error_rate_ctrl_long_threshold_man_m() (U32(0x7U) << 16U) #define nvl_sl1_error_rate_ctrl_long_threshold_man_m() (U32(0x7U) << 16U)
#define nvl_sl1_error_rate_ctrl_long_threshold_man_v(r) (((r) >> 16U) & 0x7U) #define nvl_sl1_error_rate_ctrl_long_threshold_man_v(r) (((r) >> 16U) & 0x7U)
#define nvl_sl1_rxslsm_timeout_2_r() (0x00003034U) #define nvl_sl1_rxslsm_timeout_2_r() (0x00003034U)
#define nvl_txiobist_configreg_r() (0x00002e14U) #define nvl_txiobist_configreg_r() (0x00002e14U)
#define nvl_txiobist_configreg_io_bist_mode_in_f(v) (((v)&0x1U) << 17U) #define nvl_txiobist_configreg_io_bist_mode_in_f(v) ((U32(v) & 0x1U) << 17U)
#define nvl_txiobist_configreg_io_bist_mode_in_m() (U32(0x1U) << 17U) #define nvl_txiobist_configreg_io_bist_mode_in_m() (U32(0x1U) << 17U)
#define nvl_txiobist_configreg_io_bist_mode_in_v(r) (((r) >> 17U) & 0x1U) #define nvl_txiobist_configreg_io_bist_mode_in_v(r) (((r) >> 17U) & 0x1U)
#define nvl_txiobist_config_r() (0x00002e10U) #define nvl_txiobist_config_r() (0x00002e10U)
#define nvl_txiobist_config_dpg_prbsseedld_f(v) (((v)&0x1U) << 2U) #define nvl_txiobist_config_dpg_prbsseedld_f(v) ((U32(v) & 0x1U) << 2U)
#define nvl_txiobist_config_dpg_prbsseedld_m() (U32(0x1U) << 2U) #define nvl_txiobist_config_dpg_prbsseedld_m() (U32(0x1U) << 2U)
#define nvl_txiobist_config_dpg_prbsseedld_v(r) (((r) >> 2U) & 0x1U) #define nvl_txiobist_config_dpg_prbsseedld_v(r) (((r) >> 2U) & 0x1U)
#define nvl_intr_r() (0x00000050U) #define nvl_intr_r() (0x00000050U)
#define nvl_intr_tx_replay_f(v) (((v)&0x1U) << 0U) #define nvl_intr_tx_replay_f(v) ((U32(v) & 0x1U) << 0U)
#define nvl_intr_tx_replay_m() (U32(0x1U) << 0U) #define nvl_intr_tx_replay_m() (U32(0x1U) << 0U)
#define nvl_intr_tx_replay_v(r) (((r) >> 0U) & 0x1U) #define nvl_intr_tx_replay_v(r) (((r) >> 0U) & 0x1U)
#define nvl_intr_tx_recovery_short_f(v) (((v)&0x1U) << 1U) #define nvl_intr_tx_recovery_short_f(v) ((U32(v) & 0x1U) << 1U)
#define nvl_intr_tx_recovery_short_m() (U32(0x1U) << 1U) #define nvl_intr_tx_recovery_short_m() (U32(0x1U) << 1U)
#define nvl_intr_tx_recovery_short_v(r) (((r) >> 1U) & 0x1U) #define nvl_intr_tx_recovery_short_v(r) (((r) >> 1U) & 0x1U)
#define nvl_intr_tx_recovery_long_f(v) (((v)&0x1U) << 2U) #define nvl_intr_tx_recovery_long_f(v) ((U32(v) & 0x1U) << 2U)
#define nvl_intr_tx_recovery_long_m() (U32(0x1U) << 2U) #define nvl_intr_tx_recovery_long_m() (U32(0x1U) << 2U)
#define nvl_intr_tx_recovery_long_v(r) (((r) >> 2U) & 0x1U) #define nvl_intr_tx_recovery_long_v(r) (((r) >> 2U) & 0x1U)
#define nvl_intr_tx_fault_ram_f(v) (((v)&0x1U) << 4U) #define nvl_intr_tx_fault_ram_f(v) ((U32(v) & 0x1U) << 4U)
#define nvl_intr_tx_fault_ram_m() (U32(0x1U) << 4U) #define nvl_intr_tx_fault_ram_m() (U32(0x1U) << 4U)
#define nvl_intr_tx_fault_ram_v(r) (((r) >> 4U) & 0x1U) #define nvl_intr_tx_fault_ram_v(r) (((r) >> 4U) & 0x1U)
#define nvl_intr_tx_fault_interface_f(v) (((v)&0x1U) << 5U) #define nvl_intr_tx_fault_interface_f(v) ((U32(v) & 0x1U) << 5U)
#define nvl_intr_tx_fault_interface_m() (U32(0x1U) << 5U) #define nvl_intr_tx_fault_interface_m() (U32(0x1U) << 5U)
#define nvl_intr_tx_fault_interface_v(r) (((r) >> 5U) & 0x1U) #define nvl_intr_tx_fault_interface_v(r) (((r) >> 5U) & 0x1U)
#define nvl_intr_tx_fault_sublink_change_f(v) (((v)&0x1U) << 8U) #define nvl_intr_tx_fault_sublink_change_f(v) ((U32(v) & 0x1U) << 8U)
#define nvl_intr_tx_fault_sublink_change_m() (U32(0x1U) << 8U) #define nvl_intr_tx_fault_sublink_change_m() (U32(0x1U) << 8U)
#define nvl_intr_tx_fault_sublink_change_v(r) (((r) >> 8U) & 0x1U) #define nvl_intr_tx_fault_sublink_change_v(r) (((r) >> 8U) & 0x1U)
#define nvl_intr_rx_fault_sublink_change_f(v) (((v)&0x1U) << 16U) #define nvl_intr_rx_fault_sublink_change_f(v) ((U32(v) & 0x1U) << 16U)
#define nvl_intr_rx_fault_sublink_change_m() (U32(0x1U) << 16U) #define nvl_intr_rx_fault_sublink_change_m() (U32(0x1U) << 16U)
#define nvl_intr_rx_fault_sublink_change_v(r) (((r) >> 16U) & 0x1U) #define nvl_intr_rx_fault_sublink_change_v(r) (((r) >> 16U) & 0x1U)
#define nvl_intr_rx_fault_dl_protocol_f(v) (((v)&0x1U) << 20U) #define nvl_intr_rx_fault_dl_protocol_f(v) ((U32(v) & 0x1U) << 20U)
#define nvl_intr_rx_fault_dl_protocol_m() (U32(0x1U) << 20U) #define nvl_intr_rx_fault_dl_protocol_m() (U32(0x1U) << 20U)
#define nvl_intr_rx_fault_dl_protocol_v(r) (((r) >> 20U) & 0x1U) #define nvl_intr_rx_fault_dl_protocol_v(r) (((r) >> 20U) & 0x1U)
#define nvl_intr_rx_short_error_rate_f(v) (((v)&0x1U) << 21U) #define nvl_intr_rx_short_error_rate_f(v) ((U32(v) & 0x1U) << 21U)
#define nvl_intr_rx_short_error_rate_m() (U32(0x1U) << 21U) #define nvl_intr_rx_short_error_rate_m() (U32(0x1U) << 21U)
#define nvl_intr_rx_short_error_rate_v(r) (((r) >> 21U) & 0x1U) #define nvl_intr_rx_short_error_rate_v(r) (((r) >> 21U) & 0x1U)
#define nvl_intr_rx_long_error_rate_f(v) (((v)&0x1U) << 22U) #define nvl_intr_rx_long_error_rate_f(v) ((U32(v) & 0x1U) << 22U)
#define nvl_intr_rx_long_error_rate_m() (U32(0x1U) << 22U) #define nvl_intr_rx_long_error_rate_m() (U32(0x1U) << 22U)
#define nvl_intr_rx_long_error_rate_v(r) (((r) >> 22U) & 0x1U) #define nvl_intr_rx_long_error_rate_v(r) (((r) >> 22U) & 0x1U)
#define nvl_intr_rx_ila_trigger_f(v) (((v)&0x1U) << 23U) #define nvl_intr_rx_ila_trigger_f(v) ((U32(v) & 0x1U) << 23U)
#define nvl_intr_rx_ila_trigger_m() (U32(0x1U) << 23U) #define nvl_intr_rx_ila_trigger_m() (U32(0x1U) << 23U)
#define nvl_intr_rx_ila_trigger_v(r) (((r) >> 23U) & 0x1U) #define nvl_intr_rx_ila_trigger_v(r) (((r) >> 23U) & 0x1U)
#define nvl_intr_rx_crc_counter_f(v) (((v)&0x1U) << 24U) #define nvl_intr_rx_crc_counter_f(v) ((U32(v) & 0x1U) << 24U)
#define nvl_intr_rx_crc_counter_m() (U32(0x1U) << 24U) #define nvl_intr_rx_crc_counter_m() (U32(0x1U) << 24U)
#define nvl_intr_rx_crc_counter_v(r) (((r) >> 24U) & 0x1U) #define nvl_intr_rx_crc_counter_v(r) (((r) >> 24U) & 0x1U)
#define nvl_intr_ltssm_fault_f(v) (((v)&0x1U) << 28U) #define nvl_intr_ltssm_fault_f(v) ((U32(v) & 0x1U) << 28U)
#define nvl_intr_ltssm_fault_m() (U32(0x1U) << 28U) #define nvl_intr_ltssm_fault_m() (U32(0x1U) << 28U)
#define nvl_intr_ltssm_fault_v(r) (((r) >> 28U) & 0x1U) #define nvl_intr_ltssm_fault_v(r) (((r) >> 28U) & 0x1U)
#define nvl_intr_ltssm_protocol_f(v) (((v)&0x1U) << 29U) #define nvl_intr_ltssm_protocol_f(v) ((U32(v) & 0x1U) << 29U)
#define nvl_intr_ltssm_protocol_m() (U32(0x1U) << 29U) #define nvl_intr_ltssm_protocol_m() (U32(0x1U) << 29U)
#define nvl_intr_ltssm_protocol_v(r) (((r) >> 29U) & 0x1U) #define nvl_intr_ltssm_protocol_v(r) (((r) >> 29U) & 0x1U)
#define nvl_intr_minion_request_f(v) (((v)&0x1U) << 30U) #define nvl_intr_minion_request_f(v) ((U32(v) & 0x1U) << 30U)
#define nvl_intr_minion_request_m() (U32(0x1U) << 30U) #define nvl_intr_minion_request_m() (U32(0x1U) << 30U)
#define nvl_intr_minion_request_v(r) (((r) >> 30U) & 0x1U) #define nvl_intr_minion_request_v(r) (((r) >> 30U) & 0x1U)
#define nvl_intr_sw2_r() (0x00000054U) #define nvl_intr_sw2_r() (0x00000054U)
#define nvl_intr_minion_r() (0x00000060U) #define nvl_intr_minion_r() (0x00000060U)
#define nvl_intr_minion_tx_replay_f(v) (((v)&0x1U) << 0U) #define nvl_intr_minion_tx_replay_f(v) ((U32(v) & 0x1U) << 0U)
#define nvl_intr_minion_tx_replay_m() (U32(0x1U) << 0U) #define nvl_intr_minion_tx_replay_m() (U32(0x1U) << 0U)
#define nvl_intr_minion_tx_replay_v(r) (((r) >> 0U) & 0x1U) #define nvl_intr_minion_tx_replay_v(r) (((r) >> 0U) & 0x1U)
#define nvl_intr_minion_tx_recovery_short_f(v) (((v)&0x1U) << 1U) #define nvl_intr_minion_tx_recovery_short_f(v) ((U32(v) & 0x1U) << 1U)
#define nvl_intr_minion_tx_recovery_short_m() (U32(0x1U) << 1U) #define nvl_intr_minion_tx_recovery_short_m() (U32(0x1U) << 1U)
#define nvl_intr_minion_tx_recovery_short_v(r) (((r) >> 1U) & 0x1U) #define nvl_intr_minion_tx_recovery_short_v(r) (((r) >> 1U) & 0x1U)
#define nvl_intr_minion_tx_recovery_long_f(v) (((v)&0x1U) << 2U) #define nvl_intr_minion_tx_recovery_long_f(v) ((U32(v) & 0x1U) << 2U)
#define nvl_intr_minion_tx_recovery_long_m() (U32(0x1U) << 2U) #define nvl_intr_minion_tx_recovery_long_m() (U32(0x1U) << 2U)
#define nvl_intr_minion_tx_recovery_long_v(r) (((r) >> 2U) & 0x1U) #define nvl_intr_minion_tx_recovery_long_v(r) (((r) >> 2U) & 0x1U)
#define nvl_intr_minion_tx_fault_ram_f(v) (((v)&0x1U) << 4U) #define nvl_intr_minion_tx_fault_ram_f(v) ((U32(v) & 0x1U) << 4U)
#define nvl_intr_minion_tx_fault_ram_m() (U32(0x1U) << 4U) #define nvl_intr_minion_tx_fault_ram_m() (U32(0x1U) << 4U)
#define nvl_intr_minion_tx_fault_ram_v(r) (((r) >> 4U) & 0x1U) #define nvl_intr_minion_tx_fault_ram_v(r) (((r) >> 4U) & 0x1U)
#define nvl_intr_minion_tx_fault_interface_f(v) (((v)&0x1U) << 5U) #define nvl_intr_minion_tx_fault_interface_f(v) ((U32(v) & 0x1U) << 5U)
#define nvl_intr_minion_tx_fault_interface_m() (U32(0x1U) << 5U) #define nvl_intr_minion_tx_fault_interface_m() (U32(0x1U) << 5U)
#define nvl_intr_minion_tx_fault_interface_v(r) (((r) >> 5U) & 0x1U) #define nvl_intr_minion_tx_fault_interface_v(r) (((r) >> 5U) & 0x1U)
#define nvl_intr_minion_tx_fault_sublink_change_f(v) (((v)&0x1U) << 8U) #define nvl_intr_minion_tx_fault_sublink_change_f(v) ((U32(v) & 0x1U) << 8U)
#define nvl_intr_minion_tx_fault_sublink_change_m() (U32(0x1U) << 8U) #define nvl_intr_minion_tx_fault_sublink_change_m() (U32(0x1U) << 8U)
#define nvl_intr_minion_tx_fault_sublink_change_v(r) (((r) >> 8U) & 0x1U) #define nvl_intr_minion_tx_fault_sublink_change_v(r) (((r) >> 8U) & 0x1U)
#define nvl_intr_minion_rx_fault_sublink_change_f(v) (((v)&0x1U) << 16U) #define nvl_intr_minion_rx_fault_sublink_change_f(v) ((U32(v) & 0x1U) << 16U)
#define nvl_intr_minion_rx_fault_sublink_change_m() (U32(0x1U) << 16U) #define nvl_intr_minion_rx_fault_sublink_change_m() (U32(0x1U) << 16U)
#define nvl_intr_minion_rx_fault_sublink_change_v(r) (((r) >> 16U) & 0x1U) #define nvl_intr_minion_rx_fault_sublink_change_v(r) (((r) >> 16U) & 0x1U)
#define nvl_intr_minion_rx_fault_dl_protocol_f(v) (((v)&0x1U) << 20U) #define nvl_intr_minion_rx_fault_dl_protocol_f(v) ((U32(v) & 0x1U) << 20U)
#define nvl_intr_minion_rx_fault_dl_protocol_m() (U32(0x1U) << 20U) #define nvl_intr_minion_rx_fault_dl_protocol_m() (U32(0x1U) << 20U)
#define nvl_intr_minion_rx_fault_dl_protocol_v(r) (((r) >> 20U) & 0x1U) #define nvl_intr_minion_rx_fault_dl_protocol_v(r) (((r) >> 20U) & 0x1U)
#define nvl_intr_minion_rx_short_error_rate_f(v) (((v)&0x1U) << 21U) #define nvl_intr_minion_rx_short_error_rate_f(v) ((U32(v) & 0x1U) << 21U)
#define nvl_intr_minion_rx_short_error_rate_m() (U32(0x1U) << 21U) #define nvl_intr_minion_rx_short_error_rate_m() (U32(0x1U) << 21U)
#define nvl_intr_minion_rx_short_error_rate_v(r) (((r) >> 21U) & 0x1U) #define nvl_intr_minion_rx_short_error_rate_v(r) (((r) >> 21U) & 0x1U)
#define nvl_intr_minion_rx_long_error_rate_f(v) (((v)&0x1U) << 22U) #define nvl_intr_minion_rx_long_error_rate_f(v) ((U32(v) & 0x1U) << 22U)
#define nvl_intr_minion_rx_long_error_rate_m() (U32(0x1U) << 22U) #define nvl_intr_minion_rx_long_error_rate_m() (U32(0x1U) << 22U)
#define nvl_intr_minion_rx_long_error_rate_v(r) (((r) >> 22U) & 0x1U) #define nvl_intr_minion_rx_long_error_rate_v(r) (((r) >> 22U) & 0x1U)
#define nvl_intr_minion_rx_ila_trigger_f(v) (((v)&0x1U) << 23U) #define nvl_intr_minion_rx_ila_trigger_f(v) ((U32(v) & 0x1U) << 23U)
#define nvl_intr_minion_rx_ila_trigger_m() (U32(0x1U) << 23U) #define nvl_intr_minion_rx_ila_trigger_m() (U32(0x1U) << 23U)
#define nvl_intr_minion_rx_ila_trigger_v(r) (((r) >> 23U) & 0x1U) #define nvl_intr_minion_rx_ila_trigger_v(r) (((r) >> 23U) & 0x1U)
#define nvl_intr_minion_rx_crc_counter_f(v) (((v)&0x1U) << 24U) #define nvl_intr_minion_rx_crc_counter_f(v) ((U32(v) & 0x1U) << 24U)
#define nvl_intr_minion_rx_crc_counter_m() (U32(0x1U) << 24U) #define nvl_intr_minion_rx_crc_counter_m() (U32(0x1U) << 24U)
#define nvl_intr_minion_rx_crc_counter_v(r) (((r) >> 24U) & 0x1U) #define nvl_intr_minion_rx_crc_counter_v(r) (((r) >> 24U) & 0x1U)
#define nvl_intr_minion_ltssm_fault_f(v) (((v)&0x1U) << 28U) #define nvl_intr_minion_ltssm_fault_f(v) ((U32(v) & 0x1U) << 28U)
#define nvl_intr_minion_ltssm_fault_m() (U32(0x1U) << 28U) #define nvl_intr_minion_ltssm_fault_m() (U32(0x1U) << 28U)
#define nvl_intr_minion_ltssm_fault_v(r) (((r) >> 28U) & 0x1U) #define nvl_intr_minion_ltssm_fault_v(r) (((r) >> 28U) & 0x1U)
#define nvl_intr_minion_ltssm_protocol_f(v) (((v)&0x1U) << 29U) #define nvl_intr_minion_ltssm_protocol_f(v) ((U32(v) & 0x1U) << 29U)
#define nvl_intr_minion_ltssm_protocol_m() (U32(0x1U) << 29U) #define nvl_intr_minion_ltssm_protocol_m() (U32(0x1U) << 29U)
#define nvl_intr_minion_ltssm_protocol_v(r) (((r) >> 29U) & 0x1U) #define nvl_intr_minion_ltssm_protocol_v(r) (((r) >> 29U) & 0x1U)
#define nvl_intr_minion_minion_request_f(v) (((v)&0x1U) << 30U) #define nvl_intr_minion_minion_request_f(v) ((U32(v) & 0x1U) << 30U)
#define nvl_intr_minion_minion_request_m() (U32(0x1U) << 30U) #define nvl_intr_minion_minion_request_m() (U32(0x1U) << 30U)
#define nvl_intr_minion_minion_request_v(r) (((r) >> 30U) & 0x1U) #define nvl_intr_minion_minion_request_v(r) (((r) >> 30U) & 0x1U)
#define nvl_intr_nonstall_en_r() (0x0000005cU) #define nvl_intr_nonstall_en_r() (0x0000005cU)
#define nvl_intr_stall_en_r() (0x00000058U) #define nvl_intr_stall_en_r() (0x00000058U)
#define nvl_intr_stall_en_tx_replay_f(v) (((v)&0x1U) << 0U) #define nvl_intr_stall_en_tx_replay_f(v) ((U32(v) & 0x1U) << 0U)
#define nvl_intr_stall_en_tx_replay_m() (U32(0x1U) << 0U) #define nvl_intr_stall_en_tx_replay_m() (U32(0x1U) << 0U)
#define nvl_intr_stall_en_tx_replay_v(r) (((r) >> 0U) & 0x1U) #define nvl_intr_stall_en_tx_replay_v(r) (((r) >> 0U) & 0x1U)
#define nvl_intr_stall_en_tx_recovery_short_f(v) (((v)&0x1U) << 1U) #define nvl_intr_stall_en_tx_recovery_short_f(v) ((U32(v) & 0x1U) << 1U)
#define nvl_intr_stall_en_tx_recovery_short_m() (U32(0x1U) << 1U) #define nvl_intr_stall_en_tx_recovery_short_m() (U32(0x1U) << 1U)
#define nvl_intr_stall_en_tx_recovery_short_v(r) (((r) >> 1U) & 0x1U) #define nvl_intr_stall_en_tx_recovery_short_v(r) (((r) >> 1U) & 0x1U)
#define nvl_intr_stall_en_tx_recovery_short_enable_v() (0x00000001U) #define nvl_intr_stall_en_tx_recovery_short_enable_v() (0x00000001U)
#define nvl_intr_stall_en_tx_recovery_short_enable_f() (0x2U) #define nvl_intr_stall_en_tx_recovery_short_enable_f() (0x2U)
#define nvl_intr_stall_en_tx_recovery_long_f(v) (((v)&0x1U) << 2U) #define nvl_intr_stall_en_tx_recovery_long_f(v) ((U32(v) & 0x1U) << 2U)
#define nvl_intr_stall_en_tx_recovery_long_m() (U32(0x1U) << 2U) #define nvl_intr_stall_en_tx_recovery_long_m() (U32(0x1U) << 2U)
#define nvl_intr_stall_en_tx_recovery_long_v(r) (((r) >> 2U) & 0x1U) #define nvl_intr_stall_en_tx_recovery_long_v(r) (((r) >> 2U) & 0x1U)
#define nvl_intr_stall_en_tx_recovery_long_enable_v() (0x00000001U) #define nvl_intr_stall_en_tx_recovery_long_enable_v() (0x00000001U)
#define nvl_intr_stall_en_tx_recovery_long_enable_f() (0x4U) #define nvl_intr_stall_en_tx_recovery_long_enable_f() (0x4U)
#define nvl_intr_stall_en_tx_fault_ram_f(v) (((v)&0x1U) << 4U) #define nvl_intr_stall_en_tx_fault_ram_f(v) ((U32(v) & 0x1U) << 4U)
#define nvl_intr_stall_en_tx_fault_ram_m() (U32(0x1U) << 4U) #define nvl_intr_stall_en_tx_fault_ram_m() (U32(0x1U) << 4U)
#define nvl_intr_stall_en_tx_fault_ram_v(r) (((r) >> 4U) & 0x1U) #define nvl_intr_stall_en_tx_fault_ram_v(r) (((r) >> 4U) & 0x1U)
#define nvl_intr_stall_en_tx_fault_ram_enable_v() (0x00000001U) #define nvl_intr_stall_en_tx_fault_ram_enable_v() (0x00000001U)
#define nvl_intr_stall_en_tx_fault_ram_enable_f() (0x10U) #define nvl_intr_stall_en_tx_fault_ram_enable_f() (0x10U)
#define nvl_intr_stall_en_tx_fault_interface_f(v) (((v)&0x1U) << 5U) #define nvl_intr_stall_en_tx_fault_interface_f(v) ((U32(v) & 0x1U) << 5U)
#define nvl_intr_stall_en_tx_fault_interface_m() (U32(0x1U) << 5U) #define nvl_intr_stall_en_tx_fault_interface_m() (U32(0x1U) << 5U)
#define nvl_intr_stall_en_tx_fault_interface_v(r) (((r) >> 5U) & 0x1U) #define nvl_intr_stall_en_tx_fault_interface_v(r) (((r) >> 5U) & 0x1U)
#define nvl_intr_stall_en_tx_fault_interface_enable_v() (0x00000001U) #define nvl_intr_stall_en_tx_fault_interface_enable_v() (0x00000001U)
#define nvl_intr_stall_en_tx_fault_interface_enable_f() (0x20U) #define nvl_intr_stall_en_tx_fault_interface_enable_f() (0x20U)
#define nvl_intr_stall_en_tx_fault_sublink_change_f(v) (((v)&0x1U) << 8U) #define nvl_intr_stall_en_tx_fault_sublink_change_f(v) ((U32(v) & 0x1U) << 8U)
#define nvl_intr_stall_en_tx_fault_sublink_change_m() (U32(0x1U) << 8U) #define nvl_intr_stall_en_tx_fault_sublink_change_m() (U32(0x1U) << 8U)
#define nvl_intr_stall_en_tx_fault_sublink_change_v(r) (((r) >> 8U) & 0x1U) #define nvl_intr_stall_en_tx_fault_sublink_change_v(r) (((r) >> 8U) & 0x1U)
#define nvl_intr_stall_en_tx_fault_sublink_change_enable_v() (0x00000001U) #define nvl_intr_stall_en_tx_fault_sublink_change_enable_v() (0x00000001U)
#define nvl_intr_stall_en_tx_fault_sublink_change_enable_f() (0x100U) #define nvl_intr_stall_en_tx_fault_sublink_change_enable_f() (0x100U)
#define nvl_intr_stall_en_rx_fault_sublink_change_f(v) (((v)&0x1U) << 16U) #define nvl_intr_stall_en_rx_fault_sublink_change_f(v) ((U32(v) & 0x1U) << 16U)
#define nvl_intr_stall_en_rx_fault_sublink_change_m() (U32(0x1U) << 16U) #define nvl_intr_stall_en_rx_fault_sublink_change_m() (U32(0x1U) << 16U)
#define nvl_intr_stall_en_rx_fault_sublink_change_v(r) (((r) >> 16U) & 0x1U) #define nvl_intr_stall_en_rx_fault_sublink_change_v(r) (((r) >> 16U) & 0x1U)
#define nvl_intr_stall_en_rx_fault_sublink_change_enable_v() (0x00000001U) #define nvl_intr_stall_en_rx_fault_sublink_change_enable_v() (0x00000001U)
#define nvl_intr_stall_en_rx_fault_sublink_change_enable_f() (0x10000U) #define nvl_intr_stall_en_rx_fault_sublink_change_enable_f() (0x10000U)
#define nvl_intr_stall_en_rx_fault_dl_protocol_f(v) (((v)&0x1U) << 20U) #define nvl_intr_stall_en_rx_fault_dl_protocol_f(v) ((U32(v) & 0x1U) << 20U)
#define nvl_intr_stall_en_rx_fault_dl_protocol_m() (U32(0x1U) << 20U) #define nvl_intr_stall_en_rx_fault_dl_protocol_m() (U32(0x1U) << 20U)
#define nvl_intr_stall_en_rx_fault_dl_protocol_v(r) (((r) >> 20U) & 0x1U) #define nvl_intr_stall_en_rx_fault_dl_protocol_v(r) (((r) >> 20U) & 0x1U)
#define nvl_intr_stall_en_rx_fault_dl_protocol_enable_v() (0x00000001U) #define nvl_intr_stall_en_rx_fault_dl_protocol_enable_v() (0x00000001U)
#define nvl_intr_stall_en_rx_fault_dl_protocol_enable_f() (0x100000U) #define nvl_intr_stall_en_rx_fault_dl_protocol_enable_f() (0x100000U)
#define nvl_intr_stall_en_rx_short_error_rate_f(v) (((v)&0x1U) << 21U) #define nvl_intr_stall_en_rx_short_error_rate_f(v) ((U32(v) & 0x1U) << 21U)
#define nvl_intr_stall_en_rx_short_error_rate_m() (U32(0x1U) << 21U) #define nvl_intr_stall_en_rx_short_error_rate_m() (U32(0x1U) << 21U)
#define nvl_intr_stall_en_rx_short_error_rate_v(r) (((r) >> 21U) & 0x1U) #define nvl_intr_stall_en_rx_short_error_rate_v(r) (((r) >> 21U) & 0x1U)
#define nvl_intr_stall_en_rx_short_error_rate_enable_v() (0x00000001U) #define nvl_intr_stall_en_rx_short_error_rate_enable_v() (0x00000001U)
#define nvl_intr_stall_en_rx_short_error_rate_enable_f() (0x200000U) #define nvl_intr_stall_en_rx_short_error_rate_enable_f() (0x200000U)
#define nvl_intr_stall_en_rx_long_error_rate_f(v) (((v)&0x1U) << 22U) #define nvl_intr_stall_en_rx_long_error_rate_f(v) ((U32(v) & 0x1U) << 22U)
#define nvl_intr_stall_en_rx_long_error_rate_m() (U32(0x1U) << 22U) #define nvl_intr_stall_en_rx_long_error_rate_m() (U32(0x1U) << 22U)
#define nvl_intr_stall_en_rx_long_error_rate_v(r) (((r) >> 22U) & 0x1U) #define nvl_intr_stall_en_rx_long_error_rate_v(r) (((r) >> 22U) & 0x1U)
#define nvl_intr_stall_en_rx_long_error_rate_enable_v() (0x00000001U) #define nvl_intr_stall_en_rx_long_error_rate_enable_v() (0x00000001U)
#define nvl_intr_stall_en_rx_long_error_rate_enable_f() (0x400000U) #define nvl_intr_stall_en_rx_long_error_rate_enable_f() (0x400000U)
#define nvl_intr_stall_en_rx_ila_trigger_f(v) (((v)&0x1U) << 23U) #define nvl_intr_stall_en_rx_ila_trigger_f(v) ((U32(v) & 0x1U) << 23U)
#define nvl_intr_stall_en_rx_ila_trigger_m() (U32(0x1U) << 23U) #define nvl_intr_stall_en_rx_ila_trigger_m() (U32(0x1U) << 23U)
#define nvl_intr_stall_en_rx_ila_trigger_v(r) (((r) >> 23U) & 0x1U) #define nvl_intr_stall_en_rx_ila_trigger_v(r) (((r) >> 23U) & 0x1U)
#define nvl_intr_stall_en_rx_ila_trigger_enable_v() (0x00000001U) #define nvl_intr_stall_en_rx_ila_trigger_enable_v() (0x00000001U)
#define nvl_intr_stall_en_rx_ila_trigger_enable_f() (0x800000U) #define nvl_intr_stall_en_rx_ila_trigger_enable_f() (0x800000U)
#define nvl_intr_stall_en_rx_crc_counter_f(v) (((v)&0x1U) << 24U) #define nvl_intr_stall_en_rx_crc_counter_f(v) ((U32(v) & 0x1U) << 24U)
#define nvl_intr_stall_en_rx_crc_counter_m() (U32(0x1U) << 24U) #define nvl_intr_stall_en_rx_crc_counter_m() (U32(0x1U) << 24U)
#define nvl_intr_stall_en_rx_crc_counter_v(r) (((r) >> 24U) & 0x1U) #define nvl_intr_stall_en_rx_crc_counter_v(r) (((r) >> 24U) & 0x1U)
#define nvl_intr_stall_en_rx_crc_counter_enable_v() (0x00000001U) #define nvl_intr_stall_en_rx_crc_counter_enable_v() (0x00000001U)
#define nvl_intr_stall_en_rx_crc_counter_enable_f() (0x1000000U) #define nvl_intr_stall_en_rx_crc_counter_enable_f() (0x1000000U)
#define nvl_intr_stall_en_ltssm_fault_f(v) (((v)&0x1U) << 28U) #define nvl_intr_stall_en_ltssm_fault_f(v) ((U32(v) & 0x1U) << 28U)
#define nvl_intr_stall_en_ltssm_fault_m() (U32(0x1U) << 28U) #define nvl_intr_stall_en_ltssm_fault_m() (U32(0x1U) << 28U)
#define nvl_intr_stall_en_ltssm_fault_v(r) (((r) >> 28U) & 0x1U) #define nvl_intr_stall_en_ltssm_fault_v(r) (((r) >> 28U) & 0x1U)
#define nvl_intr_stall_en_ltssm_fault_enable_v() (0x00000001U) #define nvl_intr_stall_en_ltssm_fault_enable_v() (0x00000001U)
#define nvl_intr_stall_en_ltssm_fault_enable_f() (0x10000000U) #define nvl_intr_stall_en_ltssm_fault_enable_f() (0x10000000U)
#define nvl_intr_stall_en_ltssm_protocol_f(v) (((v)&0x1U) << 29U) #define nvl_intr_stall_en_ltssm_protocol_f(v) ((U32(v) & 0x1U) << 29U)
#define nvl_intr_stall_en_ltssm_protocol_m() (U32(0x1U) << 29U) #define nvl_intr_stall_en_ltssm_protocol_m() (U32(0x1U) << 29U)
#define nvl_intr_stall_en_ltssm_protocol_v(r) (((r) >> 29U) & 0x1U) #define nvl_intr_stall_en_ltssm_protocol_v(r) (((r) >> 29U) & 0x1U)
#define nvl_intr_stall_en_ltssm_protocol_enable_v() (0x00000001U) #define nvl_intr_stall_en_ltssm_protocol_enable_v() (0x00000001U)
#define nvl_intr_stall_en_ltssm_protocol_enable_f() (0x20000000U) #define nvl_intr_stall_en_ltssm_protocol_enable_f() (0x20000000U)
#define nvl_intr_stall_en_minion_request_f(v) (((v)&0x1U) << 30U) #define nvl_intr_stall_en_minion_request_f(v) ((U32(v) & 0x1U) << 30U)
#define nvl_intr_stall_en_minion_request_m() (U32(0x1U) << 30U) #define nvl_intr_stall_en_minion_request_m() (U32(0x1U) << 30U)
#define nvl_intr_stall_en_minion_request_v(r) (((r) >> 30U) & 0x1U) #define nvl_intr_stall_en_minion_request_v(r) (((r) >> 30U) & 0x1U)
#define nvl_intr_stall_en_minion_request_enable_v() (0x00000001U) #define nvl_intr_stall_en_minion_request_enable_v() (0x00000001U)
#define nvl_intr_stall_en_minion_request_enable_f() (0x40000000U) #define nvl_intr_stall_en_minion_request_enable_f() (0x40000000U)
#define nvl_br0_cfg_cal_r() (0x0000281cU) #define nvl_br0_cfg_cal_r() (0x0000281cU)
#define nvl_br0_cfg_cal_rxcal_f(v) (((v)&0x1U) << 0U) #define nvl_br0_cfg_cal_rxcal_f(v) ((U32(v) & 0x1U) << 0U)
#define nvl_br0_cfg_cal_rxcal_m() (U32(0x1U) << 0U) #define nvl_br0_cfg_cal_rxcal_m() (U32(0x1U) << 0U)
#define nvl_br0_cfg_cal_rxcal_v(r) (((r) >> 0U) & 0x1U) #define nvl_br0_cfg_cal_rxcal_v(r) (((r) >> 0U) & 0x1U)
#define nvl_br0_cfg_cal_rxcal_on_v() (0x00000001U) #define nvl_br0_cfg_cal_rxcal_on_v() (0x00000001U)
#define nvl_br0_cfg_cal_rxcal_on_f() (0x1U) #define nvl_br0_cfg_cal_rxcal_on_f() (0x1U)
#define nvl_br0_cfg_status_cal_r() (0x00002838U) #define nvl_br0_cfg_status_cal_r() (0x00002838U)
#define nvl_br0_cfg_status_cal_rxcal_done_f(v) (((v)&0x1U) << 2U) #define nvl_br0_cfg_status_cal_rxcal_done_f(v) ((U32(v) & 0x1U) << 2U)
#define nvl_br0_cfg_status_cal_rxcal_done_m() (U32(0x1U) << 2U) #define nvl_br0_cfg_status_cal_rxcal_done_m() (U32(0x1U) << 2U)
#define nvl_br0_cfg_status_cal_rxcal_done_v(r) (((r) >> 2U) & 0x1U) #define nvl_br0_cfg_status_cal_rxcal_done_v(r) (((r) >> 2U) & 0x1U)
#endif #endif

38
drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_nvlinkip_discovery_gv100.h
View File

@@ -59,18 +59,18 @@
#include <nvgpu/types.h> #include <nvgpu/types.h>
#include <nvgpu/safe_ops.h> #include <nvgpu/safe_ops.h>
#define nvlinkip_discovery_common_entry_f(v) (((v)&0x3U) << 0U) #define nvlinkip_discovery_common_entry_f(v) ((U32(v) & 0x3U) << 0U)
#define nvlinkip_discovery_common_entry_v(r) (((r) >> 0U) & 0x3U) #define nvlinkip_discovery_common_entry_v(r) (((r) >> 0U) & 0x3U)
#define nvlinkip_discovery_common_entry_invalid_v() (0x00000000U) #define nvlinkip_discovery_common_entry_invalid_v() (0x00000000U)
#define nvlinkip_discovery_common_entry_enum_v() (0x00000001U) #define nvlinkip_discovery_common_entry_enum_v() (0x00000001U)
#define nvlinkip_discovery_common_entry_data1_v() (0x00000002U) #define nvlinkip_discovery_common_entry_data1_v() (0x00000002U)
#define nvlinkip_discovery_common_entry_data2_v() (0x00000003U) #define nvlinkip_discovery_common_entry_data2_v() (0x00000003U)
#define nvlinkip_discovery_common_contents_f(v) (((v)&0x1fffffffU) << 2U) #define nvlinkip_discovery_common_contents_f(v) ((U32(v) & 0x1fffffffU) << 2U)
#define nvlinkip_discovery_common_contents_v(r) (((r) >> 2U) & 0x1fffffffU) #define nvlinkip_discovery_common_contents_v(r) (((r) >> 2U) & 0x1fffffffU)
#define nvlinkip_discovery_common_chain_f(v) (((v)&0x1U) << 31U) #define nvlinkip_discovery_common_chain_f(v) ((U32(v) & 0x1U) << 31U)
#define nvlinkip_discovery_common_chain_v(r) (((r) >> 31U) & 0x1U) #define nvlinkip_discovery_common_chain_v(r) (((r) >> 31U) & 0x1U)
#define nvlinkip_discovery_common_chain_enable_v() (0x00000001U) #define nvlinkip_discovery_common_chain_enable_v() (0x00000001U)
#define nvlinkip_discovery_common_device_f(v) (((v)&0x3fU) << 2U) #define nvlinkip_discovery_common_device_f(v) ((U32(v) & 0x3fU) << 2U)
#define nvlinkip_discovery_common_device_v(r) (((r) >> 2U) & 0x3fU) #define nvlinkip_discovery_common_device_v(r) (((r) >> 2U) & 0x3fU)
#define nvlinkip_discovery_common_device_invalid_v() (0x00000000U) #define nvlinkip_discovery_common_device_invalid_v() (0x00000000U)
#define nvlinkip_discovery_common_device_ioctrl_v() (0x00000001U) #define nvlinkip_discovery_common_device_ioctrl_v() (0x00000001U)
@@ -86,27 +86,27 @@
#define nvlinkip_discovery_common_device_ioctrlmif_multicast_v() (0x0000000aU) #define nvlinkip_discovery_common_device_ioctrlmif_multicast_v() (0x0000000aU)
#define nvlinkip_discovery_common_device_sioctrl_v() (0x0000000cU) #define nvlinkip_discovery_common_device_sioctrl_v() (0x0000000cU)
#define nvlinkip_discovery_common_device_tioctrl_v() (0x0000000dU) #define nvlinkip_discovery_common_device_tioctrl_v() (0x0000000dU)
#define nvlinkip_discovery_common_id_f(v) (((v)&0xffU) << 8U) #define nvlinkip_discovery_common_id_f(v) ((U32(v) & 0xffU) << 8U)
#define nvlinkip_discovery_common_id_v(r) (((r) >> 8U) & 0xffU) #define nvlinkip_discovery_common_id_v(r) (((r) >> 8U) & 0xffU)
#define nvlinkip_discovery_common_version_f(v) (((v)&0x7ffU) << 20U) #define nvlinkip_discovery_common_version_f(v) ((U32(v) & 0x7ffU) << 20U)
#define nvlinkip_discovery_common_version_v(r) (((r) >> 20U) & 0x7ffU) #define nvlinkip_discovery_common_version_v(r) (((r) >> 20U) & 0x7ffU)
#define nvlinkip_discovery_common_pri_base_f(v) (((v)&0xfffU) << 12U) #define nvlinkip_discovery_common_pri_base_f(v) ((U32(v) & 0xfffU) << 12U)
#define nvlinkip_discovery_common_pri_base_v(r) (((r) >> 12U) & 0xfffU) #define nvlinkip_discovery_common_pri_base_v(r) (((r) >> 12U) & 0xfffU)
#define nvlinkip_discovery_common_intr_f(v) (((v)&0x1fU) << 7U) #define nvlinkip_discovery_common_intr_f(v) ((U32(v) & 0x1fU) << 7U)
#define nvlinkip_discovery_common_intr_v(r) (((r) >> 7U) & 0x1fU) #define nvlinkip_discovery_common_intr_v(r) (((r) >> 7U) & 0x1fU)
#define nvlinkip_discovery_common_reset_f(v) (((v)&0x1fU) << 2U) #define nvlinkip_discovery_common_reset_f(v) ((U32(v) & 0x1fU) << 2U)
#define nvlinkip_discovery_common_reset_v(r) (((r) >> 2U) & 0x1fU) #define nvlinkip_discovery_common_reset_v(r) (((r) >> 2U) & 0x1fU)
#define nvlinkip_discovery_common_ioctrl_length_f(v) (((v)&0x3fU) << 24U) #define nvlinkip_discovery_common_ioctrl_length_f(v) ((U32(v) & 0x3fU) << 24U)
#define nvlinkip_discovery_common_ioctrl_length_v(r) (((r) >> 24U) & 0x3fU) #define nvlinkip_discovery_common_ioctrl_length_v(r) (((r) >> 24U) & 0x3fU)
#define nvlinkip_discovery_common_dlpl_num_tx_f(v) (((v)&0x7U) << 24U) #define nvlinkip_discovery_common_dlpl_num_tx_f(v) ((U32(v) & 0x7U) << 24U)
#define nvlinkip_discovery_common_dlpl_num_tx_v(r) (((r) >> 24U) & 0x7U) #define nvlinkip_discovery_common_dlpl_num_tx_v(r) (((r) >> 24U) & 0x7U)
#define nvlinkip_discovery_common_dlpl_num_rx_f(v) (((v)&0x7U) << 27U) #define nvlinkip_discovery_common_dlpl_num_rx_f(v) ((U32(v) & 0x7U) << 27U)
#define nvlinkip_discovery_common_dlpl_num_rx_v(r) (((r) >> 27U) & 0x7U) #define nvlinkip_discovery_common_dlpl_num_rx_v(r) (((r) >> 27U) & 0x7U)
#define nvlinkip_discovery_common_data1_ioctrl_length_f(v)\ #define nvlinkip_discovery_common_data1_ioctrl_length_f(v)\
(((v)&0x7ffffU) << 12U) ((U32(v) & 0x7ffffU) << 12U)
#define nvlinkip_discovery_common_data1_ioctrl_length_v(r)\ #define nvlinkip_discovery_common_data1_ioctrl_length_v(r)\
(((r) >> 12U) & 0x7ffffU) (((r) >> 12U) & 0x7ffffU)
#define nvlinkip_discovery_common_data2_type_f(v) (((v)&0x1fU) << 26U) #define nvlinkip_discovery_common_data2_type_f(v) ((U32(v) & 0x1fU) << 26U)
#define nvlinkip_discovery_common_data2_type_v(r) (((r) >> 26U) & 0x1fU) #define nvlinkip_discovery_common_data2_type_v(r) (((r) >> 26U) & 0x1fU)
#define nvlinkip_discovery_common_data2_type_invalid_v() (0x00000000U) #define nvlinkip_discovery_common_data2_type_invalid_v() (0x00000000U)
#define nvlinkip_discovery_common_data2_type_pllcontrol_v() (0x00000001U) #define nvlinkip_discovery_common_data2_type_pllcontrol_v() (0x00000001U)
@@ -115,12 +115,14 @@
#define nvlinkip_discovery_common_data2_type_discovery_v() (0x00000004U) #define nvlinkip_discovery_common_data2_type_discovery_v() (0x00000004U)
#define nvlinkip_discovery_common_data2_type_unicast_v() (0x00000005U) #define nvlinkip_discovery_common_data2_type_unicast_v() (0x00000005U)
#define nvlinkip_discovery_common_data2_type_broadcast_v() (0x00000006U) #define nvlinkip_discovery_common_data2_type_broadcast_v() (0x00000006U)
#define nvlinkip_discovery_common_data2_addr_f(v) (((v)&0xffffffU) << 2U) #define nvlinkip_discovery_common_data2_addr_f(v) ((U32(v) & 0xffffffU) << 2U)
#define nvlinkip_discovery_common_data2_addr_v(r) (((r) >> 2U) & 0xffffffU) #define nvlinkip_discovery_common_data2_addr_v(r) (((r) >> 2U) & 0xffffffU)
#define nvlinkip_discovery_common_dlpl_data2_type_f(v) (((v)&0x1fU) << 26U) #define nvlinkip_discovery_common_dlpl_data2_type_f(v) ((U32(v) & 0x1fU) << 26U)
#define nvlinkip_discovery_common_dlpl_data2_type_v(r) (((r) >> 26U) & 0x1fU) #define nvlinkip_discovery_common_dlpl_data2_type_v(r) (((r) >> 26U) & 0x1fU)
#define nvlinkip_discovery_common_dlpl_data2_master_f(v) (((v)&0x1U) << 15U) #define nvlinkip_discovery_common_dlpl_data2_master_f(v)\
((U32(v) & 0x1U) << 15U)
#define nvlinkip_discovery_common_dlpl_data2_master_v(r) (((r) >> 15U) & 0x1U) #define nvlinkip_discovery_common_dlpl_data2_master_v(r) (((r) >> 15U) & 0x1U)
#define nvlinkip_discovery_common_dlpl_data2_masterid_f(v) (((v)&0x7fU) << 8U) #define nvlinkip_discovery_common_dlpl_data2_masterid_f(v)\
((U32(v) & 0x7fU) << 8U)
#define nvlinkip_discovery_common_dlpl_data2_masterid_v(r) (((r) >> 8U) & 0x7fU) #define nvlinkip_discovery_common_dlpl_data2_masterid_v(r) (((r) >> 8U) & 0x7fU)
#endif #endif

39
drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_nvlipt_gv100.h
View File

@@ -60,36 +60,39 @@
#include <nvgpu/safe_ops.h> #include <nvgpu/safe_ops.h>
#define nvlipt_intr_control_link0_r() (0x000004b4U) #define nvlipt_intr_control_link0_r() (0x000004b4U)
#define nvlipt_intr_control_link0_stallenable_f(v) (((v)&0x1U) << 0U) #define nvlipt_intr_control_link0_stallenable_f(v) ((U32(v) & 0x1U) << 0U)
#define nvlipt_intr_control_link0_stallenable_m() (U32(0x1U) << 0U) #define nvlipt_intr_control_link0_stallenable_m() (U32(0x1U) << 0U)
#define nvlipt_intr_control_link0_stallenable_v(r) (((r) >> 0U) & 0x1U) #define nvlipt_intr_control_link0_stallenable_v(r) (((r) >> 0U) & 0x1U)
#define nvlipt_intr_control_link0_nostallenable_f(v) (((v)&0x1U) << 1U) #define nvlipt_intr_control_link0_nostallenable_f(v) ((U32(v) & 0x1U) << 1U)
#define nvlipt_intr_control_link0_nostallenable_m() (U32(0x1U) << 1U) #define nvlipt_intr_control_link0_nostallenable_m() (U32(0x1U) << 1U)
#define nvlipt_intr_control_link0_nostallenable_v(r) (((r) >> 1U) & 0x1U) #define nvlipt_intr_control_link0_nostallenable_v(r) (((r) >> 1U) & 0x1U)
#define nvlipt_err_uc_status_link0_r() (0x00000524U) #define nvlipt_err_uc_status_link0_r() (0x00000524U)
#define nvlipt_err_uc_status_link0_dlprotocol_f(v) (((v)&0x1U) << 4U) #define nvlipt_err_uc_status_link0_dlprotocol_f(v) ((U32(v) & 0x1U) << 4U)
#define nvlipt_err_uc_status_link0_dlprotocol_v(r) (((r) >> 4U) & 0x1U) #define nvlipt_err_uc_status_link0_dlprotocol_v(r) (((r) >> 4U) & 0x1U)
#define nvlipt_err_uc_status_link0_datapoisoned_f(v) (((v)&0x1U) << 12U) #define nvlipt_err_uc_status_link0_datapoisoned_f(v) ((U32(v) & 0x1U) << 12U)
#define nvlipt_err_uc_status_link0_datapoisoned_v(r) (((r) >> 12U) & 0x1U) #define nvlipt_err_uc_status_link0_datapoisoned_v(r) (((r) >> 12U) & 0x1U)
#define nvlipt_err_uc_status_link0_flowcontrol_f(v) (((v)&0x1U) << 13U) #define nvlipt_err_uc_status_link0_flowcontrol_f(v) ((U32(v) & 0x1U) << 13U)
#define nvlipt_err_uc_status_link0_flowcontrol_v(r) (((r) >> 13U) & 0x1U) #define nvlipt_err_uc_status_link0_flowcontrol_v(r) (((r) >> 13U) & 0x1U)
#define nvlipt_err_uc_status_link0_responsetimeout_f(v) (((v)&0x1U) << 14U) #define nvlipt_err_uc_status_link0_responsetimeout_f(v) ((U32(v) & 0x1U) << 14U)
#define nvlipt_err_uc_status_link0_responsetimeout_v(r) (((r) >> 14U) & 0x1U) #define nvlipt_err_uc_status_link0_responsetimeout_v(r) (((r) >> 14U) & 0x1U)
#define nvlipt_err_uc_status_link0_targeterror_f(v) (((v)&0x1U) << 15U) #define nvlipt_err_uc_status_link0_targeterror_f(v) ((U32(v) & 0x1U) << 15U)
#define nvlipt_err_uc_status_link0_targeterror_v(r) (((r) >> 15U) & 0x1U) #define nvlipt_err_uc_status_link0_targeterror_v(r) (((r) >> 15U) & 0x1U)
#define nvlipt_err_uc_status_link0_unexpectedresponse_f(v) (((v)&0x1U) << 16U) #define nvlipt_err_uc_status_link0_unexpectedresponse_f(v)\
((U32(v) & 0x1U) << 16U)
#define nvlipt_err_uc_status_link0_unexpectedresponse_v(r) (((r) >> 16U) & 0x1U) #define nvlipt_err_uc_status_link0_unexpectedresponse_v(r) (((r) >> 16U) & 0x1U)
#define nvlipt_err_uc_status_link0_receiveroverflow_f(v) (((v)&0x1U) << 17U) #define nvlipt_err_uc_status_link0_receiveroverflow_f(v)\
((U32(v) & 0x1U) << 17U)
#define nvlipt_err_uc_status_link0_receiveroverflow_v(r) (((r) >> 17U) & 0x1U) #define nvlipt_err_uc_status_link0_receiveroverflow_v(r) (((r) >> 17U) & 0x1U)
#define nvlipt_err_uc_status_link0_malformedpacket_f(v) (((v)&0x1U) << 18U) #define nvlipt_err_uc_status_link0_malformedpacket_f(v) ((U32(v) & 0x1U) << 18U)
#define nvlipt_err_uc_status_link0_malformedpacket_v(r) (((r) >> 18U) & 0x1U) #define nvlipt_err_uc_status_link0_malformedpacket_v(r) (((r) >> 18U) & 0x1U)
#define nvlipt_err_uc_status_link0_stompedpacketreceived_f(v)\ #define nvlipt_err_uc_status_link0_stompedpacketreceived_f(v)\
(((v)&0x1U) << 19U) ((U32(v) & 0x1U) << 19U)
#define nvlipt_err_uc_status_link0_stompedpacketreceived_v(r)\ #define nvlipt_err_uc_status_link0_stompedpacketreceived_v(r)\
(((r) >> 19U) & 0x1U) (((r) >> 19U) & 0x1U)
#define nvlipt_err_uc_status_link0_unsupportedrequest_f(v) (((v)&0x1U) << 20U) #define nvlipt_err_uc_status_link0_unsupportedrequest_f(v)\
((U32(v) & 0x1U) << 20U)
#define nvlipt_err_uc_status_link0_unsupportedrequest_v(r) (((r) >> 20U) & 0x1U) #define nvlipt_err_uc_status_link0_unsupportedrequest_v(r) (((r) >> 20U) & 0x1U)
#define nvlipt_err_uc_status_link0_ucinternal_f(v) (((v)&0x1U) << 22U) #define nvlipt_err_uc_status_link0_ucinternal_f(v) ((U32(v) & 0x1U) << 22U)
#define nvlipt_err_uc_status_link0_ucinternal_v(r) (((r) >> 22U) & 0x1U) #define nvlipt_err_uc_status_link0_ucinternal_v(r) (((r) >> 22U) & 0x1U)
#define nvlipt_err_uc_mask_link0_r() (0x00000528U) #define nvlipt_err_uc_mask_link0_r() (0x00000528U)
#define nvlipt_err_uc_severity_link0_r() (0x0000052cU) #define nvlipt_err_uc_severity_link0_r() (0x0000052cU)
@@ -99,21 +102,21 @@
#define nvlipt_err_c_mask_link0_r() (0x0000053cU) #define nvlipt_err_c_mask_link0_r() (0x0000053cU)
#define nvlipt_err_c_first_link0_r() (0x00000540U) #define nvlipt_err_c_first_link0_r() (0x00000540U)
#define nvlipt_err_control_link0_r() (0x00000544U) #define nvlipt_err_control_link0_r() (0x00000544U)
#define nvlipt_err_control_link0_fatalenable_f(v) (((v)&0x1U) << 1U) #define nvlipt_err_control_link0_fatalenable_f(v) ((U32(v) & 0x1U) << 1U)
#define nvlipt_err_control_link0_fatalenable_m() (U32(0x1U) << 1U) #define nvlipt_err_control_link0_fatalenable_m() (U32(0x1U) << 1U)
#define nvlipt_err_control_link0_fatalenable_v(r) (((r) >> 1U) & 0x1U) #define nvlipt_err_control_link0_fatalenable_v(r) (((r) >> 1U) & 0x1U)
#define nvlipt_err_control_link0_nonfatalenable_f(v) (((v)&0x1U) << 2U) #define nvlipt_err_control_link0_nonfatalenable_f(v) ((U32(v) & 0x1U) << 2U)
#define nvlipt_err_control_link0_nonfatalenable_m() (U32(0x1U) << 2U) #define nvlipt_err_control_link0_nonfatalenable_m() (U32(0x1U) << 2U)
#define nvlipt_err_control_link0_nonfatalenable_v(r) (((r) >> 2U) & 0x1U) #define nvlipt_err_control_link0_nonfatalenable_v(r) (((r) >> 2U) & 0x1U)
#define nvlipt_intr_control_common_r() (0x000004b0U) #define nvlipt_intr_control_common_r() (0x000004b0U)
#define nvlipt_intr_control_common_stallenable_f(v) (((v)&0x1U) << 0U) #define nvlipt_intr_control_common_stallenable_f(v) ((U32(v) & 0x1U) << 0U)
#define nvlipt_intr_control_common_stallenable_m() (U32(0x1U) << 0U) #define nvlipt_intr_control_common_stallenable_m() (U32(0x1U) << 0U)
#define nvlipt_intr_control_common_stallenable_v(r) (((r) >> 0U) & 0x1U) #define nvlipt_intr_control_common_stallenable_v(r) (((r) >> 0U) & 0x1U)
#define nvlipt_intr_control_common_nonstallenable_f(v) (((v)&0x1U) << 1U) #define nvlipt_intr_control_common_nonstallenable_f(v) ((U32(v) & 0x1U) << 1U)
#define nvlipt_intr_control_common_nonstallenable_m() (U32(0x1U) << 1U) #define nvlipt_intr_control_common_nonstallenable_m() (U32(0x1U) << 1U)
#define nvlipt_intr_control_common_nonstallenable_v(r) (((r) >> 1U) & 0x1U) #define nvlipt_intr_control_common_nonstallenable_v(r) (((r) >> 1U) & 0x1U)
#define nvlipt_scratch_cold_r() (0x000007d4U) #define nvlipt_scratch_cold_r() (0x000007d4U)
#define nvlipt_scratch_cold_data_f(v) (((v)&0xffffffffU) << 0U) #define nvlipt_scratch_cold_data_f(v) ((U32(v) & 0xffffffffU) << 0U)
#define nvlipt_scratch_cold_data_v(r) (((r) >> 0U) & 0xffffffffU) #define nvlipt_scratch_cold_data_v(r) (((r) >> 0U) & 0xffffffffU)
#define nvlipt_scratch_cold_data_init_v() (0xdeadbaadU) #define nvlipt_scratch_cold_data_init_v() (0xdeadbaadU)
#endif #endif

22
drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_pbdma_gv100.h
View File

@@ -61,17 +61,17 @@
#define pbdma_gp_entry1_r() (0x10000004U) #define pbdma_gp_entry1_r() (0x10000004U)
#define pbdma_gp_entry1_get_hi_v(r) (((r) >> 0U) & 0xffU) #define pbdma_gp_entry1_get_hi_v(r) (((r) >> 0U) & 0xffU)
#define pbdma_gp_entry1_length_f(v) (((v)&0x1fffffU) << 10U) #define pbdma_gp_entry1_length_f(v) ((U32(v) & 0x1fffffU) << 10U)
#define pbdma_gp_entry1_length_v(r) (((r) >> 10U) & 0x1fffffU) #define pbdma_gp_entry1_length_v(r) (((r) >> 10U) & 0x1fffffU)
#define pbdma_gp_base_r(i)\ #define pbdma_gp_base_r(i)\
(nvgpu_safe_add_u32(0x00040048U, nvgpu_safe_mult_u32((i), 8192U))) (nvgpu_safe_add_u32(0x00040048U, nvgpu_safe_mult_u32((i), 8192U)))
#define pbdma_gp_base__size_1_v() (0x0000000eU) #define pbdma_gp_base__size_1_v() (0x0000000eU)
#define pbdma_gp_base_offset_f(v) (((v)&0x1fffffffU) << 3U) #define pbdma_gp_base_offset_f(v) ((U32(v) & 0x1fffffffU) << 3U)
#define pbdma_gp_base_rsvd_s() (3U) #define pbdma_gp_base_rsvd_s() (3U)
#define pbdma_gp_base_hi_r(i)\ #define pbdma_gp_base_hi_r(i)\
(nvgpu_safe_add_u32(0x0004004cU, nvgpu_safe_mult_u32((i), 8192U))) (nvgpu_safe_add_u32(0x0004004cU, nvgpu_safe_mult_u32((i), 8192U)))
#define pbdma_gp_base_hi_offset_f(v) (((v)&0xffU) << 0U) #define pbdma_gp_base_hi_offset_f(v) ((U32(v) & 0xffU) << 0U)
#define pbdma_gp_base_hi_limit2_f(v) (((v)&0x1fU) << 16U) #define pbdma_gp_base_hi_limit2_f(v) ((U32(v) & 0x1fU) << 16U)
#define pbdma_gp_fetch_r(i)\ #define pbdma_gp_fetch_r(i)\
(nvgpu_safe_add_u32(0x00040050U, nvgpu_safe_mult_u32((i), 8192U))) (nvgpu_safe_add_u32(0x00040050U, nvgpu_safe_mult_u32((i), 8192U)))
#define pbdma_gp_get_r(i)\ #define pbdma_gp_get_r(i)\
@@ -107,13 +107,13 @@
(nvgpu_safe_add_u32(0x00040114U, nvgpu_safe_mult_u32((i), 8192U))) (nvgpu_safe_add_u32(0x00040114U, nvgpu_safe_mult_u32((i), 8192U)))
#define pbdma_subdevice_r(i)\ #define pbdma_subdevice_r(i)\
(nvgpu_safe_add_u32(0x00040094U, nvgpu_safe_mult_u32((i), 8192U))) (nvgpu_safe_add_u32(0x00040094U, nvgpu_safe_mult_u32((i), 8192U)))
#define pbdma_subdevice_id_f(v) (((v)&0xfffU) << 0U) #define pbdma_subdevice_id_f(v) ((U32(v) & 0xfffU) << 0U)
#define pbdma_subdevice_status_active_f() (0x10000000U) #define pbdma_subdevice_status_active_f() (0x10000000U)
#define pbdma_subdevice_channel_dma_enable_f() (0x20000000U) #define pbdma_subdevice_channel_dma_enable_f() (0x20000000U)
#define pbdma_method0_r(i)\ #define pbdma_method0_r(i)\
(nvgpu_safe_add_u32(0x000400c0U, nvgpu_safe_mult_u32((i), 8192U))) (nvgpu_safe_add_u32(0x000400c0U, nvgpu_safe_mult_u32((i), 8192U)))
#define pbdma_method0_fifo_size_v() (0x00000004U) #define pbdma_method0_fifo_size_v() (0x00000004U)
#define pbdma_method0_addr_f(v) (((v)&0xfffU) << 2U) #define pbdma_method0_addr_f(v) ((U32(v) & 0xfffU) << 2U)
#define pbdma_method0_addr_v(r) (((r) >> 2U) & 0xfffU) #define pbdma_method0_addr_v(r) (((r) >> 2U) & 0xfffU)
#define pbdma_method0_subch_v(r) (((r) >> 16U) & 0x7U) #define pbdma_method0_subch_v(r) (((r) >> 16U) & 0x7U)
#define pbdma_method0_first_true_f() (0x400000U) #define pbdma_method0_first_true_f() (0x400000U)
@@ -130,10 +130,10 @@
(nvgpu_safe_add_u32(0x00040030U, nvgpu_safe_mult_u32((i), 8192U))) (nvgpu_safe_add_u32(0x00040030U, nvgpu_safe_mult_u32((i), 8192U)))
#define pbdma_acquire_retry_man_2_f() (0x2U) #define pbdma_acquire_retry_man_2_f() (0x2U)
#define pbdma_acquire_retry_exp_2_f() (0x100U) #define pbdma_acquire_retry_exp_2_f() (0x100U)
#define pbdma_acquire_timeout_exp_f(v) (((v)&0xfU) << 11U) #define pbdma_acquire_timeout_exp_f(v) ((U32(v) & 0xfU) << 11U)
#define pbdma_acquire_timeout_exp_max_v() (0x0000000fU) #define pbdma_acquire_timeout_exp_max_v() (0x0000000fU)
#define pbdma_acquire_timeout_exp_max_f() (0x7800U) #define pbdma_acquire_timeout_exp_max_f() (0x7800U)
#define pbdma_acquire_timeout_man_f(v) (((v)&0xffffU) << 15U) #define pbdma_acquire_timeout_man_f(v) ((U32(v) & 0xffffU) << 15U)
#define pbdma_acquire_timeout_man_max_v() (0x0000ffffU) #define pbdma_acquire_timeout_man_max_v() (0x0000ffffU)
#define pbdma_acquire_timeout_man_max_f() (0x7fff8000U) #define pbdma_acquire_timeout_man_max_f() (0x7fff8000U)
#define pbdma_acquire_timeout_en_enable_f() (0x80000000U) #define pbdma_acquire_timeout_en_enable_f() (0x80000000U)
@@ -151,7 +151,7 @@
#define pbdma_userd_target_vid_mem_f() (0x0U) #define pbdma_userd_target_vid_mem_f() (0x0U)
#define pbdma_userd_target_sys_mem_coh_f() (0x2U) #define pbdma_userd_target_sys_mem_coh_f() (0x2U)
#define pbdma_userd_target_sys_mem_ncoh_f() (0x3U) #define pbdma_userd_target_sys_mem_ncoh_f() (0x3U)
#define pbdma_userd_addr_f(v) (((v)&0x7fffffU) << 9U) #define pbdma_userd_addr_f(v) ((U32(v) & 0x7fffffU) << 9U)
#define pbdma_config_r(i)\ #define pbdma_config_r(i)\
(nvgpu_safe_add_u32(0x000400f4U, nvgpu_safe_mult_u32((i), 8192U))) (nvgpu_safe_add_u32(0x000400f4U, nvgpu_safe_mult_u32((i), 8192U)))
#define pbdma_config_l2_evict_first_f() (0x0U) #define pbdma_config_l2_evict_first_f() (0x0U)
@@ -164,7 +164,7 @@
#define pbdma_config_userd_writeback_enable_f() (0x1000U) #define pbdma_config_userd_writeback_enable_f() (0x1000U)
#define pbdma_userd_hi_r(i)\ #define pbdma_userd_hi_r(i)\
(nvgpu_safe_add_u32(0x0004000cU, nvgpu_safe_mult_u32((i), 8192U))) (nvgpu_safe_add_u32(0x0004000cU, nvgpu_safe_mult_u32((i), 8192U)))
#define pbdma_userd_hi_addr_f(v) (((v)&0xffU) << 0U) #define pbdma_userd_hi_addr_f(v) ((U32(v) & 0xffU) << 0U)
#define pbdma_hce_ctrl_r(i)\ #define pbdma_hce_ctrl_r(i)\
(nvgpu_safe_add_u32(0x000400e4U, nvgpu_safe_mult_u32((i), 8192U))) (nvgpu_safe_add_u32(0x000400e4U, nvgpu_safe_mult_u32((i), 8192U)))
#define pbdma_hce_ctrl_hce_priv_mode_yes_f() (0x20U) #define pbdma_hce_ctrl_hce_priv_mode_yes_f() (0x20U)
@@ -242,7 +242,7 @@
#define pbdma_target_needs_host_tsg_event_false_f() (0x0U) #define pbdma_target_needs_host_tsg_event_false_f() (0x0U)
#define pbdma_set_channel_info_r(i)\ #define pbdma_set_channel_info_r(i)\
(nvgpu_safe_add_u32(0x000400fcU, nvgpu_safe_mult_u32((i), 8192U))) (nvgpu_safe_add_u32(0x000400fcU, nvgpu_safe_mult_u32((i), 8192U)))
#define pbdma_set_channel_info_veid_f(v) (((v)&0x3fU) << 8U) #define pbdma_set_channel_info_veid_f(v) ((U32(v) & 0x3fU) << 8U)
#define pbdma_timeout_r(i)\ #define pbdma_timeout_r(i)\
(nvgpu_safe_add_u32(0x0004012cU, nvgpu_safe_mult_u32((i), 8192U))) (nvgpu_safe_add_u32(0x0004012cU, nvgpu_safe_mult_u32((i), 8192U)))
#define pbdma_timeout_period_m() (U32(0xffffffffU) << 0U) #define pbdma_timeout_period_m() (U32(0xffffffffU) << 0U)

20
drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_perf_gv100.h
View File

@@ -70,13 +70,13 @@
#define perf_pmasys_control_membuf_status_v(r) (((r) >> 4U) & 0x1U) #define perf_pmasys_control_membuf_status_v(r) (((r) >> 4U) & 0x1U)
#define perf_pmasys_control_membuf_status_overflowed_v() (0x00000001U) #define perf_pmasys_control_membuf_status_overflowed_v() (0x00000001U)
#define perf_pmasys_control_membuf_status_overflowed_f() (0x10U) #define perf_pmasys_control_membuf_status_overflowed_f() (0x10U)
#define perf_pmasys_control_membuf_clear_status_f(v) (((v)&0x1U) << 5U) #define perf_pmasys_control_membuf_clear_status_f(v) ((U32(v) & 0x1U) << 5U)
#define perf_pmasys_control_membuf_clear_status_v(r) (((r) >> 5U) & 0x1U) #define perf_pmasys_control_membuf_clear_status_v(r) (((r) >> 5U) & 0x1U)
#define perf_pmasys_control_membuf_clear_status_doit_v() (0x00000001U) #define perf_pmasys_control_membuf_clear_status_doit_v() (0x00000001U)
#define perf_pmasys_control_membuf_clear_status_doit_f() (0x20U) #define perf_pmasys_control_membuf_clear_status_doit_f() (0x20U)
#define perf_pmasys_mem_block_r() (0x0024a070U) #define perf_pmasys_mem_block_r() (0x0024a070U)
#define perf_pmasys_mem_block_base_f(v) (((v)&0xfffffffU) << 0U) #define perf_pmasys_mem_block_base_f(v) ((U32(v) & 0xfffffffU) << 0U)
#define perf_pmasys_mem_block_target_f(v) (((v)&0x3U) << 28U) #define perf_pmasys_mem_block_target_f(v) ((U32(v) & 0x3U) << 28U)
#define perf_pmasys_mem_block_target_v(r) (((r) >> 28U) & 0x3U) #define perf_pmasys_mem_block_target_v(r) (((r) >> 28U) & 0x3U)
#define perf_pmasys_mem_block_target_lfb_v() (0x00000000U) #define perf_pmasys_mem_block_target_lfb_v() (0x00000000U)
#define perf_pmasys_mem_block_target_lfb_f() (0x0U) #define perf_pmasys_mem_block_target_lfb_f() (0x0U)
@@ -84,24 +84,24 @@
#define perf_pmasys_mem_block_target_sys_coh_f() (0x20000000U) #define perf_pmasys_mem_block_target_sys_coh_f() (0x20000000U)
#define perf_pmasys_mem_block_target_sys_ncoh_v() (0x00000003U) #define perf_pmasys_mem_block_target_sys_ncoh_v() (0x00000003U)
#define perf_pmasys_mem_block_target_sys_ncoh_f() (0x30000000U) #define perf_pmasys_mem_block_target_sys_ncoh_f() (0x30000000U)
#define perf_pmasys_mem_block_valid_f(v) (((v)&0x1U) << 31U) #define perf_pmasys_mem_block_valid_f(v) ((U32(v) & 0x1U) << 31U)
#define perf_pmasys_mem_block_valid_v(r) (((r) >> 31U) & 0x1U) #define perf_pmasys_mem_block_valid_v(r) (((r) >> 31U) & 0x1U)
#define perf_pmasys_mem_block_valid_true_v() (0x00000001U) #define perf_pmasys_mem_block_valid_true_v() (0x00000001U)
#define perf_pmasys_mem_block_valid_true_f() (0x80000000U) #define perf_pmasys_mem_block_valid_true_f() (0x80000000U)
#define perf_pmasys_mem_block_valid_false_v() (0x00000000U) #define perf_pmasys_mem_block_valid_false_v() (0x00000000U)
#define perf_pmasys_mem_block_valid_false_f() (0x0U) #define perf_pmasys_mem_block_valid_false_f() (0x0U)
#define perf_pmasys_outbase_r() (0x0024a074U) #define perf_pmasys_outbase_r() (0x0024a074U)
#define perf_pmasys_outbase_ptr_f(v) (((v)&0x7ffffffU) << 5U) #define perf_pmasys_outbase_ptr_f(v) ((U32(v) & 0x7ffffffU) << 5U)
#define perf_pmasys_outbaseupper_r() (0x0024a078U) #define perf_pmasys_outbaseupper_r() (0x0024a078U)
#define perf_pmasys_outbaseupper_ptr_f(v) (((v)&0xffU) << 0U) #define perf_pmasys_outbaseupper_ptr_f(v) ((U32(v) & 0xffU) << 0U)
#define perf_pmasys_outsize_r() (0x0024a07cU) #define perf_pmasys_outsize_r() (0x0024a07cU)
#define perf_pmasys_outsize_numbytes_f(v) (((v)&0x7ffffffU) << 5U) #define perf_pmasys_outsize_numbytes_f(v) ((U32(v) & 0x7ffffffU) << 5U)
#define perf_pmasys_mem_bytes_r() (0x0024a084U) #define perf_pmasys_mem_bytes_r() (0x0024a084U)
#define perf_pmasys_mem_bytes_numbytes_f(v) (((v)&0xfffffffU) << 4U) #define perf_pmasys_mem_bytes_numbytes_f(v) ((U32(v) & 0xfffffffU) << 4U)
#define perf_pmasys_mem_bump_r() (0x0024a088U) #define perf_pmasys_mem_bump_r() (0x0024a088U)
#define perf_pmasys_mem_bump_numbytes_f(v) (((v)&0xfffffffU) << 4U) #define perf_pmasys_mem_bump_numbytes_f(v) ((U32(v) & 0xfffffffU) << 4U)
#define perf_pmasys_enginestatus_r() (0x0024a0a4U) #define perf_pmasys_enginestatus_r() (0x0024a0a4U)
#define perf_pmasys_enginestatus_rbufempty_f(v) (((v)&0x1U) << 4U) #define perf_pmasys_enginestatus_rbufempty_f(v) ((U32(v) & 0x1U) << 4U)
#define perf_pmasys_enginestatus_rbufempty_empty_v() (0x00000001U) #define perf_pmasys_enginestatus_rbufempty_empty_v() (0x00000001U)
#define perf_pmasys_enginestatus_rbufempty_empty_f() (0x10U) #define perf_pmasys_enginestatus_rbufempty_empty_f() (0x10U)
#define perf_pmmsys_engine_sel_r(i)\ #define perf_pmmsys_engine_sel_r(i)\

116
drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_pgsp_gv100.h
View File

@@ -68,51 +68,51 @@
#define pgsp_falcon_irqstat_swgen0_true_f() (0x40U) #define pgsp_falcon_irqstat_swgen0_true_f() (0x40U)
#define pgsp_falcon_irqmode_r() (0x0011000cU) #define pgsp_falcon_irqmode_r() (0x0011000cU)
#define pgsp_falcon_irqmset_r() (0x00110010U) #define pgsp_falcon_irqmset_r() (0x00110010U)
#define pgsp_falcon_irqmset_gptmr_f(v) (((v)&0x1U) << 0U) #define pgsp_falcon_irqmset_gptmr_f(v) ((U32(v) & 0x1U) << 0U)
#define pgsp_falcon_irqmset_wdtmr_f(v) (((v)&0x1U) << 1U) #define pgsp_falcon_irqmset_wdtmr_f(v) ((U32(v) & 0x1U) << 1U)
#define pgsp_falcon_irqmset_mthd_f(v) (((v)&0x1U) << 2U) #define pgsp_falcon_irqmset_mthd_f(v) ((U32(v) & 0x1U) << 2U)
#define pgsp_falcon_irqmset_ctxsw_f(v) (((v)&0x1U) << 3U) #define pgsp_falcon_irqmset_ctxsw_f(v) ((U32(v) & 0x1U) << 3U)
#define pgsp_falcon_irqmset_halt_f(v) (((v)&0x1U) << 4U) #define pgsp_falcon_irqmset_halt_f(v) ((U32(v) & 0x1U) << 4U)
#define pgsp_falcon_irqmset_exterr_f(v) (((v)&0x1U) << 5U) #define pgsp_falcon_irqmset_exterr_f(v) ((U32(v) & 0x1U) << 5U)
#define pgsp_falcon_irqmset_swgen0_f(v) (((v)&0x1U) << 6U) #define pgsp_falcon_irqmset_swgen0_f(v) ((U32(v) & 0x1U) << 6U)
#define pgsp_falcon_irqmset_swgen1_f(v) (((v)&0x1U) << 7U) #define pgsp_falcon_irqmset_swgen1_f(v) ((U32(v) & 0x1U) << 7U)
#define pgsp_falcon_irqmclr_r() (0x00110014U) #define pgsp_falcon_irqmclr_r() (0x00110014U)
#define pgsp_falcon_irqmclr_gptmr_f(v) (((v)&0x1U) << 0U) #define pgsp_falcon_irqmclr_gptmr_f(v) ((U32(v) & 0x1U) << 0U)
#define pgsp_falcon_irqmclr_wdtmr_f(v) (((v)&0x1U) << 1U) #define pgsp_falcon_irqmclr_wdtmr_f(v) ((U32(v) & 0x1U) << 1U)
#define pgsp_falcon_irqmclr_mthd_f(v) (((v)&0x1U) << 2U) #define pgsp_falcon_irqmclr_mthd_f(v) ((U32(v) & 0x1U) << 2U)
#define pgsp_falcon_irqmclr_ctxsw_f(v) (((v)&0x1U) << 3U) #define pgsp_falcon_irqmclr_ctxsw_f(v) ((U32(v) & 0x1U) << 3U)
#define pgsp_falcon_irqmclr_halt_f(v) (((v)&0x1U) << 4U) #define pgsp_falcon_irqmclr_halt_f(v) ((U32(v) & 0x1U) << 4U)
#define pgsp_falcon_irqmclr_exterr_f(v) (((v)&0x1U) << 5U) #define pgsp_falcon_irqmclr_exterr_f(v) ((U32(v) & 0x1U) << 5U)
#define pgsp_falcon_irqmclr_swgen0_f(v) (((v)&0x1U) << 6U) #define pgsp_falcon_irqmclr_swgen0_f(v) ((U32(v) & 0x1U) << 6U)
#define pgsp_falcon_irqmclr_swgen1_f(v) (((v)&0x1U) << 7U) #define pgsp_falcon_irqmclr_swgen1_f(v) ((U32(v) & 0x1U) << 7U)
#define pgsp_falcon_irqmclr_ext_f(v) (((v)&0xffU) << 8U) #define pgsp_falcon_irqmclr_ext_f(v) ((U32(v) & 0xffU) << 8U)
#define pgsp_falcon_irqmask_r() (0x00110018U) #define pgsp_falcon_irqmask_r() (0x00110018U)
#define pgsp_falcon_irqdest_r() (0x0011001cU) #define pgsp_falcon_irqdest_r() (0x0011001cU)
#define pgsp_falcon_irqdest_host_gptmr_f(v) (((v)&0x1U) << 0U) #define pgsp_falcon_irqdest_host_gptmr_f(v) ((U32(v) & 0x1U) << 0U)
#define pgsp_falcon_irqdest_host_wdtmr_f(v) (((v)&0x1U) << 1U) #define pgsp_falcon_irqdest_host_wdtmr_f(v) ((U32(v) & 0x1U) << 1U)
#define pgsp_falcon_irqdest_host_mthd_f(v) (((v)&0x1U) << 2U) #define pgsp_falcon_irqdest_host_mthd_f(v) ((U32(v) & 0x1U) << 2U)
#define pgsp_falcon_irqdest_host_ctxsw_f(v) (((v)&0x1U) << 3U) #define pgsp_falcon_irqdest_host_ctxsw_f(v) ((U32(v) & 0x1U) << 3U)
#define pgsp_falcon_irqdest_host_halt_f(v) (((v)&0x1U) << 4U) #define pgsp_falcon_irqdest_host_halt_f(v) ((U32(v) & 0x1U) << 4U)
#define pgsp_falcon_irqdest_host_exterr_f(v) (((v)&0x1U) << 5U) #define pgsp_falcon_irqdest_host_exterr_f(v) ((U32(v) & 0x1U) << 5U)
#define pgsp_falcon_irqdest_host_swgen0_f(v) (((v)&0x1U) << 6U) #define pgsp_falcon_irqdest_host_swgen0_f(v) ((U32(v) & 0x1U) << 6U)
#define pgsp_falcon_irqdest_host_swgen1_f(v) (((v)&0x1U) << 7U) #define pgsp_falcon_irqdest_host_swgen1_f(v) ((U32(v) & 0x1U) << 7U)
#define pgsp_falcon_irqdest_host_ext_f(v) (((v)&0xffU) << 8U) #define pgsp_falcon_irqdest_host_ext_f(v) ((U32(v) & 0xffU) << 8U)
#define pgsp_falcon_irqdest_target_gptmr_f(v) (((v)&0x1U) << 16U) #define pgsp_falcon_irqdest_target_gptmr_f(v) ((U32(v) & 0x1U) << 16U)
#define pgsp_falcon_irqdest_target_wdtmr_f(v) (((v)&0x1U) << 17U) #define pgsp_falcon_irqdest_target_wdtmr_f(v) ((U32(v) & 0x1U) << 17U)
#define pgsp_falcon_irqdest_target_mthd_f(v) (((v)&0x1U) << 18U) #define pgsp_falcon_irqdest_target_mthd_f(v) ((U32(v) & 0x1U) << 18U)
#define pgsp_falcon_irqdest_target_ctxsw_f(v) (((v)&0x1U) << 19U) #define pgsp_falcon_irqdest_target_ctxsw_f(v) ((U32(v) & 0x1U) << 19U)
#define pgsp_falcon_irqdest_target_halt_f(v) (((v)&0x1U) << 20U) #define pgsp_falcon_irqdest_target_halt_f(v) ((U32(v) & 0x1U) << 20U)
#define pgsp_falcon_irqdest_target_exterr_f(v) (((v)&0x1U) << 21U) #define pgsp_falcon_irqdest_target_exterr_f(v) ((U32(v) & 0x1U) << 21U)
#define pgsp_falcon_irqdest_target_swgen0_f(v) (((v)&0x1U) << 22U) #define pgsp_falcon_irqdest_target_swgen0_f(v) ((U32(v) & 0x1U) << 22U)
#define pgsp_falcon_irqdest_target_swgen1_f(v) (((v)&0x1U) << 23U) #define pgsp_falcon_irqdest_target_swgen1_f(v) ((U32(v) & 0x1U) << 23U)
#define pgsp_falcon_irqdest_target_ext_f(v) (((v)&0xffU) << 24U) #define pgsp_falcon_irqdest_target_ext_f(v) ((U32(v) & 0xffU) << 24U)
#define pgsp_falcon_curctx_r() (0x00110050U) #define pgsp_falcon_curctx_r() (0x00110050U)
#define pgsp_falcon_nxtctx_r() (0x00110054U) #define pgsp_falcon_nxtctx_r() (0x00110054U)
#define pgsp_falcon_nxtctx_ctxptr_f(v) (((v)&0xfffffffU) << 0U) #define pgsp_falcon_nxtctx_ctxptr_f(v) ((U32(v) & 0xfffffffU) << 0U)
#define pgsp_falcon_nxtctx_ctxtgt_fb_f() (0x0U) #define pgsp_falcon_nxtctx_ctxtgt_fb_f() (0x0U)
#define pgsp_falcon_nxtctx_ctxtgt_sys_coh_f() (0x20000000U) #define pgsp_falcon_nxtctx_ctxtgt_sys_coh_f() (0x20000000U)
#define pgsp_falcon_nxtctx_ctxtgt_sys_ncoh_f() (0x30000000U) #define pgsp_falcon_nxtctx_ctxtgt_sys_ncoh_f() (0x30000000U)
#define pgsp_falcon_nxtctx_ctxvalid_f(v) (((v)&0x1U) << 30U) #define pgsp_falcon_nxtctx_ctxvalid_f(v) ((U32(v) & 0x1U) << 30U)
#define pgsp_falcon_mailbox0_r() (0x00110040U) #define pgsp_falcon_mailbox0_r() (0x00110040U)
#define pgsp_falcon_mailbox1_r() (0x00110044U) #define pgsp_falcon_mailbox1_r() (0x00110044U)
#define pgsp_falcon_itfen_r() (0x00110048U) #define pgsp_falcon_itfen_r() (0x00110048U)
@@ -125,20 +125,20 @@
#define pgsp_falcon_engctl_switch_context_true_f() (0x8U) #define pgsp_falcon_engctl_switch_context_true_f() (0x8U)
#define pgsp_falcon_engctl_switch_context_false_f() (0x0U) #define pgsp_falcon_engctl_switch_context_false_f() (0x0U)
#define pgsp_falcon_cpuctl_r() (0x00110100U) #define pgsp_falcon_cpuctl_r() (0x00110100U)
#define pgsp_falcon_cpuctl_startcpu_f(v) (((v)&0x1U) << 1U) #define pgsp_falcon_cpuctl_startcpu_f(v) ((U32(v) & 0x1U) << 1U)
#define pgsp_falcon_cpuctl_halt_intr_f(v) (((v)&0x1U) << 4U) #define pgsp_falcon_cpuctl_halt_intr_f(v) ((U32(v) & 0x1U) << 4U)
#define pgsp_falcon_cpuctl_halt_intr_m() (U32(0x1U) << 4U) #define pgsp_falcon_cpuctl_halt_intr_m() (U32(0x1U) << 4U)
#define pgsp_falcon_cpuctl_halt_intr_v(r) (((r) >> 4U) & 0x1U) #define pgsp_falcon_cpuctl_halt_intr_v(r) (((r) >> 4U) & 0x1U)
#define pgsp_falcon_cpuctl_cpuctl_alias_en_f(v) (((v)&0x1U) << 6U) #define pgsp_falcon_cpuctl_cpuctl_alias_en_f(v) ((U32(v) & 0x1U) << 6U)
#define pgsp_falcon_cpuctl_cpuctl_alias_en_m() (U32(0x1U) << 6U) #define pgsp_falcon_cpuctl_cpuctl_alias_en_m() (U32(0x1U) << 6U)
#define pgsp_falcon_cpuctl_cpuctl_alias_en_v(r) (((r) >> 6U) & 0x1U) #define pgsp_falcon_cpuctl_cpuctl_alias_en_v(r) (((r) >> 6U) & 0x1U)
#define pgsp_falcon_cpuctl_alias_r() (0x00110130U) #define pgsp_falcon_cpuctl_alias_r() (0x00110130U)
#define pgsp_falcon_cpuctl_alias_startcpu_f(v) (((v)&0x1U) << 1U) #define pgsp_falcon_cpuctl_alias_startcpu_f(v) ((U32(v) & 0x1U) << 1U)
#define pgsp_falcon_imemc_r(i)\ #define pgsp_falcon_imemc_r(i)\
(nvgpu_safe_add_u32(0x00110180U, nvgpu_safe_mult_u32((i), 16U))) (nvgpu_safe_add_u32(0x00110180U, nvgpu_safe_mult_u32((i), 16U)))
#define pgsp_falcon_imemc_offs_f(v) (((v)&0x3fU) << 2U) #define pgsp_falcon_imemc_offs_f(v) ((U32(v) & 0x3fU) << 2U)
#define pgsp_falcon_imemc_blk_f(v) (((v)&0xffU) << 8U) #define pgsp_falcon_imemc_blk_f(v) ((U32(v) & 0xffU) << 8U)
#define pgsp_falcon_imemc_aincw_f(v) (((v)&0x1U) << 24U) #define pgsp_falcon_imemc_aincw_f(v) ((U32(v) & 0x1U) << 24U)
#define pgsp_falcon_imemd_r(i)\ #define pgsp_falcon_imemd_r(i)\
(nvgpu_safe_add_u32(0x00110184U, nvgpu_safe_mult_u32((i), 16U))) (nvgpu_safe_add_u32(0x00110184U, nvgpu_safe_mult_u32((i), 16U)))
#define pgsp_falcon_imemt_r(i)\ #define pgsp_falcon_imemt_r(i)\
@@ -146,11 +146,11 @@
#define pgsp_falcon_sctl_r() (0x00110240U) #define pgsp_falcon_sctl_r() (0x00110240U)
#define pgsp_falcon_mmu_phys_sec_r() (0x00100ce4U) #define pgsp_falcon_mmu_phys_sec_r() (0x00100ce4U)
#define pgsp_falcon_bootvec_r() (0x00110104U) #define pgsp_falcon_bootvec_r() (0x00110104U)
#define pgsp_falcon_bootvec_vec_f(v) (((v)&0xffffffffU) << 0U) #define pgsp_falcon_bootvec_vec_f(v) ((U32(v) & 0xffffffffU) << 0U)
#define pgsp_falcon_dmactl_r() (0x0011010cU) #define pgsp_falcon_dmactl_r() (0x0011010cU)
#define pgsp_falcon_dmactl_dmem_scrubbing_m() (U32(0x1U) << 1U) #define pgsp_falcon_dmactl_dmem_scrubbing_m() (U32(0x1U) << 1U)
#define pgsp_falcon_dmactl_imem_scrubbing_m() (U32(0x1U) << 2U) #define pgsp_falcon_dmactl_imem_scrubbing_m() (U32(0x1U) << 2U)
#define pgsp_falcon_dmactl_require_ctx_f(v) (((v)&0x1U) << 0U) #define pgsp_falcon_dmactl_require_ctx_f(v) ((U32(v) & 0x1U) << 0U)
#define pgsp_falcon_hwcfg_r() (0x00110108U) #define pgsp_falcon_hwcfg_r() (0x00110108U)
#define pgsp_falcon_hwcfg_imem_size_v(r) (((r) >> 0U) & 0x1ffU) #define pgsp_falcon_hwcfg_imem_size_v(r) (((r) >> 0U) & 0x1ffU)
#define pgsp_falcon_hwcfg_dmem_size_v(r) (((r) >> 9U) & 0x1ffU) #define pgsp_falcon_hwcfg_dmem_size_v(r) (((r) >> 9U) & 0x1ffU)
@@ -158,10 +158,10 @@
#define pgsp_falcon_dmatrfbase1_r() (0x00110128U) #define pgsp_falcon_dmatrfbase1_r() (0x00110128U)
#define pgsp_falcon_dmatrfmoffs_r() (0x00110114U) #define pgsp_falcon_dmatrfmoffs_r() (0x00110114U)
#define pgsp_falcon_dmatrfcmd_r() (0x00110118U) #define pgsp_falcon_dmatrfcmd_r() (0x00110118U)
#define pgsp_falcon_dmatrfcmd_imem_f(v) (((v)&0x1U) << 4U) #define pgsp_falcon_dmatrfcmd_imem_f(v) ((U32(v) & 0x1U) << 4U)
#define pgsp_falcon_dmatrfcmd_write_f(v) (((v)&0x1U) << 5U) #define pgsp_falcon_dmatrfcmd_write_f(v) ((U32(v) & 0x1U) << 5U)
#define pgsp_falcon_dmatrfcmd_size_f(v) (((v)&0x7U) << 8U) #define pgsp_falcon_dmatrfcmd_size_f(v) ((U32(v) & 0x7U) << 8U)
#define pgsp_falcon_dmatrfcmd_ctxdma_f(v) (((v)&0x7U) << 12U) #define pgsp_falcon_dmatrfcmd_ctxdma_f(v) ((U32(v) & 0x7U) << 12U)
#define pgsp_falcon_dmatrffboffs_r() (0x0011011cU) #define pgsp_falcon_dmatrffboffs_r() (0x0011011cU)
#define pgsp_falcon_exterraddr_r() (0x00110168U) #define pgsp_falcon_exterraddr_r() (0x00110168U)
#define pgsp_falcon_exterrstat_r() (0x0011016cU) #define pgsp_falcon_exterrstat_r() (0x0011016cU)
@@ -170,26 +170,26 @@
#define pgsp_falcon_exterrstat_valid_true_v() (0x00000001U) #define pgsp_falcon_exterrstat_valid_true_v() (0x00000001U)
#define pgsp_sec2_falcon_icd_cmd_r() (0x00110200U) #define pgsp_sec2_falcon_icd_cmd_r() (0x00110200U)
#define pgsp_sec2_falcon_icd_cmd_opc_s() (4U) #define pgsp_sec2_falcon_icd_cmd_opc_s() (4U)
#define pgsp_sec2_falcon_icd_cmd_opc_f(v) (((v)&0xfU) << 0U) #define pgsp_sec2_falcon_icd_cmd_opc_f(v) ((U32(v) & 0xfU) << 0U)
#define pgsp_sec2_falcon_icd_cmd_opc_m() (U32(0xfU) << 0U) #define pgsp_sec2_falcon_icd_cmd_opc_m() (U32(0xfU) << 0U)
#define pgsp_sec2_falcon_icd_cmd_opc_v(r) (((r) >> 0U) & 0xfU) #define pgsp_sec2_falcon_icd_cmd_opc_v(r) (((r) >> 0U) & 0xfU)
#define pgsp_sec2_falcon_icd_cmd_opc_rreg_f() (0x8U) #define pgsp_sec2_falcon_icd_cmd_opc_rreg_f() (0x8U)
#define pgsp_sec2_falcon_icd_cmd_opc_rstat_f() (0xeU) #define pgsp_sec2_falcon_icd_cmd_opc_rstat_f() (0xeU)
#define pgsp_sec2_falcon_icd_cmd_idx_f(v) (((v)&0x1fU) << 8U) #define pgsp_sec2_falcon_icd_cmd_idx_f(v) ((U32(v) & 0x1fU) << 8U)
#define pgsp_sec2_falcon_icd_rdata_r() (0x0011020cU) #define pgsp_sec2_falcon_icd_rdata_r() (0x0011020cU)
#define pgsp_falcon_dmemc_r(i)\ #define pgsp_falcon_dmemc_r(i)\
(nvgpu_safe_add_u32(0x001101c0U, nvgpu_safe_mult_u32((i), 8U))) (nvgpu_safe_add_u32(0x001101c0U, nvgpu_safe_mult_u32((i), 8U)))
#define pgsp_falcon_dmemc_offs_f(v) (((v)&0x3fU) << 2U) #define pgsp_falcon_dmemc_offs_f(v) ((U32(v) & 0x3fU) << 2U)
#define pgsp_falcon_dmemc_offs_m() (U32(0x3fU) << 2U) #define pgsp_falcon_dmemc_offs_m() (U32(0x3fU) << 2U)
#define pgsp_falcon_dmemc_blk_f(v) (((v)&0xffU) << 8U) #define pgsp_falcon_dmemc_blk_f(v) ((U32(v) & 0xffU) << 8U)
#define pgsp_falcon_dmemc_blk_m() (U32(0xffU) << 8U) #define pgsp_falcon_dmemc_blk_m() (U32(0xffU) << 8U)
#define pgsp_falcon_dmemc_aincw_f(v) (((v)&0x1U) << 24U) #define pgsp_falcon_dmemc_aincw_f(v) ((U32(v) & 0x1U) << 24U)
#define pgsp_falcon_dmemc_aincr_f(v) (((v)&0x1U) << 25U) #define pgsp_falcon_dmemc_aincr_f(v) ((U32(v) & 0x1U) << 25U)
#define pgsp_falcon_dmemd_r(i)\ #define pgsp_falcon_dmemd_r(i)\
(nvgpu_safe_add_u32(0x001101c4U, nvgpu_safe_mult_u32((i), 8U))) (nvgpu_safe_add_u32(0x001101c4U, nvgpu_safe_mult_u32((i), 8U)))
#define pgsp_falcon_debug1_r() (0x00110090U) #define pgsp_falcon_debug1_r() (0x00110090U)
#define pgsp_falcon_debug1_ctxsw_mode_s() (1U) #define pgsp_falcon_debug1_ctxsw_mode_s() (1U)
#define pgsp_falcon_debug1_ctxsw_mode_f(v) (((v)&0x1U) << 16U) #define pgsp_falcon_debug1_ctxsw_mode_f(v) ((U32(v) & 0x1U) << 16U)
#define pgsp_falcon_debug1_ctxsw_mode_m() (U32(0x1U) << 16U) #define pgsp_falcon_debug1_ctxsw_mode_m() (U32(0x1U) << 16U)
#define pgsp_falcon_debug1_ctxsw_mode_v(r) (((r) >> 16U) & 0x1U) #define pgsp_falcon_debug1_ctxsw_mode_v(r) (((r) >> 16U) & 0x1U)
#define pgsp_falcon_debug1_ctxsw_mode_init_f() (0x0U) #define pgsp_falcon_debug1_ctxsw_mode_init_f() (0x0U)
@@ -199,7 +199,7 @@
#define pgsp_fbif_transcfg_target_coherent_sysmem_f() (0x1U) #define pgsp_fbif_transcfg_target_coherent_sysmem_f() (0x1U)
#define pgsp_fbif_transcfg_target_noncoherent_sysmem_f() (0x2U) #define pgsp_fbif_transcfg_target_noncoherent_sysmem_f() (0x2U)
#define pgsp_fbif_transcfg_mem_type_s() (1U) #define pgsp_fbif_transcfg_mem_type_s() (1U)
#define pgsp_fbif_transcfg_mem_type_f(v) (((v)&0x1U) << 2U) #define pgsp_fbif_transcfg_mem_type_f(v) ((U32(v) & 0x1U) << 2U)
#define pgsp_fbif_transcfg_mem_type_m() (U32(0x1U) << 2U) #define pgsp_fbif_transcfg_mem_type_m() (U32(0x1U) << 2U)
#define pgsp_fbif_transcfg_mem_type_v(r) (((r) >> 2U) & 0x1U) #define pgsp_fbif_transcfg_mem_type_v(r) (((r) >> 2U) & 0x1U)
#define pgsp_fbif_transcfg_mem_type_virtual_f() (0x0U) #define pgsp_fbif_transcfg_mem_type_virtual_f() (0x0U)

186
drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_pwr_gv100.h
View File

@@ -69,69 +69,69 @@
#define pwr_falcon_irqstat_ext_second_true_f() (0x800U) #define pwr_falcon_irqstat_ext_second_true_f() (0x800U)
#define pwr_falcon_irqmode_r() (0x0010a00cU) #define pwr_falcon_irqmode_r() (0x0010a00cU)
#define pwr_falcon_irqmset_r() (0x0010a010U) #define pwr_falcon_irqmset_r() (0x0010a010U)
#define pwr_falcon_irqmset_gptmr_f(v) (((v)&0x1U) << 0U) #define pwr_falcon_irqmset_gptmr_f(v) ((U32(v) & 0x1U) << 0U)
#define pwr_falcon_irqmset_wdtmr_f(v) (((v)&0x1U) << 1U) #define pwr_falcon_irqmset_wdtmr_f(v) ((U32(v) & 0x1U) << 1U)
#define pwr_falcon_irqmset_mthd_f(v) (((v)&0x1U) << 2U) #define pwr_falcon_irqmset_mthd_f(v) ((U32(v) & 0x1U) << 2U)
#define pwr_falcon_irqmset_ctxsw_f(v) (((v)&0x1U) << 3U) #define pwr_falcon_irqmset_ctxsw_f(v) ((U32(v) & 0x1U) << 3U)
#define pwr_falcon_irqmset_halt_f(v) (((v)&0x1U) << 4U) #define pwr_falcon_irqmset_halt_f(v) ((U32(v) & 0x1U) << 4U)
#define pwr_falcon_irqmset_exterr_f(v) (((v)&0x1U) << 5U) #define pwr_falcon_irqmset_exterr_f(v) ((U32(v) & 0x1U) << 5U)
#define pwr_falcon_irqmset_swgen0_f(v) (((v)&0x1U) << 6U) #define pwr_falcon_irqmset_swgen0_f(v) ((U32(v) & 0x1U) << 6U)
#define pwr_falcon_irqmset_swgen1_f(v) (((v)&0x1U) << 7U) #define pwr_falcon_irqmset_swgen1_f(v) ((U32(v) & 0x1U) << 7U)
#define pwr_falcon_irqmset_ext_f(v) (((v)&0xffU) << 8U) #define pwr_falcon_irqmset_ext_f(v) ((U32(v) & 0xffU) << 8U)
#define pwr_falcon_irqmset_ext_ctxe_f(v) (((v)&0x1U) << 8U) #define pwr_falcon_irqmset_ext_ctxe_f(v) ((U32(v) & 0x1U) << 8U)
#define pwr_falcon_irqmset_ext_limitv_f(v) (((v)&0x1U) << 9U) #define pwr_falcon_irqmset_ext_limitv_f(v) ((U32(v) & 0x1U) << 9U)
#define pwr_falcon_irqmset_ext_second_f(v) (((v)&0x1U) << 11U) #define pwr_falcon_irqmset_ext_second_f(v) ((U32(v) & 0x1U) << 11U)
#define pwr_falcon_irqmset_ext_therm_f(v) (((v)&0x1U) << 12U) #define pwr_falcon_irqmset_ext_therm_f(v) ((U32(v) & 0x1U) << 12U)
#define pwr_falcon_irqmset_ext_miscio_f(v) (((v)&0x1U) << 13U) #define pwr_falcon_irqmset_ext_miscio_f(v) ((U32(v) & 0x1U) << 13U)
#define pwr_falcon_irqmset_ext_rttimer_f(v) (((v)&0x1U) << 14U) #define pwr_falcon_irqmset_ext_rttimer_f(v) ((U32(v) & 0x1U) << 14U)
#define pwr_falcon_irqmclr_r() (0x0010a014U) #define pwr_falcon_irqmclr_r() (0x0010a014U)
#define pwr_falcon_irqmclr_gptmr_f(v) (((v)&0x1U) << 0U) #define pwr_falcon_irqmclr_gptmr_f(v) ((U32(v) & 0x1U) << 0U)
#define pwr_falcon_irqmclr_wdtmr_f(v) (((v)&0x1U) << 1U) #define pwr_falcon_irqmclr_wdtmr_f(v) ((U32(v) & 0x1U) << 1U)
#define pwr_falcon_irqmclr_mthd_f(v) (((v)&0x1U) << 2U) #define pwr_falcon_irqmclr_mthd_f(v) ((U32(v) & 0x1U) << 2U)
#define pwr_falcon_irqmclr_ctxsw_f(v) (((v)&0x1U) << 3U) #define pwr_falcon_irqmclr_ctxsw_f(v) ((U32(v) & 0x1U) << 3U)
#define pwr_falcon_irqmclr_halt_f(v) (((v)&0x1U) << 4U) #define pwr_falcon_irqmclr_halt_f(v) ((U32(v) & 0x1U) << 4U)
#define pwr_falcon_irqmclr_exterr_f(v) (((v)&0x1U) << 5U) #define pwr_falcon_irqmclr_exterr_f(v) ((U32(v) & 0x1U) << 5U)
#define pwr_falcon_irqmclr_swgen0_f(v) (((v)&0x1U) << 6U) #define pwr_falcon_irqmclr_swgen0_f(v) ((U32(v) & 0x1U) << 6U)
#define pwr_falcon_irqmclr_swgen1_f(v) (((v)&0x1U) << 7U) #define pwr_falcon_irqmclr_swgen1_f(v) ((U32(v) & 0x1U) << 7U)
#define pwr_falcon_irqmclr_ext_f(v) (((v)&0xffU) << 8U) #define pwr_falcon_irqmclr_ext_f(v) ((U32(v) & 0xffU) << 8U)
#define pwr_falcon_irqmclr_ext_ctxe_f(v) (((v)&0x1U) << 8U) #define pwr_falcon_irqmclr_ext_ctxe_f(v) ((U32(v) & 0x1U) << 8U)
#define pwr_falcon_irqmclr_ext_limitv_f(v) (((v)&0x1U) << 9U) #define pwr_falcon_irqmclr_ext_limitv_f(v) ((U32(v) & 0x1U) << 9U)
#define pwr_falcon_irqmclr_ext_second_f(v) (((v)&0x1U) << 11U) #define pwr_falcon_irqmclr_ext_second_f(v) ((U32(v) & 0x1U) << 11U)
#define pwr_falcon_irqmclr_ext_therm_f(v) (((v)&0x1U) << 12U) #define pwr_falcon_irqmclr_ext_therm_f(v) ((U32(v) & 0x1U) << 12U)
#define pwr_falcon_irqmclr_ext_miscio_f(v) (((v)&0x1U) << 13U) #define pwr_falcon_irqmclr_ext_miscio_f(v) ((U32(v) & 0x1U) << 13U)
#define pwr_falcon_irqmclr_ext_rttimer_f(v) (((v)&0x1U) << 14U) #define pwr_falcon_irqmclr_ext_rttimer_f(v) ((U32(v) & 0x1U) << 14U)
#define pwr_falcon_irqmask_r() (0x0010a018U) #define pwr_falcon_irqmask_r() (0x0010a018U)
#define pwr_falcon_irqdest_r() (0x0010a01cU) #define pwr_falcon_irqdest_r() (0x0010a01cU)
#define pwr_falcon_irqdest_host_gptmr_f(v) (((v)&0x1U) << 0U) #define pwr_falcon_irqdest_host_gptmr_f(v) ((U32(v) & 0x1U) << 0U)
#define pwr_falcon_irqdest_host_wdtmr_f(v) (((v)&0x1U) << 1U) #define pwr_falcon_irqdest_host_wdtmr_f(v) ((U32(v) & 0x1U) << 1U)
#define pwr_falcon_irqdest_host_mthd_f(v) (((v)&0x1U) << 2U) #define pwr_falcon_irqdest_host_mthd_f(v) ((U32(v) & 0x1U) << 2U)
#define pwr_falcon_irqdest_host_ctxsw_f(v) (((v)&0x1U) << 3U) #define pwr_falcon_irqdest_host_ctxsw_f(v) ((U32(v) & 0x1U) << 3U)
#define pwr_falcon_irqdest_host_halt_f(v) (((v)&0x1U) << 4U) #define pwr_falcon_irqdest_host_halt_f(v) ((U32(v) & 0x1U) << 4U)
#define pwr_falcon_irqdest_host_exterr_f(v) (((v)&0x1U) << 5U) #define pwr_falcon_irqdest_host_exterr_f(v) ((U32(v) & 0x1U) << 5U)
#define pwr_falcon_irqdest_host_swgen0_f(v) (((v)&0x1U) << 6U) #define pwr_falcon_irqdest_host_swgen0_f(v) ((U32(v) & 0x1U) << 6U)
#define pwr_falcon_irqdest_host_swgen1_f(v) (((v)&0x1U) << 7U) #define pwr_falcon_irqdest_host_swgen1_f(v) ((U32(v) & 0x1U) << 7U)
#define pwr_falcon_irqdest_host_ext_f(v) (((v)&0xffU) << 8U) #define pwr_falcon_irqdest_host_ext_f(v) ((U32(v) & 0xffU) << 8U)
#define pwr_falcon_irqdest_host_ext_ctxe_f(v) (((v)&0x1U) << 8U) #define pwr_falcon_irqdest_host_ext_ctxe_f(v) ((U32(v) & 0x1U) << 8U)
#define pwr_falcon_irqdest_host_ext_limitv_f(v) (((v)&0x1U) << 9U) #define pwr_falcon_irqdest_host_ext_limitv_f(v) ((U32(v) & 0x1U) << 9U)
#define pwr_falcon_irqdest_host_ext_second_f(v) (((v)&0x1U) << 11U) #define pwr_falcon_irqdest_host_ext_second_f(v) ((U32(v) & 0x1U) << 11U)
#define pwr_falcon_irqdest_host_ext_therm_f(v) (((v)&0x1U) << 12U) #define pwr_falcon_irqdest_host_ext_therm_f(v) ((U32(v) & 0x1U) << 12U)
#define pwr_falcon_irqdest_host_ext_miscio_f(v) (((v)&0x1U) << 13U) #define pwr_falcon_irqdest_host_ext_miscio_f(v) ((U32(v) & 0x1U) << 13U)
#define pwr_falcon_irqdest_host_ext_rttimer_f(v) (((v)&0x1U) << 14U) #define pwr_falcon_irqdest_host_ext_rttimer_f(v) ((U32(v) & 0x1U) << 14U)
#define pwr_falcon_irqdest_target_gptmr_f(v) (((v)&0x1U) << 16U) #define pwr_falcon_irqdest_target_gptmr_f(v) ((U32(v) & 0x1U) << 16U)
#define pwr_falcon_irqdest_target_wdtmr_f(v) (((v)&0x1U) << 17U) #define pwr_falcon_irqdest_target_wdtmr_f(v) ((U32(v) & 0x1U) << 17U)
#define pwr_falcon_irqdest_target_mthd_f(v) (((v)&0x1U) << 18U) #define pwr_falcon_irqdest_target_mthd_f(v) ((U32(v) & 0x1U) << 18U)
#define pwr_falcon_irqdest_target_ctxsw_f(v) (((v)&0x1U) << 19U) #define pwr_falcon_irqdest_target_ctxsw_f(v) ((U32(v) & 0x1U) << 19U)
#define pwr_falcon_irqdest_target_halt_f(v) (((v)&0x1U) << 20U) #define pwr_falcon_irqdest_target_halt_f(v) ((U32(v) & 0x1U) << 20U)
#define pwr_falcon_irqdest_target_exterr_f(v) (((v)&0x1U) << 21U) #define pwr_falcon_irqdest_target_exterr_f(v) ((U32(v) & 0x1U) << 21U)
#define pwr_falcon_irqdest_target_swgen0_f(v) (((v)&0x1U) << 22U) #define pwr_falcon_irqdest_target_swgen0_f(v) ((U32(v) & 0x1U) << 22U)
#define pwr_falcon_irqdest_target_swgen1_f(v) (((v)&0x1U) << 23U) #define pwr_falcon_irqdest_target_swgen1_f(v) ((U32(v) & 0x1U) << 23U)
#define pwr_falcon_irqdest_target_ext_f(v) (((v)&0xffU) << 24U) #define pwr_falcon_irqdest_target_ext_f(v) ((U32(v) & 0xffU) << 24U)
#define pwr_falcon_irqdest_target_ext_ctxe_f(v) (((v)&0x1U) << 24U) #define pwr_falcon_irqdest_target_ext_ctxe_f(v) ((U32(v) & 0x1U) << 24U)
#define pwr_falcon_irqdest_target_ext_limitv_f(v) (((v)&0x1U) << 25U) #define pwr_falcon_irqdest_target_ext_limitv_f(v) ((U32(v) & 0x1U) << 25U)
#define pwr_falcon_irqdest_target_ext_second_f(v) (((v)&0x1U) << 27U) #define pwr_falcon_irqdest_target_ext_second_f(v) ((U32(v) & 0x1U) << 27U)
#define pwr_falcon_irqdest_target_ext_therm_f(v) (((v)&0x1U) << 28U) #define pwr_falcon_irqdest_target_ext_therm_f(v) ((U32(v) & 0x1U) << 28U)
#define pwr_falcon_irqdest_target_ext_miscio_f(v) (((v)&0x1U) << 29U) #define pwr_falcon_irqdest_target_ext_miscio_f(v) ((U32(v) & 0x1U) << 29U)
#define pwr_falcon_irqdest_target_ext_rttimer_f(v) (((v)&0x1U) << 30U) #define pwr_falcon_irqdest_target_ext_rttimer_f(v) ((U32(v) & 0x1U) << 30U)
#define pwr_falcon_curctx_r() (0x0010a050U) #define pwr_falcon_curctx_r() (0x0010a050U)
#define pwr_falcon_nxtctx_r() (0x0010a054U) #define pwr_falcon_nxtctx_r() (0x0010a054U)
#define pwr_falcon_mailbox0_r() (0x0010a040U) #define pwr_falcon_mailbox0_r() (0x0010a040U)
@@ -144,24 +144,24 @@
#define pwr_falcon_os_r() (0x0010a080U) #define pwr_falcon_os_r() (0x0010a080U)
#define pwr_falcon_engctl_r() (0x0010a0a4U) #define pwr_falcon_engctl_r() (0x0010a0a4U)
#define pwr_falcon_cpuctl_r() (0x0010a100U) #define pwr_falcon_cpuctl_r() (0x0010a100U)
#define pwr_falcon_cpuctl_startcpu_f(v) (((v)&0x1U) << 1U) #define pwr_falcon_cpuctl_startcpu_f(v) ((U32(v) & 0x1U) << 1U)
#define pwr_falcon_cpuctl_halt_intr_f(v) (((v)&0x1U) << 4U) #define pwr_falcon_cpuctl_halt_intr_f(v) ((U32(v) & 0x1U) << 4U)
#define pwr_falcon_cpuctl_halt_intr_m() (U32(0x1U) << 4U) #define pwr_falcon_cpuctl_halt_intr_m() (U32(0x1U) << 4U)
#define pwr_falcon_cpuctl_halt_intr_v(r) (((r) >> 4U) & 0x1U) #define pwr_falcon_cpuctl_halt_intr_v(r) (((r) >> 4U) & 0x1U)
#define pwr_falcon_cpuctl_cpuctl_alias_en_f(v) (((v)&0x1U) << 6U) #define pwr_falcon_cpuctl_cpuctl_alias_en_f(v) ((U32(v) & 0x1U) << 6U)
#define pwr_falcon_cpuctl_cpuctl_alias_en_m() (U32(0x1U) << 6U) #define pwr_falcon_cpuctl_cpuctl_alias_en_m() (U32(0x1U) << 6U)
#define pwr_falcon_cpuctl_cpuctl_alias_en_v(r) (((r) >> 6U) & 0x1U) #define pwr_falcon_cpuctl_cpuctl_alias_en_v(r) (((r) >> 6U) & 0x1U)
#define pwr_falcon_cpuctl_alias_r() (0x0010a130U) #define pwr_falcon_cpuctl_alias_r() (0x0010a130U)
#define pwr_falcon_cpuctl_alias_startcpu_f(v) (((v)&0x1U) << 1U) #define pwr_falcon_cpuctl_alias_startcpu_f(v) ((U32(v) & 0x1U) << 1U)
#define pwr_pmu_scpctl_stat_r() (0x0010ac08U) #define pwr_pmu_scpctl_stat_r() (0x0010ac08U)
#define pwr_pmu_scpctl_stat_debug_mode_f(v) (((v)&0x1U) << 20U) #define pwr_pmu_scpctl_stat_debug_mode_f(v) ((U32(v) & 0x1U) << 20U)
#define pwr_pmu_scpctl_stat_debug_mode_m() (U32(0x1U) << 20U) #define pwr_pmu_scpctl_stat_debug_mode_m() (U32(0x1U) << 20U)
#define pwr_pmu_scpctl_stat_debug_mode_v(r) (((r) >> 20U) & 0x1U) #define pwr_pmu_scpctl_stat_debug_mode_v(r) (((r) >> 20U) & 0x1U)
#define pwr_falcon_imemc_r(i)\ #define pwr_falcon_imemc_r(i)\
(nvgpu_safe_add_u32(0x0010a180U, nvgpu_safe_mult_u32((i), 16U))) (nvgpu_safe_add_u32(0x0010a180U, nvgpu_safe_mult_u32((i), 16U)))
#define pwr_falcon_imemc_offs_f(v) (((v)&0x3fU) << 2U) #define pwr_falcon_imemc_offs_f(v) ((U32(v) & 0x3fU) << 2U)
#define pwr_falcon_imemc_blk_f(v) (((v)&0xffU) << 8U) #define pwr_falcon_imemc_blk_f(v) ((U32(v) & 0xffU) << 8U)
#define pwr_falcon_imemc_aincw_f(v) (((v)&0x1U) << 24U) #define pwr_falcon_imemc_aincw_f(v) ((U32(v) & 0x1U) << 24U)
#define pwr_falcon_imemd_r(i)\ #define pwr_falcon_imemd_r(i)\
(nvgpu_safe_add_u32(0x0010a184U, nvgpu_safe_mult_u32((i), 16U))) (nvgpu_safe_add_u32(0x0010a184U, nvgpu_safe_mult_u32((i), 16U)))
#define pwr_falcon_imemt_r(i)\ #define pwr_falcon_imemt_r(i)\
@@ -169,7 +169,7 @@
#define pwr_falcon_sctl_r() (0x0010a240U) #define pwr_falcon_sctl_r() (0x0010a240U)
#define pwr_falcon_mmu_phys_sec_r() (0x00100ce4U) #define pwr_falcon_mmu_phys_sec_r() (0x00100ce4U)
#define pwr_falcon_bootvec_r() (0x0010a104U) #define pwr_falcon_bootvec_r() (0x0010a104U)
#define pwr_falcon_bootvec_vec_f(v) (((v)&0xffffffffU) << 0U) #define pwr_falcon_bootvec_vec_f(v) ((U32(v) & 0xffffffffU) << 0U)
#define pwr_falcon_dmactl_r() (0x0010a10cU) #define pwr_falcon_dmactl_r() (0x0010a10cU)
#define pwr_falcon_dmactl_dmem_scrubbing_m() (U32(0x1U) << 1U) #define pwr_falcon_dmactl_dmem_scrubbing_m() (U32(0x1U) << 1U)
#define pwr_falcon_dmactl_imem_scrubbing_m() (U32(0x1U) << 2U) #define pwr_falcon_dmactl_imem_scrubbing_m() (U32(0x1U) << 2U)
@@ -180,10 +180,10 @@
#define pwr_falcon_dmatrfbase1_r() (0x0010a128U) #define pwr_falcon_dmatrfbase1_r() (0x0010a128U)
#define pwr_falcon_dmatrfmoffs_r() (0x0010a114U) #define pwr_falcon_dmatrfmoffs_r() (0x0010a114U)
#define pwr_falcon_dmatrfcmd_r() (0x0010a118U) #define pwr_falcon_dmatrfcmd_r() (0x0010a118U)
#define pwr_falcon_dmatrfcmd_imem_f(v) (((v)&0x1U) << 4U) #define pwr_falcon_dmatrfcmd_imem_f(v) ((U32(v) & 0x1U) << 4U)
#define pwr_falcon_dmatrfcmd_write_f(v) (((v)&0x1U) << 5U) #define pwr_falcon_dmatrfcmd_write_f(v) ((U32(v) & 0x1U) << 5U)
#define pwr_falcon_dmatrfcmd_size_f(v) (((v)&0x7U) << 8U) #define pwr_falcon_dmatrfcmd_size_f(v) ((U32(v) & 0x7U) << 8U)
#define pwr_falcon_dmatrfcmd_ctxdma_f(v) (((v)&0x7U) << 12U) #define pwr_falcon_dmatrfcmd_ctxdma_f(v) ((U32(v) & 0x7U) << 12U)
#define pwr_falcon_dmatrffboffs_r() (0x0010a11cU) #define pwr_falcon_dmatrffboffs_r() (0x0010a11cU)
#define pwr_falcon_exterraddr_r() (0x0010a168U) #define pwr_falcon_exterraddr_r() (0x0010a168U)
#define pwr_falcon_exterrstat_r() (0x0010a16cU) #define pwr_falcon_exterrstat_r() (0x0010a16cU)
@@ -192,59 +192,59 @@
#define pwr_falcon_exterrstat_valid_true_v() (0x00000001U) #define pwr_falcon_exterrstat_valid_true_v() (0x00000001U)
#define pwr_pmu_falcon_icd_cmd_r() (0x0010a200U) #define pwr_pmu_falcon_icd_cmd_r() (0x0010a200U)
#define pwr_pmu_falcon_icd_cmd_opc_s() (4U) #define pwr_pmu_falcon_icd_cmd_opc_s() (4U)
#define pwr_pmu_falcon_icd_cmd_opc_f(v) (((v)&0xfU) << 0U) #define pwr_pmu_falcon_icd_cmd_opc_f(v) ((U32(v) & 0xfU) << 0U)
#define pwr_pmu_falcon_icd_cmd_opc_m() (U32(0xfU) << 0U) #define pwr_pmu_falcon_icd_cmd_opc_m() (U32(0xfU) << 0U)
#define pwr_pmu_falcon_icd_cmd_opc_v(r) (((r) >> 0U) & 0xfU) #define pwr_pmu_falcon_icd_cmd_opc_v(r) (((r) >> 0U) & 0xfU)
#define pwr_pmu_falcon_icd_cmd_opc_rreg_f() (0x8U) #define pwr_pmu_falcon_icd_cmd_opc_rreg_f() (0x8U)
#define pwr_pmu_falcon_icd_cmd_opc_rstat_f() (0xeU) #define pwr_pmu_falcon_icd_cmd_opc_rstat_f() (0xeU)
#define pwr_pmu_falcon_icd_cmd_idx_f(v) (((v)&0x1fU) << 8U) #define pwr_pmu_falcon_icd_cmd_idx_f(v) ((U32(v) & 0x1fU) << 8U)
#define pwr_pmu_falcon_icd_rdata_r() (0x0010a20cU) #define pwr_pmu_falcon_icd_rdata_r() (0x0010a20cU)
#define pwr_falcon_dmemc_r(i)\ #define pwr_falcon_dmemc_r(i)\
(nvgpu_safe_add_u32(0x0010a1c0U, nvgpu_safe_mult_u32((i), 8U))) (nvgpu_safe_add_u32(0x0010a1c0U, nvgpu_safe_mult_u32((i), 8U)))
#define pwr_falcon_dmemc_offs_f(v) (((v)&0x3fU) << 2U) #define pwr_falcon_dmemc_offs_f(v) ((U32(v) & 0x3fU) << 2U)
#define pwr_falcon_dmemc_offs_m() (U32(0x3fU) << 2U) #define pwr_falcon_dmemc_offs_m() (U32(0x3fU) << 2U)
#define pwr_falcon_dmemc_blk_f(v) (((v)&0xffU) << 8U) #define pwr_falcon_dmemc_blk_f(v) ((U32(v) & 0xffU) << 8U)
#define pwr_falcon_dmemc_blk_m() (U32(0xffU) << 8U) #define pwr_falcon_dmemc_blk_m() (U32(0xffU) << 8U)
#define pwr_falcon_dmemc_aincw_f(v) (((v)&0x1U) << 24U) #define pwr_falcon_dmemc_aincw_f(v) ((U32(v) & 0x1U) << 24U)
#define pwr_falcon_dmemc_aincr_f(v) (((v)&0x1U) << 25U) #define pwr_falcon_dmemc_aincr_f(v) ((U32(v) & 0x1U) << 25U)
#define pwr_falcon_dmemd_r(i)\ #define pwr_falcon_dmemd_r(i)\
(nvgpu_safe_add_u32(0x0010a1c4U, nvgpu_safe_mult_u32((i), 8U))) (nvgpu_safe_add_u32(0x0010a1c4U, nvgpu_safe_mult_u32((i), 8U)))
#define pwr_pmu_new_instblk_r() (0x0010a480U) #define pwr_pmu_new_instblk_r() (0x0010a480U)
#define pwr_pmu_new_instblk_ptr_f(v) (((v)&0xfffffffU) << 0U) #define pwr_pmu_new_instblk_ptr_f(v) ((U32(v) & 0xfffffffU) << 0U)
#define pwr_pmu_new_instblk_target_fb_f() (0x0U) #define pwr_pmu_new_instblk_target_fb_f() (0x0U)
#define pwr_pmu_new_instblk_target_sys_coh_f() (0x20000000U) #define pwr_pmu_new_instblk_target_sys_coh_f() (0x20000000U)
#define pwr_pmu_new_instblk_target_sys_ncoh_f() (0x30000000U) #define pwr_pmu_new_instblk_target_sys_ncoh_f() (0x30000000U)
#define pwr_pmu_new_instblk_valid_f(v) (((v)&0x1U) << 30U) #define pwr_pmu_new_instblk_valid_f(v) ((U32(v) & 0x1U) << 30U)
#define pwr_pmu_mutex_id_r() (0x0010a488U) #define pwr_pmu_mutex_id_r() (0x0010a488U)
#define pwr_pmu_mutex_id_value_v(r) (((r) >> 0U) & 0xffU) #define pwr_pmu_mutex_id_value_v(r) (((r) >> 0U) & 0xffU)
#define pwr_pmu_mutex_id_value_init_v() (0x00000000U) #define pwr_pmu_mutex_id_value_init_v() (0x00000000U)
#define pwr_pmu_mutex_id_value_not_avail_v() (0x000000ffU) #define pwr_pmu_mutex_id_value_not_avail_v() (0x000000ffU)
#define pwr_pmu_mutex_id_release_r() (0x0010a48cU) #define pwr_pmu_mutex_id_release_r() (0x0010a48cU)
#define pwr_pmu_mutex_id_release_value_f(v) (((v)&0xffU) << 0U) #define pwr_pmu_mutex_id_release_value_f(v) ((U32(v) & 0xffU) << 0U)
#define pwr_pmu_mutex_id_release_value_m() (U32(0xffU) << 0U) #define pwr_pmu_mutex_id_release_value_m() (U32(0xffU) << 0U)
#define pwr_pmu_mutex_id_release_value_init_v() (0x00000000U) #define pwr_pmu_mutex_id_release_value_init_v() (0x00000000U)
#define pwr_pmu_mutex_id_release_value_init_f() (0x0U) #define pwr_pmu_mutex_id_release_value_init_f() (0x0U)
#define pwr_pmu_mutex_r(i)\ #define pwr_pmu_mutex_r(i)\
(nvgpu_safe_add_u32(0x0010a580U, nvgpu_safe_mult_u32((i), 4U))) (nvgpu_safe_add_u32(0x0010a580U, nvgpu_safe_mult_u32((i), 4U)))
#define pwr_pmu_mutex__size_1_v() (0x00000010U) #define pwr_pmu_mutex__size_1_v() (0x00000010U)
#define pwr_pmu_mutex_value_f(v) (((v)&0xffU) << 0U) #define pwr_pmu_mutex_value_f(v) ((U32(v) & 0xffU) << 0U)
#define pwr_pmu_mutex_value_v(r) (((r) >> 0U) & 0xffU) #define pwr_pmu_mutex_value_v(r) (((r) >> 0U) & 0xffU)
#define pwr_pmu_mutex_value_initial_lock_f() (0x0U) #define pwr_pmu_mutex_value_initial_lock_f() (0x0U)
#define pwr_pmu_queue_head_r(i)\ #define pwr_pmu_queue_head_r(i)\
(nvgpu_safe_add_u32(0x0010a800U, nvgpu_safe_mult_u32((i), 4U))) (nvgpu_safe_add_u32(0x0010a800U, nvgpu_safe_mult_u32((i), 4U)))
#define pwr_pmu_queue_head__size_1_v() (0x00000008U) #define pwr_pmu_queue_head__size_1_v() (0x00000008U)
#define pwr_pmu_queue_head_address_f(v) (((v)&0xffffffffU) << 0U) #define pwr_pmu_queue_head_address_f(v) ((U32(v) & 0xffffffffU) << 0U)
#define pwr_pmu_queue_head_address_v(r) (((r) >> 0U) & 0xffffffffU) #define pwr_pmu_queue_head_address_v(r) (((r) >> 0U) & 0xffffffffU)
#define pwr_pmu_queue_tail_r(i)\ #define pwr_pmu_queue_tail_r(i)\
(nvgpu_safe_add_u32(0x0010a820U, nvgpu_safe_mult_u32((i), 4U))) (nvgpu_safe_add_u32(0x0010a820U, nvgpu_safe_mult_u32((i), 4U)))
#define pwr_pmu_queue_tail__size_1_v() (0x00000008U) #define pwr_pmu_queue_tail__size_1_v() (0x00000008U)
#define pwr_pmu_queue_tail_address_f(v) (((v)&0xffffffffU) << 0U) #define pwr_pmu_queue_tail_address_f(v) ((U32(v) & 0xffffffffU) << 0U)
#define pwr_pmu_queue_tail_address_v(r) (((r) >> 0U) & 0xffffffffU) #define pwr_pmu_queue_tail_address_v(r) (((r) >> 0U) & 0xffffffffU)
#define pwr_pmu_msgq_head_r() (0x0010a4c8U) #define pwr_pmu_msgq_head_r() (0x0010a4c8U)
#define pwr_pmu_msgq_head_val_f(v) (((v)&0xffffffffU) << 0U) #define pwr_pmu_msgq_head_val_f(v) ((U32(v) & 0xffffffffU) << 0U)
#define pwr_pmu_msgq_head_val_v(r) (((r) >> 0U) & 0xffffffffU) #define pwr_pmu_msgq_head_val_v(r) (((r) >> 0U) & 0xffffffffU)
#define pwr_pmu_msgq_tail_r() (0x0010a4ccU) #define pwr_pmu_msgq_tail_r() (0x0010a4ccU)
#define pwr_pmu_msgq_tail_val_f(v) (((v)&0xffffffffU) << 0U) #define pwr_pmu_msgq_tail_val_f(v) ((U32(v) & 0xffffffffU) << 0U)
#define pwr_pmu_msgq_tail_val_v(r) (((r) >> 0U) & 0xffffffffU) #define pwr_pmu_msgq_tail_val_v(r) (((r) >> 0U) & 0xffffffffU)
#define pwr_pmu_idle_mask_r(i)\ #define pwr_pmu_idle_mask_r(i)\
(nvgpu_safe_add_u32(0x0010a504U, nvgpu_safe_mult_u32((i), 16U))) (nvgpu_safe_add_u32(0x0010a504U, nvgpu_safe_mult_u32((i), 16U)))
@@ -252,9 +252,9 @@
#define pwr_pmu_idle_mask_ce_2_enabled_f() (0x200000U) #define pwr_pmu_idle_mask_ce_2_enabled_f() (0x200000U)
#define pwr_pmu_idle_count_r(i)\ #define pwr_pmu_idle_count_r(i)\
(nvgpu_safe_add_u32(0x0010a508U, nvgpu_safe_mult_u32((i), 16U))) (nvgpu_safe_add_u32(0x0010a508U, nvgpu_safe_mult_u32((i), 16U)))
#define pwr_pmu_idle_count_value_f(v) (((v)&0x7fffffffU) << 0U) #define pwr_pmu_idle_count_value_f(v) ((U32(v) & 0x7fffffffU) << 0U)
#define pwr_pmu_idle_count_value_v(r) (((r) >> 0U) & 0x7fffffffU) #define pwr_pmu_idle_count_value_v(r) (((r) >> 0U) & 0x7fffffffU)
#define pwr_pmu_idle_count_reset_f(v) (((v)&0x1U) << 31U) #define pwr_pmu_idle_count_reset_f(v) ((U32(v) & 0x1U) << 31U)
#define pwr_pmu_idle_ctrl_r(i)\ #define pwr_pmu_idle_ctrl_r(i)\
(nvgpu_safe_add_u32(0x0010a50cU, nvgpu_safe_mult_u32((i), 16U))) (nvgpu_safe_add_u32(0x0010a50cU, nvgpu_safe_mult_u32((i), 16U)))
#define pwr_pmu_idle_ctrl_value_m() (U32(0x3U) << 0U) #define pwr_pmu_idle_ctrl_value_m() (U32(0x3U) << 0U)
@@ -264,13 +264,13 @@
#define pwr_pmu_idle_ctrl_filter_disabled_f() (0x0U) #define pwr_pmu_idle_ctrl_filter_disabled_f() (0x0U)
#define pwr_pmu_idle_threshold_r(i)\ #define pwr_pmu_idle_threshold_r(i)\
(nvgpu_safe_add_u32(0x0010a8a0U, nvgpu_safe_mult_u32((i), 4U))) (nvgpu_safe_add_u32(0x0010a8a0U, nvgpu_safe_mult_u32((i), 4U)))
#define pwr_pmu_idle_threshold_value_f(v) (((v)&0x7fffffffU) << 0U) #define pwr_pmu_idle_threshold_value_f(v) ((U32(v) & 0x7fffffffU) << 0U)
#define pwr_pmu_idle_intr_r() (0x0010a9e8U) #define pwr_pmu_idle_intr_r() (0x0010a9e8U)
#define pwr_pmu_idle_intr_en_f(v) (((v)&0x1U) << 0U) #define pwr_pmu_idle_intr_en_f(v) ((U32(v) & 0x1U) << 0U)
#define pwr_pmu_idle_intr_en_disabled_v() (0x00000000U) #define pwr_pmu_idle_intr_en_disabled_v() (0x00000000U)
#define pwr_pmu_idle_intr_en_enabled_v() (0x00000001U) #define pwr_pmu_idle_intr_en_enabled_v() (0x00000001U)
#define pwr_pmu_idle_intr_status_r() (0x0010a9ecU) #define pwr_pmu_idle_intr_status_r() (0x0010a9ecU)
#define pwr_pmu_idle_intr_status_intr_f(v) (((v)&0x1U) << 0U) #define pwr_pmu_idle_intr_status_intr_f(v) ((U32(v) & 0x1U) << 0U)
#define pwr_pmu_idle_intr_status_intr_m() (U32(0x1U) << 0U) #define pwr_pmu_idle_intr_status_intr_m() (U32(0x1U) << 0U)
#define pwr_pmu_idle_intr_status_intr_v(r) (((r) >> 0U) & 0x1U) #define pwr_pmu_idle_intr_status_intr_v(r) (((r) >> 0U) & 0x1U)
#define pwr_pmu_idle_intr_status_intr_pending_v() (0x00000001U) #define pwr_pmu_idle_intr_status_intr_pending_v() (0x00000001U)
@@ -314,7 +314,7 @@
#define pwr_fbif_transcfg_target_coherent_sysmem_f() (0x1U) #define pwr_fbif_transcfg_target_coherent_sysmem_f() (0x1U)
#define pwr_fbif_transcfg_target_noncoherent_sysmem_f() (0x2U) #define pwr_fbif_transcfg_target_noncoherent_sysmem_f() (0x2U)
#define pwr_fbif_transcfg_mem_type_s() (1U) #define pwr_fbif_transcfg_mem_type_s() (1U)
#define pwr_fbif_transcfg_mem_type_f(v) (((v)&0x1U) << 2U) #define pwr_fbif_transcfg_mem_type_f(v) ((U32(v) & 0x1U) << 2U)
#define pwr_fbif_transcfg_mem_type_m() (U32(0x1U) << 2U) #define pwr_fbif_transcfg_mem_type_m() (U32(0x1U) << 2U)
#define pwr_fbif_transcfg_mem_type_v(r) (((r) >> 2U) & 0x1U) #define pwr_fbif_transcfg_mem_type_v(r) (((r) >> 2U) & 0x1U)
#define pwr_fbif_transcfg_mem_type_virtual_f() (0x0U) #define pwr_fbif_transcfg_mem_type_virtual_f() (0x0U)

98
drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_ram_gv100.h
View File

@@ -61,7 +61,7 @@
#define ram_in_ramfc_s() (4096U) #define ram_in_ramfc_s() (4096U)
#define ram_in_ramfc_w() (0U) #define ram_in_ramfc_w() (0U)
#define ram_in_page_dir_base_target_f(v) (((v)&0x3U) << 0U) #define ram_in_page_dir_base_target_f(v) ((U32(v) & 0x3U) << 0U)
#define ram_in_page_dir_base_target_w() (128U) #define ram_in_page_dir_base_target_w() (128U)
#define ram_in_page_dir_base_target_vid_mem_f() (0x0U) #define ram_in_page_dir_base_target_vid_mem_f() (0x0U)
#define ram_in_page_dir_base_target_sys_mem_coh_f() (0x2U) #define ram_in_page_dir_base_target_sys_mem_coh_f() (0x2U)
@@ -69,113 +69,113 @@
#define ram_in_page_dir_base_vol_w() (128U) #define ram_in_page_dir_base_vol_w() (128U)
#define ram_in_page_dir_base_vol_true_f() (0x4U) #define ram_in_page_dir_base_vol_true_f() (0x4U)
#define ram_in_page_dir_base_vol_false_f() (0x0U) #define ram_in_page_dir_base_vol_false_f() (0x0U)
#define ram_in_page_dir_base_fault_replay_tex_f(v) (((v)&0x1U) << 4U) #define ram_in_page_dir_base_fault_replay_tex_f(v) ((U32(v) & 0x1U) << 4U)
#define ram_in_page_dir_base_fault_replay_tex_m() (U32(0x1U) << 4U) #define ram_in_page_dir_base_fault_replay_tex_m() (U32(0x1U) << 4U)
#define ram_in_page_dir_base_fault_replay_tex_w() (128U) #define ram_in_page_dir_base_fault_replay_tex_w() (128U)
#define ram_in_page_dir_base_fault_replay_tex_true_f() (0x10U) #define ram_in_page_dir_base_fault_replay_tex_true_f() (0x10U)
#define ram_in_page_dir_base_fault_replay_gcc_f(v) (((v)&0x1U) << 5U) #define ram_in_page_dir_base_fault_replay_gcc_f(v) ((U32(v) & 0x1U) << 5U)
#define ram_in_page_dir_base_fault_replay_gcc_m() (U32(0x1U) << 5U) #define ram_in_page_dir_base_fault_replay_gcc_m() (U32(0x1U) << 5U)
#define ram_in_page_dir_base_fault_replay_gcc_w() (128U) #define ram_in_page_dir_base_fault_replay_gcc_w() (128U)
#define ram_in_page_dir_base_fault_replay_gcc_true_f() (0x20U) #define ram_in_page_dir_base_fault_replay_gcc_true_f() (0x20U)
#define ram_in_use_ver2_pt_format_f(v) (((v)&0x1U) << 10U) #define ram_in_use_ver2_pt_format_f(v) ((U32(v) & 0x1U) << 10U)
#define ram_in_use_ver2_pt_format_m() (U32(0x1U) << 10U) #define ram_in_use_ver2_pt_format_m() (U32(0x1U) << 10U)
#define ram_in_use_ver2_pt_format_w() (128U) #define ram_in_use_ver2_pt_format_w() (128U)
#define ram_in_use_ver2_pt_format_true_f() (0x400U) #define ram_in_use_ver2_pt_format_true_f() (0x400U)
#define ram_in_use_ver2_pt_format_false_f() (0x0U) #define ram_in_use_ver2_pt_format_false_f() (0x0U)
#define ram_in_big_page_size_f(v) (((v)&0x1U) << 11U) #define ram_in_big_page_size_f(v) ((U32(v) & 0x1U) << 11U)
#define ram_in_big_page_size_m() (U32(0x1U) << 11U) #define ram_in_big_page_size_m() (U32(0x1U) << 11U)
#define ram_in_big_page_size_w() (128U) #define ram_in_big_page_size_w() (128U)
#define ram_in_big_page_size_128kb_f() (0x0U) #define ram_in_big_page_size_128kb_f() (0x0U)
#define ram_in_big_page_size_64kb_f() (0x800U) #define ram_in_big_page_size_64kb_f() (0x800U)
#define ram_in_page_dir_base_lo_f(v) (((v)&0xfffffU) << 12U) #define ram_in_page_dir_base_lo_f(v) ((U32(v) & 0xfffffU) << 12U)
#define ram_in_page_dir_base_lo_w() (128U) #define ram_in_page_dir_base_lo_w() (128U)
#define ram_in_page_dir_base_hi_f(v) (((v)&0xffffffffU) << 0U) #define ram_in_page_dir_base_hi_f(v) ((U32(v) & 0xffffffffU) << 0U)
#define ram_in_page_dir_base_hi_w() (129U) #define ram_in_page_dir_base_hi_w() (129U)
#define ram_in_engine_cs_w() (132U) #define ram_in_engine_cs_w() (132U)
#define ram_in_engine_cs_wfi_v() (0x00000000U) #define ram_in_engine_cs_wfi_v() (0x00000000U)
#define ram_in_engine_cs_wfi_f() (0x0U) #define ram_in_engine_cs_wfi_f() (0x0U)
#define ram_in_engine_cs_fg_v() (0x00000001U) #define ram_in_engine_cs_fg_v() (0x00000001U)
#define ram_in_engine_cs_fg_f() (0x8U) #define ram_in_engine_cs_fg_f() (0x8U)
#define ram_in_engine_wfi_mode_f(v) (((v)&0x1U) << 2U) #define ram_in_engine_wfi_mode_f(v) ((U32(v) & 0x1U) << 2U)
#define ram_in_engine_wfi_mode_w() (132U) #define ram_in_engine_wfi_mode_w() (132U)
#define ram_in_engine_wfi_mode_physical_v() (0x00000000U) #define ram_in_engine_wfi_mode_physical_v() (0x00000000U)
#define ram_in_engine_wfi_mode_virtual_v() (0x00000001U) #define ram_in_engine_wfi_mode_virtual_v() (0x00000001U)
#define ram_in_engine_wfi_target_f(v) (((v)&0x3U) << 0U) #define ram_in_engine_wfi_target_f(v) ((U32(v) & 0x3U) << 0U)
#define ram_in_engine_wfi_target_w() (132U) #define ram_in_engine_wfi_target_w() (132U)
#define ram_in_engine_wfi_target_sys_mem_coh_v() (0x00000002U) #define ram_in_engine_wfi_target_sys_mem_coh_v() (0x00000002U)
#define ram_in_engine_wfi_target_sys_mem_ncoh_v() (0x00000003U) #define ram_in_engine_wfi_target_sys_mem_ncoh_v() (0x00000003U)
#define ram_in_engine_wfi_target_local_mem_v() (0x00000000U) #define ram_in_engine_wfi_target_local_mem_v() (0x00000000U)
#define ram_in_engine_wfi_ptr_lo_f(v) (((v)&0xfffffU) << 12U) #define ram_in_engine_wfi_ptr_lo_f(v) ((U32(v) & 0xfffffU) << 12U)
#define ram_in_engine_wfi_ptr_lo_w() (132U) #define ram_in_engine_wfi_ptr_lo_w() (132U)
#define ram_in_engine_wfi_ptr_hi_f(v) (((v)&0xffU) << 0U) #define ram_in_engine_wfi_ptr_hi_f(v) ((U32(v) & 0xffU) << 0U)
#define ram_in_engine_wfi_ptr_hi_w() (133U) #define ram_in_engine_wfi_ptr_hi_w() (133U)
#define ram_in_engine_wfi_veid_f(v) (((v)&0x3fU) << 0U) #define ram_in_engine_wfi_veid_f(v) ((U32(v) & 0x3fU) << 0U)
#define ram_in_engine_wfi_veid_w() (134U) #define ram_in_engine_wfi_veid_w() (134U)
#define ram_in_eng_method_buffer_addr_lo_f(v) (((v)&0xffffffffU) << 0U) #define ram_in_eng_method_buffer_addr_lo_f(v) ((U32(v) & 0xffffffffU) << 0U)
#define ram_in_eng_method_buffer_addr_lo_w() (136U) #define ram_in_eng_method_buffer_addr_lo_w() (136U)
#define ram_in_eng_method_buffer_addr_hi_f(v) (((v)&0x1ffffU) << 0U) #define ram_in_eng_method_buffer_addr_hi_f(v) ((U32(v) & 0x1ffffU) << 0U)
#define ram_in_eng_method_buffer_addr_hi_w() (137U) #define ram_in_eng_method_buffer_addr_hi_w() (137U)
#define ram_in_sc_pdb_valid_w(i)\ #define ram_in_sc_pdb_valid_w(i)\
(166U + ((i*1U)/32U)) (166U + (((i)*1U)/32U))
#define ram_in_sc_pdb_valid__size_1_v() (0x00000040U) #define ram_in_sc_pdb_valid__size_1_v() (0x00000040U)
#define ram_in_sc_page_dir_base_target_f(v, i)\ #define ram_in_sc_page_dir_base_target_f(v, i)\
(((v) & 0x3) << (0U + i*0U)) ((U32(v) & 0x3U) << (0U + (i)*0U))
#define ram_in_sc_page_dir_base_target__size_1_v() (0x00000040U) #define ram_in_sc_page_dir_base_target__size_1_v() (0x00000040U)
#define ram_in_sc_page_dir_base_target_vid_mem_v() (0x00000000U) #define ram_in_sc_page_dir_base_target_vid_mem_v() (0x00000000U)
#define ram_in_sc_page_dir_base_target_invalid_v() (0x00000001U) #define ram_in_sc_page_dir_base_target_invalid_v() (0x00000001U)
#define ram_in_sc_page_dir_base_target_sys_mem_coh_v() (0x00000002U) #define ram_in_sc_page_dir_base_target_sys_mem_coh_v() (0x00000002U)
#define ram_in_sc_page_dir_base_target_sys_mem_ncoh_v() (0x00000003U) #define ram_in_sc_page_dir_base_target_sys_mem_ncoh_v() (0x00000003U)
#define ram_in_sc_page_dir_base_vol_f(v, i)\ #define ram_in_sc_page_dir_base_vol_f(v, i)\
(((v) & 0x1) << (2U + i*0U)) ((U32(v) & 0x1U) << (2U + (i)*0U))
#define ram_in_sc_page_dir_base_vol_w(i)\ #define ram_in_sc_page_dir_base_vol_w(i)\
(168U + ((i*128U)/32U)) (168U + (((i)*128U)/32U))
#define ram_in_sc_page_dir_base_vol__size_1_v() (0x00000040U) #define ram_in_sc_page_dir_base_vol__size_1_v() (0x00000040U)
#define ram_in_sc_page_dir_base_vol_true_v() (0x00000001U) #define ram_in_sc_page_dir_base_vol_true_v() (0x00000001U)
#define ram_in_sc_page_dir_base_vol_false_v() (0x00000000U) #define ram_in_sc_page_dir_base_vol_false_v() (0x00000000U)
#define ram_in_sc_page_dir_base_fault_replay_tex_f(v, i)\ #define ram_in_sc_page_dir_base_fault_replay_tex_f(v, i)\
(((v) & 0x1) << (4U + i*0U)) ((U32(v) & 0x1U) << (4U + (i)*0U))
#define ram_in_sc_page_dir_base_fault_replay_tex__size_1_v() (0x00000040U) #define ram_in_sc_page_dir_base_fault_replay_tex__size_1_v() (0x00000040U)
#define ram_in_sc_page_dir_base_fault_replay_tex_enabled_v() (0x00000001U) #define ram_in_sc_page_dir_base_fault_replay_tex_enabled_v() (0x00000001U)
#define ram_in_sc_page_dir_base_fault_replay_tex_disabled_v() (0x00000000U) #define ram_in_sc_page_dir_base_fault_replay_tex_disabled_v() (0x00000000U)
#define ram_in_sc_page_dir_base_fault_replay_gcc_f(v, i)\ #define ram_in_sc_page_dir_base_fault_replay_gcc_f(v, i)\
(((v) & 0x1) << (5U + i*0U)) ((U32(v) & 0x1U) << (5U + (i)*0U))
#define ram_in_sc_page_dir_base_fault_replay_gcc__size_1_v() (0x00000040U) #define ram_in_sc_page_dir_base_fault_replay_gcc__size_1_v() (0x00000040U)
#define ram_in_sc_page_dir_base_fault_replay_gcc_enabled_v() (0x00000001U) #define ram_in_sc_page_dir_base_fault_replay_gcc_enabled_v() (0x00000001U)
#define ram_in_sc_page_dir_base_fault_replay_gcc_disabled_v() (0x00000000U) #define ram_in_sc_page_dir_base_fault_replay_gcc_disabled_v() (0x00000000U)
#define ram_in_sc_use_ver2_pt_format_f(v, i)\ #define ram_in_sc_use_ver2_pt_format_f(v, i)\
(((v) & 0x1) << (10U + i*0U)) ((U32(v) & 0x1U) << (10U + (i)*0U))
#define ram_in_sc_use_ver2_pt_format__size_1_v() (0x00000040U) #define ram_in_sc_use_ver2_pt_format__size_1_v() (0x00000040U)
#define ram_in_sc_use_ver2_pt_format_false_v() (0x00000000U) #define ram_in_sc_use_ver2_pt_format_false_v() (0x00000000U)
#define ram_in_sc_use_ver2_pt_format_true_v() (0x00000001U) #define ram_in_sc_use_ver2_pt_format_true_v() (0x00000001U)
#define ram_in_sc_big_page_size_f(v, i)\ #define ram_in_sc_big_page_size_f(v, i)\
(((v) & 0x1) << (11U + i*0U)) ((U32(v) & 0x1U) << (11U + (i)*0U))
#define ram_in_sc_big_page_size__size_1_v() (0x00000040U) #define ram_in_sc_big_page_size__size_1_v() (0x00000040U)
#define ram_in_sc_big_page_size_64kb_v() (0x00000001U) #define ram_in_sc_big_page_size_64kb_v() (0x00000001U)
#define ram_in_sc_page_dir_base_lo_f(v, i)\ #define ram_in_sc_page_dir_base_lo_f(v, i)\
(((v) & 0xfffff) << (12U + i*0U)) ((U32(v) & 0xfffffU) << (12U + (i)*0U))
#define ram_in_sc_page_dir_base_lo_w(i)\ #define ram_in_sc_page_dir_base_lo_w(i)\
(168U + ((i*128U)/32U)) (168U + (((i)*128U)/32U))
#define ram_in_sc_page_dir_base_lo__size_1_v() (0x00000040U) #define ram_in_sc_page_dir_base_lo__size_1_v() (0x00000040U)
#define ram_in_sc_page_dir_base_hi_f(v, i)\ #define ram_in_sc_page_dir_base_hi_f(v, i)\
(((v) & 0xffffffff) << (0U + i*0U)) ((U32(v) & 0xffffffffU) << (0U + (i)*0U))
#define ram_in_sc_page_dir_base_hi_w(i)\ #define ram_in_sc_page_dir_base_hi_w(i)\
(169U + ((i*128U)/32U)) (169U + (((i)*128U)/32U))
#define ram_in_sc_page_dir_base_hi__size_1_v() (0x00000040U) #define ram_in_sc_page_dir_base_hi__size_1_v() (0x00000040U)
#define ram_in_sc_page_dir_base_target_0_f(v) (((v)&0x3U) << 0U) #define ram_in_sc_page_dir_base_target_0_f(v) ((U32(v) & 0x3U) << 0U)
#define ram_in_sc_page_dir_base_target_0_w() (168U) #define ram_in_sc_page_dir_base_target_0_w() (168U)
#define ram_in_sc_page_dir_base_vol_0_f(v) (((v)&0x1U) << 2U) #define ram_in_sc_page_dir_base_vol_0_f(v) ((U32(v) & 0x1U) << 2U)
#define ram_in_sc_page_dir_base_vol_0_w() (168U) #define ram_in_sc_page_dir_base_vol_0_w() (168U)
#define ram_in_sc_page_dir_base_fault_replay_tex_0_f(v) (((v)&0x1U) << 4U) #define ram_in_sc_page_dir_base_fault_replay_tex_0_f(v) ((U32(v) & 0x1U) << 4U)
#define ram_in_sc_page_dir_base_fault_replay_tex_0_w() (168U) #define ram_in_sc_page_dir_base_fault_replay_tex_0_w() (168U)
#define ram_in_sc_page_dir_base_fault_replay_gcc_0_f(v) (((v)&0x1U) << 5U) #define ram_in_sc_page_dir_base_fault_replay_gcc_0_f(v) ((U32(v) & 0x1U) << 5U)
#define ram_in_sc_page_dir_base_fault_replay_gcc_0_w() (168U) #define ram_in_sc_page_dir_base_fault_replay_gcc_0_w() (168U)
#define ram_in_sc_use_ver2_pt_format_0_f(v) (((v)&0x1U) << 10U) #define ram_in_sc_use_ver2_pt_format_0_f(v) ((U32(v) & 0x1U) << 10U)
#define ram_in_sc_use_ver2_pt_format_0_w() (168U) #define ram_in_sc_use_ver2_pt_format_0_w() (168U)
#define ram_in_sc_big_page_size_0_f(v) (((v)&0x1U) << 11U) #define ram_in_sc_big_page_size_0_f(v) ((U32(v) & 0x1U) << 11U)
#define ram_in_sc_big_page_size_0_w() (168U) #define ram_in_sc_big_page_size_0_w() (168U)
#define ram_in_sc_page_dir_base_lo_0_f(v) (((v)&0xfffffU) << 12U) #define ram_in_sc_page_dir_base_lo_0_f(v) ((U32(v) & 0xfffffU) << 12U)
#define ram_in_sc_page_dir_base_lo_0_w() (168U) #define ram_in_sc_page_dir_base_lo_0_w() (168U)
#define ram_in_sc_page_dir_base_hi_0_f(v) (((v)&0xffffffffU) << 0U) #define ram_in_sc_page_dir_base_hi_0_f(v) ((U32(v) & 0xffffffffU) << 0U)
#define ram_in_sc_page_dir_base_hi_0_w() (169U) #define ram_in_sc_page_dir_base_hi_0_w() (169U)
#define ram_in_base_shift_v() (0x0000000cU) #define ram_in_base_shift_v() (0x0000000cU)
#define ram_in_alloc_size_v() (0x00001000U) #define ram_in_alloc_size_v() (0x00001000U)
@@ -208,7 +208,7 @@
#define ram_fc_target_w() (43U) #define ram_fc_target_w() (43U)
#define ram_fc_hce_ctrl_w() (57U) #define ram_fc_hce_ctrl_w() (57U)
#define ram_fc_chid_w() (58U) #define ram_fc_chid_w() (58U)
#define ram_fc_chid_id_f(v) (((v)&0xfffU) << 0U) #define ram_fc_chid_id_f(v) ((U32(v) & 0xfffU) << 0U)
#define ram_fc_chid_id_w() (0U) #define ram_fc_chid_id_w() (0U)
#define ram_fc_config_w() (61U) #define ram_fc_config_w() (61U)
#define ram_fc_runlist_timeslice_w() (62U) #define ram_fc_runlist_timeslice_w() (62U)
@@ -227,36 +227,36 @@
#define ram_userd_gp_top_level_get_w() (22U) #define ram_userd_gp_top_level_get_w() (22U)
#define ram_userd_gp_top_level_get_hi_w() (23U) #define ram_userd_gp_top_level_get_hi_w() (23U)
#define ram_rl_entry_size_v() (0x00000010U) #define ram_rl_entry_size_v() (0x00000010U)
#define ram_rl_entry_type_f(v) (((v)&0x1U) << 0U) #define ram_rl_entry_type_f(v) ((U32(v) & 0x1U) << 0U)
#define ram_rl_entry_type_channel_v() (0x00000000U) #define ram_rl_entry_type_channel_v() (0x00000000U)
#define ram_rl_entry_type_tsg_v() (0x00000001U) #define ram_rl_entry_type_tsg_v() (0x00000001U)
#define ram_rl_entry_id_f(v) (((v)&0xfffU) << 0U) #define ram_rl_entry_id_f(v) ((U32(v) & 0xfffU) << 0U)
#define ram_rl_entry_chan_runqueue_selector_f(v) (((v)&0x1U) << 1U) #define ram_rl_entry_chan_runqueue_selector_f(v) ((U32(v) & 0x1U) << 1U)
#define ram_rl_entry_chan_inst_target_f(v) (((v)&0x3U) << 4U) #define ram_rl_entry_chan_inst_target_f(v) ((U32(v) & 0x3U) << 4U)
#define ram_rl_entry_chan_inst_target_sys_mem_ncoh_v() (0x00000003U) #define ram_rl_entry_chan_inst_target_sys_mem_ncoh_v() (0x00000003U)
#define ram_rl_entry_chan_inst_target_sys_mem_coh_v() (0x00000002U) #define ram_rl_entry_chan_inst_target_sys_mem_coh_v() (0x00000002U)
#define ram_rl_entry_chan_inst_target_vid_mem_v() (0x00000000U) #define ram_rl_entry_chan_inst_target_vid_mem_v() (0x00000000U)
#define ram_rl_entry_chan_userd_target_f(v) (((v)&0x3U) << 6U) #define ram_rl_entry_chan_userd_target_f(v) ((U32(v) & 0x3U) << 6U)
#define ram_rl_entry_chan_userd_target_vid_mem_v() (0x00000000U) #define ram_rl_entry_chan_userd_target_vid_mem_v() (0x00000000U)
#define ram_rl_entry_chan_userd_target_vid_mem_nvlink_coh_v() (0x00000001U) #define ram_rl_entry_chan_userd_target_vid_mem_nvlink_coh_v() (0x00000001U)
#define ram_rl_entry_chan_userd_target_sys_mem_coh_v() (0x00000002U) #define ram_rl_entry_chan_userd_target_sys_mem_coh_v() (0x00000002U)
#define ram_rl_entry_chan_userd_target_sys_mem_ncoh_v() (0x00000003U) #define ram_rl_entry_chan_userd_target_sys_mem_ncoh_v() (0x00000003U)
#define ram_rl_entry_chan_userd_ptr_lo_f(v) (((v)&0xffffffU) << 8U) #define ram_rl_entry_chan_userd_ptr_lo_f(v) ((U32(v) & 0xffffffU) << 8U)
#define ram_rl_entry_chan_userd_ptr_hi_f(v) (((v)&0xffffffffU) << 0U) #define ram_rl_entry_chan_userd_ptr_hi_f(v) ((U32(v) & 0xffffffffU) << 0U)
#define ram_rl_entry_chid_f(v) (((v)&0xfffU) << 0U) #define ram_rl_entry_chid_f(v) ((U32(v) & 0xfffU) << 0U)
#define ram_rl_entry_chan_inst_ptr_lo_f(v) (((v)&0xfffffU) << 12U) #define ram_rl_entry_chan_inst_ptr_lo_f(v) ((U32(v) & 0xfffffU) << 12U)
#define ram_rl_entry_chan_inst_ptr_hi_f(v) (((v)&0xffffffffU) << 0U) #define ram_rl_entry_chan_inst_ptr_hi_f(v) ((U32(v) & 0xffffffffU) << 0U)
#define ram_rl_entry_tsg_timeslice_scale_f(v) (((v)&0xfU) << 16U) #define ram_rl_entry_tsg_timeslice_scale_f(v) ((U32(v) & 0xfU) << 16U)
#define ram_rl_entry_tsg_timeslice_scale_v(r) (((r) >> 16U) & 0xfU) #define ram_rl_entry_tsg_timeslice_scale_v(r) (((r) >> 16U) & 0xfU)
#define ram_rl_entry_tsg_timeslice_scale_3_v() (0x00000003U) #define ram_rl_entry_tsg_timeslice_scale_3_v() (0x00000003U)
#define ram_rl_entry_tsg_timeslice_timeout_f(v) (((v)&0xffU) << 24U) #define ram_rl_entry_tsg_timeslice_timeout_f(v) ((U32(v) & 0xffU) << 24U)
#define ram_rl_entry_tsg_timeslice_timeout_v(r) (((r) >> 24U) & 0xffU) #define ram_rl_entry_tsg_timeslice_timeout_v(r) (((r) >> 24U) & 0xffU)
#define ram_rl_entry_tsg_timeslice_timeout_128_v() (0x00000080U) #define ram_rl_entry_tsg_timeslice_timeout_128_v() (0x00000080U)
#define ram_rl_entry_tsg_length_f(v) (((v)&0xffU) << 0U) #define ram_rl_entry_tsg_length_f(v) ((U32(v) & 0xffU) << 0U)
#define ram_rl_entry_tsg_length_init_v() (0x00000000U) #define ram_rl_entry_tsg_length_init_v() (0x00000000U)
#define ram_rl_entry_tsg_length_min_v() (0x00000001U) #define ram_rl_entry_tsg_length_min_v() (0x00000001U)
#define ram_rl_entry_tsg_length_max_v() (0x00000080U) #define ram_rl_entry_tsg_length_max_v() (0x00000080U)
#define ram_rl_entry_tsg_tsgid_f(v) (((v)&0xfffU) << 0U) #define ram_rl_entry_tsg_tsgid_f(v) ((U32(v) & 0xfffU) << 0U)
#define ram_rl_entry_chan_userd_ptr_align_shift_v() (0x00000008U) #define ram_rl_entry_chan_userd_ptr_align_shift_v() (0x00000008U)
#define ram_rl_entry_chan_userd_align_shift_v() (0x00000008U) #define ram_rl_entry_chan_userd_align_shift_v() (0x00000008U)
#define ram_rl_entry_chan_inst_ptr_align_shift_v() (0x0000000cU) #define ram_rl_entry_chan_inst_ptr_align_shift_v() (0x0000000cU)

33
drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_therm_gv100.h
View File

@@ -62,8 +62,8 @@
#define therm_weight_1_r() (0x00020024U) #define therm_weight_1_r() (0x00020024U)
#define therm_config1_r() (0x00020050U) #define therm_config1_r() (0x00020050U)
#define therm_config2_r() (0x00020130U) #define therm_config2_r() (0x00020130U)
#define therm_config2_slowdown_factor_extended_f(v) (((v)&0x1U) << 24U) #define therm_config2_slowdown_factor_extended_f(v) ((U32(v) & 0x1U) << 24U)
#define therm_config2_grad_enable_f(v) (((v)&0x1U) << 31U) #define therm_config2_grad_enable_f(v) ((U32(v) & 0x1U) << 31U)
#define therm_gate_ctrl_r(i)\ #define therm_gate_ctrl_r(i)\
(nvgpu_safe_add_u32(0x00020200U, nvgpu_safe_mult_u32((i), 4U))) (nvgpu_safe_add_u32(0x00020200U, nvgpu_safe_mult_u32((i), 4U)))
#define therm_gate_ctrl_eng_clk_m() (U32(0x3U) << 0U) #define therm_gate_ctrl_eng_clk_m() (U32(0x3U) << 0U)
@@ -76,13 +76,13 @@
#define therm_gate_ctrl_idle_holdoff_m() (U32(0x1U) << 4U) #define therm_gate_ctrl_idle_holdoff_m() (U32(0x1U) << 4U)
#define therm_gate_ctrl_idle_holdoff_off_f() (0x0U) #define therm_gate_ctrl_idle_holdoff_off_f() (0x0U)
#define therm_gate_ctrl_idle_holdoff_on_f() (0x10U) #define therm_gate_ctrl_idle_holdoff_on_f() (0x10U)
#define therm_gate_ctrl_eng_idle_filt_exp_f(v) (((v)&0x1fU) << 8U) #define therm_gate_ctrl_eng_idle_filt_exp_f(v) ((U32(v) & 0x1fU) << 8U)
#define therm_gate_ctrl_eng_idle_filt_exp_m() (U32(0x1fU) << 8U) #define therm_gate_ctrl_eng_idle_filt_exp_m() (U32(0x1fU) << 8U)
#define therm_gate_ctrl_eng_idle_filt_mant_f(v) (((v)&0x7U) << 13U) #define therm_gate_ctrl_eng_idle_filt_mant_f(v) ((U32(v) & 0x7U) << 13U)
#define therm_gate_ctrl_eng_idle_filt_mant_m() (U32(0x7U) << 13U) #define therm_gate_ctrl_eng_idle_filt_mant_m() (U32(0x7U) << 13U)
#define therm_gate_ctrl_eng_delay_before_f(v) (((v)&0xfU) << 16U) #define therm_gate_ctrl_eng_delay_before_f(v) ((U32(v) & 0xfU) << 16U)
#define therm_gate_ctrl_eng_delay_before_m() (U32(0xfU) << 16U) #define therm_gate_ctrl_eng_delay_before_m() (U32(0xfU) << 16U)
#define therm_gate_ctrl_eng_delay_after_f(v) (((v)&0xfU) << 20U) #define therm_gate_ctrl_eng_delay_after_f(v) ((U32(v) & 0xfU) << 20U)
#define therm_gate_ctrl_eng_delay_after_m() (U32(0xfU) << 20U) #define therm_gate_ctrl_eng_delay_after_m() (U32(0xfU) << 20U)
#define therm_fecs_idle_filter_r() (0x00020288U) #define therm_fecs_idle_filter_r() (0x00020288U)
#define therm_fecs_idle_filter_value_m() (U32(0xffffffffU) << 0U) #define therm_fecs_idle_filter_value_m() (U32(0xffffffffU) << 0U)
@@ -90,37 +90,40 @@
#define therm_hubmmu_idle_filter_value_m() (U32(0xffffffffU) << 0U) #define therm_hubmmu_idle_filter_value_m() (U32(0xffffffffU) << 0U)
#define therm_clk_slowdown_r(i)\ #define therm_clk_slowdown_r(i)\
(nvgpu_safe_add_u32(0x00020160U, nvgpu_safe_mult_u32((i), 4U))) (nvgpu_safe_add_u32(0x00020160U, nvgpu_safe_mult_u32((i), 4U)))
#define therm_clk_slowdown_idle_factor_f(v) (((v)&0x3fU) << 16U) #define therm_clk_slowdown_idle_factor_f(v) ((U32(v) & 0x3fU) << 16U)
#define therm_clk_slowdown_idle_factor_m() (U32(0x3fU) << 16U) #define therm_clk_slowdown_idle_factor_m() (U32(0x3fU) << 16U)
#define therm_clk_slowdown_idle_factor_v(r) (((r) >> 16U) & 0x3fU) #define therm_clk_slowdown_idle_factor_v(r) (((r) >> 16U) & 0x3fU)
#define therm_clk_slowdown_idle_factor_disabled_f() (0x0U) #define therm_clk_slowdown_idle_factor_disabled_f() (0x0U)
#define therm_grad_stepping_table_r(i)\ #define therm_grad_stepping_table_r(i)\
(nvgpu_safe_add_u32(0x000202c8U, nvgpu_safe_mult_u32((i), 4U))) (nvgpu_safe_add_u32(0x000202c8U, nvgpu_safe_mult_u32((i), 4U)))
#define therm_grad_stepping_table_slowdown_factor0_f(v) (((v)&0x3fU) << 0U) #define therm_grad_stepping_table_slowdown_factor0_f(v) ((U32(v) & 0x3fU) << 0U)
#define therm_grad_stepping_table_slowdown_factor0_m() (U32(0x3fU) << 0U) #define therm_grad_stepping_table_slowdown_factor0_m() (U32(0x3fU) << 0U)
#define therm_grad_stepping_table_slowdown_factor0_fpdiv_by1p5_f() (0x1U) #define therm_grad_stepping_table_slowdown_factor0_fpdiv_by1p5_f() (0x1U)
#define therm_grad_stepping_table_slowdown_factor0_fpdiv_by2_f() (0x2U) #define therm_grad_stepping_table_slowdown_factor0_fpdiv_by2_f() (0x2U)
#define therm_grad_stepping_table_slowdown_factor0_fpdiv_by4_f() (0x6U) #define therm_grad_stepping_table_slowdown_factor0_fpdiv_by4_f() (0x6U)
#define therm_grad_stepping_table_slowdown_factor0_fpdiv_by8_f() (0xeU) #define therm_grad_stepping_table_slowdown_factor0_fpdiv_by8_f() (0xeU)
#define therm_grad_stepping_table_slowdown_factor1_f(v) (((v)&0x3fU) << 6U) #define therm_grad_stepping_table_slowdown_factor1_f(v) ((U32(v) & 0x3fU) << 6U)
#define therm_grad_stepping_table_slowdown_factor1_m() (U32(0x3fU) << 6U) #define therm_grad_stepping_table_slowdown_factor1_m() (U32(0x3fU) << 6U)
#define therm_grad_stepping_table_slowdown_factor2_f(v) (((v)&0x3fU) << 12U) #define therm_grad_stepping_table_slowdown_factor2_f(v)\
((U32(v) & 0x3fU) << 12U)
#define therm_grad_stepping_table_slowdown_factor2_m() (U32(0x3fU) << 12U) #define therm_grad_stepping_table_slowdown_factor2_m() (U32(0x3fU) << 12U)
#define therm_grad_stepping_table_slowdown_factor3_f(v) (((v)&0x3fU) << 18U) #define therm_grad_stepping_table_slowdown_factor3_f(v)\
((U32(v) & 0x3fU) << 18U)
#define therm_grad_stepping_table_slowdown_factor3_m() (U32(0x3fU) << 18U) #define therm_grad_stepping_table_slowdown_factor3_m() (U32(0x3fU) << 18U)
#define therm_grad_stepping_table_slowdown_factor4_f(v) (((v)&0x3fU) << 24U) #define therm_grad_stepping_table_slowdown_factor4_f(v)\
((U32(v) & 0x3fU) << 24U)
#define therm_grad_stepping_table_slowdown_factor4_m() (U32(0x3fU) << 24U) #define therm_grad_stepping_table_slowdown_factor4_m() (U32(0x3fU) << 24U)
#define therm_grad_stepping0_r() (0x000202c0U) #define therm_grad_stepping0_r() (0x000202c0U)
#define therm_grad_stepping0_feature_s() (1U) #define therm_grad_stepping0_feature_s() (1U)
#define therm_grad_stepping0_feature_f(v) (((v)&0x1U) << 0U) #define therm_grad_stepping0_feature_f(v) ((U32(v) & 0x1U) << 0U)
#define therm_grad_stepping0_feature_m() (U32(0x1U) << 0U) #define therm_grad_stepping0_feature_m() (U32(0x1U) << 0U)
#define therm_grad_stepping0_feature_v(r) (((r) >> 0U) & 0x1U) #define therm_grad_stepping0_feature_v(r) (((r) >> 0U) & 0x1U)
#define therm_grad_stepping0_feature_enable_f() (0x1U) #define therm_grad_stepping0_feature_enable_f() (0x1U)
#define therm_grad_stepping1_r() (0x000202c4U) #define therm_grad_stepping1_r() (0x000202c4U)
#define therm_grad_stepping1_pdiv_duration_f(v) (((v)&0x1ffffU) << 0U) #define therm_grad_stepping1_pdiv_duration_f(v) ((U32(v) & 0x1ffffU) << 0U)
#define therm_clk_timing_r(i)\ #define therm_clk_timing_r(i)\
(nvgpu_safe_add_u32(0x000203c0U, nvgpu_safe_mult_u32((i), 4U))) (nvgpu_safe_add_u32(0x000203c0U, nvgpu_safe_mult_u32((i), 4U)))
#define therm_clk_timing_grad_slowdown_f(v) (((v)&0x1U) << 16U) #define therm_clk_timing_grad_slowdown_f(v) ((U32(v) & 0x1U) << 16U)
#define therm_clk_timing_grad_slowdown_m() (U32(0x1U) << 16U) #define therm_clk_timing_grad_slowdown_m() (U32(0x1U) << 16U)
#define therm_clk_timing_grad_slowdown_enabled_f() (0x10000U) #define therm_clk_timing_grad_slowdown_enabled_f() (0x10000U)
#endif #endif

4
drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_timer_gv100.h
View File

@@ -60,10 +60,10 @@
#include <nvgpu/safe_ops.h> #include <nvgpu/safe_ops.h>
#define timer_pri_timeout_r() (0x00009080U) #define timer_pri_timeout_r() (0x00009080U)
#define timer_pri_timeout_period_f(v) (((v)&0xffffffU) << 0U) #define timer_pri_timeout_period_f(v) ((U32(v) & 0xffffffU) << 0U)
#define timer_pri_timeout_period_m() (U32(0xffffffU) << 0U) #define timer_pri_timeout_period_m() (U32(0xffffffU) << 0U)
#define timer_pri_timeout_period_v(r) (((r) >> 0U) & 0xffffffU) #define timer_pri_timeout_period_v(r) (((r) >> 0U) & 0xffffffU)
#define timer_pri_timeout_en_f(v) (((v)&0x1U) << 31U) #define timer_pri_timeout_en_f(v) ((U32(v) & 0x1U) << 31U)
#define timer_pri_timeout_en_m() (U32(0x1U) << 31U) #define timer_pri_timeout_en_m() (U32(0x1U) << 31U)
#define timer_pri_timeout_en_v(r) (((r) >> 31U) & 0x1U) #define timer_pri_timeout_en_v(r) (((r) >> 31U) & 0x1U)
#define timer_pri_timeout_en_en_enabled_f() (0x80000000U) #define timer_pri_timeout_en_en_enabled_f() (0x80000000U)

14
drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_top_gv100.h
View File

@@ -115,25 +115,25 @@
#define top_device_info_data_fault_id_v(r) (((r) >> 2U) & 0x1U) #define top_device_info_data_fault_id_v(r) (((r) >> 2U) & 0x1U)
#define top_device_info_data_fault_id_valid_v() (0x00000001U) #define top_device_info_data_fault_id_valid_v() (0x00000001U)
#define top_nvhsclk_ctrl_r() (0x00022424U) #define top_nvhsclk_ctrl_r() (0x00022424U)
#define top_nvhsclk_ctrl_e_clk_nvl_f(v) (((v)&0x7U) << 0U) #define top_nvhsclk_ctrl_e_clk_nvl_f(v) ((U32(v) & 0x7U) << 0U)
#define top_nvhsclk_ctrl_e_clk_nvl_m() (U32(0x7U) << 0U) #define top_nvhsclk_ctrl_e_clk_nvl_m() (U32(0x7U) << 0U)
#define top_nvhsclk_ctrl_e_clk_nvl_v(r) (((r) >> 0U) & 0x7U) #define top_nvhsclk_ctrl_e_clk_nvl_v(r) (((r) >> 0U) & 0x7U)
#define top_nvhsclk_ctrl_e_clk_pcie_f(v) (((v)&0x1U) << 3U) #define top_nvhsclk_ctrl_e_clk_pcie_f(v) ((U32(v) & 0x1U) << 3U)
#define top_nvhsclk_ctrl_e_clk_pcie_m() (U32(0x1U) << 3U) #define top_nvhsclk_ctrl_e_clk_pcie_m() (U32(0x1U) << 3U)
#define top_nvhsclk_ctrl_e_clk_pcie_v(r) (((r) >> 3U) & 0x1U) #define top_nvhsclk_ctrl_e_clk_pcie_v(r) (((r) >> 3U) & 0x1U)
#define top_nvhsclk_ctrl_e_clk_core_f(v) (((v)&0x1U) << 4U) #define top_nvhsclk_ctrl_e_clk_core_f(v) ((U32(v) & 0x1U) << 4U)
#define top_nvhsclk_ctrl_e_clk_core_m() (U32(0x1U) << 4U) #define top_nvhsclk_ctrl_e_clk_core_m() (U32(0x1U) << 4U)
#define top_nvhsclk_ctrl_e_clk_core_v(r) (((r) >> 4U) & 0x1U) #define top_nvhsclk_ctrl_e_clk_core_v(r) (((r) >> 4U) & 0x1U)
#define top_nvhsclk_ctrl_rfu_f(v) (((v)&0xfU) << 5U) #define top_nvhsclk_ctrl_rfu_f(v) ((U32(v) & 0xfU) << 5U)
#define top_nvhsclk_ctrl_rfu_m() (U32(0xfU) << 5U) #define top_nvhsclk_ctrl_rfu_m() (U32(0xfU) << 5U)
#define top_nvhsclk_ctrl_rfu_v(r) (((r) >> 5U) & 0xfU) #define top_nvhsclk_ctrl_rfu_v(r) (((r) >> 5U) & 0xfU)
#define top_nvhsclk_ctrl_swap_clk_nvl_f(v) (((v)&0x7U) << 10U) #define top_nvhsclk_ctrl_swap_clk_nvl_f(v) ((U32(v) & 0x7U) << 10U)
#define top_nvhsclk_ctrl_swap_clk_nvl_m() (U32(0x7U) << 10U) #define top_nvhsclk_ctrl_swap_clk_nvl_m() (U32(0x7U) << 10U)
#define top_nvhsclk_ctrl_swap_clk_nvl_v(r) (((r) >> 10U) & 0x7U) #define top_nvhsclk_ctrl_swap_clk_nvl_v(r) (((r) >> 10U) & 0x7U)
#define top_nvhsclk_ctrl_swap_clk_pcie_f(v) (((v)&0x1U) << 9U) #define top_nvhsclk_ctrl_swap_clk_pcie_f(v) ((U32(v) & 0x1U) << 9U)
#define top_nvhsclk_ctrl_swap_clk_pcie_m() (U32(0x1U) << 9U) #define top_nvhsclk_ctrl_swap_clk_pcie_m() (U32(0x1U) << 9U)
#define top_nvhsclk_ctrl_swap_clk_pcie_v(r) (((r) >> 9U) & 0x1U) #define top_nvhsclk_ctrl_swap_clk_pcie_v(r) (((r) >> 9U) & 0x1U)
#define top_nvhsclk_ctrl_swap_clk_core_f(v) (((v)&0x1U) << 13U) #define top_nvhsclk_ctrl_swap_clk_core_f(v) ((U32(v) & 0x1U) << 13U)
#define top_nvhsclk_ctrl_swap_clk_core_m() (U32(0x1U) << 13U) #define top_nvhsclk_ctrl_swap_clk_core_m() (U32(0x1U) << 13U)
#define top_nvhsclk_ctrl_swap_clk_core_v(r) (((r) >> 13U) & 0x1U) #define top_nvhsclk_ctrl_swap_clk_core_v(r) (((r) >> 13U) & 0x1U)
#endif #endif

16
drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_trim_gv100.h
View File

@@ -61,34 +61,36 @@
#define trim_sys_nvlink_uphy_cfg_r() (0x00132410U) #define trim_sys_nvlink_uphy_cfg_r() (0x00132410U)
#define trim_sys_nvlink_uphy_cfg_lockdect_wait_dly_length_f(v)\ #define trim_sys_nvlink_uphy_cfg_lockdect_wait_dly_length_f(v)\
(((v)&0x3ffU) << 0U) ((U32(v) & 0x3ffU) << 0U)
#define trim_sys_nvlink_uphy_cfg_lockdect_wait_dly_length_m()\ #define trim_sys_nvlink_uphy_cfg_lockdect_wait_dly_length_m()\
(U32(0x3ffU) << 0U) (U32(0x3ffU) << 0U)
#define trim_sys_nvlink_uphy_cfg_lockdect_wait_dly_length_v(r)\ #define trim_sys_nvlink_uphy_cfg_lockdect_wait_dly_length_v(r)\
(((r) >> 0U) & 0x3ffU) (((r) >> 0U) & 0x3ffU)
#define trim_sys_nvlink_uphy_cfg_phy2clks_use_lockdet_f(v) (((v)&0x1U) << 12U) #define trim_sys_nvlink_uphy_cfg_phy2clks_use_lockdet_f(v)\
((U32(v) & 0x1U) << 12U)
#define trim_sys_nvlink_uphy_cfg_phy2clks_use_lockdet_m() (U32(0x1U) << 12U) #define trim_sys_nvlink_uphy_cfg_phy2clks_use_lockdet_m() (U32(0x1U) << 12U)
#define trim_sys_nvlink_uphy_cfg_phy2clks_use_lockdet_v(r) (((r) >> 12U) & 0x1U) #define trim_sys_nvlink_uphy_cfg_phy2clks_use_lockdet_v(r) (((r) >> 12U) & 0x1U)
#define trim_sys_nvlink_uphy_cfg_nvlink_wait_dly_f(v) (((v)&0xffU) << 16U) #define trim_sys_nvlink_uphy_cfg_nvlink_wait_dly_f(v) ((U32(v) & 0xffU) << 16U)
#define trim_sys_nvlink_uphy_cfg_nvlink_wait_dly_m() (U32(0xffU) << 16U) #define trim_sys_nvlink_uphy_cfg_nvlink_wait_dly_m() (U32(0xffU) << 16U)
#define trim_sys_nvlink_uphy_cfg_nvlink_wait_dly_v(r) (((r) >> 16U) & 0xffU) #define trim_sys_nvlink_uphy_cfg_nvlink_wait_dly_v(r) (((r) >> 16U) & 0xffU)
#define trim_sys_nvlink0_ctrl_r() (0x00132420U) #define trim_sys_nvlink0_ctrl_r() (0x00132420U)
#define trim_sys_nvlink0_ctrl_unit2clks_pll_turn_off_f(v) (((v)&0x1U) << 0U) #define trim_sys_nvlink0_ctrl_unit2clks_pll_turn_off_f(v)\
((U32(v) & 0x1U) << 0U)
#define trim_sys_nvlink0_ctrl_unit2clks_pll_turn_off_m() (U32(0x1U) << 0U) #define trim_sys_nvlink0_ctrl_unit2clks_pll_turn_off_m() (U32(0x1U) << 0U)
#define trim_sys_nvlink0_ctrl_unit2clks_pll_turn_off_v(r) (((r) >> 0U) & 0x1U) #define trim_sys_nvlink0_ctrl_unit2clks_pll_turn_off_v(r) (((r) >> 0U) & 0x1U)
#define trim_sys_nvlink0_status_r() (0x00132424U) #define trim_sys_nvlink0_status_r() (0x00132424U)
#define trim_sys_nvlink0_status_pll_off_f(v) (((v)&0x1U) << 5U) #define trim_sys_nvlink0_status_pll_off_f(v) ((U32(v) & 0x1U) << 5U)
#define trim_sys_nvlink0_status_pll_off_m() (U32(0x1U) << 5U) #define trim_sys_nvlink0_status_pll_off_m() (U32(0x1U) << 5U)
#define trim_sys_nvlink0_status_pll_off_v(r) (((r) >> 5U) & 0x1U) #define trim_sys_nvlink0_status_pll_off_v(r) (((r) >> 5U) & 0x1U)
#define trim_sys_nvl_common_clk_alt_switch_r() (0x001371c4U) #define trim_sys_nvl_common_clk_alt_switch_r() (0x001371c4U)
#define trim_sys_nvl_common_clk_alt_switch_slowclk_f(v) (((v)&0x3U) << 16U) #define trim_sys_nvl_common_clk_alt_switch_slowclk_f(v) ((U32(v) & 0x3U) << 16U)
#define trim_sys_nvl_common_clk_alt_switch_slowclk_m() (U32(0x3U) << 16U) #define trim_sys_nvl_common_clk_alt_switch_slowclk_m() (U32(0x3U) << 16U)
#define trim_sys_nvl_common_clk_alt_switch_slowclk_v(r) (((r) >> 16U) & 0x3U) #define trim_sys_nvl_common_clk_alt_switch_slowclk_v(r) (((r) >> 16U) & 0x3U)
#define trim_sys_nvl_common_clk_alt_switch_slowclk_xtal4x_v() (0x00000003U) #define trim_sys_nvl_common_clk_alt_switch_slowclk_xtal4x_v() (0x00000003U)
#define trim_sys_nvl_common_clk_alt_switch_slowclk_xtal4x_f() (0x30000U) #define trim_sys_nvl_common_clk_alt_switch_slowclk_xtal4x_f() (0x30000U)
#define trim_sys_nvl_common_clk_alt_switch_slowclk_xtal_in_v() (0x00000000U) #define trim_sys_nvl_common_clk_alt_switch_slowclk_xtal_in_v() (0x00000000U)
#define trim_sys_nvl_common_clk_alt_switch_slowclk_xtal_in_f() (0x0U) #define trim_sys_nvl_common_clk_alt_switch_slowclk_xtal_in_f() (0x0U)
#define trim_sys_nvl_common_clk_alt_switch_finalsel_f(v) (((v)&0x3U) << 0U) #define trim_sys_nvl_common_clk_alt_switch_finalsel_f(v) ((U32(v) & 0x3U) << 0U)
#define trim_sys_nvl_common_clk_alt_switch_finalsel_m() (U32(0x3U) << 0U) #define trim_sys_nvl_common_clk_alt_switch_finalsel_m() (U32(0x3U) << 0U)
#define trim_sys_nvl_common_clk_alt_switch_finalsel_v(r) (((r) >> 0U) & 0x3U) #define trim_sys_nvl_common_clk_alt_switch_finalsel_v(r) (((r) >> 0U) & 0x3U)
#define trim_sys_nvl_common_clk_alt_switch_finalsel_slowclk_v() (0x00000000U) #define trim_sys_nvl_common_clk_alt_switch_finalsel_slowclk_v() (0x00000000U)

8
drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_usermode_gv100.h
View File

@@ -60,12 +60,12 @@
#include <nvgpu/safe_ops.h> #include <nvgpu/safe_ops.h>
#define usermode_cfg0_r() (0x00810000U) #define usermode_cfg0_r() (0x00810000U)
#define usermode_cfg0_class_id_f(v) (((v)&0xffffU) << 0U) #define usermode_cfg0_class_id_f(v) ((U32(v) & 0xffffU) << 0U)
#define usermode_cfg0_class_id_value_v() (0x0000c361U) #define usermode_cfg0_class_id_value_v() (0x0000c361U)
#define usermode_time_0_r() (0x00810080U) #define usermode_time_0_r() (0x00810080U)
#define usermode_time_0_nsec_f(v) (((v)&0x7ffffffU) << 5U) #define usermode_time_0_nsec_f(v) ((U32(v) & 0x7ffffffU) << 5U)
#define usermode_time_1_r() (0x00810084U) #define usermode_time_1_r() (0x00810084U)
#define usermode_time_1_nsec_f(v) (((v)&0x1fffffffU) << 0U) #define usermode_time_1_nsec_f(v) ((U32(v) & 0x1fffffffU) << 0U)
#define usermode_notify_channel_pending_r() (0x00810090U) #define usermode_notify_channel_pending_r() (0x00810090U)
#define usermode_notify_channel_pending_id_f(v) (((v)&0xffffffffU) << 0U) #define usermode_notify_channel_pending_id_f(v) ((U32(v) & 0xffffffffU) << 0U)
#endif #endif

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