diff --git a/drivers/gpu/nvgpu/common/mm/mm.c b/drivers/gpu/nvgpu/common/mm/mm.c
index 035400585..1eeee43fb 100644
--- a/drivers/gpu/nvgpu/common/mm/mm.c
+++ b/drivers/gpu/nvgpu/common/mm/mm.c
@@ -108,6 +108,10 @@ int nvgpu_alloc_inst_block(struct gk20a *g, struct nvgpu_mem *inst_block)
 		return err;
 	}
 
+	if (g->ops.ramin.set_magic_value != NULL) {
+		g->ops.ramin.set_magic_value(g, inst_block);
+	}
+
 	nvgpu_log_fn(g, "done");
 	return 0;
 }
diff --git a/drivers/gpu/nvgpu/hal/fifo/ramin_ga10b.h b/drivers/gpu/nvgpu/hal/fifo/ramin_ga10b.h
index 2c6f78fea..337e2bf6d 100644
--- a/drivers/gpu/nvgpu/hal/fifo/ramin_ga10b.h
+++ b/drivers/gpu/nvgpu/hal/fifo/ramin_ga10b.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2020, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2020-2022, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -30,5 +30,6 @@ struct nvgpu_mem;
 
 void ga10b_ramin_init_pdb(struct gk20a *g, struct nvgpu_mem *inst_block,
 		u64 pdb_addr, struct nvgpu_mem *pdb_mem);
+void ga10b_ramin_set_magic_value(struct gk20a *g, struct nvgpu_mem *inst_block);
 
 #endif /* NVGPU_RAMIN_GA10B_H */
diff --git a/drivers/gpu/nvgpu/hal/fifo/ramin_ga10b_fusa.c b/drivers/gpu/nvgpu/hal/fifo/ramin_ga10b_fusa.c
index 6f23303dc..868d49b26 100644
--- a/drivers/gpu/nvgpu/hal/fifo/ramin_ga10b_fusa.c
+++ b/drivers/gpu/nvgpu/hal/fifo/ramin_ga10b_fusa.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2020, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2020-2022, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -50,3 +50,9 @@ void ga10b_ramin_init_pdb(struct gk20a *g, struct nvgpu_mem *inst_block,
 	nvgpu_mem_wr32(g, inst_block, ram_in_page_dir_base_hi_w(),
 		ram_in_page_dir_base_hi_f(pdb_addr_hi));
 }
+
+void ga10b_ramin_set_magic_value(struct gk20a *g, struct nvgpu_mem *inst_block)
+{
+	nvgpu_mem_wr32(g, inst_block, ram_in_engine_fw_magic_value_w(),
+			ram_in_engine_fw_magic_value_engine_fw_magic_value_v());
+}
diff --git a/drivers/gpu/nvgpu/hal/init/hal_ga10b.c b/drivers/gpu/nvgpu/hal/init/hal_ga10b.c
index cf77f89b4..65c5c5369 100644
--- a/drivers/gpu/nvgpu/hal/init/hal_ga10b.c
+++ b/drivers/gpu/nvgpu/hal/init/hal_ga10b.c
@@ -1154,6 +1154,7 @@ static const struct gops_ramin ga10b_ops_ramin = {
 	.base_shift = gk20a_ramin_base_shift,
 	.alloc_size = gk20a_ramin_alloc_size,
 	.set_eng_method_buffer = gv11b_ramin_set_eng_method_buffer,
+	.set_magic_value = ga10b_ramin_set_magic_value,
 };
 
 static const struct gops_runlist ga10b_ops_runlist = {
diff --git a/drivers/gpu/nvgpu/include/nvgpu/gops/ramin.h b/drivers/gpu/nvgpu/include/nvgpu/gops/ramin.h
index 1e3c54678..6256dde1c 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/gops/ramin.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/gops/ramin.h
@@ -214,6 +214,8 @@ struct gops_ramin {
 			struct nvgpu_mem *inst_block, u64 va_limit);
 	void (*set_eng_method_buffer)(struct gk20a *g,
 			struct nvgpu_mem *inst_block, u64 gpu_va);
+	void (*set_magic_value)(struct gk20a *g,
+			struct nvgpu_mem *inst_block);
 
 	/** @endcond DOXYGEN_SHOULD_SKIP_THIS */
 };
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/ga10b/hw_ram_ga10b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/ga10b/hw_ram_ga10b.h
index 0de328bbc..ca51348d1 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/hw/ga10b/hw_ram_ga10b.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/ga10b/hw_ram_ga10b.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2019-2021, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2019-2022, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -72,6 +72,8 @@
 #define ram_in_page_dir_base_lo_w()                                       (128U)
 #define ram_in_page_dir_base_hi_f(v)              ((U32(v) & 0xffffffffU) << 0U)
 #define ram_in_page_dir_base_hi_w()                                       (129U)
+#define ram_in_engine_fw_magic_value_w()                                  (131U)
+#define ram_in_engine_fw_magic_value_engine_fw_magic_value_v()     (0xcafeca11U)
 #define ram_in_engine_cs_s()                                                (1U)
 #define ram_in_engine_cs_f(v)                            ((U32(v) & 0x1U) << 3U)
 #define ram_in_engine_cs_m()                                   (U32(0x1U) << 3U)