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gpu: nvgpu: Add CHANNEL_SETUP_BIND IOCTL

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For a long time now, the ALLOC_GPFIFO_EX channel IOCTL has done much
more than just gpfifo allocation, and its signature does not match
support that's needed soon. Add a new one called SETUP_BIND to hopefully
cover our future needs and deprecate ALLOC_GPFIFO_EX.

Change nvgpu internals to match this new naming as well.

Bug 200145225

Change-Id: I766f9283a064e140656f6004b2b766db70bd6cad
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1835186
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Konsta Holtta
2018-09-20 14:27:25 +03:00
committed by mobile promotions
parent 0fd9c84f87
commit e0c8a16c8d
8 changed files with 127 additions and 76 deletions
Download Patch File Download Diff File Expand all files Collapse all files

26
drivers/gpu/nvgpu/common/fifo/channel.c
View File

@@ -1088,8 +1088,8 @@ static void channel_gk20a_free_prealloc_resources(struct channel_gk20a *c)
c->joblist.pre_alloc.enabled = false; c->joblist.pre_alloc.enabled = false;
} }
int gk20a_channel_alloc_gpfifo(struct channel_gk20a *c, int nvgpu_channel_setup_bind(struct channel_gk20a *c,
struct nvgpu_gpfifo_args *gpfifo_args) struct nvgpu_setup_bind_args *args)
{ {
struct gk20a *g = c->g; struct gk20a *g = c->g;
struct vm_gk20a *ch_vm; struct vm_gk20a *ch_vm;
@@ -1098,14 +1098,14 @@ int gk20a_channel_alloc_gpfifo(struct channel_gk20a *c,
int err = 0; int err = 0;
unsigned long acquire_timeout; unsigned long acquire_timeout;
gpfifo_size = gpfifo_args->num_entries; gpfifo_size = args->num_gpfifo_entries;
gpfifo_entry_size = nvgpu_get_gpfifo_entry_size(); gpfifo_entry_size = nvgpu_get_gpfifo_entry_size();
if (gpfifo_args->flags & NVGPU_GPFIFO_FLAGS_SUPPORT_VPR) { if (args->flags & NVGPU_SETUP_BIND_FLAGS_SUPPORT_VPR) {
c->vpr = true; c->vpr = true;
} }
if (gpfifo_args->flags & NVGPU_GPFIFO_FLAGS_SUPPORT_DETERMINISTIC) { if (args->flags & NVGPU_SETUP_BIND_FLAGS_SUPPORT_DETERMINISTIC) {
nvgpu_rwsem_down_read(&g->deterministic_busy); nvgpu_rwsem_down_read(&g->deterministic_busy);
/* /*
* Railgating isn't deterministic; instead of disallowing * Railgating isn't deterministic; instead of disallowing
@@ -1129,8 +1129,7 @@ int gk20a_channel_alloc_gpfifo(struct channel_gk20a *c,
/* an address space needs to have been bound at this point. */ /* an address space needs to have been bound at this point. */
if (!gk20a_channel_as_bound(c)) { if (!gk20a_channel_as_bound(c)) {
nvgpu_err(g, nvgpu_err(g,
"not bound to an address space at time of gpfifo" "not bound to an address space at time of setup_bind");
" allocation.");
err = -EINVAL; err = -EINVAL;
goto clean_up_idle; goto clean_up_idle;
} }
@@ -1144,10 +1143,9 @@ int gk20a_channel_alloc_gpfifo(struct channel_gk20a *c,
goto clean_up_idle; goto clean_up_idle;
} }
if (gpfifo_args->flags & NVGPU_GPFIFO_FLAGS_USERMODE_SUPPORT) { if (args->flags & NVGPU_SETUP_BIND_FLAGS_USERMODE_SUPPORT) {
if (g->os_channel.alloc_usermode_buffers) { if (g->os_channel.alloc_usermode_buffers) {
err = g->os_channel.alloc_usermode_buffers(c, err = g->os_channel.alloc_usermode_buffers(c, args);
gpfifo_args);
if (err) { if (err) {
nvgpu_err(g, "Usermode buffer alloc failed"); nvgpu_err(g, "Usermode buffer alloc failed");
goto clean_up; goto clean_up;
@@ -1215,16 +1213,16 @@ int gk20a_channel_alloc_gpfifo(struct channel_gk20a *c,
err = g->ops.fifo.setup_ramfc(c, gpfifo_gpu_va, err = g->ops.fifo.setup_ramfc(c, gpfifo_gpu_va,
c->gpfifo.entry_num, c->gpfifo.entry_num,
acquire_timeout, gpfifo_args->flags); acquire_timeout, args->flags);
if (err) { if (err) {
goto clean_up_sync; goto clean_up_sync;
} }
/* TBD: setup engine contexts */ /* TBD: setup engine contexts */
if (gpfifo_args->num_inflight_jobs) { if (args->num_inflight_jobs) {
err = channel_gk20a_prealloc_resources(c, err = channel_gk20a_prealloc_resources(c,
gpfifo_args->num_inflight_jobs); args->num_inflight_jobs);
if (err) { if (err) {
goto clean_up_sync; goto clean_up_sync;
} }
@@ -1248,7 +1246,7 @@ int gk20a_channel_alloc_gpfifo(struct channel_gk20a *c,
clean_up_priv_cmd: clean_up_priv_cmd:
channel_gk20a_free_priv_cmdbuf(c); channel_gk20a_free_priv_cmdbuf(c);
clean_up_prealloc: clean_up_prealloc:
if (gpfifo_args->num_inflight_jobs) { if (args->num_inflight_jobs) {
channel_gk20a_free_prealloc_resources(c); channel_gk20a_free_prealloc_resources(c);
} }
clean_up_sync: clean_up_sync:

13
drivers/gpu/nvgpu/gk20a/ce2_gk20a.c
View File

@@ -439,7 +439,7 @@ u32 gk20a_ce_create_context(struct gk20a *g,
{ {
struct gk20a_gpu_ctx *ce_ctx; struct gk20a_gpu_ctx *ce_ctx;
struct gk20a_ce_app *ce_app = g->ce_app; struct gk20a_ce_app *ce_app = g->ce_app;
struct nvgpu_gpfifo_args gpfifo_args; struct nvgpu_setup_bind_args setup_bind_args;
u32 ctx_id = ~0; u32 ctx_id = ~0;
int err = 0; int err = 0;
@@ -495,13 +495,12 @@ u32 gk20a_ce_create_context(struct gk20a *g,
goto end; goto end;
} }
gpfifo_args.num_entries = 1024; setup_bind_args.num_gpfifo_entries = 1024;
gpfifo_args.num_inflight_jobs = 0; setup_bind_args.num_inflight_jobs = 0;
gpfifo_args.flags = 0; setup_bind_args.flags = 0;
/* allocate gpfifo (1024 should be more than enough) */ err = nvgpu_channel_setup_bind(ce_ctx->ch, &setup_bind_args);
err = gk20a_channel_alloc_gpfifo(ce_ctx->ch, &gpfifo_args);
if (err != 0) { if (err != 0) {
nvgpu_err(g, "ce: unable to allocate gpfifo"); nvgpu_err(g, "ce: unable to setup and bind channel");
goto end; goto end;
} }

2
drivers/gpu/nvgpu/gv11b/fifo_gv11b.c
View File

@@ -147,7 +147,7 @@ int channel_gv11b_setup_ramfc(struct channel_gk20a *c,
nvgpu_memset(g, mem, 0, 0, ram_fc_size_val_v()); nvgpu_memset(g, mem, 0, 0, ram_fc_size_val_v());
if ((flags & NVGPU_GPFIFO_FLAGS_REPLAYABLE_FAULTS_ENABLE) != 0) { if ((flags & NVGPU_SETUP_BIND_FLAGS_REPLAYABLE_FAULTS_ENABLE) != 0) {
replayable = true; replayable = true;
} }
gv11b_init_subcontext_pdb(c->vm, mem, replayable); gv11b_init_subcontext_pdb(c->vm, mem, replayable);

18
drivers/gpu/nvgpu/include/nvgpu/channel.h
View File

@@ -38,11 +38,11 @@ struct fifo_profile_gk20a;
struct nvgpu_channel_sync; struct nvgpu_channel_sync;
struct nvgpu_gpfifo_userdata; struct nvgpu_gpfifo_userdata;
/* Flags to be passed to gk20a_channel_alloc_gpfifo() */ /* Flags to be passed to nvgpu_channel_setup_bind() */
#define NVGPU_GPFIFO_FLAGS_SUPPORT_VPR (1U << 0U) #define NVGPU_SETUP_BIND_FLAGS_SUPPORT_VPR (1U << 0U)
#define NVGPU_GPFIFO_FLAGS_SUPPORT_DETERMINISTIC (1U << 1U) #define NVGPU_SETUP_BIND_FLAGS_SUPPORT_DETERMINISTIC (1U << 1U)
#define NVGPU_GPFIFO_FLAGS_REPLAYABLE_FAULTS_ENABLE (1U << 2U) #define NVGPU_SETUP_BIND_FLAGS_REPLAYABLE_FAULTS_ENABLE (1U << 2U)
#define NVGPU_GPFIFO_FLAGS_USERMODE_SUPPORT (1U << 3U) #define NVGPU_SETUP_BIND_FLAGS_USERMODE_SUPPORT (1U << 3U)
/* Flags to be passed to nvgpu_submit_channel_gpfifo() */ /* Flags to be passed to nvgpu_submit_channel_gpfifo() */
#define NVGPU_SUBMIT_FLAGS_FENCE_WAIT (1U << 0U) #define NVGPU_SUBMIT_FLAGS_FENCE_WAIT (1U << 0U)
@@ -91,8 +91,8 @@ struct gpfifo_desc {
void *pipe; void *pipe;
}; };
struct nvgpu_gpfifo_args { struct nvgpu_setup_bind_args {
u32 num_entries; u32 num_gpfifo_entries;
u32 num_inflight_jobs; u32 num_inflight_jobs;
u32 userd_dmabuf_fd; u32 userd_dmabuf_fd;
u32 gpfifo_dmabuf_fd; u32 gpfifo_dmabuf_fd;
@@ -401,8 +401,8 @@ struct channel_gk20a *gk20a_open_new_channel(struct gk20a *g,
bool is_privileged_channel, bool is_privileged_channel,
pid_t pid, pid_t tid); pid_t pid, pid_t tid);
int gk20a_channel_alloc_gpfifo(struct channel_gk20a *c, int nvgpu_channel_setup_bind(struct channel_gk20a *c,
struct nvgpu_gpfifo_args *gpfifo_args); struct nvgpu_setup_bind_args *args);
void gk20a_channel_timeout_restart_all_channels(struct gk20a *g); void gk20a_channel_timeout_restart_all_channels(struct gk20a *g);

4
drivers/gpu/nvgpu/include/nvgpu/gk20a.h
View File

@@ -48,7 +48,7 @@ struct nvgpu_clk_arb;
struct nvgpu_gpu_ctxsw_trace_filter; struct nvgpu_gpu_ctxsw_trace_filter;
#endif #endif
struct priv_cmd_entry; struct priv_cmd_entry;
struct nvgpu_gpfifo_args; struct nvgpu_setup_bind_args;
#include <nvgpu/lock.h> #include <nvgpu/lock.h>
#include <nvgpu/thread.h> #include <nvgpu/thread.h>
@@ -1612,7 +1612,7 @@ struct gk20a {
struct nvgpu_gpfifo_userdata userdata, struct nvgpu_gpfifo_userdata userdata,
u32 start, u32 length); u32 start, u32 length);
int (*alloc_usermode_buffers)(struct channel_gk20a *c, int (*alloc_usermode_buffers)(struct channel_gk20a *c,
struct nvgpu_gpfifo_args *gpfifo_args); struct nvgpu_setup_bind_args *args);
} os_channel; } os_channel;
struct gk20a_scale_profile *scale_profile; struct gk20a_scale_profile *scale_profile;

19
drivers/gpu/nvgpu/os/linux/cde.c
View File

@@ -1311,7 +1311,7 @@ static int gk20a_cde_load(struct gk20a_cde_ctx *cde_ctx)
struct channel_gk20a *ch; struct channel_gk20a *ch;
struct tsg_gk20a *tsg; struct tsg_gk20a *tsg;
struct gr_gk20a *gr = &g->gr; struct gr_gk20a *gr = &g->gr;
struct nvgpu_gpfifo_args gpfifo_args; struct nvgpu_setup_bind_args setup_bind_args;
int err = 0; int err = 0;
u64 vaddr; u64 vaddr;
@@ -1350,17 +1350,16 @@ static int gk20a_cde_load(struct gk20a_cde_ctx *cde_ctx)
err = gk20a_tsg_bind_channel(tsg, ch); err = gk20a_tsg_bind_channel(tsg, ch);
if (err) { if (err) {
nvgpu_err(g, "cde: unable to bind to tsg"); nvgpu_err(g, "cde: unable to bind to tsg");
goto err_alloc_gpfifo; goto err_setup_bind;
} }
gpfifo_args.num_entries = 1024; setup_bind_args.num_gpfifo_entries = 1024;
gpfifo_args.num_inflight_jobs = 0; setup_bind_args.num_inflight_jobs = 0;
gpfifo_args.flags = 0; setup_bind_args.flags = 0;
/* allocate gpfifo (1024 should be more than enough) */ err = nvgpu_channel_setup_bind(ch, &setup_bind_args);
err = gk20a_channel_alloc_gpfifo(ch, &gpfifo_args);
if (err) { if (err) {
nvgpu_warn(g, "cde: unable to allocate gpfifo"); nvgpu_warn(g, "cde: unable to setup channel");
goto err_alloc_gpfifo; goto err_setup_bind;
} }
/* map backing store to gpu virtual space */ /* map backing store to gpu virtual space */
@@ -1398,7 +1397,7 @@ static int gk20a_cde_load(struct gk20a_cde_ctx *cde_ctx)
err_init_cde_img: err_init_cde_img:
nvgpu_gmmu_unmap(ch->vm, &g->gr.compbit_store.mem, vaddr); nvgpu_gmmu_unmap(ch->vm, &g->gr.compbit_store.mem, vaddr);
err_map_backingstore: err_map_backingstore:
err_alloc_gpfifo: err_setup_bind:
nvgpu_vm_put(ch->vm); nvgpu_vm_put(ch->vm);
err_commit_va: err_commit_va:
err_get_gk20a_channel: err_get_gk20a_channel:

82
drivers/gpu/nvgpu/os/linux/ioctl_channel.c
View File

@@ -577,44 +577,58 @@ clean_up:
return err; return err;
} }
static u32 nvgpu_gpfifo_user_flags_to_common_flags(u32 user_flags) static u32 nvgpu_setup_bind_user_flags_to_common_flags(u32 user_flags)
{ {
u32 flags = 0; u32 flags = 0;
if (user_flags & NVGPU_ALLOC_GPFIFO_EX_FLAGS_VPR_ENABLED) if (user_flags & NVGPU_CHANNEL_SETUP_BIND_FLAGS_VPR_ENABLED)
flags |= NVGPU_GPFIFO_FLAGS_SUPPORT_VPR; flags |= NVGPU_SETUP_BIND_FLAGS_SUPPORT_VPR;
if (user_flags & NVGPU_ALLOC_GPFIFO_EX_FLAGS_DETERMINISTIC) if (user_flags & NVGPU_CHANNEL_SETUP_BIND_FLAGS_DETERMINISTIC)
flags |= NVGPU_GPFIFO_FLAGS_SUPPORT_DETERMINISTIC; flags |= NVGPU_SETUP_BIND_FLAGS_SUPPORT_DETERMINISTIC;
if (user_flags & NVGPU_ALLOC_GPFIFO_FLAGS_REPLAYABLE_FAULTS_ENABLE) if (user_flags & NVGPU_CHANNEL_SETUP_BIND_FLAGS_REPLAYABLE_FAULTS_ENABLE)
flags |= NVGPU_GPFIFO_FLAGS_REPLAYABLE_FAULTS_ENABLE; flags |= NVGPU_SETUP_BIND_FLAGS_REPLAYABLE_FAULTS_ENABLE;
return flags; return flags;
} }
static void nvgpu_get_setup_bind_args(
struct nvgpu_channel_setup_bind_args *channel_setup_bind_args,
struct nvgpu_setup_bind_args *setup_bind_args)
{
setup_bind_args->num_gpfifo_entries =
channel_setup_bind_args->num_gpfifo_entries;
setup_bind_args->num_inflight_jobs =
channel_setup_bind_args->num_inflight_jobs;
setup_bind_args->flags = nvgpu_setup_bind_user_flags_to_common_flags(
channel_setup_bind_args->flags);
}
static void nvgpu_get_gpfifo_ex_args( static void nvgpu_get_gpfifo_ex_args(
struct nvgpu_alloc_gpfifo_ex_args *alloc_gpfifo_ex_args, struct nvgpu_alloc_gpfifo_ex_args *alloc_gpfifo_ex_args,
struct nvgpu_gpfifo_args *gpfifo_args) struct nvgpu_setup_bind_args *setup_bind_args)
{ {
gpfifo_args->num_entries = alloc_gpfifo_ex_args->num_entries; setup_bind_args->num_gpfifo_entries = alloc_gpfifo_ex_args->num_entries;
gpfifo_args->num_inflight_jobs = alloc_gpfifo_ex_args->num_inflight_jobs; setup_bind_args->num_inflight_jobs =
gpfifo_args->flags = nvgpu_gpfifo_user_flags_to_common_flags( alloc_gpfifo_ex_args->num_inflight_jobs;
setup_bind_args->flags = nvgpu_setup_bind_user_flags_to_common_flags(
alloc_gpfifo_ex_args->flags); alloc_gpfifo_ex_args->flags);
} }
static void nvgpu_get_gpfifo_args( static void nvgpu_get_gpfifo_args(
struct nvgpu_alloc_gpfifo_args *alloc_gpfifo_args, struct nvgpu_alloc_gpfifo_args *alloc_gpfifo_args,
struct nvgpu_gpfifo_args *gpfifo_args) struct nvgpu_setup_bind_args *setup_bind_args)
{ {
/* /*
* Kernel can insert one extra gpfifo entry before user * Kernel can insert one extra gpfifo entry before user
* submitted gpfifos and another one after, for internal usage. * submitted gpfifos and another one after, for internal usage.
* Triple the requested size. * Triple the requested size.
*/ */
gpfifo_args->num_entries = alloc_gpfifo_args->num_entries * 3; setup_bind_args->num_gpfifo_entries =
gpfifo_args->num_inflight_jobs = 0; alloc_gpfifo_args->num_entries * 3;
gpfifo_args->flags = nvgpu_gpfifo_user_flags_to_common_flags( setup_bind_args->num_inflight_jobs = 0;
setup_bind_args->flags = nvgpu_setup_bind_user_flags_to_common_flags(
alloc_gpfifo_args->flags); alloc_gpfifo_args->flags);
} }
@@ -1114,13 +1128,39 @@ long gk20a_channel_ioctl(struct file *filp,
gk20a_idle(ch->g); gk20a_idle(ch->g);
break; break;
} }
case NVGPU_IOCTL_CHANNEL_SETUP_BIND:
{
struct nvgpu_channel_setup_bind_args *channel_setup_bind_args =
(struct nvgpu_channel_setup_bind_args *)buf;
struct nvgpu_setup_bind_args setup_bind_args;
nvgpu_get_setup_bind_args(channel_setup_bind_args,
&setup_bind_args);
err = gk20a_busy(ch->g);
if (err) {
dev_err(dev,
"%s: failed to host gk20a for ioctl cmd: 0x%x",
__func__, cmd);
break;
}
if (!is_power_of_2(setup_bind_args.num_gpfifo_entries)) {
err = -EINVAL;
gk20a_idle(ch->g);
break;
}
err = nvgpu_channel_setup_bind(ch, &setup_bind_args);
gk20a_idle(ch->g);
break;
}
case NVGPU_IOCTL_CHANNEL_ALLOC_GPFIFO_EX: case NVGPU_IOCTL_CHANNEL_ALLOC_GPFIFO_EX:
{ {
struct nvgpu_alloc_gpfifo_ex_args *alloc_gpfifo_ex_args = struct nvgpu_alloc_gpfifo_ex_args *alloc_gpfifo_ex_args =
(struct nvgpu_alloc_gpfifo_ex_args *)buf; (struct nvgpu_alloc_gpfifo_ex_args *)buf;
struct nvgpu_gpfifo_args gpfifo_args; struct nvgpu_setup_bind_args setup_bind_args;
nvgpu_get_gpfifo_ex_args(alloc_gpfifo_ex_args, &gpfifo_args); nvgpu_get_gpfifo_ex_args(alloc_gpfifo_ex_args, &setup_bind_args);
err = gk20a_busy(ch->g); err = gk20a_busy(ch->g);
if (err) { if (err) {
@@ -1135,7 +1175,7 @@ long gk20a_channel_ioctl(struct file *filp,
gk20a_idle(ch->g); gk20a_idle(ch->g);
break; break;
} }
err = gk20a_channel_alloc_gpfifo(ch, &gpfifo_args); err = nvgpu_channel_setup_bind(ch, &setup_bind_args);
gk20a_idle(ch->g); gk20a_idle(ch->g);
break; break;
} }
@@ -1143,9 +1183,9 @@ long gk20a_channel_ioctl(struct file *filp,
{ {
struct nvgpu_alloc_gpfifo_args *alloc_gpfifo_args = struct nvgpu_alloc_gpfifo_args *alloc_gpfifo_args =
(struct nvgpu_alloc_gpfifo_args *)buf; (struct nvgpu_alloc_gpfifo_args *)buf;
struct nvgpu_gpfifo_args gpfifo_args; struct nvgpu_setup_bind_args setup_bind_args;
nvgpu_get_gpfifo_args(alloc_gpfifo_args, &gpfifo_args); nvgpu_get_gpfifo_args(alloc_gpfifo_args, &setup_bind_args);
err = gk20a_busy(ch->g); err = gk20a_busy(ch->g);
if (err) { if (err) {
@@ -1155,7 +1195,7 @@ long gk20a_channel_ioctl(struct file *filp,
break; break;
} }
err = gk20a_channel_alloc_gpfifo(ch, &gpfifo_args); err = nvgpu_channel_setup_bind(ch, &setup_bind_args);
gk20a_idle(ch->g); gk20a_idle(ch->g);
break; break;
} }

35
include/uapi/linux/nvgpu.h
View File

@@ -1468,22 +1468,32 @@ struct nvgpu_alloc_obj_ctx_args {
__u64 obj_id; /* output, used to free later */ __u64 obj_id; /* output, used to free later */
}; };
/* Deprecated. Use the SETUP_BIND IOCTL instead. */
struct nvgpu_alloc_gpfifo_args { struct nvgpu_alloc_gpfifo_args {
__u32 num_entries; __u32 num_entries;
#define NVGPU_ALLOC_GPFIFO_FLAGS_VPR_ENABLED (1 << 0) /* set owner channel of this gpfifo as a vpr channel */ #define NVGPU_ALLOC_GPFIFO_FLAGS_VPR_ENABLED (1 << 0)
/*
* this flag is used in struct nvgpu_alloc_gpfifo_args
* to enable re-playable faults for that channel
*/
#define NVGPU_ALLOC_GPFIFO_FLAGS_REPLAYABLE_FAULTS_ENABLE (1 << 2) #define NVGPU_ALLOC_GPFIFO_FLAGS_REPLAYABLE_FAULTS_ENABLE (1 << 2)
__u32 flags; __u32 flags;
}; };
/* Deprecated. Use the SETUP_BIND IOCTL instead. */
struct nvgpu_alloc_gpfifo_ex_args { struct nvgpu_alloc_gpfifo_ex_args {
__u32 num_entries; __u32 num_entries;
__u32 num_inflight_jobs; __u32 num_inflight_jobs;
/* Set owner channel of this gpfifo as a vpr channel. */
#define NVGPU_ALLOC_GPFIFO_EX_FLAGS_VPR_ENABLED (1 << 0) #define NVGPU_ALLOC_GPFIFO_EX_FLAGS_VPR_ENABLED (1 << 0)
#define NVGPU_ALLOC_GPFIFO_EX_FLAGS_DETERMINISTIC (1 << 1)
__u32 flags;
__u32 reserved[5];
};
/*
* Setup the channel and bind it (enable).
*/
struct nvgpu_channel_setup_bind_args {
__u32 num_gpfifo_entries;
__u32 num_inflight_jobs;
/* Set owner channel of this gpfifo as a vpr channel. */
#define NVGPU_CHANNEL_SETUP_BIND_FLAGS_VPR_ENABLED (1 << 0)
/* /*
* Channel shall exhibit deterministic behavior in the submit path. * Channel shall exhibit deterministic behavior in the submit path.
* *
@@ -1501,9 +1511,11 @@ struct nvgpu_alloc_gpfifo_ex_args {
* NVGPU_GPU_FLAGS_SUPPORT_DETERMINISTIC_SUBMIT_NO_JOBTRACKING; this flag or * NVGPU_GPU_FLAGS_SUPPORT_DETERMINISTIC_SUBMIT_NO_JOBTRACKING; this flag or
* num_inflight_jobs are not necessary in that case. * num_inflight_jobs are not necessary in that case.
*/ */
#define NVGPU_ALLOC_GPFIFO_EX_FLAGS_DETERMINISTIC (1 << 1) #define NVGPU_CHANNEL_SETUP_BIND_FLAGS_DETERMINISTIC (1 << 1)
/* enable replayable gmmu faults for this channel */
#define NVGPU_CHANNEL_SETUP_BIND_FLAGS_REPLAYABLE_FAULTS_ENABLE (1 << 2)
__u32 flags; __u32 flags;
__u32 reserved[5]; __u32 reserved[16];
}; };
struct nvgpu_fence { struct nvgpu_fence {
@@ -1763,10 +1775,13 @@ struct nvgpu_reschedule_runlist_args {
_IOR(NVGPU_IOCTL_MAGIC, 126, struct nvgpu_get_user_syncpoint_args) _IOR(NVGPU_IOCTL_MAGIC, 126, struct nvgpu_get_user_syncpoint_args)
#define NVGPU_IOCTL_CHANNEL_RESCHEDULE_RUNLIST \ #define NVGPU_IOCTL_CHANNEL_RESCHEDULE_RUNLIST \
_IOW(NVGPU_IOCTL_MAGIC, 127, struct nvgpu_reschedule_runlist_args) _IOW(NVGPU_IOCTL_MAGIC, 127, struct nvgpu_reschedule_runlist_args)
#define NVGPU_IOCTL_CHANNEL_SETUP_BIND \
_IOWR(NVGPU_IOCTL_MAGIC, 128, struct nvgpu_channel_setup_bind_args)
#define NVGPU_IOCTL_CHANNEL_LAST \ #define NVGPU_IOCTL_CHANNEL_LAST \
_IOC_NR(NVGPU_IOCTL_CHANNEL_RESCHEDULE_RUNLIST) _IOC_NR(NVGPU_IOCTL_CHANNEL_SETUP_BIND)
#define NVGPU_IOCTL_CHANNEL_MAX_ARG_SIZE sizeof(struct nvgpu_alloc_gpfifo_ex_args) #define NVGPU_IOCTL_CHANNEL_MAX_ARG_SIZE \
sizeof(struct nvgpu_channel_setup_bind_args)
/* /*
* /dev/nvhost-as-gpu device * /dev/nvhost-as-gpu device