From e0dd79cd435ce9f5db7423354ce9547480835f00 Mon Sep 17 00:00:00 2001
From: Vedashree Vidwans <vvidwans@nvidia.com>
Date: Fri, 4 Sep 2020 00:32:48 -0700
Subject: [PATCH] gpu: nvgpu: rearch mc reset and enable hals

Remove current mc hals
- mc.reset()
- mc.enable()
- mc.disable()
- mc.reset_mask()
- mc.reset_engine()
- mc.reset_engine_enable()

Add new mc hals
- mc.enable_units(g, units, enable)
  > enable/disable given unit(s)
- mc.enable_dev(g, dev, enable)
  > enable/disable engine represented by given device pointer
- mc.enable_devtype(g, devtype)
  > enable/disable all engines of given devtype

Move common mc intr functions to common/mc/mc_intr.c.
Add below common mc functions
- nvgpu_mc_reset_units(g, units)
  > reset given logical OR of nvgpu unit bitmap
- nvgpu_mc_reset_dev(g, dev)
  > reset given single engine via dev
  > if engine is graphics, reset gpcs for nvgpu_next
- nvgpu_mc_reset_devtype(g, devtype)
  > reset all engines of given devtype
  > if devtype is graphics, reset gpcs for nvgpu_next

Bug 200648985
Bug 3109773

Change-Id: Idc67a14a0a7cde83de44fbfbec13007fead3ed5c
Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2408523
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
---
 arch/nvgpu-common.yaml                        |   1 +
 drivers/gpu/nvgpu/Makefile                    |   1 +
 drivers/gpu/nvgpu/Makefile.sources            |   1 +
 drivers/gpu/nvgpu/common/ce/ce.c              |  21 +--
 drivers/gpu/nvgpu/common/fifo/engines.c       |  49 +-----
 drivers/gpu/nvgpu/common/gr/gr.c              |  56 +++----
 drivers/gpu/nvgpu/common/mc/mc.c              | 127 +++++---------
 drivers/gpu/nvgpu/common/mc/mc_intr.c         | 125 ++++++++++++++
 drivers/gpu/nvgpu/common/nvlink/nvlink.c      |   9 +-
 .../nvgpu/common/profiler/pm_reservation.c    |  14 +-
 drivers/gpu/nvgpu/hal/fb/fb_gv100.c           |   5 +-
 drivers/gpu/nvgpu/hal/fifo/fifo_gk20a.c       |   6 +-
 drivers/gpu/nvgpu/hal/fifo/fifo_gv11b_fusa.c  |   6 +-
 drivers/gpu/nvgpu/hal/init/hal_gm20b.c        |   7 +-
 drivers/gpu/nvgpu/hal/init/hal_gp10b.c        |   7 +-
 drivers/gpu/nvgpu/hal/init/hal_gv11b.c        |   8 +-
 drivers/gpu/nvgpu/hal/init/hal_tu104.c        |   7 +-
 drivers/gpu/nvgpu/hal/mc/mc_gm20b.c           |   3 +-
 drivers/gpu/nvgpu/hal/mc/mc_gm20b.h           |  20 +--
 drivers/gpu/nvgpu/hal/mc/mc_gm20b_fusa.c      | 155 ++++++++++++++----
 drivers/gpu/nvgpu/hal/mc/mc_gp10b.h           |   4 +-
 drivers/gpu/nvgpu/hal/mc/mc_gp10b_fusa.c      |   3 +-
 drivers/gpu/nvgpu/hal/mc/mc_gv100.c           |  53 +++++-
 drivers/gpu/nvgpu/hal/mc/mc_gv100.h           |   2 +-
 drivers/gpu/nvgpu/hal/pmu/pmu_gk20a.c         |   8 +-
 .../gpu/nvgpu/hal/vgpu/init/vgpu_hal_gp10b.c  |   7 +-
 .../gpu/nvgpu/hal/vgpu/init/vgpu_hal_gv11b.c  |   7 +-
 drivers/gpu/nvgpu/include/nvgpu/engines.h     |   8 -
 drivers/gpu/nvgpu/include/nvgpu/gk20a.h       |   1 -
 drivers/gpu/nvgpu/include/nvgpu/gops/mc.h     |  76 +--------
 drivers/gpu/nvgpu/include/nvgpu/mc.h          |  97 +++++++++--
 libs/dgpu/libnvgpu-drv-dgpu_safe.export       |   4 +-
 libs/igpu/libnvgpu-drv-igpu_safe.export       |   4 +-
 userspace/required_tests.ini                  |   1 -
 userspace/units/ce/nvgpu-ce.c                 |  12 +-
 userspace/units/mc/nvgpu-mc.c                 |  59 ++-----
 36 files changed, 557 insertions(+), 417 deletions(-)
 create mode 100644 drivers/gpu/nvgpu/common/mc/mc_intr.c

diff --git a/arch/nvgpu-common.yaml b/arch/nvgpu-common.yaml
index 33e51dcc7..78054da2f 100644
--- a/arch/nvgpu-common.yaml
+++ b/arch/nvgpu-common.yaml
@@ -135,6 +135,7 @@ mc:
   safe: yes
   owner: Seema K
   sources: [ common/mc/mc.c,
+             common/mc/mc_intr.c,
              include/nvgpu/mc.h,
              include/nvgpu/gops/mc.h ]
 class:
diff --git a/drivers/gpu/nvgpu/Makefile b/drivers/gpu/nvgpu/Makefile
index 22fbe3248..bd1be6c12 100644
--- a/drivers/gpu/nvgpu/Makefile
+++ b/drivers/gpu/nvgpu/Makefile
@@ -195,6 +195,7 @@ nvgpu-y += \
 	common/perf/perfbuf.o \
 	common/therm/therm.o \
 	common/mc/mc.o \
+	common/mc/mc_intr.o \
 	common/sync/channel_sync.o \
 	common/sync/channel_sync_semaphore.o \
 	common/semaphore/semaphore_sea.o \
diff --git a/drivers/gpu/nvgpu/Makefile.sources b/drivers/gpu/nvgpu/Makefile.sources
index d9ddb5cac..eefd8d35b 100644
--- a/drivers/gpu/nvgpu/Makefile.sources
+++ b/drivers/gpu/nvgpu/Makefile.sources
@@ -148,6 +148,7 @@ srcs +=	common/device.c \
 	common/fifo/engines.c \
 	common/fifo/pbdma_status.c \
 	common/mc/mc.c \
+	common/mc/mc_intr.c \
 	common/rc/rc.c \
 	common/ce/ce.c \
 	common/grmgr/grmgr.c \
diff --git a/drivers/gpu/nvgpu/common/ce/ce.c b/drivers/gpu/nvgpu/common/ce/ce.c
index 7de7fd6a6..2b149f3d5 100644
--- a/drivers/gpu/nvgpu/common/ce/ce.c
+++ b/drivers/gpu/nvgpu/common/ce/ce.c
@@ -30,30 +30,17 @@
 
 int nvgpu_ce_init_support(struct gk20a *g)
 {
-	u32 ce_reset_mask;
-#if defined(CONFIG_NVGPU_NON_FUSA) && defined(CONFIG_NVGPU_NEXT)
 	int err = 0;
-#endif
 
 	if (g->ops.ce.set_pce2lce_mapping != NULL) {
 		g->ops.ce.set_pce2lce_mapping(g);
 	}
 
-#if defined(CONFIG_NVGPU_NON_FUSA) && defined(CONFIG_NVGPU_NEXT)
-	if (g->ops.mc.reset_engine != NULL) {
-		err = nvgpu_next_mc_reset_engine(g, NVGPU_DEVTYPE_LCE);
-		if (err != 0) {
-			nvgpu_err(g, "NVGPU_ENGINE_GRCE reset failed");
-			return err;
-		}
-	} else {
-#endif
-	ce_reset_mask = nvgpu_engine_get_all_ce_reset_mask(g);
-
-	g->ops.mc.reset(g, ce_reset_mask);
-#if defined(CONFIG_NVGPU_NON_FUSA) && defined(CONFIG_NVGPU_NEXT)
+	err = nvgpu_mc_reset_devtype(g, NVGPU_DEVTYPE_LCE);
+	if (err != 0) {
+		nvgpu_err(g, "NVGPU_DEVTYPE_LCE reset failed");
+		return err;
 	}
-#endif
 
 	nvgpu_cg_slcg_ce2_load_enable(g);
 
diff --git a/drivers/gpu/nvgpu/common/fifo/engines.c b/drivers/gpu/nvgpu/common/fifo/engines.c
index e2fd844e4..6a3f3ce93 100644
--- a/drivers/gpu/nvgpu/common/fifo/engines.c
+++ b/drivers/gpu/nvgpu/common/fifo/engines.c
@@ -178,37 +178,6 @@ u32 nvgpu_ce_engine_interrupt_mask(struct gk20a *g)
 	return mask;
 }
 
-u32 nvgpu_engine_get_all_ce_reset_mask(struct gk20a *g)
-{
-	u32 mask = 0U;
-	const struct nvgpu_device *dev;
-	u32 i;
-
-	/*
-	 * Same principle as nvgpu_ce_engine_interrupt_mask.
-	 */
-	for (i = NVGPU_DEVTYPE_COPY0; i <= NVGPU_DEVTYPE_COPY2; i++) {
-		dev = nvgpu_device_get(g, i, i - NVGPU_DEVTYPE_COPY0);
-		if (dev == NULL) {
-			continue;
-		}
-
-		mask |= BIT32(dev->reset_id);
-	}
-
-	/*
-	 * Now take care of LCEs.
-	 */
-	for (i = 0U; i < nvgpu_device_count(g, NVGPU_DEVTYPE_LCE); i++) {
-		dev = nvgpu_device_get(g, NVGPU_DEVTYPE_LCE, i);
-		nvgpu_assert(dev != NULL);
-
-		mask |= BIT32(dev->reset_id);
-	}
-
-	return mask;
-}
-
 #ifdef CONFIG_NVGPU_FIFO_ENGINE_ACTIVITY
 
 static void nvgpu_engine_enable_activity(struct gk20a *g,
@@ -481,6 +450,7 @@ void nvgpu_engine_reset(struct gk20a *g, u32 engine_id)
 {
 	struct nvgpu_swprofiler *prof = &g->fifo.eng_reset_profiler;
 	const struct nvgpu_device *dev;
+	int err = 0;
 
 	nvgpu_log_fn(g, " ");
 
@@ -506,20 +476,11 @@ void nvgpu_engine_reset(struct gk20a *g, u32 engine_id)
 	 * Simple case first: reset a copy engine.
 	 */
 	if (nvgpu_device_is_ce(g, dev)) {
-#if !defined(CONFIG_NVGPU_NON_FUSA) || !defined(CONFIG_NVGPU_NEXT)
-		g->ops.mc.reset(g, BIT32(dev->reset_id));
-#else
-		int err = 0;
-
-		if (g->ops.mc.reset_engine != NULL) {
-			err = g->ops.mc.reset_engine(g, dev->type);
-			if (err != 0) {
-				nvgpu_err(g, "failed to reset ce engine");
-			}
-		} else {
-			g->ops.mc.reset(g, BIT32(dev->reset_id));
+		err = nvgpu_mc_reset_dev(g, dev);
+		if (err != 0) {
+			nvgpu_log_info(g, "CE engine [id:%u] reset failed",
+				dev->engine_id);
 		}
-#endif
 		return;
 	}
 
diff --git a/drivers/gpu/nvgpu/common/gr/gr.c b/drivers/gpu/nvgpu/common/gr/gr.c
index b57e9b797..4d47a6c0c 100644
--- a/drivers/gpu/nvgpu/common/gr/gr.c
+++ b/drivers/gpu/nvgpu/common/gr/gr.c
@@ -586,44 +586,42 @@ static int gr_init_prepare_hw(struct gk20a *g)
 
 static int gr_reset_engine(struct gk20a *g)
 {
-#if defined(CONFIG_NVGPU_NON_FUSA) && defined(CONFIG_NVGPU_NEXT)
 	int err;
+	const struct nvgpu_device *dev =
+		nvgpu_device_get(g, NVGPU_DEVTYPE_GRAPHICS,
+			nvgpu_gr_get_syspipe_id(g, g->mig.cur_gr_instance));
 
+	/* Reset GR engine: Disable then enable GR engine */
+	err = g->ops.mc.enable_dev(g, dev, false);
+	if (err != 0) {
+		nvgpu_log(g, gpu_dbg_info, "Device reset_id:%u disable failed",
+			dev->reset_id);
+		return err;
+	}
+
+#if defined(CONFIG_NVGPU_NON_FUSA) && defined(CONFIG_NVGPU_NEXT)
 	if (g->ops.gr.init.reset_gpcs != NULL) {
-		const struct nvgpu_device *dev =
-			nvgpu_device_get(g, NVGPU_DEVTYPE_GRAPHICS,
-				 nvgpu_gr_get_syspipe_id(g, g->mig.cur_gr_instance));
-
-		g->ops.mc.reset(g, g->ops.mc.reset_mask(g, NVGPU_UNIT_PERFMON));
-
-		err = g->ops.mc.reset_engine_enable(g, dev->reset_id, false);
-		if (err != 0) {
-			nvgpu_err(g, "GR reset disable failed");
-			return err;
-		}
-
 		err = g->ops.gr.init.reset_gpcs(g);
 		if (err != 0) {
-			nvgpu_err(g, "GR reset GPCs failed");
-			g->ops.mc.reset_engine_enable(g, dev->reset_id, true);
+			nvgpu_err(g, "Reset gpcs failed");
 			return err;
 		}
-
-		err = g->ops.mc.reset_engine_enable(g, dev->reset_id, true);
-		if (err != 0) {
-			nvgpu_err(g, "GR reset enable failed");
-			return err;
-		}
-	} else {
-#endif
-		/* reset gr engine */
-		g->ops.mc.reset(g, g->ops.mc.reset_mask(g, NVGPU_UNIT_GRAPH) |
-				g->ops.mc.reset_mask(g, NVGPU_UNIT_BLG) |
-				g->ops.mc.reset_mask(g, NVGPU_UNIT_PERFMON));
-
-#if defined(CONFIG_NVGPU_NON_FUSA) && defined(CONFIG_NVGPU_NEXT)
 	}
 #endif
+
+	err = g->ops.mc.enable_dev(g, dev, true);
+	if (err != 0) {
+		nvgpu_log(g, gpu_dbg_info, "Device reset_id:%u enable failed",
+			dev->reset_id);
+		return err;
+	}
+
+	err = nvgpu_mc_reset_units(g, NVGPU_UNIT_PERFMON | NVGPU_UNIT_BLG);
+	if (err != 0) {
+		nvgpu_log_info(g, "PERMON | BLG unit reset failed");
+		return err;
+	}
+
 	return 0;
 }
 
diff --git a/drivers/gpu/nvgpu/common/mc/mc.c b/drivers/gpu/nvgpu/common/mc/mc.c
index 148187a2b..6dbc33998 100644
--- a/drivers/gpu/nvgpu/common/mc/mc.c
+++ b/drivers/gpu/nvgpu/common/mc/mc.c
@@ -22,104 +22,63 @@
  * DEALINGS IN THE SOFTWARE.
  */
 
-#include <nvgpu/mc.h>
 #include <nvgpu/gk20a.h>
-#include <nvgpu/bug.h>
+#include <nvgpu/device.h>
+#include <nvgpu/mc.h>
 
-void nvgpu_wait_for_deferred_interrupts(struct gk20a *g)
+int nvgpu_mc_reset_units(struct gk20a *g, u32 units)
 {
-	/* wait until all stalling irqs are handled */
-	NVGPU_COND_WAIT(&g->mc.sw_irq_stall_last_handled_cond,
-			nvgpu_atomic_read(&g->mc.sw_irq_stall_pending) == 0,
-			0U);
+	int err;
 
-	/* wait until all non-stalling irqs are handled */
-	NVGPU_COND_WAIT(&g->mc.sw_irq_nonstall_last_handled_cond,
-			nvgpu_atomic_read(&g->mc.sw_irq_nonstall_pending) == 0,
-			0U);
-}
-
-void nvgpu_mc_intr_mask(struct gk20a *g)
-{
-	unsigned long flags = 0;
-
-	if (g->ops.mc.intr_mask != NULL) {
-		nvgpu_spinlock_irqsave(&g->mc.intr_lock, flags);
-		g->ops.mc.intr_mask(g);
-		nvgpu_spinunlock_irqrestore(&g->mc.intr_lock, flags);
+	err = g->ops.mc.enable_units(g, units, false);
+	if (err != 0) {
+		nvgpu_log(g, gpu_dbg_info, "Unit disable failed");
+		return err;
 	}
-}
 
-#ifdef CONFIG_NVGPU_NON_FUSA
-void nvgpu_mc_log_pending_intrs(struct gk20a *g)
-{
-	if (g->ops.mc.log_pending_intrs != NULL) {
-		g->ops.mc.log_pending_intrs(g);
+	err = g->ops.mc.enable_units(g, units, true);
+	if (err != 0) {
+		nvgpu_log(g, gpu_dbg_info, "Unit disable failed");
+		return err;
 	}
+	return 0;
 }
 
-void nvgpu_mc_intr_enable(struct gk20a *g)
+int nvgpu_mc_reset_dev(struct gk20a *g, const struct nvgpu_device *dev)
 {
-	unsigned long flags = 0;
+	int err;
 
-	if (g->ops.mc.intr_enable != NULL) {
-		nvgpu_spinlock_irqsave(&g->mc.intr_lock, flags);
-		g->ops.mc.intr_enable(g);
-		nvgpu_spinunlock_irqrestore(&g->mc.intr_lock, flags);
+	err = g->ops.mc.enable_dev(g, dev, false);
+	if (err != 0) {
+		nvgpu_device_dump_dev(g, dev);
+		return err;
 	}
-}
-#endif
 
-void nvgpu_mc_intr_stall_unit_config(struct gk20a *g, u32 unit, bool enable)
+	err = g->ops.mc.enable_dev(g, dev, true);
+	if (err != 0) {
+		nvgpu_device_dump_dev(g, dev);
+		return err;
+	}
+	return 0;
+}
+
+int nvgpu_mc_reset_devtype(struct gk20a *g, u32 devtype)
 {
-	unsigned long flags = 0;
+	int err;
 
-	nvgpu_spinlock_irqsave(&g->mc.intr_lock, flags);
-	g->ops.mc.intr_stall_unit_config(g, unit, enable);
-	nvgpu_spinunlock_irqrestore(&g->mc.intr_lock, flags);
+	err = g->ops.mc.enable_devtype(g, devtype, false);
+	if (err != 0) {
+		nvgpu_log(g, gpu_dbg_info, "Devtype:%u disable failed",
+			devtype);
+		return err;
+	}
+
+	err = g->ops.mc.enable_devtype(g, devtype, true);
+	if (err != 0) {
+		nvgpu_log(g, gpu_dbg_info, "Devtype:%u enable failed",
+			devtype);
+		return err;
+	}
+	return 0;
 }
 
-void nvgpu_mc_intr_nonstall_unit_config(struct gk20a *g, u32 unit, bool enable)
-{
-	unsigned long flags = 0;
-
-	nvgpu_spinlock_irqsave(&g->mc.intr_lock, flags);
-	g->ops.mc.intr_nonstall_unit_config(g, unit, enable);
-	nvgpu_spinunlock_irqrestore(&g->mc.intr_lock, flags);
-}
-
-void nvgpu_mc_intr_stall_pause(struct gk20a *g)
-{
-	unsigned long flags = 0;
-
-	nvgpu_spinlock_irqsave(&g->mc.intr_lock, flags);
-	g->ops.mc.intr_stall_pause(g);
-	nvgpu_spinunlock_irqrestore(&g->mc.intr_lock, flags);
-}
-
-void nvgpu_mc_intr_stall_resume(struct gk20a *g)
-{
-	unsigned long flags = 0;
-
-	nvgpu_spinlock_irqsave(&g->mc.intr_lock, flags);
-	g->ops.mc.intr_stall_resume(g);
-	nvgpu_spinunlock_irqrestore(&g->mc.intr_lock, flags);
-}
-
-void nvgpu_mc_intr_nonstall_pause(struct gk20a *g)
-{
-	unsigned long flags = 0;
-
-	nvgpu_spinlock_irqsave(&g->mc.intr_lock, flags);
-	g->ops.mc.intr_nonstall_pause(g);
-	nvgpu_spinunlock_irqrestore(&g->mc.intr_lock, flags);
-}
-
-void nvgpu_mc_intr_nonstall_resume(struct gk20a *g)
-{
-	unsigned long flags = 0;
-
-	nvgpu_spinlock_irqsave(&g->mc.intr_lock, flags);
-	g->ops.mc.intr_nonstall_resume(g);
-	nvgpu_spinunlock_irqrestore(&g->mc.intr_lock, flags);
-}
diff --git a/drivers/gpu/nvgpu/common/mc/mc_intr.c b/drivers/gpu/nvgpu/common/mc/mc_intr.c
new file mode 100644
index 000000000..8d5ff1794
--- /dev/null
+++ b/drivers/gpu/nvgpu/common/mc/mc_intr.c
@@ -0,0 +1,125 @@
+/*
+ * GK20A Master Interrupt Control
+ *
+ * Copyright (c) 2014-2020, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#include <nvgpu/mc.h>
+#include <nvgpu/gk20a.h>
+#include <nvgpu/bug.h>
+
+void nvgpu_wait_for_deferred_interrupts(struct gk20a *g)
+{
+	/* wait until all stalling irqs are handled */
+	NVGPU_COND_WAIT(&g->mc.sw_irq_stall_last_handled_cond,
+			nvgpu_atomic_read(&g->mc.sw_irq_stall_pending) == 0,
+			0U);
+
+	/* wait until all non-stalling irqs are handled */
+	NVGPU_COND_WAIT(&g->mc.sw_irq_nonstall_last_handled_cond,
+			nvgpu_atomic_read(&g->mc.sw_irq_nonstall_pending) == 0,
+			0U);
+}
+
+void nvgpu_mc_intr_mask(struct gk20a *g)
+{
+	unsigned long flags = 0;
+
+	if (g->ops.mc.intr_mask != NULL) {
+		nvgpu_spinlock_irqsave(&g->mc.intr_lock, flags);
+		g->ops.mc.intr_mask(g);
+		nvgpu_spinunlock_irqrestore(&g->mc.intr_lock, flags);
+	}
+}
+
+#ifdef CONFIG_NVGPU_NON_FUSA
+void nvgpu_mc_log_pending_intrs(struct gk20a *g)
+{
+	if (g->ops.mc.log_pending_intrs != NULL) {
+		g->ops.mc.log_pending_intrs(g);
+	}
+}
+
+void nvgpu_mc_intr_enable(struct gk20a *g)
+{
+	unsigned long flags = 0;
+
+	if (g->ops.mc.intr_enable != NULL) {
+		nvgpu_spinlock_irqsave(&g->mc.intr_lock, flags);
+		g->ops.mc.intr_enable(g);
+		nvgpu_spinunlock_irqrestore(&g->mc.intr_lock, flags);
+	}
+}
+#endif
+
+void nvgpu_mc_intr_stall_unit_config(struct gk20a *g, u32 unit, bool enable)
+{
+	unsigned long flags = 0;
+
+	nvgpu_spinlock_irqsave(&g->mc.intr_lock, flags);
+	g->ops.mc.intr_stall_unit_config(g, unit, enable);
+	nvgpu_spinunlock_irqrestore(&g->mc.intr_lock, flags);
+}
+
+void nvgpu_mc_intr_nonstall_unit_config(struct gk20a *g, u32 unit, bool enable)
+{
+	unsigned long flags = 0;
+
+	nvgpu_spinlock_irqsave(&g->mc.intr_lock, flags);
+	g->ops.mc.intr_nonstall_unit_config(g, unit, enable);
+	nvgpu_spinunlock_irqrestore(&g->mc.intr_lock, flags);
+}
+
+void nvgpu_mc_intr_stall_pause(struct gk20a *g)
+{
+	unsigned long flags = 0;
+
+	nvgpu_spinlock_irqsave(&g->mc.intr_lock, flags);
+	g->ops.mc.intr_stall_pause(g);
+	nvgpu_spinunlock_irqrestore(&g->mc.intr_lock, flags);
+}
+
+void nvgpu_mc_intr_stall_resume(struct gk20a *g)
+{
+	unsigned long flags = 0;
+
+	nvgpu_spinlock_irqsave(&g->mc.intr_lock, flags);
+	g->ops.mc.intr_stall_resume(g);
+	nvgpu_spinunlock_irqrestore(&g->mc.intr_lock, flags);
+}
+
+void nvgpu_mc_intr_nonstall_pause(struct gk20a *g)
+{
+	unsigned long flags = 0;
+
+	nvgpu_spinlock_irqsave(&g->mc.intr_lock, flags);
+	g->ops.mc.intr_nonstall_pause(g);
+	nvgpu_spinunlock_irqrestore(&g->mc.intr_lock, flags);
+}
+
+void nvgpu_mc_intr_nonstall_resume(struct gk20a *g)
+{
+	unsigned long flags = 0;
+
+	nvgpu_spinlock_irqsave(&g->mc.intr_lock, flags);
+	g->ops.mc.intr_nonstall_resume(g);
+	nvgpu_spinunlock_irqrestore(&g->mc.intr_lock, flags);
+}
diff --git a/drivers/gpu/nvgpu/common/nvlink/nvlink.c b/drivers/gpu/nvgpu/common/nvlink/nvlink.c
index 07685226e..1c18ab88a 100644
--- a/drivers/gpu/nvgpu/common/nvlink/nvlink.c
+++ b/drivers/gpu/nvgpu/common/nvlink/nvlink.c
@@ -210,7 +210,6 @@ static int nvgpu_nvlink_discover_ioctrl(struct gk20a *g)
 int nvgpu_nvlink_early_init(struct gk20a *g)
 {
 	int err = 0;
-	u32 mc_reset_nvlink_mask;
 
 	if (!nvgpu_is_enabled(g, NVGPU_SUPPORT_NVLINK)) {
 		return -EINVAL;
@@ -228,10 +227,12 @@ int nvgpu_nvlink_early_init(struct gk20a *g)
 	}
 
 	/* Enable NVLINK in MC */
-	mc_reset_nvlink_mask = BIT32(g->nvlink.ioctrl_table[0].reset_enum);
 	nvgpu_log(g, gpu_dbg_nvlink, "mc_reset_nvlink_mask: 0x%x",
-							mc_reset_nvlink_mask);
-	g->ops.mc.reset(g, mc_reset_nvlink_mask);
+			BIT32(g->nvlink.ioctrl_table[0].reset_enum));
+	err = nvgpu_mc_reset_units(g, NVGPU_UNIT_NVLINK);
+	if (err != 0) {
+		nvgpu_err(g, "Failed to reset NVLINK unit");
+	}
 
 	nvgpu_mc_intr_stall_unit_config(g, MC_INTR_UNIT_NVLINK,
 					MC_INTR_ENABLE);
diff --git a/drivers/gpu/nvgpu/common/profiler/pm_reservation.c b/drivers/gpu/nvgpu/common/profiler/pm_reservation.c
index 74b79c277..dfe0f46b2 100644
--- a/drivers/gpu/nvgpu/common/profiler/pm_reservation.c
+++ b/drivers/gpu/nvgpu/common/profiler/pm_reservation.c
@@ -31,6 +31,8 @@
 static void prepare_resource_reservation(struct gk20a *g,
 		enum nvgpu_profiler_pm_resource_type pm_resource, bool acquire)
 {
+	int err;
+
 	if ((pm_resource != NVGPU_PROFILER_PM_RESOURCE_TYPE_HWPM_LEGACY) &&
 	    (pm_resource != NVGPU_PROFILER_PM_RESOURCE_TYPE_PMA_STREAM)) {
 		return;
@@ -44,8 +46,10 @@ static void prepare_resource_reservation(struct gk20a *g,
 		if (nvgpu_atomic_read(&g->hwpm_refcount) == 1) {
 			nvgpu_log(g, gpu_dbg_prof,
 				"Trigger HWPM system reset, disable perf SLCG");
-			g->ops.mc.reset(g, g->ops.mc.reset_mask(g,
-				NVGPU_UNIT_PERFMON));
+			err = nvgpu_mc_reset_units(g, NVGPU_UNIT_PERFMON);
+			if (err != 0) {
+				nvgpu_err(g, "Failed to reset PERFMON unit");
+			}
 			nvgpu_cg_slcg_perf_load_enable(g, false);
 		}
 	} else {
@@ -56,8 +60,10 @@ static void prepare_resource_reservation(struct gk20a *g,
 		if (nvgpu_atomic_read(&g->hwpm_refcount) == 0) {
 			nvgpu_log(g, gpu_dbg_prof,
 				"Trigger HWPM system reset, re-enable perf SLCG");
-			g->ops.mc.reset(g, g->ops.mc.reset_mask(g,
-				NVGPU_UNIT_PERFMON));
+			err = nvgpu_mc_reset_units(g, NVGPU_UNIT_PERFMON);
+			if (err != 0) {
+				nvgpu_err(g, "Failed to reset PERFMON unit");
+			}
 			nvgpu_cg_slcg_perf_load_enable(g, true);
 		}
 	}
diff --git a/drivers/gpu/nvgpu/hal/fb/fb_gv100.c b/drivers/gpu/nvgpu/hal/fb/fb_gv100.c
index b41151b2c..4ad43ca83 100644
--- a/drivers/gpu/nvgpu/hal/fb/fb_gv100.c
+++ b/drivers/gpu/nvgpu/hal/fb/fb_gv100.c
@@ -152,7 +152,10 @@ int gv100_fb_memory_unlock(struct gk20a *g)
 	}
 
 	/* Enable nvdec */
-	g->ops.mc.enable(g, g->ops.mc.reset_mask(g, NVGPU_UNIT_NVDEC));
+	err = nvgpu_mc_reset_units(g, NVGPU_UNIT_NVDEC);
+	if (err != 0) {
+		nvgpu_err(g, "Failed to reset NVDEC unit");
+	}
 
 	hs_bin_hdr = (struct mem_unlock_bin_hdr *)(void *)mem_unlock_fw->data;
 	fw_hdr = (struct mem_unlock_fw_header *)(void *)(mem_unlock_fw->data +
diff --git a/drivers/gpu/nvgpu/hal/fifo/fifo_gk20a.c b/drivers/gpu/nvgpu/hal/fifo/fifo_gk20a.c
index b0586d7a5..c8dc22e64 100644
--- a/drivers/gpu/nvgpu/hal/fifo/fifo_gk20a.c
+++ b/drivers/gpu/nvgpu/hal/fifo/fifo_gk20a.c
@@ -46,11 +46,15 @@ static void enable_fifo_interrupts(struct gk20a *g)
 int gk20a_init_fifo_reset_enable_hw(struct gk20a *g)
 {
 	u32 timeout;
+	int err;
 
 	nvgpu_log_fn(g, " ");
 
 	/* enable pmc pfifo */
-	g->ops.mc.reset(g, g->ops.mc.reset_mask(g, NVGPU_UNIT_FIFO));
+	err = nvgpu_mc_reset_units(g, NVGPU_UNIT_FIFO);
+	if (err != 0) {
+		nvgpu_err(g, "Failed to reset FIFO unit");
+	}
 
 	nvgpu_cg_slcg_fifo_load_enable(g);
 
diff --git a/drivers/gpu/nvgpu/hal/fifo/fifo_gv11b_fusa.c b/drivers/gpu/nvgpu/hal/fifo/fifo_gv11b_fusa.c
index ac24049e7..a12de86fc 100644
--- a/drivers/gpu/nvgpu/hal/fifo/fifo_gv11b_fusa.c
+++ b/drivers/gpu/nvgpu/hal/fifo/fifo_gv11b_fusa.c
@@ -49,11 +49,15 @@ static void enable_fifo_interrupts(struct gk20a *g)
 int gv11b_init_fifo_reset_enable_hw(struct gk20a *g)
 {
 	u32 timeout;
+	int err;
 
 	nvgpu_log_fn(g, " ");
 
 	/* enable pmc pfifo */
-	g->ops.mc.reset(g, g->ops.mc.reset_mask(g, NVGPU_UNIT_FIFO));
+	err = nvgpu_mc_reset_units(g, NVGPU_UNIT_FIFO);
+	if (err != 0) {
+		nvgpu_err(g, "Failed to reset FIFO unit");
+	}
 
 	nvgpu_cg_slcg_ce2_load_enable(g);
 
diff --git a/drivers/gpu/nvgpu/hal/init/hal_gm20b.c b/drivers/gpu/nvgpu/hal/init/hal_gm20b.c
index b83114098..2d8e64eb8 100644
--- a/drivers/gpu/nvgpu/hal/init/hal_gm20b.c
+++ b/drivers/gpu/nvgpu/hal/init/hal_gm20b.c
@@ -884,12 +884,11 @@ static const struct gops_mc gm20b_ops_mc = {
 	.intr_nonstall_pause = gm20b_mc_intr_nonstall_pause,
 	.intr_nonstall_resume = gm20b_mc_intr_nonstall_resume,
 	.isr_nonstall = gm20b_mc_isr_nonstall,
-	.enable = gm20b_mc_enable,
-	.disable = gm20b_mc_disable,
-	.reset = gm20b_mc_reset,
 	.is_intr1_pending = gm20b_mc_is_intr1_pending,
 	.log_pending_intrs = gm20b_mc_log_pending_intrs,
-	.reset_mask = gm20b_mc_reset_mask,
+	.enable_units = gm20b_mc_enable_units,
+	.enable_dev = gm20b_mc_enable_dev,
+	.enable_devtype = gm20b_mc_enable_devtype,
 #ifdef CONFIG_NVGPU_LS_PMU
 	.is_enabled = gm20b_mc_is_enabled,
 #endif
diff --git a/drivers/gpu/nvgpu/hal/init/hal_gp10b.c b/drivers/gpu/nvgpu/hal/init/hal_gp10b.c
index d89c89ada..c33eea15a 100644
--- a/drivers/gpu/nvgpu/hal/init/hal_gp10b.c
+++ b/drivers/gpu/nvgpu/hal/init/hal_gp10b.c
@@ -969,12 +969,11 @@ static const struct gops_mc gp10b_ops_mc = {
 	.intr_nonstall_pause = mc_gp10b_intr_nonstall_pause,
 	.intr_nonstall_resume = mc_gp10b_intr_nonstall_resume,
 	.isr_nonstall = gm20b_mc_isr_nonstall,
-	.enable = gm20b_mc_enable,
-	.disable = gm20b_mc_disable,
-	.reset = gm20b_mc_reset,
 	.is_intr1_pending = mc_gp10b_is_intr1_pending,
 	.log_pending_intrs = mc_gp10b_log_pending_intrs,
-	.reset_mask = gm20b_mc_reset_mask,
+	.enable_units = gm20b_mc_enable_units,
+	.enable_dev = gm20b_mc_enable_dev,
+	.enable_devtype = gm20b_mc_enable_devtype,
 #ifdef CONFIG_NVGPU_LS_PMU
 	.is_enabled = gm20b_mc_is_enabled,
 #endif
diff --git a/drivers/gpu/nvgpu/hal/init/hal_gv11b.c b/drivers/gpu/nvgpu/hal/init/hal_gv11b.c
index 236fb0ba9..45f60296b 100644
--- a/drivers/gpu/nvgpu/hal/init/hal_gv11b.c
+++ b/drivers/gpu/nvgpu/hal/init/hal_gv11b.c
@@ -1181,16 +1181,16 @@ static const struct gops_mc gv11b_ops_mc = {
 	.intr_nonstall_pause = mc_gp10b_intr_nonstall_pause,
 	.intr_nonstall_resume = mc_gp10b_intr_nonstall_resume,
 	.isr_nonstall = gm20b_mc_isr_nonstall,
-	.enable = gm20b_mc_enable,
-	.disable = gm20b_mc_disable,
-	.reset = gm20b_mc_reset,
 	.is_intr1_pending = mc_gp10b_is_intr1_pending,
+	.enable_units = gm20b_mc_enable_units,
+	.enable_dev = gm20b_mc_enable_dev,
+	.enable_devtype = gm20b_mc_enable_devtype,
 #ifdef CONFIG_NVGPU_NON_FUSA
 	.log_pending_intrs = mc_gp10b_log_pending_intrs,
 #endif
 	.is_intr_hub_pending = gv11b_mc_is_intr_hub_pending,
 	.is_stall_and_eng_intr_pending = gv11b_mc_is_stall_and_eng_intr_pending,
-	.reset_mask = gm20b_mc_reset_mask,
+
 #ifdef CONFIG_NVGPU_LS_PMU
 	.is_enabled = gm20b_mc_is_enabled,
 #endif
diff --git a/drivers/gpu/nvgpu/hal/init/hal_tu104.c b/drivers/gpu/nvgpu/hal/init/hal_tu104.c
index 419571039..98878596b 100644
--- a/drivers/gpu/nvgpu/hal/init/hal_tu104.c
+++ b/drivers/gpu/nvgpu/hal/init/hal_tu104.c
@@ -1245,9 +1245,6 @@ static const struct gops_mc tu104_ops_mc = {
 	.intr_nonstall_pause = intr_tu104_nonstall_pause,
 	.intr_nonstall_resume = intr_tu104_nonstall_resume,
 	.isr_nonstall = intr_tu104_isr_nonstall,
-	.enable = gm20b_mc_enable,
-	.disable = gm20b_mc_disable,
-	.reset = gm20b_mc_reset,
 	.is_intr1_pending = NULL,
 #ifdef CONFIG_NVGPU_NON_FUSA
 	.log_pending_intrs = intr_tu104_log_pending_intrs,
@@ -1256,7 +1253,9 @@ static const struct gops_mc tu104_ops_mc = {
 	.is_intr_nvlink_pending = gv100_mc_is_intr_nvlink_pending,
 	.is_stall_and_eng_intr_pending = gv100_mc_is_stall_and_eng_intr_pending,
 	.fbpa_isr = mc_tu104_fbpa_isr,
-	.reset_mask = gv100_mc_reset_mask,
+	.enable_units = gv100_mc_enable_units,
+	.enable_dev = gm20b_mc_enable_dev,
+	.enable_devtype = gm20b_mc_enable_devtype,
 #ifdef CONFIG_NVGPU_LS_PMU
 	.is_enabled = gm20b_mc_is_enabled,
 #endif
diff --git a/drivers/gpu/nvgpu/hal/mc/mc_gm20b.c b/drivers/gpu/nvgpu/hal/mc/mc_gm20b.c
index 7636e602e..9ee52325c 100644
--- a/drivers/gpu/nvgpu/hal/mc/mc_gm20b.c
+++ b/drivers/gpu/nvgpu/hal/mc/mc_gm20b.c
@@ -212,8 +212,7 @@ u32 gm20b_mc_intr_nonstall(struct gk20a *g)
 	return nvgpu_readl(g, mc_intr_r(NVGPU_MC_INTR_NONSTALLING));
 }
 
-bool gm20b_mc_is_intr1_pending(struct gk20a *g,
-			       enum nvgpu_unit unit, u32 mc_intr_1)
+bool gm20b_mc_is_intr1_pending(struct gk20a *g, u32 unit, u32 mc_intr_1)
 {
 	u32 mask;
 	bool is_pending;
diff --git a/drivers/gpu/nvgpu/hal/mc/mc_gm20b.h b/drivers/gpu/nvgpu/hal/mc/mc_gm20b.h
index 75c32a249..14c7baa93 100644
--- a/drivers/gpu/nvgpu/hal/mc/mc_gm20b.h
+++ b/drivers/gpu/nvgpu/hal/mc/mc_gm20b.h
@@ -25,22 +25,19 @@
 
 #include <nvgpu/types.h>
 
-#define MC_ENABLE_DELAY_US	20U
-#define MC_RESET_DELAY_US	20U
-#define MC_RESET_CE_DELAY_US	500U
-
 struct gk20a;
-enum nvgpu_unit;
+struct nvgpu_device;
 
 u32 gm20b_get_chip_details(struct gk20a *g, u32 *arch, u32 *impl, u32 *rev);
 
 u32  gm20b_mc_isr_nonstall(struct gk20a *g);
-void gm20b_mc_enable(struct gk20a *g, u32 units);
-void gm20b_mc_disable(struct gk20a *g, u32 units);
-void gm20b_mc_reset(struct gk20a *g, u32 units);
-u32  gm20b_mc_reset_mask(struct gk20a *g, enum nvgpu_unit unit);
+int gm20b_mc_enable_units(struct gk20a *g, u32 units, bool enable);
+int gm20b_mc_enable_dev(struct gk20a *g, const struct nvgpu_device *dev,
+			bool enable);
+int gm20b_mc_enable_devtype(struct gk20a *g, u32 devtype, bool enable);
+
 #ifdef CONFIG_NVGPU_LS_PMU
-bool gm20b_mc_is_enabled(struct gk20a *g, enum nvgpu_unit unit);
+bool gm20b_mc_is_enabled(struct gk20a *g, u32 unit);
 #endif
 
 #ifdef CONFIG_NVGPU_HAL_NON_FUSA
@@ -57,8 +54,7 @@ void gm20b_mc_intr_stall_resume(struct gk20a *g);
 u32  gm20b_mc_intr_nonstall(struct gk20a *g);
 void gm20b_mc_intr_nonstall_pause(struct gk20a *g);
 void gm20b_mc_intr_nonstall_resume(struct gk20a *g);
-bool gm20b_mc_is_intr1_pending(struct gk20a *g,
-		enum nvgpu_unit unit, u32 mc_intr_1);
+bool gm20b_mc_is_intr1_pending(struct gk20a *g, u32 unit, u32 mc_intr_1);
 void gm20b_mc_log_pending_intrs(struct gk20a *g);
 void gm20b_mc_fb_reset(struct gk20a *g);
 void gm20b_mc_ltc_isr(struct gk20a *g);
diff --git a/drivers/gpu/nvgpu/hal/mc/mc_gm20b_fusa.c b/drivers/gpu/nvgpu/hal/mc/mc_gm20b_fusa.c
index a8eea958e..077e1a22d 100644
--- a/drivers/gpu/nvgpu/hal/mc/mc_gm20b_fusa.c
+++ b/drivers/gpu/nvgpu/hal/mc/mc_gm20b_fusa.c
@@ -96,47 +96,33 @@ u32 gm20b_mc_isr_nonstall(struct gk20a *g)
 	return ops;
 }
 
-void gm20b_mc_disable(struct gk20a *g, u32 units)
+static int gm20b_mc_enable(struct gk20a *g, u32 mask, bool enable)
 {
-	u32 pmc;
-
-	nvgpu_log(g, gpu_dbg_info, "pmc disable: %08x", units);
+	u32 mc_enable_val = 0U;
+	u32 reg_val = 0U;
 
 	nvgpu_spinlock_acquire(&g->mc.enable_lock);
-	pmc = nvgpu_readl(g, mc_enable_r());
-	pmc &= ~units;
-	nvgpu_writel(g, mc_enable_r(), pmc);
-	nvgpu_spinlock_release(&g->mc.enable_lock);
-}
-
-void gm20b_mc_enable(struct gk20a *g, u32 units)
-{
-	u32 pmc;
-
-	nvgpu_log(g, gpu_dbg_info, "pmc enable: %08x", units);
-
-	nvgpu_spinlock_acquire(&g->mc.enable_lock);
-	pmc = nvgpu_readl(g, mc_enable_r());
-	pmc |= units;
-	nvgpu_writel(g, mc_enable_r(), pmc);
-	pmc = nvgpu_readl(g, mc_enable_r());
+	reg_val = nvgpu_readl(g, mc_enable_r());
+	if (enable) {
+		mc_enable_val = reg_val | mask;
+	} else {
+		mc_enable_val = reg_val & (~mask);
+	}
+	nvgpu_writel(g, mc_enable_r(), mc_enable_val);
+	reg_val = nvgpu_readl(g, mc_enable_r());
 	nvgpu_spinlock_release(&g->mc.enable_lock);
 
 	nvgpu_udelay(MC_ENABLE_DELAY_US);
-}
 
-void gm20b_mc_reset(struct gk20a *g, u32 units)
-{
-	g->ops.mc.disable(g, units);
-	if ((units & nvgpu_engine_get_all_ce_reset_mask(g)) != 0U) {
-		nvgpu_udelay(MC_RESET_CE_DELAY_US);
-	} else {
-		nvgpu_udelay(MC_RESET_DELAY_US);
+	if (reg_val != mc_enable_val) {
+		nvgpu_err(g, "Failed to %s mc_enable mask = 0x%08x",
+			(enable ? "enable" : "disable"), mask);
+		return -EINVAL;
 	}
-	g->ops.mc.enable(g, units);
+	return 0U;
 }
 
-u32 gm20b_mc_reset_mask(struct gk20a *g, enum nvgpu_unit unit)
+static u32 gm20b_mc_unit_reset_mask(struct gk20a *g, u32 unit)
 {
 	u32 mask = 0U;
 
@@ -158,6 +144,12 @@ u32 gm20b_mc_reset_mask(struct gk20a *g, enum nvgpu_unit unit)
 		mask = mc_enable_pwr_enabled_f();
 		break;
 #endif
+	case NVGPU_UNIT_NVLINK:
+		mask = BIT32(g->nvlink.ioctrl_table[0].reset_enum);
+		break;
+	case NVGPU_UNIT_CE2:
+		mask = mc_enable_ce2_enabled_f();
+		break;
 	default:
 		WARN(true, "unknown reset unit %d", unit);
 		break;
@@ -166,10 +158,105 @@ u32 gm20b_mc_reset_mask(struct gk20a *g, enum nvgpu_unit unit)
 	return mask;
 }
 
-#ifdef CONFIG_NVGPU_LS_PMU
-bool gm20b_mc_is_enabled(struct gk20a *g, enum nvgpu_unit unit)
+static u32 gm20b_mc_get_unit_reset_mask(struct gk20a *g, u32 units)
 {
-	u32 mask = g->ops.mc.reset_mask(g, unit);
+	u32 mask = 0U;
+	unsigned long i = 0U;
+	unsigned long units_bitmask = units;
+
+	for_each_set_bit(i, &units_bitmask, 32U) {
+		mask |= gm20b_mc_unit_reset_mask(g, BIT32(i));
+	}
+	return mask;
+}
+
+int gm20b_mc_enable_units(struct gk20a *g, u32 units, bool enable)
+{
+	int err = 0;
+	u32 mask = gm20b_mc_get_unit_reset_mask(g, units);
+
+	nvgpu_log(g, gpu_dbg_info, "%s units: mc_enable mask = 0x%08x",
+			(enable ? "enable" : "disable"), mask);
+	if (enable) {
+		nvgpu_udelay(MC_RESET_DELAY_US);
+	}
+
+	err = gm20b_mc_enable(g, mask, enable);
+	if (err != 0) {
+		nvgpu_err(g, "Failed to %s units: mc_enable mask = 0x%08x",
+			(enable ? "enable" : "disable"), mask);
+	}
+	return err;
+}
+
+int gm20b_mc_enable_dev(struct gk20a *g, const struct nvgpu_device *dev,
+			bool enable)
+{
+	int err = 0;
+
+	nvgpu_log(g, gpu_dbg_info, "%s device: mc_enable mask = 0x%08x",
+			(enable ? "enable" : "disable"), BIT32(dev->reset_id));
+	if (enable) {
+		nvgpu_udelay(MC_RESET_DELAY_US);
+	}
+
+	err = gm20b_mc_enable(g, BIT32(dev->reset_id), enable);
+	if (err != 0) {
+		nvgpu_err(g, "Failed to %s device: mc_enable mask = 0x%08x",
+			(enable ? "enable" : "disable"), BIT32(dev->reset_id));
+	}
+	return err;
+}
+
+static u32 gm20b_mc_get_devtype_reset_mask(struct gk20a *g, u32 devtype)
+{
+	u32 mask = 0U;
+	const struct nvgpu_device *dev = NULL;
+
+	nvgpu_device_for_each(g, dev, devtype) {
+		mask |= BIT32(dev->reset_id);
+	}
+
+	if (devtype == NVGPU_DEVTYPE_LCE) {
+		nvgpu_device_for_each(g, dev, NVGPU_DEVTYPE_COPY0) {
+			mask |= BIT32(dev->reset_id);
+		}
+		nvgpu_device_for_each(g, dev, NVGPU_DEVTYPE_COPY1) {
+			mask |= BIT32(dev->reset_id);
+		}
+		nvgpu_device_for_each(g, dev, NVGPU_DEVTYPE_COPY2) {
+			mask |= BIT32(dev->reset_id);
+		}
+	}
+	return mask;
+}
+
+int gm20b_mc_enable_devtype(struct gk20a *g, u32 devtype, bool enable)
+{
+	int err = 0;
+	u32 mask = gm20b_mc_get_devtype_reset_mask(g, devtype);
+
+	nvgpu_log(g, gpu_dbg_info, "%s devtype %u: mc_enable mask = 0x%08x",
+			(enable ? "enable" : "disable"), devtype, mask);
+
+	if (enable && (devtype == NVGPU_DEVTYPE_LCE)) {
+		nvgpu_udelay(MC_RESET_CE_DELAY_US);
+	} else {
+		nvgpu_udelay(MC_RESET_DELAY_US);
+	}
+
+	err = gm20b_mc_enable(g, mask, enable);
+	if (err != 0) {
+		nvgpu_err(g, "Failed to %s devtype %u: mc_enable mask = 0x%08x",
+			(enable ? "enable" : "disable"), devtype, mask);
+	}
+	return err;
+}
+
+#ifdef CONFIG_NVGPU_LS_PMU
+bool gm20b_mc_is_enabled(struct gk20a *g, u32 unit)
+{
+	u32 mask = gm20b_mc_unit_reset_mask(g, unit);
 
 	return (nvgpu_readl(g, mc_enable_r()) & mask) != 0U;
 }
diff --git a/drivers/gpu/nvgpu/hal/mc/mc_gp10b.h b/drivers/gpu/nvgpu/hal/mc/mc_gp10b.h
index 80da0e540..964b46d0f 100644
--- a/drivers/gpu/nvgpu/hal/mc/mc_gp10b.h
+++ b/drivers/gpu/nvgpu/hal/mc/mc_gp10b.h
@@ -31,7 +31,6 @@
 
 struct gk20a;
 struct nvgpu_device;
-enum nvgpu_unit;
 enum nvgpu_fifo_engine;
 
 void mc_gp10b_intr_mask(struct gk20a *g);
@@ -41,8 +40,7 @@ void mc_gp10b_isr_stall_secondary_1(struct gk20a *g, u32 mc_intr_0);
 void mc_gp10b_isr_stall_secondary_0(struct gk20a *g, u32 mc_intr_0);
 void mc_gp10b_isr_stall_engine(struct gk20a *g, const struct nvgpu_device *dev);
 void mc_gp10b_isr_stall(struct gk20a *g);
-bool mc_gp10b_is_intr1_pending(struct gk20a *g,
-				      enum nvgpu_unit unit, u32 mc_intr_1);
+bool mc_gp10b_is_intr1_pending(struct gk20a *g, u32 unit, u32 mc_intr_1);
 
 #ifdef CONFIG_NVGPU_NON_FUSA
 void mc_gp10b_log_pending_intrs(struct gk20a *g);
diff --git a/drivers/gpu/nvgpu/hal/mc/mc_gp10b_fusa.c b/drivers/gpu/nvgpu/hal/mc/mc_gp10b_fusa.c
index 22c63fc98..88a6cc026 100644
--- a/drivers/gpu/nvgpu/hal/mc/mc_gp10b_fusa.c
+++ b/drivers/gpu/nvgpu/hal/mc/mc_gp10b_fusa.c
@@ -238,8 +238,7 @@ void mc_gp10b_intr_nonstall_resume(struct gk20a *g)
 			g->mc.intr_mask_restore[NVGPU_MC_INTR_NONSTALLING]);
 }
 
-bool mc_gp10b_is_intr1_pending(struct gk20a *g,
-				      enum nvgpu_unit unit, u32 mc_intr_1)
+bool mc_gp10b_is_intr1_pending(struct gk20a *g, u32 unit, u32 mc_intr_1)
 {
 	u32 mask;
 	bool is_pending;
diff --git a/drivers/gpu/nvgpu/hal/mc/mc_gv100.c b/drivers/gpu/nvgpu/hal/mc/mc_gv100.c
index 3164405a6..d65e6fbf7 100644
--- a/drivers/gpu/nvgpu/hal/mc/mc_gv100.c
+++ b/drivers/gpu/nvgpu/hal/mc/mc_gv100.c
@@ -62,7 +62,7 @@ bool gv100_mc_is_stall_and_eng_intr_pending(struct gk20a *g, u32 engine_id,
 	return (mc_intr_0 & (eng_intr_mask | stall_intr)) != 0U;
 }
 
-u32 gv100_mc_reset_mask(struct gk20a *g, enum nvgpu_unit unit)
+static u32 gv100_mc_unit_reset_mask(struct gk20a *g, u32 unit)
 {
 	u32 mask = 0U;
 
@@ -87,6 +87,12 @@ u32 gv100_mc_reset_mask(struct gk20a *g, enum nvgpu_unit unit)
 	case NVGPU_UNIT_NVDEC:
 		mask = mc_enable_nvdec_enabled_f();
 		break;
+	case NVGPU_UNIT_NVLINK:
+		mask = BIT32(g->nvlink.ioctrl_table[0].reset_enum);
+		break;
+	case NVGPU_UNIT_CE2:
+		mask = mc_enable_ce2_enabled_f();
+		break;
 	default:
 		WARN(1, "unknown reset unit %d", unit);
 		break;
@@ -94,3 +100,48 @@ u32 gv100_mc_reset_mask(struct gk20a *g, enum nvgpu_unit unit)
 
 	return mask;
 }
+
+static u32 gv100_mc_get_unit_reset_mask(struct gk20a *g, u32 units)
+{
+	u32 mask = 0U;
+	unsigned long i = 0U;
+	unsigned long units_bitmask = units;
+
+	for_each_set_bit(i, &units_bitmask, 32U) {
+		mask |= gv100_mc_unit_reset_mask(g, BIT32(i));
+	}
+	return mask;
+}
+
+int gv100_mc_enable_units(struct gk20a *g, u32 units, bool enable)
+{
+	u32 mc_enable_val = 0U;
+	u32 reg_val = 0U;
+	u32 mask = gv100_mc_get_unit_reset_mask(g, units);
+
+	nvgpu_log(g, gpu_dbg_info, "%s units: mc_enable mask = 0x%08x",
+			(enable ? "enable" : "disable"), mask);
+	if (enable) {
+		nvgpu_udelay(MC_RESET_DELAY_US);
+	}
+
+	nvgpu_spinlock_acquire(&g->mc.enable_lock);
+	reg_val = nvgpu_readl(g, mc_enable_r());
+	if (enable) {
+		mc_enable_val = reg_val | mask;
+	} else {
+		mc_enable_val = reg_val & (~mask);
+	}
+	nvgpu_writel(g, mc_enable_r(), mc_enable_val);
+	reg_val = nvgpu_readl(g, mc_enable_r());
+	nvgpu_spinlock_release(&g->mc.enable_lock);
+
+	nvgpu_udelay(MC_ENABLE_DELAY_US);
+
+	if (reg_val != mc_enable_val) {
+		nvgpu_err(g, "Failed to %s units: mc_enable mask = 0x%08x",
+			(enable ? "enable" : "disable"), mask);
+		return -EINVAL;
+	}
+	return 0U;
+}
diff --git a/drivers/gpu/nvgpu/hal/mc/mc_gv100.h b/drivers/gpu/nvgpu/hal/mc/mc_gv100.h
index 4ffc4ad0c..d61046f49 100644
--- a/drivers/gpu/nvgpu/hal/mc/mc_gv100.h
+++ b/drivers/gpu/nvgpu/hal/mc/mc_gv100.h
@@ -30,6 +30,6 @@ struct gk20a;
 bool gv100_mc_is_intr_nvlink_pending(struct gk20a *g, u32 mc_intr_0);
 bool gv100_mc_is_stall_and_eng_intr_pending(struct gk20a *g, u32 engine_id,
 			u32 *eng_intr_pending);
-u32  gv100_mc_reset_mask(struct gk20a *g, enum nvgpu_unit unit);
+int gv100_mc_enable_units(struct gk20a *g, u32 units, bool enable);
 
 #endif /* NVGPU_MC_GV100_H */
diff --git a/drivers/gpu/nvgpu/hal/pmu/pmu_gk20a.c b/drivers/gpu/nvgpu/hal/pmu/pmu_gk20a.c
index 82b55dd2a..2a5514f89 100644
--- a/drivers/gpu/nvgpu/hal/pmu/pmu_gk20a.c
+++ b/drivers/gpu/nvgpu/hal/pmu/pmu_gk20a.c
@@ -699,13 +699,7 @@ bool gk20a_pmu_is_engine_in_reset(struct gk20a *g)
 
 void gk20a_pmu_engine_reset(struct gk20a *g, bool do_reset)
 {
-	u32 reset_mask = g->ops.mc.reset_mask(g, NVGPU_UNIT_PWR);
-
-	if (do_reset) {
-		g->ops.mc.enable(g, reset_mask);
-	} else {
-		g->ops.mc.disable(g, reset_mask);
-	}
+	g->ops.mc.enable_units(g, NVGPU_UNIT_PWR, do_reset);
 }
 #endif
 
diff --git a/drivers/gpu/nvgpu/hal/vgpu/init/vgpu_hal_gp10b.c b/drivers/gpu/nvgpu/hal/vgpu/init/vgpu_hal_gp10b.c
index 28a140cb1..fe75a2e03 100644
--- a/drivers/gpu/nvgpu/hal/vgpu/init/vgpu_hal_gp10b.c
+++ b/drivers/gpu/nvgpu/hal/vgpu/init/vgpu_hal_gp10b.c
@@ -737,15 +737,14 @@ static const struct gops_mc vgpu_gp10b_ops_mc = {
 	.intr_nonstall_pause = NULL,
 	.intr_nonstall_resume = NULL,
 	.isr_nonstall = NULL,
-	.enable = NULL,
-	.disable = NULL,
-	.reset = NULL,
 	.is_intr1_pending = NULL,
 	.log_pending_intrs = NULL,
-	.reset_mask = NULL,
 	.is_enabled = NULL,
 	.fb_reset = NULL,
 	.is_mmu_fault_pending = NULL,
+	.enable_units = NULL,
+	.enable_dev = NULL,
+	.enable_devtype = NULL,
 };
 
 static const struct gops_debug vgpu_gp10b_ops_debug = {
diff --git a/drivers/gpu/nvgpu/hal/vgpu/init/vgpu_hal_gv11b.c b/drivers/gpu/nvgpu/hal/vgpu/init/vgpu_hal_gv11b.c
index 6c35e9994..e3e09bb95 100644
--- a/drivers/gpu/nvgpu/hal/vgpu/init/vgpu_hal_gv11b.c
+++ b/drivers/gpu/nvgpu/hal/vgpu/init/vgpu_hal_gv11b.c
@@ -848,16 +848,15 @@ static const struct gops_mc vgpu_gv11b_ops_mc = {
 	.intr_nonstall_pause = NULL,
 	.intr_nonstall_resume = NULL,
 	.isr_nonstall = NULL,
-	.enable = NULL,
-	.disable = NULL,
-	.reset = NULL,
 	.is_intr1_pending = NULL,
 	.is_intr_hub_pending = NULL,
 	.log_pending_intrs = NULL,
-	.reset_mask = NULL,
 	.is_enabled = NULL,
 	.fb_reset = NULL,
 	.is_mmu_fault_pending = NULL,
+	.enable_units = NULL,
+	.enable_dev = NULL,
+	.enable_devtype = NULL,
 };
 
 static const struct gops_debug vgpu_gv11b_ops_debug = {
diff --git a/drivers/gpu/nvgpu/include/nvgpu/engines.h b/drivers/gpu/nvgpu/include/nvgpu/engines.h
index 4e3a40efd..f3ad99ae8 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/engines.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/engines.h
@@ -161,14 +161,6 @@ u32 nvgpu_ce_engine_interrupt_mask(struct gk20a *g);
  *         corresponding device.
  */
 u32 nvgpu_engine_act_interrupt_mask(struct gk20a *g, u32 engine_id);
-/**
- * @brief Get engine reset mask for CE engines.
- *
- * @param g [in]		The GPU driver struct.
- *
- * @return The logical OR of the reset mask of each CE present on the GPU.
- */
-u32 nvgpu_engine_get_all_ce_reset_mask(struct gk20a *g);
 /**
  * @brief Allocate and initialize s/w context for engine related info.
  *
diff --git a/drivers/gpu/nvgpu/include/nvgpu/gk20a.h b/drivers/gpu/nvgpu/include/nvgpu/gk20a.h
index 0edd01e81..4ad6525da 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/gk20a.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/gk20a.h
@@ -111,7 +111,6 @@ struct clk_domains_mon_status_params;
 enum nvgpu_flush_op;
 enum gk20a_mem_rw_flag;
 enum nvgpu_nvlink_minion_dlcmd;
-enum nvgpu_unit;
 enum nvgpu_profiler_pm_resource_type;
 enum nvgpu_profiler_pm_reservation_scope;
 
diff --git a/drivers/gpu/nvgpu/include/nvgpu/gops/mc.h b/drivers/gpu/nvgpu/include/nvgpu/gops/mc.h
index 0b82315a0..53db3f957 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/gops/mc.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/gops/mc.h
@@ -34,6 +34,7 @@
  * MC HAL interface.
  */
 struct gk20a;
+struct nvgpu_device;
 
 /**
  * MC HAL operations.
@@ -199,70 +200,7 @@ struct gops_mc {
 	bool (*is_stall_and_eng_intr_pending)(struct gk20a *g,
 				u32 engine_id, u32 *eng_intr_pending);
 
-	/**
-	 * @brief Reset the HW unit/engine.
-	 *
-	 * @param g [in]	The GPU driver struct.
-	 * @param units [in]	Bitmask of values designating GPU HW engines
-	 *			controlled by MC. This is used to update bits in
-	 *			the mc_enable_r register.
-	 *			- Supported values are:
-	 *			  - #NVGPU_UNIT_FIFO
-	 *			  - #NVGPU_UNIT_PERFMON
-	 *			  - #NVGPU_UNIT_GRAPH
-	 *			  - #NVGPU_UNIT_BLG
-	 *			  - Reset id of supported engines from the
-	 *                          device info. For e.g. GR engine has reset
-	 *                          id of 12. @see #nvgpu_device.
-	 *
-	 * This function is invoked to reset the engines while initializing
-	 * FIFO, GR and other engines during #nvgpu_finalize_poweron.
-	 *
-	 * Steps:
-	 * - Disable the HW unit/engine.
-	 *   - Acquire g->mc.enable_lock spinlock.
-	 *   - Read mc_enable_r register and clear the bits in the read value
-	 *     corresponding to HW unit to be disabled.
-	 *   - Write mc_enable_r with the updated value.
-	 *   - Release g->mc.enable_lock spinlock.
-	 * - Sleep/wait for 500us if resetting CE engines else sleep for 20us.
-	 * - Enable the HW unit/engine.
-	 *   - Acquire g->mc.enable_lock spinlock.
-	 *   - Read mc_enable_r register and set the bits in the read value
-	 *     corresponding to HW unit to be disabled.
-	 *   - Write mc_enable_r with the updated value.
-	 *   - Read back mc_enable_r.
-	 *   - Release g->mc.enable_lock spinlock.
-	 *   - Sleep/wait for 20us.
-	 */
-	void (*reset)(struct gk20a *g, u32 units);
 
-	/**
-	 * @brief Get the reset mask for the HW unit/engine.
-	 *
-	 * @param g [in]	The GPU driver struct.
-	 * @param unit [in]	Value designating the GPU HW unit/engine
-	 *                      controlled by MC. Supported values are:
-	 *			  - #NVGPU_UNIT_FIFO
-	 *			  - #NVGPU_UNIT_PERFMON
-	 *			  - #NVGPU_UNIT_GRAPH
-	 *			  - #NVGPU_UNIT_BLG
-	 *
-	 * This function is invoked to get the reset mask of the engines for
-	 * resetting CE, GR, FIFO during #nvgpu_finalize_poweron.
-	 *
-	 * Steps:
-	 * - If \a unit is #NVGPU_UNIT_FIFO, return mc_enable_pfifo_enabled_f.
-	 * - else if \a unit is #NVGPU_UNIT_PERFMON,
-	 *   return mc_enable_perfmon_enabled_f.
-	 * - else if \a unit is #NVGPU_UNIT_GRAPH,
-	 *   return mc_enable_pgraph_enabled_f.
-	 * - else if \a unit is #NVGPU_UNIT_BLG, return mc_enable_blg_enabled_f.
-	 * - else return 0.
-	 *
-	 * @return bitmask corresponding to supported engines, else 0.
-	 */
-	u32 (*reset_mask)(struct gk20a *g, enum nvgpu_unit unit);
 
 	/** @cond DOXYGEN_SHOULD_SKIP_THIS */
 
@@ -286,16 +224,18 @@ struct gops_mc {
 
 	void (*intr_nonstall_resume)(struct gk20a *g);
 
-	void (*enable)(struct gk20a *g, u32 units);
+	int (*enable_units)(struct gk20a *g, u32 units, bool enable);
 
-	void (*disable)(struct gk20a *g, u32 units);
+	int (*enable_dev)(struct gk20a *g, const struct nvgpu_device *dev,
+			bool enable);
+
+	int (*enable_devtype)(struct gk20a *g, u32 devtype, bool enable);
 
 #ifdef CONFIG_NVGPU_LS_PMU
-	bool (*is_enabled)(struct gk20a *g, enum nvgpu_unit unit);
+	bool (*is_enabled)(struct gk20a *g, u32 unit);
 #endif
 
-	bool (*is_intr1_pending)(struct gk20a *g, enum nvgpu_unit unit,
-				 u32 mc_intr_1);
+	bool (*is_intr1_pending)(struct gk20a *g, u32 unit, u32 mc_intr_1);
 
 	bool (*is_mmu_fault_pending)(struct gk20a *g);
 
diff --git a/drivers/gpu/nvgpu/include/nvgpu/mc.h b/drivers/gpu/nvgpu/include/nvgpu/mc.h
index d1c728631..c41119486 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/mc.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/mc.h
@@ -116,15 +116,21 @@
 #include <nvgpu/cond.h>
 #include <nvgpu/atomic.h>
 #include <nvgpu/lock.h>
+#include <nvgpu/bitops.h>
 
 struct gk20a;
+struct nvgpu_device;
 
 #if defined(CONFIG_NVGPU_NON_FUSA) && defined(CONFIG_NVGPU_NEXT)
 #include "include/nvgpu/nvgpu_next_mc.h"
 #endif
 
+#define MC_ENABLE_DELAY_US	20U
+#define MC_RESET_DELAY_US	20U
+#define MC_RESET_CE_DELAY_US	500U
+
 /**
- * @defgroup NVGPU_MC_UNIT_ENUMS
+ * @defgroup NVGPU_MC_UNIT_DEFINES
  *
  * Enumeration of all units intended to be used by enabling/disabling HAL
  * that requires unit as parameter. Units are added to the enumeration as
@@ -132,24 +138,27 @@ struct gk20a;
  */
 
 /**
- * @ingroup NVGPU_MC_UNIT_ENUMS
+ * @ingroup NVGPU_MC_UNIT_DEFINES
  */
-enum nvgpu_unit {
-	/** FIFO Engine */
-	NVGPU_UNIT_FIFO,
-	/** Performance Monitoring unit */
-	NVGPU_UNIT_PERFMON,
-	/** Graphics Engine */
-	NVGPU_UNIT_GRAPH,
-	/** BLPG and BLCG controllers within Graphics Engine */
-	NVGPU_UNIT_BLG,
+
+/** FIFO Engine */
+#define NVGPU_UNIT_FIFO		BIT32(0)
+/** Performance Monitoring unit */
+#define NVGPU_UNIT_PERFMON	BIT32(1)
+/** Graphics Engine */
+#define NVGPU_UNIT_GRAPH	BIT32(2)
+/** BLPG and BLCG controllers within Graphics Engine */
+#define NVGPU_UNIT_BLG		BIT32(3)
 #ifdef CONFIG_NVGPU_HAL_NON_FUSA
-	NVGPU_UNIT_PWR,
+#define NVGPU_UNIT_PWR		BIT32(4)
 #endif
 #ifdef CONFIG_NVGPU_DGPU
-	NVGPU_UNIT_NVDEC,
+#define NVGPU_UNIT_NVDEC	BIT32(5)
 #endif
-};
+/** CE2 unit */
+#define NVGPU_UNIT_CE2		BIT32(6)
+/** NVLINK unit */
+#define NVGPU_UNIT_NVLINK	BIT32(7)
 
 /** Bit offset of the Architecture field in the HW version register */
 #define NVGPU_GPU_ARCHITECTURE_SHIFT 4U
@@ -481,4 +490,64 @@ void nvgpu_mc_intr_nonstall_pause(struct gk20a *g);
  */
 void nvgpu_mc_intr_nonstall_resume(struct gk20a *g);
 
+/**
+ * @brief Reset given HW unit(s).
+ *
+ * @param g [in]	The GPU driver struct.
+ * @param units [in]	Value designating the GPU HW unit(s)
+ *                      controlled by MC. Supported values are:
+ *			  - #NVGPU_UNIT_FIFO
+ *			  - #NVGPU_UNIT_PERFMON
+ *			  - #NVGPU_UNIT_GRAPH
+ *			  - #NVGPU_UNIT_BLG
+ *			The logical OR of the reset mask of each given units.
+ *
+ * This function is called to reset one or multiple units.
+ *
+ * Steps:
+ * - Compute bitmask of given unit or units.
+ * - Disable and enable given unit or units.
+ *
+ * @return -EINVAL if register write fails, else 0.
+ */
+int nvgpu_mc_reset_units(struct gk20a *g, u32 units);
+
+/**
+ * @brief Reset given HW engine.
+ *
+ * @param g [in]	The GPU driver struct.
+ * @param dev [in]	Nvgpu_device struct that
+ *                      contains info of engine to be reset.
+ *
+ * This function is called to reset a single engine.
+ * Note: Currently, this API is used to reset non-GR engines only.
+ *
+ * Steps:
+ * - Compute bitmask of given engine from reset_id.
+ * - Disable and enable given engine.
+ *
+ * @return -EINVAL if register write fails, else 0.
+ */
+int nvgpu_mc_reset_dev(struct gk20a *g, const struct nvgpu_device *dev);
+
+/**
+ * @brief Reset all engines of given devtype.
+ *
+ * @param g [in]	The GPU driver struct.
+ * @param devtype [in]	Type of device.
+ *                      Supported values are:
+ *			   - NVGPU_DEVTYPE_GRAPHICS
+ *			   - NVGPU_DEVTYPE_LCE
+ *
+ * This function is called to reset engines of given devtype.
+ * Note: Currently, this API is used to reset non-GR engines only.
+ *
+ * Steps:
+ * - Compute bitmask of all engines of given devtype.
+ * - Disable and enable given engines.
+ *
+ * @return -EINVAL if register write fails, else 0.
+ */
+int nvgpu_mc_reset_devtype(struct gk20a *g, u32 devtype);
+
 #endif
diff --git a/libs/dgpu/libnvgpu-drv-dgpu_safe.export b/libs/dgpu/libnvgpu-drv-dgpu_safe.export
index 628417f47..b35ea2a1e 100644
--- a/libs/dgpu/libnvgpu-drv-dgpu_safe.export
+++ b/libs/dgpu/libnvgpu-drv-dgpu_safe.export
@@ -348,7 +348,6 @@ nvgpu_engine_check_valid_id
 nvgpu_engine_cleanup_sw
 nvgpu_engine_find_busy_doing_ctxsw
 nvgpu_engine_get_active_eng_info
-nvgpu_engine_get_all_ce_reset_mask
 nvgpu_engine_get_fast_ce_runlist_id
 nvgpu_engine_get_gr_id
 nvgpu_engine_get_gr_runlist_id
@@ -534,6 +533,9 @@ nvgpu_mc_intr_nonstall_unit_config
 nvgpu_mc_intr_stall_pause
 nvgpu_mc_intr_stall_resume
 nvgpu_mc_intr_stall_unit_config
+nvgpu_mc_reset_dev
+nvgpu_mc_reset_devtype
+nvgpu_mc_reset_units
 nvgpu_memcmp
 nvgpu_memcpy
 nvgpu_memset
diff --git a/libs/igpu/libnvgpu-drv-igpu_safe.export b/libs/igpu/libnvgpu-drv-igpu_safe.export
index f166f066e..1cabaf053 100644
--- a/libs/igpu/libnvgpu-drv-igpu_safe.export
+++ b/libs/igpu/libnvgpu-drv-igpu_safe.export
@@ -360,7 +360,6 @@ nvgpu_engine_check_valid_id
 nvgpu_engine_cleanup_sw
 nvgpu_engine_find_busy_doing_ctxsw
 nvgpu_engine_get_active_eng_info
-nvgpu_engine_get_all_ce_reset_mask
 nvgpu_engine_get_fast_ce_runlist_id
 nvgpu_engine_get_gr_id
 nvgpu_engine_get_gr_runlist_id
@@ -549,6 +548,9 @@ nvgpu_mc_intr_nonstall_unit_config
 nvgpu_mc_intr_stall_pause
 nvgpu_mc_intr_stall_resume
 nvgpu_mc_intr_stall_unit_config
+nvgpu_mc_reset_dev
+nvgpu_mc_reset_devtype
+nvgpu_mc_reset_units
 nvgpu_memcmp
 nvgpu_memcpy
 nvgpu_memset
diff --git a/userspace/required_tests.ini b/userspace/required_tests.ini
index 9e2ea6c5a..2f8bca490 100644
--- a/userspace/required_tests.ini
+++ b/userspace/required_tests.ini
@@ -332,7 +332,6 @@ test_is_stall_and_eng_intr_pending.intr_is_stall_and_eng_intr_pending=2
 test_isr_nonstall.isr_nonstall=2
 test_isr_stall.isr_stall=2
 test_pause_resume_mask.pause_resume_mask=0
-test_reset_mask.reset_mask=0
 test_setup_env.mc_setup_env=0
 test_unit_config.unit_config=2
 test_wait_for_deferred_interrupts.wait_for_deferred_interrupts=0
diff --git a/userspace/units/ce/nvgpu-ce.c b/userspace/units/ce/nvgpu-ce.c
index 34ea722c8..b7583c3f2 100644
--- a/userspace/units/ce/nvgpu-ce.c
+++ b/userspace/units/ce/nvgpu-ce.c
@@ -95,9 +95,14 @@ static void mock_void_return(struct gk20a *g)
 	/* noop */
 }
 
-static void mock_mc_reset(struct gk20a *g, u32 arg1)
+static int mock_mc_enable_units(struct gk20a *g, u32 units, bool enable)
 {
-	/* noop */
+	return 0;
+}
+static int mock_mc_enable_dev(struct gk20a *g, const struct nvgpu_device *dev,
+			bool enable)
+{
+	return 0;
 }
 
 static void mock_intr_unit_config(struct gk20a *g, u32 unit, bool enable)
@@ -142,7 +147,8 @@ int test_ce_init_support(struct unit_module *m, struct gk20a *g, void *args)
 	g->fifo.num_engines = 0;
 	g->ops.ce.set_pce2lce_mapping = mock_void_return;
 	g->ops.ce.init_prod_values = mock_void_return;
-	g->ops.mc.reset = mock_mc_reset;
+	g->ops.mc.enable_units = mock_mc_enable_units;
+	g->ops.mc.enable_dev = mock_mc_enable_dev;
 	g->ops.mc.intr_nonstall_unit_config = mock_intr_unit_config;
 	g->ops.mc.intr_stall_unit_config = mock_intr_unit_config;
 
diff --git a/userspace/units/mc/nvgpu-mc.c b/userspace/units/mc/nvgpu-mc.c
index 8951a587b..bc9d2b1d5 100644
--- a/userspace/units/mc/nvgpu-mc.c
+++ b/userspace/units/mc/nvgpu-mc.c
@@ -547,7 +547,7 @@ int test_isr_stall(struct unit_module *m, struct gk20a *g, void *args)
 int test_is_intr1_pending(struct unit_module *m, struct gk20a *g, void *args)
 {
 	struct match_struct {
-		enum nvgpu_unit unit;
+		u32 unit;
 		u32 mask;
 		bool expect;
 	};
@@ -617,22 +617,23 @@ int test_isr_nonstall(struct unit_module *m, struct gk20a *g, void *args)
 
 int test_enable_disable_reset(struct unit_module *m, struct gk20a *g, void *args)
 {
-	u32 units = (g->ops.mc.reset_mask(g, NVGPU_UNIT_FIFO) |
-		     g->ops.mc.reset_mask(g, NVGPU_UNIT_GRAPH) |
-		     g->ops.mc.reset_mask(g, NVGPU_UNIT_BLG) |
-			mc_enable_ce2_enabled_f());
+	u32 units = (mc_enable_pfifo_enabled_f() |
+		     mc_enable_pgraph_enabled_f() |
+		     mc_enable_blg_enabled_f() | mc_enable_ce2_enabled_f());
 	u32 val;
 
 	/* test enable */
 	nvgpu_posix_io_writel_reg_space(g, mc_enable_r(), 0);
-	g->ops.mc.enable(g, units);
+	g->ops.mc.enable_units(g, (NVGPU_UNIT_FIFO | NVGPU_UNIT_GRAPH |
+		     NVGPU_UNIT_BLG | NVGPU_UNIT_CE2), true);
 	val = nvgpu_posix_io_readl_reg_space(g, mc_enable_r());
 	if (val != units) {
 		unit_return_fail(m, "failed to reset units val=0x%08x\n", val);
 	}
 
 	/* test disable */
-	g->ops.mc.disable(g, units);
+	g->ops.mc.enable_units(g, (NVGPU_UNIT_FIFO | NVGPU_UNIT_GRAPH |
+		     NVGPU_UNIT_BLG | NVGPU_UNIT_CE2), false);
 	val = nvgpu_posix_io_readl_reg_space(g, mc_enable_r());
 	if (val != 0U) {
 		unit_return_fail(m, "failed to reset units val=0x%08x\n", val);
@@ -640,52 +641,13 @@ int test_enable_disable_reset(struct unit_module *m, struct gk20a *g, void *args
 
 	/* test reset */
 	nvgpu_posix_io_writel_reg_space(g, mc_enable_r(), units);
-	g->ops.mc.reset(g, units);
+	nvgpu_mc_reset_units(g, (NVGPU_UNIT_FIFO | NVGPU_UNIT_GRAPH |
+		     NVGPU_UNIT_BLG | NVGPU_UNIT_CE2));
 	val = nvgpu_posix_io_readl_reg_space(g, mc_enable_r());
 	if (val != units) {
 		unit_return_fail(m, "failed to reset units val=0x%08x\n", val);
 	}
 
-	/* for branch coverage, do not include CE's */
-	units = NVGPU_UNIT_FIFO | NVGPU_UNIT_GRAPH;
-	nvgpu_posix_io_writel_reg_space(g, mc_enable_r(), units);
-	g->ops.mc.reset(g, units);
-	val = nvgpu_posix_io_readl_reg_space(g, mc_enable_r());
-	if (val != units) {
-		unit_return_fail(m, "failed to reset units val=0x%08x\n", val);
-	}
-
-	return UNIT_SUCCESS;
-}
-
-int test_reset_mask(struct unit_module *m, struct gk20a *g, void *args)
-{
-	struct match_struct {
-		enum nvgpu_unit unit;
-		u32 mask;
-	};
-	const struct match_struct match_table[] = {
-		{ NVGPU_UNIT_FIFO, mc_enable_pfifo_enabled_f() },
-		{ NVGPU_UNIT_PERFMON, mc_enable_perfmon_enabled_f() },
-		{ NVGPU_UNIT_GRAPH, mc_enable_pgraph_enabled_f() },
-		{ NVGPU_UNIT_BLG, mc_enable_blg_enabled_f() },
-	};
-	unsigned int i;
-	u32 val;
-
-	for (i = 0U; i < ARRAY_SIZE(match_table); i++) {
-		val = g->ops.mc.reset_mask(g, match_table[i].unit);
-		if (val != match_table[i].mask) {
-			unit_return_fail(m, "incorrect mask returned\n");
-		}
-	}
-
-	/* pass invalid unit for branch coverage */
-	val = g->ops.mc.reset_mask(g, INVALID_UNIT);
-	if (val != 0U) {
-		unit_return_fail(m, "incorrect mask returned\n");
-	}
-
 	return UNIT_SUCCESS;
 }
 
@@ -731,7 +693,6 @@ struct unit_module_test mc_tests[] = {
 	UNIT_TEST(isr_nonstall,			test_isr_nonstall,			NULL, 2),
 	UNIT_TEST(is_intr1_pending,		test_is_intr1_pending,			NULL, 0),
 	UNIT_TEST(enable_disable_reset,		test_enable_disable_reset,		NULL, 0),
-	UNIT_TEST(reset_mask,			test_reset_mask,			NULL, 0),
 	UNIT_TEST(wait_for_deferred_interrupts,	test_wait_for_deferred_interrupts,	NULL, 0),
 	UNIT_TEST(mc_free_env,			test_free_env,				NULL, 0),
 };