diff --git a/drivers/gpu/nvgpu/gv100/gr_gv100.c b/drivers/gpu/nvgpu/gv100/gr_gv100.c index 2180fa1c8..680bcba3e 100644 --- a/drivers/gpu/nvgpu/gv100/gr_gv100.c +++ b/drivers/gpu/nvgpu/gv100/gr_gv100.c @@ -37,6 +37,7 @@ #include #include #include +#include /* @@ -371,9 +372,13 @@ u32 gr_gv100_get_patch_slots(struct gk20a *g) return size; } -static u32 gr_gv100_get_active_fpba_mask(struct gk20a *g, u32 num_fbpas) +static u32 gr_gv100_get_active_fpba_mask(struct gk20a *g) { u32 active_fbpa_mask; + u32 num_fbpas, val; + + val = nvgpu_readl(g, top_num_fbpas_r()); + num_fbpas = top_num_fbpas_value_v(val); /* * Read active fbpa mask from fuse @@ -404,7 +409,7 @@ int gr_gv100_add_ctxsw_reg_pm_fbpa(struct gk20a *g, if ((cnt + (regs->count * num_fbpas)) > max_cnt) return -EINVAL; - active_fbpa_mask = gr_gv100_get_active_fpba_mask(g, num_fbpas); + active_fbpa_mask = gr_gv100_get_active_fpba_mask(g); for (idx = 0; idx < regs->count; idx++) { for (fbpa_id = 0; fbpa_id < num_fbpas; fbpa_id++) { @@ -439,7 +444,7 @@ void gr_gv100_split_fbpa_broadcast_addr(struct gk20a *g, u32 addr, u32 active_fbpa_mask; u32 fbpa_id; - active_fbpa_mask = gr_gv100_get_active_fpba_mask(g, num_fbpas); + active_fbpa_mask = gr_gv100_get_active_fpba_mask(g); for (fbpa_id = 0; fbpa_id < num_fbpas; fbpa_id++) { if (active_fbpa_mask & BIT(fbpa_id)) { diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_top_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_top_gv100.h index ff9c046c0..506a8181f 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_top_gv100.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_top_gv100.h @@ -80,6 +80,14 @@ static inline u32 top_num_fbps_value_v(u32 r) { return (r >> 0U) & 0x1fU; } +static inline u32 top_num_fbpas_r(void) +{ + return 0x0002243cU; +} +static inline u32 top_num_fbpas_value_v(u32 r) +{ + return (r >> 0U) & 0x1fU; +} static inline u32 top_ltc_per_fbp_r(void) { return 0x00022450U;