From e1a4bc8401dda287ff64bd15145a98ce931611aa Mon Sep 17 00:00:00 2001 From: aalex Date: Fri, 21 Sep 2018 23:02:41 +0530 Subject: [PATCH] Revert "Revert "gpu: nvgpu: refactor SET_SM_EXCEPTION_MASK ioctl"" This patch was reverted as the "set_sm_exception_type_mask" HAL assignment for gp10b was missing causing regression on Pascal platform. Added missing gp10b HAL assignment for setting SM exception mask. Bug 200447406 This reverts commit ce5228e09411f9c54e96cfb0f7e9c857fd9b480d. Change-Id: Ic48f4661fd4b6100310f8b4d23d902847e31f5df Signed-off-by: aalex Reviewed-on: https://git-master.nvidia.com/r/1837653 Reviewed-by: svc-misra-checker Reviewed-by: svc-mobile-coverity GVS: Gerrit_Virtual_Submit Reviewed-by: Deepak Nibade Reviewed-by: Aparna Das Tested-by: Sandarbh Jain Reviewed-by: Nirav Patel Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/common/fifo/tsg.c | 24 +++++++++ drivers/gpu/nvgpu/gm20b/hal_gm20b.c | 1 + drivers/gpu/nvgpu/gp106/hal_gp106.c | 1 + drivers/gpu/nvgpu/gp10b/hal_gp10b.c | 1 + drivers/gpu/nvgpu/gv100/hal_gv100.c | 1 + drivers/gpu/nvgpu/gv11b/hal_gv11b.c | 1 + drivers/gpu/nvgpu/include/nvgpu/gk20a.h | 2 + drivers/gpu/nvgpu/include/nvgpu/tsg.h | 3 ++ .../gpu/nvgpu/include/nvgpu/vgpu/tegra_vgpu.h | 7 +++ drivers/gpu/nvgpu/os/linux/ioctl_dbg.c | 54 +++++-------------- drivers/gpu/nvgpu/tu104/hal_tu104.c | 1 + drivers/gpu/nvgpu/vgpu/fifo_vgpu.h | 2 +- drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c | 1 + drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c | 1 + drivers/gpu/nvgpu/vgpu/tsg_vgpu.c | 23 ++++++++ 15 files changed, 81 insertions(+), 42 deletions(-) diff --git a/drivers/gpu/nvgpu/common/fifo/tsg.c b/drivers/gpu/nvgpu/common/fifo/tsg.c index 0892e8bff..729e85ce3 100644 --- a/drivers/gpu/nvgpu/common/fifo/tsg.c +++ b/drivers/gpu/nvgpu/common/fifo/tsg.c @@ -366,6 +366,7 @@ void gk20a_tsg_release(struct nvgpu_ref *ref) if(tsg->sm_error_states != NULL) { nvgpu_kfree(g, tsg->sm_error_states); tsg->sm_error_states = NULL; + nvgpu_mutex_destroy(&tsg->sm_exception_mask_lock); } /* unhook all events created on this TSG */ @@ -406,6 +407,11 @@ int gk20a_tsg_alloc_sm_error_states_mem(struct gk20a *g, int err = 0; if (tsg->sm_error_states != NULL) { + return -EINVAL; + } + + err = nvgpu_mutex_init(&tsg->sm_exception_mask_lock); + if (err != 0) { return err; } @@ -414,6 +420,7 @@ int gk20a_tsg_alloc_sm_error_states_mem(struct gk20a *g, * num_sm); if (tsg->sm_error_states == NULL) { nvgpu_err(g, "sm_error_states mem allocation failed"); + nvgpu_mutex_destroy(&tsg->sm_exception_mask_lock); err = -ENOMEM; } @@ -439,3 +446,20 @@ void gk20a_tsg_update_sm_error_state_locked(struct tsg_gk20a *tsg, tsg_sm_error_states->hww_warp_esr_report_mask = sm_error_state->hww_warp_esr_report_mask; } + +int gk20a_tsg_set_sm_exception_type_mask(struct channel_gk20a *ch, + u32 exception_mask) +{ + struct tsg_gk20a *tsg; + + tsg = tsg_gk20a_from_ch(ch); + if (tsg == NULL) { + return -EINVAL; + } + + nvgpu_mutex_acquire(&tsg->sm_exception_mask_lock); + tsg->sm_exception_mask_type = exception_mask; + nvgpu_mutex_release(&tsg->sm_exception_mask_lock); + + return 0; +} diff --git a/drivers/gpu/nvgpu/gm20b/hal_gm20b.c b/drivers/gpu/nvgpu/gm20b/hal_gm20b.c index 39e96d2c3..f7f32ff8f 100644 --- a/drivers/gpu/nvgpu/gm20b/hal_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/hal_gm20b.c @@ -479,6 +479,7 @@ static const struct gpu_ops gm20b_ops = { .get_sema_wait_cmd_size = gk20a_fifo_get_sema_wait_cmd_size, .get_sema_incr_cmd_size = gk20a_fifo_get_sema_incr_cmd_size, .add_sema_cmd = gk20a_fifo_add_sema_cmd, + .set_sm_exception_type_mask = gk20a_tsg_set_sm_exception_type_mask, }, .gr_ctx = { .get_netlist_name = gr_gm20b_get_netlist_name, diff --git a/drivers/gpu/nvgpu/gp106/hal_gp106.c b/drivers/gpu/nvgpu/gp106/hal_gp106.c index 600f068cf..80c7bbd90 100644 --- a/drivers/gpu/nvgpu/gp106/hal_gp106.c +++ b/drivers/gpu/nvgpu/gp106/hal_gp106.c @@ -556,6 +556,7 @@ static const struct gpu_ops gp106_ops = { .get_sema_wait_cmd_size = gk20a_fifo_get_sema_wait_cmd_size, .get_sema_incr_cmd_size = gk20a_fifo_get_sema_incr_cmd_size, .add_sema_cmd = gk20a_fifo_add_sema_cmd, + .set_sm_exception_type_mask = gk20a_tsg_set_sm_exception_type_mask, }, .gr_ctx = { .get_netlist_name = gr_gp106_get_netlist_name, diff --git a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c index eae53db9a..2fcb8e1bf 100644 --- a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c @@ -521,6 +521,7 @@ static const struct gpu_ops gp10b_ops = { .get_sema_wait_cmd_size = gk20a_fifo_get_sema_wait_cmd_size, .get_sema_incr_cmd_size = gk20a_fifo_get_sema_incr_cmd_size, .add_sema_cmd = gk20a_fifo_add_sema_cmd, + .set_sm_exception_type_mask = gk20a_tsg_set_sm_exception_type_mask, }, .gr_ctx = { .get_netlist_name = gr_gp10b_get_netlist_name, diff --git a/drivers/gpu/nvgpu/gv100/hal_gv100.c b/drivers/gpu/nvgpu/gv100/hal_gv100.c index cb94759a6..7592c706c 100644 --- a/drivers/gpu/nvgpu/gv100/hal_gv100.c +++ b/drivers/gpu/nvgpu/gv100/hal_gv100.c @@ -655,6 +655,7 @@ static const struct gpu_ops gv100_ops = { .get_sema_wait_cmd_size = gv11b_fifo_get_sema_wait_cmd_size, .get_sema_incr_cmd_size = gv11b_fifo_get_sema_incr_cmd_size, .add_sema_cmd = gv11b_fifo_add_sema_cmd, + .set_sm_exception_type_mask = gk20a_tsg_set_sm_exception_type_mask, }, .gr_ctx = { .get_netlist_name = gr_gv100_get_netlist_name, diff --git a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c index 72c3b4dc2..9639980f0 100644 --- a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c @@ -618,6 +618,7 @@ static const struct gpu_ops gv11b_ops = { .get_sema_wait_cmd_size = gv11b_fifo_get_sema_wait_cmd_size, .get_sema_incr_cmd_size = gv11b_fifo_get_sema_incr_cmd_size, .add_sema_cmd = gv11b_fifo_add_sema_cmd, + .set_sm_exception_type_mask = gk20a_tsg_set_sm_exception_type_mask, }, .gr_ctx = { .get_netlist_name = gr_gv11b_get_netlist_name, diff --git a/drivers/gpu/nvgpu/include/nvgpu/gk20a.h b/drivers/gpu/nvgpu/include/nvgpu/gk20a.h index 9707ed502..58e7ce898 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/gk20a.h +++ b/drivers/gpu/nvgpu/include/nvgpu/gk20a.h @@ -759,6 +759,8 @@ struct gpu_ops { u32 off, bool acquire, bool wfi); int (*init_pdb_cache_war)(struct gk20a *g); void (*deinit_pdb_cache_war)(struct gk20a *g); + int (*set_sm_exception_type_mask)(struct channel_gk20a *ch, + u32 exception_mask); } fifo; struct pmu_v { u32 (*get_pmu_cmdline_args_size)(struct nvgpu_pmu *pmu); diff --git a/drivers/gpu/nvgpu/include/nvgpu/tsg.h b/drivers/gpu/nvgpu/include/nvgpu/tsg.h index bed84986f..2852f0d31 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/tsg.h +++ b/drivers/gpu/nvgpu/include/nvgpu/tsg.h @@ -82,6 +82,7 @@ struct tsg_gk20a { #define NVGPU_SM_EXCEPTION_TYPE_MASK_NONE (0x0U) #define NVGPU_SM_EXCEPTION_TYPE_MASK_FATAL (0x1U << 0) u32 sm_exception_mask_type; + struct nvgpu_mutex sm_exception_mask_lock; }; int gk20a_enable_tsg(struct tsg_gk20a *tsg); @@ -103,6 +104,8 @@ int gk20a_tsg_alloc_sm_error_states_mem(struct gk20a *g, void gk20a_tsg_update_sm_error_state_locked(struct tsg_gk20a *tsg, u32 sm_id, struct nvgpu_tsg_sm_error_state *sm_error_state); +int gk20a_tsg_set_sm_exception_type_mask(struct channel_gk20a *ch, + u32 exception_mask); struct gk20a_event_id_data { struct gk20a *g; diff --git a/drivers/gpu/nvgpu/include/nvgpu/vgpu/tegra_vgpu.h b/drivers/gpu/nvgpu/include/nvgpu/vgpu/tegra_vgpu.h index 5ee50b189..aa71e2951 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/vgpu/tegra_vgpu.h +++ b/drivers/gpu/nvgpu/include/nvgpu/vgpu/tegra_vgpu.h @@ -123,6 +123,7 @@ enum { TEGRA_VGPU_CMD_RESUME = 83, TEGRA_VGPU_CMD_GET_ECC_INFO = 84, TEGRA_VGPU_CMD_GET_ECC_COUNTER_VALUE = 85, + TEGRA_VGPU_CMD_SET_SM_EXCEPTION_TYPE_MASK = 86, }; struct tegra_vgpu_connect_params { @@ -467,6 +468,11 @@ struct tegra_vgpu_gpu_clk_rate_params { u32 rate; /* in kHz */ }; +struct tegra_vgpu_set_sm_exception_type_mask_params { + u64 handle; + u32 mask; +}; + /* TEGRA_VGPU_MAX_ENGINES must be equal or greater than num_engines */ #define TEGRA_VGPU_MAX_ENGINES 4 struct tegra_vgpu_engines_info { @@ -678,6 +684,7 @@ struct tegra_vgpu_cmd_msg { struct tegra_vgpu_channel_update_pc_sampling update_pc_sampling; struct tegra_vgpu_ecc_info_params ecc_info; struct tegra_vgpu_ecc_counter_params ecc_counter; + struct tegra_vgpu_set_sm_exception_type_mask_params set_sm_exception_mask; char padding[192]; } params; }; diff --git a/drivers/gpu/nvgpu/os/linux/ioctl_dbg.c b/drivers/gpu/nvgpu/os/linux/ioctl_dbg.c index 510b53254..85247261c 100644 --- a/drivers/gpu/nvgpu/os/linux/ioctl_dbg.c +++ b/drivers/gpu/nvgpu/os/linux/ioctl_dbg.c @@ -154,10 +154,6 @@ static int dbg_unbind_all_channels_gk20a(struct dbg_session_gk20a *dbg_s); static int gk20a_dbg_gpu_do_dev_open(struct inode *inode, struct file *filp, bool is_profiler); -static int nvgpu_set_sm_exception_type_mask_locked( - struct dbg_session_gk20a *dbg_s, - u32 exception_mask); - unsigned int gk20a_dbg_gpu_dev_poll(struct file *filep, poll_table *wait) { unsigned int mask = 0; @@ -1807,44 +1803,13 @@ out: return err; } -static int nvgpu_set_sm_exception_type_mask_locked( - struct dbg_session_gk20a *dbg_s, - u32 exception_mask) -{ - struct gk20a *g = dbg_s->g; - int err = 0; - struct channel_gk20a *ch = NULL; - - /* - * Obtain the fisrt channel from the channel list in - * dbg_session, find the context associated with channel - * and set the sm_mask_type to that context - */ - ch = nvgpu_dbg_gpu_get_session_channel(dbg_s); - if (ch != NULL) { - struct tsg_gk20a *tsg; - - tsg = tsg_gk20a_from_ch(ch); - if (tsg != NULL) { - tsg->sm_exception_mask_type = exception_mask; - goto type_mask_end; - } - } - - nvgpu_log_fn(g, "unable to find the TSG\n"); - err = -EINVAL; - -type_mask_end: - return err; -} - -static int nvgpu_dbg_gpu_set_sm_exception_type_mask( - struct dbg_session_gk20a *dbg_s, +static int nvgpu_dbg_gpu_set_sm_exception_type_mask(struct dbg_session_gk20a *dbg_s, struct nvgpu_dbg_gpu_set_sm_exception_type_mask_args *args) { int err = 0; struct gk20a *g = dbg_s->g; u32 sm_exception_mask_type = NVGPU_SM_EXCEPTION_TYPE_MASK_NONE; + struct channel_gk20a *ch = NULL; switch (args->exception_type_mask) { case NVGPU_DBG_GPU_IOCTL_SET_SM_EXCEPTION_TYPE_MASK_FATAL: @@ -1865,10 +1830,17 @@ static int nvgpu_dbg_gpu_set_sm_exception_type_mask( return err; } - nvgpu_mutex_acquire(&g->dbg_sessions_lock); - err = nvgpu_set_sm_exception_type_mask_locked(dbg_s, - sm_exception_mask_type); - nvgpu_mutex_release(&g->dbg_sessions_lock); + ch = nvgpu_dbg_gpu_get_session_channel(dbg_s); + if (ch != NULL) { + if (g->ops.fifo.set_sm_exception_type_mask == NULL) { + nvgpu_err(g, "set_sm_exception_type_mask not set"); + return -EINVAL; + } + err = g->ops.fifo.set_sm_exception_type_mask(ch, + sm_exception_mask_type); + } else { + err = -EINVAL; + } return err; } diff --git a/drivers/gpu/nvgpu/tu104/hal_tu104.c b/drivers/gpu/nvgpu/tu104/hal_tu104.c index 0e16bc2c2..1c255676e 100644 --- a/drivers/gpu/nvgpu/tu104/hal_tu104.c +++ b/drivers/gpu/nvgpu/tu104/hal_tu104.c @@ -632,6 +632,7 @@ static const struct gpu_ops tu104_ops = { .add_sema_cmd = gv11b_fifo_add_sema_cmd, .init_pdb_cache_war = tu104_init_pdb_cache_war, .deinit_pdb_cache_war = tu104_deinit_pdb_cache_war, + .set_sm_exception_type_mask = gk20a_tsg_set_sm_exception_type_mask, }, .gr_ctx = { .get_netlist_name = gr_tu104_get_netlist_name, diff --git a/drivers/gpu/nvgpu/vgpu/fifo_vgpu.h b/drivers/gpu/nvgpu/vgpu/fifo_vgpu.h index 20205d3c1..ecaaaf232 100644 --- a/drivers/gpu/nvgpu/vgpu/fifo_vgpu.h +++ b/drivers/gpu/nvgpu/vgpu/fifo_vgpu.h @@ -61,5 +61,5 @@ int vgpu_tsg_bind_channel(struct tsg_gk20a *tsg, int vgpu_tsg_unbind_channel(struct channel_gk20a *ch); int vgpu_tsg_set_timeslice(struct tsg_gk20a *tsg, u32 timeslice); int vgpu_enable_tsg(struct tsg_gk20a *tsg); - +int vgpu_set_sm_exception_type_mask(struct channel_gk20a *ch, u32 mask); #endif diff --git a/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c b/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c index 2f9fe6386..c7072b17d 100644 --- a/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c +++ b/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c @@ -359,6 +359,7 @@ static const struct gpu_ops vgpu_gp10b_ops = { .get_sema_wait_cmd_size = gk20a_fifo_get_sema_wait_cmd_size, .get_sema_incr_cmd_size = gk20a_fifo_get_sema_incr_cmd_size, .add_sema_cmd = gk20a_fifo_add_sema_cmd, + .set_sm_exception_type_mask = vgpu_set_sm_exception_type_mask, }, .gr_ctx = { .get_netlist_name = gr_gp10b_get_netlist_name, diff --git a/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c b/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c index 1b2535242..b9cf88d66 100644 --- a/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c +++ b/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c @@ -429,6 +429,7 @@ static const struct gpu_ops vgpu_gv11b_ops = { .get_sema_wait_cmd_size = gv11b_fifo_get_sema_wait_cmd_size, .get_sema_incr_cmd_size = gv11b_fifo_get_sema_incr_cmd_size, .add_sema_cmd = gv11b_fifo_add_sema_cmd, + .set_sm_exception_type_mask = vgpu_set_sm_exception_type_mask, }, .gr_ctx = { .get_netlist_name = gr_gv11b_get_netlist_name, diff --git a/drivers/gpu/nvgpu/vgpu/tsg_vgpu.c b/drivers/gpu/nvgpu/vgpu/tsg_vgpu.c index 3553bf51d..d89dc9f54 100644 --- a/drivers/gpu/nvgpu/vgpu/tsg_vgpu.c +++ b/drivers/gpu/nvgpu/vgpu/tsg_vgpu.c @@ -164,3 +164,26 @@ int vgpu_tsg_set_timeslice(struct tsg_gk20a *tsg, u32 timeslice) return err; } + +int vgpu_set_sm_exception_type_mask(struct channel_gk20a *ch, + u32 exception_mask) +{ + struct tegra_vgpu_cmd_msg msg; + struct tegra_vgpu_set_sm_exception_type_mask_params *p = + &msg.params.set_sm_exception_mask; + int err = 0; + struct gk20a *g = ch->g; + + nvgpu_log_fn(g, " "); + + msg.cmd = TEGRA_VGPU_CMD_SET_SM_EXCEPTION_TYPE_MASK; + msg.handle = vgpu_get_handle(g); + p->handle = ch->virt_ctx; + p->mask = exception_mask; + err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg)); + err = err ? err : msg.ret; + WARN_ON(err); + + return err; +} +