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gpu: nvgpu: fix CERT EXP34-C issue

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Fix CERT issue in nvgpu_gr_falcon_bind_fecs_elpg where nvgpu_pmu_pg_buf
could return NULL. nvgpu_pmu_pg_buf is called from context where PG
will be enabled hence remove the NULL return logic as it is dead
code.

Replace nvgpu_pmu_pg_buf and nvgpu_pmu_pg_buf_get_cpu_va functions by
new function nvgpu_pmu_pg_buf_alloc.

CID 17860
Bug 3512546

Change-Id: I09820a966dadeb258167ce1433ca256f94845896
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2692466
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Sagar Kamble
2022-04-06 08:46:26 +05:30
committed by mobile promotions
parent 02b108d26d
commit e1cdfaa208
3 changed files with 17 additions and 23 deletions
Download Patch File Download Diff File Expand all files Collapse all files

11
drivers/gpu/nvgpu/common/gr/gr_falcon.c
View File

@@ -90,7 +90,6 @@ int nvgpu_gr_falcon_bind_fecs_elpg(struct gk20a *g)
#ifdef CONFIG_NVGPU_LS_PMU #ifdef CONFIG_NVGPU_LS_PMU
struct nvgpu_pmu *pmu = g->pmu; struct nvgpu_pmu *pmu = g->pmu;
struct mm_gk20a *mm = &g->mm; struct mm_gk20a *mm = &g->mm;
struct vm_gk20a *vm = mm->pmu.vm;
int err = 0; int err = 0;
u32 size; u32 size;
u32 data; u32 data;
@@ -109,12 +108,10 @@ int nvgpu_gr_falcon_bind_fecs_elpg(struct gk20a *g)
nvgpu_log(g, gpu_dbg_gr, "FECS PG buffer size = %u", size); nvgpu_log(g, gpu_dbg_gr, "FECS PG buffer size = %u", size);
if (nvgpu_pmu_pg_buf_get_cpu_va(g, pmu) == NULL) { err = nvgpu_pmu_pg_buf_alloc(g, pmu, size);
err = nvgpu_dma_alloc_map_sys(vm, size, nvgpu_pmu_pg_buf(g, pmu)); if (err != 0) {
if (err != 0) { nvgpu_err(g, "failed to allocate pg_buf memory");
nvgpu_err(g, "failed to allocate memory"); return err;
return -ENOMEM;
}
} }
data = g->ops.gr.falcon.get_fecs_current_ctx_data(g, data = g->ops.gr.falcon.get_fecs_current_ctx_data(g,

25
drivers/gpu/nvgpu/common/pmu/pg/pmu_pg.c
View File

@@ -1188,22 +1188,21 @@ u64 nvgpu_pmu_pg_buf_get_gpu_va(struct gk20a *g, struct nvgpu_pmu *pmu)
return pmu->pg->pg_buf.gpu_va; return pmu->pg->pg_buf.gpu_va;
} }
struct nvgpu_mem *nvgpu_pmu_pg_buf(struct gk20a *g, struct nvgpu_pmu *pmu) int nvgpu_pmu_pg_buf_alloc(struct gk20a *g, struct nvgpu_pmu *pmu, u32 size)
{ {
if (!is_pg_supported(g, pmu->pg)) { struct mm_gk20a *mm = &g->mm;
return NULL; struct vm_gk20a *vm = mm->pmu.vm;
int err = 0;
if (!nvgpu_mem_is_valid(&pmu->pg->pg_buf)) {
err = nvgpu_dma_alloc_map_sys(vm, size, &pmu->pg->pg_buf);
if (err != 0) {
nvgpu_err(g, "failed to allocate pg_buf");
return err;
}
} }
return &pmu->pg->pg_buf; return err;
}
void *nvgpu_pmu_pg_buf_get_cpu_va(struct gk20a *g, struct nvgpu_pmu *pmu)
{
if (!is_pg_supported(g, pmu->pg)) {
return NULL;
}
return pmu->pg->pg_buf.cpu_va;
} }
int nvgpu_pmu_restore_golden_img_state(struct gk20a *g) int nvgpu_pmu_restore_golden_img_state(struct gk20a *g)

4
drivers/gpu/nvgpu/include/nvgpu/pmu/pmu_pg.h
View File

@@ -176,9 +176,7 @@ int nvgpu_pmu_elpg_statistics(struct gk20a *g, u32 pg_engine_id,
struct pmu_pg_stats_data *pg_stat_data); struct pmu_pg_stats_data *pg_stat_data);
void nvgpu_pmu_save_zbc(struct gk20a *g, u32 entries); void nvgpu_pmu_save_zbc(struct gk20a *g, u32 entries);
bool nvgpu_pmu_is_lpwr_feature_supported(struct gk20a *g, u32 feature_id); bool nvgpu_pmu_is_lpwr_feature_supported(struct gk20a *g, u32 feature_id);
int nvgpu_pmu_pg_buf_alloc(struct gk20a *g, struct nvgpu_pmu *pmu, u32 size);
u64 nvgpu_pmu_pg_buf_get_gpu_va(struct gk20a *g, struct nvgpu_pmu *pmu); u64 nvgpu_pmu_pg_buf_get_gpu_va(struct gk20a *g, struct nvgpu_pmu *pmu);
struct nvgpu_mem *nvgpu_pmu_pg_buf(struct gk20a *g, struct nvgpu_pmu *pmu);
void *nvgpu_pmu_pg_buf_get_cpu_va(struct gk20a *g, struct nvgpu_pmu *pmu);
#endif /* NVGPU_PMU_PG_H */ #endif /* NVGPU_PMU_PG_H */