From e1d6b8af8d79a0b05ebb5cb45d1b95913b900afe Mon Sep 17 00:00:00 2001 From: dt Date: Fri, 12 Nov 2021 06:37:42 +0000 Subject: [PATCH] gpu: nvgpu: ga10x: compute gnic_stride GNIC register stride calculation is fixed by adding new hal to compute the stride by getting the difference of gpc1 and gpc0 xbar_gnic strides for ga10x GPUs. Bug 200782045 Change-Id: Iaa84109bd9f1a974ef1af6fee136ca1fcc89bbb1 Signed-off-by: Dinesh T Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2624848 Tested-by: mobile promotions Reviewed-by: mobile promotions --- arch/nvgpu-gpu_hw.yaml | 4 +- drivers/gpu/nvgpu/common/gr/hwpm_map.c | 2 +- .../hal/gr/ctxsw_prog/ctxsw_prog_ga100.c | 10 ++- .../hal/gr/ctxsw_prog/ctxsw_prog_ga100.h | 3 +- .../hal/gr/ctxsw_prog/ctxsw_prog_gm20b.h | 4 ++ .../hal/gr/ctxsw_prog/ctxsw_prog_gm20b_dbg.c | 7 +- drivers/gpu/nvgpu/hal/init/hal_ga100.c | 1 + drivers/gpu/nvgpu/hal/init/hal_ga10b.c | 2 + drivers/gpu/nvgpu/hal/init/hal_gm20b.c | 1 + drivers/gpu/nvgpu/hal/init/hal_gp10b.c | 1 + drivers/gpu/nvgpu/hal/init/hal_gv11b.c | 1 + drivers/gpu/nvgpu/hal/init/hal_tu104.c | 1 + .../gpu/nvgpu/hal/vgpu/init/vgpu_hal_ga10b.c | 2 + .../gpu/nvgpu/hal/vgpu/init/vgpu_hal_gv11b.c | 1 + drivers/gpu/nvgpu/include/nvgpu/gops/gr.h | 3 +- .../include/nvgpu/hw/ga100/hw_xbar_ga100.h | 64 +++++++++++++++++++ .../include/nvgpu/hw/ga10b/hw_xbar_ga10b.h | 64 +++++++++++++++++++ 17 files changed, 165 insertions(+), 6 deletions(-) create mode 100644 drivers/gpu/nvgpu/include/nvgpu/hw/ga100/hw_xbar_ga100.h create mode 100644 drivers/gpu/nvgpu/include/nvgpu/hw/ga10b/hw_xbar_ga10b.h diff --git a/arch/nvgpu-gpu_hw.yaml b/arch/nvgpu-gpu_hw.yaml index 3f26fc045..232721763 100644 --- a/arch/nvgpu-gpu_hw.yaml +++ b/arch/nvgpu-gpu_hw.yaml @@ -259,6 +259,7 @@ headers: include/nvgpu/hw/ga100/hw_xp_ga100.h, include/nvgpu/hw/ga100/hw_xve_ga100.h, include/nvgpu/hw/ga100/hw_fbpa_ga100.h, + include/nvgpu/hw/ga100/hw_xbar_ga100.h, include/nvgpu/hw/ga10b/hw_bus_ga10b.h, include/nvgpu/hw/ga10b/hw_ccsr_ga10b.h, include/nvgpu/hw/ga10b/hw_ce_ga10b.h, @@ -290,4 +291,5 @@ headers: include/nvgpu/hw/ga10b/hw_smcarb_ga10b.h, include/nvgpu/hw/ga10b/hw_therm_ga10b.h, include/nvgpu/hw/ga10b/hw_timer_ga10b.h, - include/nvgpu/hw/ga10b/hw_top_ga10b.h ] + include/nvgpu/hw/ga10b/hw_top_ga10b.h, + include/nvgpu/hw/ga10b/hw_xbar_ga10b.h ] diff --git a/drivers/gpu/nvgpu/common/gr/hwpm_map.c b/drivers/gpu/nvgpu/common/gr/hwpm_map.c index 8a31b12f3..368b8e0c3 100644 --- a/drivers/gpu/nvgpu/common/gr/hwpm_map.c +++ b/drivers/gpu/nvgpu/common/gr/hwpm_map.c @@ -286,7 +286,7 @@ static int add_ctxsw_buffer_map_entries_gpcs(struct gk20a *g, return -EINVAL; } - base = NV_XBAR_MXBAR_PRI_GPC_GNIC_STRIDE * gpc_num; + base = (g->ops.gr.ctxsw_prog.hw_get_pm_gpc_gnic_stride(g)) * gpc_num; if (add_ctxsw_buffer_map_entries(map, nvgpu_netlist_get_pm_ucgpc_ctxsw_regs(g), count, offset, max_cnt, base, ~U32(0U)) != 0) { diff --git a/drivers/gpu/nvgpu/hal/gr/ctxsw_prog/ctxsw_prog_ga100.c b/drivers/gpu/nvgpu/hal/gr/ctxsw_prog/ctxsw_prog_ga100.c index 264cfb892..4f538a317 100644 --- a/drivers/gpu/nvgpu/hal/gr/ctxsw_prog/ctxsw_prog_ga100.c +++ b/drivers/gpu/nvgpu/hal/gr/ctxsw_prog/ctxsw_prog_ga100.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2020-2021, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -25,6 +25,7 @@ #include #include +#include #ifdef CONFIG_DEBUG_FS void ga100_ctxsw_prog_dump_ctxsw_stats(struct gk20a *g, @@ -82,3 +83,10 @@ void ga100_ctxsw_prog_dump_ctxsw_stats(struct gk20a *g, ctxsw_prog_main_image_compute_preemption_options_o())); } #endif +#ifdef CONFIG_NVGPU_DEBUGGER +u32 ga100_ctxsw_prog_hw_get_pm_gpc_gnic_stride(struct gk20a *g) +{ + return (xbar_mxbar_pri_gpc1_gnic0_preg_pm_ctrl_r() - + xbar_mxbar_pri_gpc0_gnic0_preg_pm_ctrl_r()); +} +#endif diff --git a/drivers/gpu/nvgpu/hal/gr/ctxsw_prog/ctxsw_prog_ga100.h b/drivers/gpu/nvgpu/hal/gr/ctxsw_prog/ctxsw_prog_ga100.h index c8ef806ef..448a91b36 100644 --- a/drivers/gpu/nvgpu/hal/gr/ctxsw_prog/ctxsw_prog_ga100.h +++ b/drivers/gpu/nvgpu/hal/gr/ctxsw_prog/ctxsw_prog_ga100.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2020-2021, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -34,6 +34,7 @@ u32 ga100_ctxsw_prog_hw_get_fecs_header_size(void); u32 ga100_ctxsw_prog_hw_get_gpccs_header_size(void); bool ga100_ctxsw_prog_check_main_image_header_magic(u32 *context); bool ga100_ctxsw_prog_check_local_header_magic(u32 *context); +u32 ga100_ctxsw_prog_hw_get_pm_gpc_gnic_stride(struct gk20a *g); #endif /* CONFIG_NVGPU_DEBUGGER */ #ifdef CONFIG_DEBUG_FS void ga100_ctxsw_prog_dump_ctxsw_stats(struct gk20a *g, diff --git a/drivers/gpu/nvgpu/hal/gr/ctxsw_prog/ctxsw_prog_gm20b.h b/drivers/gpu/nvgpu/hal/gr/ctxsw_prog/ctxsw_prog_gm20b.h index 517ae10e5..515c1a6b7 100644 --- a/drivers/gpu/nvgpu/hal/gr/ctxsw_prog/ctxsw_prog_gm20b.h +++ b/drivers/gpu/nvgpu/hal/gr/ctxsw_prog/ctxsw_prog_gm20b.h @@ -58,6 +58,9 @@ void gm20b_ctxsw_prog_set_zcull_mode_no_ctxsw(struct gk20a *g, bool gm20b_ctxsw_prog_is_zcull_mode_separate_buffer(u32 mode); #endif /* CONFIG_NVGPU_GRAPHICS */ #ifdef CONFIG_NVGPU_DEBUGGER + +#define NV_XBAR_MXBAR_PRI_GPC_GNIC_STRIDE 0x20U + u32 gm20b_ctxsw_prog_hw_get_gpccs_header_size(void); u32 gm20b_ctxsw_prog_hw_get_extended_buffer_segments_size_in_bytes(void); u32 gm20b_ctxsw_prog_hw_extended_marker_size_in_bytes(void); @@ -83,6 +86,7 @@ void gm20b_ctxsw_prog_get_extended_buffer_size_offset(u32 *context, u32 *size, u32 *offset); void gm20b_ctxsw_prog_get_ppc_info(u32 *context, u32 *num_ppcs, u32 *ppc_mask); u32 gm20b_ctxsw_prog_get_local_priv_register_ctl_offset(u32 *context); +u32 gm20b_ctxsw_prog_hw_get_pm_gpc_gnic_stride(struct gk20a *g); #endif /* CONFIG_NVGPU_DEBUGGER */ #ifdef CONFIG_NVGPU_FECS_TRACE u32 gm20b_ctxsw_prog_hw_get_ts_tag_invalid_timestamp(void); diff --git a/drivers/gpu/nvgpu/hal/gr/ctxsw_prog/ctxsw_prog_gm20b_dbg.c b/drivers/gpu/nvgpu/hal/gr/ctxsw_prog/ctxsw_prog_gm20b_dbg.c index f641ae205..98e8c7b6b 100644 --- a/drivers/gpu/nvgpu/hal/gr/ctxsw_prog/ctxsw_prog_gm20b_dbg.c +++ b/drivers/gpu/nvgpu/hal/gr/ctxsw_prog/ctxsw_prog_gm20b_dbg.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018-2019, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2018-2021, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -167,4 +167,9 @@ u32 gm20b_ctxsw_prog_get_local_priv_register_ctl_offset(u32 *context) u32 data = *(context + (ctxsw_prog_local_priv_register_ctl_o() >> 2)); return ctxsw_prog_local_priv_register_ctl_offset_v(data); } + +u32 gm20b_ctxsw_prog_hw_get_pm_gpc_gnic_stride(struct gk20a *g) +{ + return NV_XBAR_MXBAR_PRI_GPC_GNIC_STRIDE; +} #endif /* CONFIG_NVGPU_DEBUGGER */ diff --git a/drivers/gpu/nvgpu/hal/init/hal_ga100.c b/drivers/gpu/nvgpu/hal/init/hal_ga100.c index e5ddefeb0..0fbd4e4d8 100644 --- a/drivers/gpu/nvgpu/hal/init/hal_ga100.c +++ b/drivers/gpu/nvgpu/hal/init/hal_ga100.c @@ -492,6 +492,7 @@ static const struct gops_gr_ctxsw_prog ga100_ops_gr_ctxsw_prog = { .get_local_priv_register_ctl_offset = gm20b_ctxsw_prog_get_local_priv_register_ctl_offset, .set_pmu_options_boost_clock_frequencies = NULL, .hw_get_perf_counter_register_stride = gv11b_ctxsw_prog_hw_get_perf_counter_register_stride, + .hw_get_pm_gpc_gnic_stride = ga100_ctxsw_prog_hw_get_pm_gpc_gnic_stride, #endif /* CONFIG_NVGPU_DEBUGGER */ #ifdef CONFIG_DEBUG_FS .dump_ctxsw_stats = ga100_ctxsw_prog_dump_ctxsw_stats, diff --git a/drivers/gpu/nvgpu/hal/init/hal_ga10b.c b/drivers/gpu/nvgpu/hal/init/hal_ga10b.c index 03804eb83..161a74e24 100644 --- a/drivers/gpu/nvgpu/hal/init/hal_ga10b.c +++ b/drivers/gpu/nvgpu/hal/init/hal_ga10b.c @@ -200,6 +200,7 @@ #include "hal/gr/ctxsw_prog/ctxsw_prog_gp10b.h" #include "hal/gr/ctxsw_prog/ctxsw_prog_gv11b.h" #include "hal/gr/ctxsw_prog/ctxsw_prog_ga10b.h" +#include "hal/gr/ctxsw_prog/ctxsw_prog_ga100.h" #ifdef CONFIG_NVGPU_DEBUGGER #include "hal/gr/gr/gr_gk20a.h" #include "hal/gr/gr/gr_gm20b.h" @@ -459,6 +460,7 @@ static const struct gops_gr_ctxsw_prog ga10b_ops_gr_ctxsw_prog = { .get_local_priv_register_ctl_offset = gm20b_ctxsw_prog_get_local_priv_register_ctl_offset, .set_pmu_options_boost_clock_frequencies = NULL, .hw_get_perf_counter_register_stride = gv11b_ctxsw_prog_hw_get_perf_counter_register_stride, + .hw_get_pm_gpc_gnic_stride = ga100_ctxsw_prog_hw_get_pm_gpc_gnic_stride, .hw_get_main_header_size = ga10b_ctxsw_prog_hw_get_main_header_size, .hw_get_gpccs_header_stride = ga10b_ctxsw_prog_hw_get_gpccs_header_stride, .get_compute_sysreglist_offset = ga10b_ctxsw_prog_get_compute_sysreglist_offset, diff --git a/drivers/gpu/nvgpu/hal/init/hal_gm20b.c b/drivers/gpu/nvgpu/hal/init/hal_gm20b.c index 604319efe..bbbfe057a 100644 --- a/drivers/gpu/nvgpu/hal/init/hal_gm20b.c +++ b/drivers/gpu/nvgpu/hal/init/hal_gm20b.c @@ -234,6 +234,7 @@ static const struct gops_gr_ctxsw_prog gm20b_ops_gr_ctxsw_prog = { .get_extended_buffer_size_offset = gm20b_ctxsw_prog_get_extended_buffer_size_offset, .get_ppc_info = gm20b_ctxsw_prog_get_ppc_info, .get_local_priv_register_ctl_offset = gm20b_ctxsw_prog_get_local_priv_register_ctl_offset, + .hw_get_pm_gpc_gnic_stride = gm20b_ctxsw_prog_hw_get_pm_gpc_gnic_stride, #endif /* CONFIG_NVGPU_DEBUGGER */ #ifdef CONFIG_NVGPU_FECS_TRACE .hw_get_ts_tag_invalid_timestamp = gm20b_ctxsw_prog_hw_get_ts_tag_invalid_timestamp, diff --git a/drivers/gpu/nvgpu/hal/init/hal_gp10b.c b/drivers/gpu/nvgpu/hal/init/hal_gp10b.c index 5c27c8c92..b5a422121 100644 --- a/drivers/gpu/nvgpu/hal/init/hal_gp10b.c +++ b/drivers/gpu/nvgpu/hal/init/hal_gp10b.c @@ -297,6 +297,7 @@ static const struct gops_gr_ctxsw_prog gp10b_ops_gr_ctxsw_prog = { .get_ppc_info = gm20b_ctxsw_prog_get_ppc_info, .get_local_priv_register_ctl_offset = gm20b_ctxsw_prog_get_local_priv_register_ctl_offset, .set_pmu_options_boost_clock_frequencies = gp10b_ctxsw_prog_set_pmu_options_boost_clock_frequencies, + .hw_get_pm_gpc_gnic_stride = gm20b_ctxsw_prog_hw_get_pm_gpc_gnic_stride, #endif /* CONFIG_NVGPU_DEBUGGER */ #ifdef CONFIG_DEBUG_FS .dump_ctxsw_stats = gp10b_ctxsw_prog_dump_ctxsw_stats, diff --git a/drivers/gpu/nvgpu/hal/init/hal_gv11b.c b/drivers/gpu/nvgpu/hal/init/hal_gv11b.c index 9ff90b1c7..f731fde76 100644 --- a/drivers/gpu/nvgpu/hal/init/hal_gv11b.c +++ b/drivers/gpu/nvgpu/hal/init/hal_gv11b.c @@ -379,6 +379,7 @@ static const struct gops_gr_ctxsw_prog gv11b_ops_gr_ctxsw_prog = { .get_local_priv_register_ctl_offset = gm20b_ctxsw_prog_get_local_priv_register_ctl_offset, .set_pmu_options_boost_clock_frequencies = NULL, .hw_get_perf_counter_register_stride = gv11b_ctxsw_prog_hw_get_perf_counter_register_stride, + .hw_get_pm_gpc_gnic_stride = gm20b_ctxsw_prog_hw_get_pm_gpc_gnic_stride, #endif /* CONFIG_NVGPU_DEBUGGER */ #ifdef CONFIG_DEBUG_FS .dump_ctxsw_stats = gp10b_ctxsw_prog_dump_ctxsw_stats, diff --git a/drivers/gpu/nvgpu/hal/init/hal_tu104.c b/drivers/gpu/nvgpu/hal/init/hal_tu104.c index 248098528..70a92300d 100644 --- a/drivers/gpu/nvgpu/hal/init/hal_tu104.c +++ b/drivers/gpu/nvgpu/hal/init/hal_tu104.c @@ -423,6 +423,7 @@ static const struct gops_gr_ctxsw_prog tu104_ops_gr_ctxsw_prog = { .get_local_priv_register_ctl_offset = gm20b_ctxsw_prog_get_local_priv_register_ctl_offset, .set_pmu_options_boost_clock_frequencies = gp10b_ctxsw_prog_set_pmu_options_boost_clock_frequencies, .hw_get_perf_counter_register_stride = gv11b_ctxsw_prog_hw_get_perf_counter_register_stride, + .hw_get_pm_gpc_gnic_stride = gm20b_ctxsw_prog_hw_get_pm_gpc_gnic_stride, #endif /* CONFIG_NVGPU_DEBUGGER */ #ifdef CONFIG_DEBUG_FS .dump_ctxsw_stats = gp10b_ctxsw_prog_dump_ctxsw_stats, diff --git a/drivers/gpu/nvgpu/hal/vgpu/init/vgpu_hal_ga10b.c b/drivers/gpu/nvgpu/hal/vgpu/init/vgpu_hal_ga10b.c index 8be8e89dd..203f3d35f 100644 --- a/drivers/gpu/nvgpu/hal/vgpu/init/vgpu_hal_ga10b.c +++ b/drivers/gpu/nvgpu/hal/vgpu/init/vgpu_hal_ga10b.c @@ -54,6 +54,7 @@ #include "hal/fifo/usermode_tu104.h" #include "hal/fifo/usermode_ga10b.h" #include "hal/fifo/fifo_intr_gv11b.h" +#include "hal/gr/ctxsw_prog/ctxsw_prog_ga100.h" #include "hal/gr/ctxsw_prog/ctxsw_prog_ga10b.h" #include "hal/gr/gr/gr_ga10b.h" #include "hal/gr/init/gr_init_ga10b.h" @@ -321,6 +322,7 @@ static const struct gops_gr_ctxsw_prog vgpu_ga10b_ops_gr_ctxsw_prog = { .get_extended_buffer_size_offset = gm20b_ctxsw_prog_get_extended_buffer_size_offset, .get_ppc_info = gm20b_ctxsw_prog_get_ppc_info, .get_local_priv_register_ctl_offset = gm20b_ctxsw_prog_get_local_priv_register_ctl_offset, + .hw_get_pm_gpc_gnic_stride = ga100_ctxsw_prog_hw_get_pm_gpc_gnic_stride, #endif /* CONFIG_NVGPU_DEBUGGER */ #ifdef CONFIG_NVGPU_FECS_TRACE .hw_get_ts_tag_invalid_timestamp = gm20b_ctxsw_prog_hw_get_ts_tag_invalid_timestamp, diff --git a/drivers/gpu/nvgpu/hal/vgpu/init/vgpu_hal_gv11b.c b/drivers/gpu/nvgpu/hal/vgpu/init/vgpu_hal_gv11b.c index 5335c1263..9356b7344 100644 --- a/drivers/gpu/nvgpu/hal/vgpu/init/vgpu_hal_gv11b.c +++ b/drivers/gpu/nvgpu/hal/vgpu/init/vgpu_hal_gv11b.c @@ -292,6 +292,7 @@ static const struct gops_gr_ctxsw_prog vgpu_gv11b_ops_gr_ctxsw_prog = { .get_extended_buffer_size_offset = gm20b_ctxsw_prog_get_extended_buffer_size_offset, .get_ppc_info = gm20b_ctxsw_prog_get_ppc_info, .get_local_priv_register_ctl_offset = gm20b_ctxsw_prog_get_local_priv_register_ctl_offset, + .hw_get_pm_gpc_gnic_stride = gm20b_ctxsw_prog_hw_get_pm_gpc_gnic_stride, #endif /* CONFIG_NVGPU_DEBUGGER */ #ifdef CONFIG_NVGPU_FECS_TRACE .hw_get_ts_tag_invalid_timestamp = gm20b_ctxsw_prog_hw_get_ts_tag_invalid_timestamp, diff --git a/drivers/gpu/nvgpu/include/nvgpu/gops/gr.h b/drivers/gpu/nvgpu/include/nvgpu/gops/gr.h index 328067055..58d294f9c 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/gops/gr.h +++ b/drivers/gpu/nvgpu/include/nvgpu/gops/gr.h @@ -1014,7 +1014,8 @@ struct gops_gr_ctxsw_prog { struct gk20a *g, struct nvgpu_mem *ctx_mem, u32 boosted_ctx); -#endif + u32 (*hw_get_pm_gpc_gnic_stride)(struct gk20a *g); +#endif /* CONFIG_NVGPU_DEBUGGER */ #ifdef CONFIG_DEBUG_FS void (*dump_ctxsw_stats)(struct gk20a *g, struct nvgpu_mem *ctx_mem); diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/ga100/hw_xbar_ga100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/ga100/hw_xbar_ga100.h new file mode 100644 index 000000000..53833fc84 --- /dev/null +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/ga100/hw_xbar_ga100.h @@ -0,0 +1,64 @@ +/* + * Copyright (c) 2021, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +/* + * Function/Macro naming determines intended use: + * + * _r(void) : Returns the offset for register . + * + * _o(void) : Returns the offset for element . + * + * _w(void) : Returns the word offset for word (4 byte) element . + * + * __s(void) : Returns size of field of register in bits. + * + * __f(u32 v) : Returns a value based on 'v' which has been shifted + * and masked to place it at field of register . This value + * can be |'d with others to produce a full register value for + * register . + * + * __m(void) : Returns a mask for field of register . This + * value can be ~'d and then &'d to clear the value of field for + * register . + * + * ___f(void) : Returns the constant value after being shifted + * to place it at field of register . This value can be |'d + * with others to produce a full register value for . + * + * __v(u32 r) : Returns the value of field from a full register + * value 'r' after being shifted to place its LSB at bit 0. + * This value is suitable for direct comparison with other unshifted + * values appropriate for use in field of register . + * + * ___v(void) : Returns the constant value for defined for + * field of register . This value is suitable for direct + * comparison with unshifted values appropriate for use in field + * of register . + */ +#ifndef NVGPU_HW_XBAR_GA100_H +#define NVGPU_HW_XBAR_GA100_H + +#include +#include + +#define xbar_mxbar_pri_gpc0_gnic0_preg_pm_ctrl_r() (0x0013cc14U) +#define xbar_mxbar_pri_gpc1_gnic0_preg_pm_ctrl_r() (0x0013cc94U) +#endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/ga10b/hw_xbar_ga10b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/ga10b/hw_xbar_ga10b.h new file mode 100644 index 000000000..4a90ed28e --- /dev/null +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/ga10b/hw_xbar_ga10b.h @@ -0,0 +1,64 @@ +/* + * Copyright (c) 2021, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +/* + * Function/Macro naming determines intended use: + * + * _r(void) : Returns the offset for register . + * + * _o(void) : Returns the offset for element . + * + * _w(void) : Returns the word offset for word (4 byte) element . + * + * __s(void) : Returns size of field of register in bits. + * + * __f(u32 v) : Returns a value based on 'v' which has been shifted + * and masked to place it at field of register . This value + * can be |'d with others to produce a full register value for + * register . + * + * __m(void) : Returns a mask for field of register . This + * value can be ~'d and then &'d to clear the value of field for + * register . + * + * ___f(void) : Returns the constant value after being shifted + * to place it at field of register . This value can be |'d + * with others to produce a full register value for . + * + * __v(u32 r) : Returns the value of field from a full register + * value 'r' after being shifted to place its LSB at bit 0. + * This value is suitable for direct comparison with other unshifted + * values appropriate for use in field of register . + * + * ___v(void) : Returns the constant value for defined for + * field of register . This value is suitable for direct + * comparison with unshifted values appropriate for use in field + * of register . + */ +#ifndef NVGPU_HW_XBAR_GA10B_H +#define NVGPU_HW_XBAR_GA10B_H + +#include +#include + +#define xbar_mxbar_pri_gpc0_gnic0_preg_pm_ctrl_r() (0x0013cc14U) +#define xbar_mxbar_pri_gpc1_gnic0_preg_pm_ctrl_r() (0x0013cc94U) +#endif