gpu: nvgpu: nvgpu_memcpy changes to linux os code

MISRA Rule 21.15 prohibits use of memcpy() with incompatible ptrs
to qualified/unqualified types.

To circumvent this issue we've introduced a new MISRA-compliant
nvgpu_memcpy() function.

While linux os code does not need to be MISRA-compliant this
change switches over all memcpy() uses to nvgpu_memcpy()
with appropriate casts applied to maintain consistency within
the nvgpu source base.

JIRA NVGPU-849

Change-Id: I2c21a7845df5709dafa19508c121f8afa27cc4fc
Signed-off-by: Scott Long <scottl@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1950995
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Nitin Kumbhar <nkumbhar@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

drivers/gpu/nvgpu/os/linux/cde.c

@@ -35,6 +35,7 @@
 #include <nvgpu/channel.h>
 #include <nvgpu/utils.h>
 #include <nvgpu/gk20a.h>
+#include <nvgpu/string.h>
 
 #include <nvgpu/linux/vm.h>
 
@@ -290,8 +291,9 @@ static int gk20a_init_cde_buf(struct gk20a_cde_ctx *cde_ctx,
 
 	/* copy the content */
 	if (buf->data_byte_offset != 0)
-		(void) memcpy(mem->cpu_va, img->data + buf->data_byte_offset,
+		nvgpu_memcpy((u8 *)mem->cpu_va,
-		       buf->num_bytes);
+			(u8 *)(img->data + buf->data_byte_offset),
+			buf->num_bytes);
 
 	cde_ctx->num_bufs++;
 
@@ -644,9 +646,10 @@ static int gk20a_cde_pack_cmdbufs(struct gk20a_cde_ctx *cde_ctx)
 	}
 
 	/* move the original init here and append convert */
-	(void) memcpy(combined_cmd, cde_ctx->init_convert_cmd, init_bytes);
+	nvgpu_memcpy((u8 *)combined_cmd,
-	(void) memcpy(combined_cmd + cde_ctx->init_cmd_num_entries,
+		(u8 *)cde_ctx->init_convert_cmd, init_bytes);
-			cde_ctx->convert_cmd, conv_bytes);
+	nvgpu_memcpy((u8 *)(combined_cmd + cde_ctx->init_cmd_num_entries),
+		(u8 *)cde_ctx->convert_cmd, conv_bytes);
 
 	nvgpu_kfree(g, cde_ctx->init_convert_cmd);
 	nvgpu_kfree(g, cde_ctx->convert_cmd);
@@ -714,8 +717,8 @@ static int gk20a_init_cde_img(struct gk20a_cde_ctx *cde_ctx,
 			break;
 		}
 		case TYPE_ARRAY:
-			(void) memcpy(&cde_app->arrays[elem->array.id][0],
+			nvgpu_memcpy((u8 *)&cde_app->arrays[elem->array.id][0],
-				elem->array.data,
+				(u8 *)elem->array.data,
 				MAX_CDE_ARRAY_ENTRIES*sizeof(u32));
 			break;
 		default:

drivers/gpu/nvgpu/os/linux/ctxsw_trace.c

@@ -27,6 +27,7 @@
 #include <nvgpu/barrier.h>
 #include <nvgpu/gk20a.h>
 #include <nvgpu/channel.h>
+#include <nvgpu/string.h>
 
 #include "gk20a/gr_gk20a.h"
 #include "gk20a/fecs_trace_gk20a.h"
@@ -252,14 +253,14 @@ static int gk20a_ctxsw_dev_ioctl_ring_setup(struct gk20a_ctxsw_dev *dev,
 static void nvgpu_set_ctxsw_trace_filter_args(struct nvgpu_gpu_ctxsw_trace_filter *filter_dst,
         struct nvgpu_ctxsw_trace_filter *filter_src)
 {
-	(void) memcpy(filter_dst->tag_bits, filter_src->tag_bits,
+	nvgpu_memcpy((u8 *)filter_dst->tag_bits, (u8 *)filter_src->tag_bits,
 		(NVGPU_CTXSW_FILTER_SIZE + 63) / 64);
 }
 
 static void nvgpu_get_ctxsw_trace_filter_args(struct nvgpu_ctxsw_trace_filter *filter_dst,
 	struct nvgpu_gpu_ctxsw_trace_filter *filter_src)
 {
-	(void) memcpy(filter_dst->tag_bits, filter_src->tag_bits,
+	nvgpu_memcpy((u8 *)filter_dst->tag_bits, (u8 *)filter_src->tag_bits,
 		(NVGPU_CTXSW_FILTER_SIZE + 63) / 64);
 }
 

drivers/gpu/nvgpu/os/linux/firmware.c

@@ -20,6 +20,7 @@
 #include <nvgpu/bug.h>
 #include <nvgpu/firmware.h>
 #include <nvgpu/gk20a.h>
+#include <nvgpu/string.h>
 
 #include "platform_gk20a.h"
 #include "os_linux.h"
@@ -93,7 +94,7 @@ struct nvgpu_firmware *nvgpu_request_firmware(struct gk20a *g,
 	if (!fw->data)
 		goto err_release;
 
-	(void) memcpy(fw->data, linux_fw->data, linux_fw->size);
+	nvgpu_memcpy((u8 *)fw->data, (u8 *)linux_fw->data, linux_fw->size);
 	fw->size = linux_fw->size;
 
 	release_firmware(linux_fw);

drivers/gpu/nvgpu/os/linux/nvgpu_mem.c

@@ -24,6 +24,7 @@
 #include <nvgpu/kmem.h>
 #include <nvgpu/vidmem.h>
 #include <nvgpu/gk20a.h>
+#include <nvgpu/string.h>
 
 #include <nvgpu/linux/dma.h>
 
@@ -202,7 +203,8 @@ int __nvgpu_mem_create_from_pages(struct gk20a *g, struct nvgpu_mem *dest,
 	if (!our_pages)
 		return -ENOMEM;
 
-	(void) memcpy(our_pages, pages, sizeof(struct page *) * nr_pages);
+	nvgpu_memcpy((u8 *)our_pages, (u8 *)pages,
+		sizeof(struct page *) * nr_pages);
 
 	if (nvgpu_get_sgtable_from_pages(g, &sgt, pages, 0,
 					 nr_pages * PAGE_SIZE)) {

drivers/gpu/nvgpu/os/linux/pci.c

@@ -28,6 +28,7 @@
 #include <nvgpu/soc.h>
 #include <nvgpu/sim.h>
 #include <nvgpu/gk20a.h>
+#include <nvgpu/string.h>
 
 #include "nvlink.h"
 #include "clk/clk.h"
@@ -701,8 +702,8 @@ static int nvgpu_pci_probe(struct pci_dev *pdev,
 	}
 
 	/* copy detected device data to allocated platform space*/
-	(void) memcpy((void *)platform,
+	nvgpu_memcpy((u8 *)platform,
-		(void *)&nvgpu_pci_device[pent->driver_data],
+		(u8 *)&nvgpu_pci_device[pent->driver_data],
 		sizeof(struct gk20a_platform));
 
 	pci_set_drvdata(pdev, platform);

drivers/gpu/nvgpu/os/linux/sched.c

@@ -24,6 +24,7 @@
 #include <nvgpu/bug.h>
 #include <nvgpu/barrier.h>
 #include <nvgpu/gk20a.h>
+#include <nvgpu/string.h>
 
 #include "gk20a/gr_gk20a.h"
 #include "sched.h"
@@ -418,8 +419,9 @@ int gk20a_sched_dev_open(struct inode *inode, struct file *filp)
 		goto free_ref;
 	}
 
-	(void) memcpy(sched->recent_tsg_bitmap, sched->active_tsg_bitmap,
+	nvgpu_memcpy((u8 *)sched->recent_tsg_bitmap,
-			sched->bitmap_size);
+		(u8 *)sched->active_tsg_bitmap,
+		sched->bitmap_size);
 	(void) memset(sched->ref_tsg_bitmap, 0, sched->bitmap_size);
 
 	filp->private_data = sched;

drivers/gpu/nvgpu/os/linux/sysfs.c

@@ -21,6 +21,7 @@
 #include <nvgpu/kmem.h>
 #include <nvgpu/nvhost.h>
 #include <nvgpu/ptimer.h>
+#include <nvgpu/string.h>
 
 #include "os_linux.h"
 #include "sysfs.h"
@@ -655,7 +656,8 @@ static ssize_t aelpg_param_store(struct device *dev,
 	/* If parameter value is 0 then reset to SW default values*/
 	if ((paramlist[0] | paramlist[1] | paramlist[2]
 		| paramlist[3] | paramlist[4]) == 0x00) {
-		(void) memcpy(paramlist, defaultparam, sizeof(defaultparam));
+		nvgpu_memcpy((u8 *)paramlist, (u8 *)defaultparam,
+			sizeof(defaultparam));
 	}
 
 	/* If aelpg is enabled & pmu is ready then post values to