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gpu: nvgpu: Wait for idle via FIFO registers

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Wait for engine idle via FIFO's engine status instead of submitting
WFI to channel. Submitting WFI and waiting is not robust, and wait
might invoke debug dump which cannot be done while powering down.

Bug 1499214

Change-Id: I4d52e8558e1a862ad4292036594d81ebfbd5f36b
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/432151
Reviewed-by: Sachin Nikam <snikam@nvidia.com>
Tested-by: Sachin Nikam <snikam@nvidia.com>
This commit is contained in:
Terje Bergstrom
2014-06-27 13:45:02 +03:00
committed by Dan Willemsen
parent 2c15c3265b
commit e2638d73fd
4 changed files with 42 additions and 19 deletions
Download Patch File Download Diff File Expand all files Collapse all files

21
drivers/gpu/nvgpu/gk20a/channel_gk20a.c
View File

@@ -1948,29 +1948,14 @@ int gk20a_channel_suspend(struct gk20a *g)
struct fifo_gk20a *f = &g->fifo;
u32 chid;
bool channels_in_use = false;
struct device *d = dev_from_gk20a(g);
int err;
gk20a_dbg_fn("");
/* idle the engine by submitting WFI on non-KEPLER_C channel */
for (chid = 0; chid < f->num_channels; chid++) {
struct channel_gk20a *c = &f->channel[chid];
if (c->in_use && c->obj_class != KEPLER_C && !c->has_timedout) {
err = gk20a_channel_submit_wfi(c);
if (err) {
gk20a_err(d, "cannot idle channel %d\n",
chid);
/* wait for engine idle */
err = gk20a_fifo_wait_engine_idle(g);
if (err)
return err;
}
if (c->sync)
c->sync->wait_cpu(c->sync,
&c->last_submit.post_fence,
500000);
break;
}
}
for (chid = 0; chid < f->num_channels; chid++) {
if (f->channel[chid].in_use) {

2
drivers/gpu/nvgpu/gk20a/dbg_gpu_gk20a.c
View File

@@ -633,6 +633,8 @@ static int dbg_set_powergate(struct dbg_session_gk20a *dbg_s,
break;
}
gk20a_dbg(gpu_dbg_fn|gpu_dbg_gpu_dbg, "%s powergate mode = %d done",
dev_name(dbg_s->dev), powermode);
return err;
}

35
drivers/gpu/nvgpu/gk20a/fifo_gk20a.c
View File

@@ -1955,6 +1955,41 @@ bool gk20a_fifo_mmu_fault_pending(struct gk20a *g)
return false;
}
int gk20a_fifo_wait_engine_idle(struct gk20a *g)
{
unsigned long end_jiffies = jiffies +
msecs_to_jiffies(gk20a_get_gr_idle_timeout(g));
unsigned long delay = GR_IDLE_CHECK_DEFAULT;
int ret = -ETIMEDOUT;
u32 i;
struct device *d = dev_from_gk20a(g);
gk20a_dbg_fn("");
for (i = 0; i < fifo_engine_status__size_1_v(); i++) {
do {
u32 status = gk20a_readl(g, fifo_engine_status_r(i));
if (!fifo_engine_status_engine_v(status)) {
ret = 0;
break;
}
usleep_range(delay, delay * 2);
delay = min_t(unsigned long,
delay << 1, GR_IDLE_CHECK_MAX);
} while (time_before(jiffies, end_jiffies) ||
!tegra_platform_is_silicon());
if (ret) {
gk20a_err(d, "cannot idle engine %u\n", i);
break;
}
}
gk20a_dbg_fn("done");
return ret;
}
void gk20a_init_fifo(struct gpu_ops *gops)
{
gk20a_init_channel(gops);

1
drivers/gpu/nvgpu/gk20a/fifo_gk20a.h
View File

@@ -169,4 +169,5 @@ void gk20a_init_fifo(struct gpu_ops *gops);
void fifo_gk20a_finish_mmu_fault_handling(struct gk20a *g,
unsigned long fault_id);
int gk20a_fifo_wait_engine_idle(struct gk20a *g);
#endif /*__GR_GK20A_H__*/