From e2fc8dcb2f887aea6de22f6dd0a0ae84b1b89c93 Mon Sep 17 00:00:00 2001 From: Tejal Kudav Date: Thu, 21 Feb 2019 14:40:36 +0530 Subject: [PATCH] gpu: nvgpu: Fix MISRA 20.7 violations in nvlink MISRA 20.7 rule requires macro paramaters to be wrapped in parantheses when the parameter expands into an expression. Fix such 20.7 violations in nvlink code by adding parantheses around the macro parameters. JIRA NVGPU-1921 Change-Id: Id09193247bc66cb41338ada88889548f92a846a4 Signed-off-by: Tejal Kudav Reviewed-on: https://git-master.nvidia.com/r/2024810 Reviewed-by: svc-mobile-coverity Reviewed-by: svc-mobile-misra Reviewed-by: svc-misra-checker GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu Reviewed-by: mobile promotions Tested-by: mobile promotions --- .../gpu/nvgpu/common/nvlink/nvlink_gv100.c | 4 ++-- drivers/gpu/nvgpu/include/nvgpu/nvlink.h | 24 +++++++++---------- 2 files changed, 14 insertions(+), 14 deletions(-) diff --git a/drivers/gpu/nvgpu/common/nvlink/nvlink_gv100.c b/drivers/gpu/nvgpu/common/nvlink/nvlink_gv100.c index 3a9cbd7e4..f589565b3 100644 --- a/drivers/gpu/nvgpu/common/nvlink/nvlink_gv100.c +++ b/drivers/gpu/nvgpu/common/nvlink/nvlink_gv100.c @@ -482,8 +482,8 @@ static int gv100_nvlink_state_load_hal(struct gk20a *g) return gv100_nvlink_minion_load(g); } -#define TRIM_SYS_NVLINK_CTRL(i) (trim_sys_nvlink0_ctrl_r() + 16U*i) -#define TRIM_SYS_NVLINK_STATUS(i) (trim_sys_nvlink0_status_r() + 16U*i) +#define TRIM_SYS_NVLINK_CTRL(i) (trim_sys_nvlink0_ctrl_r() + 16U*(i)) +#define TRIM_SYS_NVLINK_STATUS(i) (trim_sys_nvlink0_status_r() + 16U*(i)) int gv100_nvlink_setup_pll(struct gk20a *g, unsigned long link_mask) { diff --git a/drivers/gpu/nvgpu/include/nvgpu/nvlink.h b/drivers/gpu/nvgpu/include/nvgpu/nvlink.h index 6504daf91..c1cc98ee0 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/nvlink.h +++ b/drivers/gpu/nvgpu/include/nvgpu/nvlink.h @@ -33,18 +33,18 @@ #define INITPLL_1 U8(1) #define INITPLL_7 U8(7) -#define MINION_REG_RD32(g, off) gk20a_readl(g, g->nvlink.minion_base + (off)) -#define MINION_REG_WR32(g, off, v) gk20a_writel(g, g->nvlink.minion_base + (off), (v)) -#define IOCTRL_REG_RD32(g, off) gk20a_readl(g, g->nvlink.ioctrl_base + (off)) -#define IOCTRL_REG_WR32(g, off, v) gk20a_writel(g, g->nvlink.ioctrl_base + (off), (v)) -#define MIF_REG_RD32(g, id, off) gk20a_readl(g, g->nvlink.links[(id)].mif_base + (off)) -#define MIF_REG_WR32(g, id, off, v) gk20a_writel(g, g->nvlink.links[(id)].mif_base + (off), (v)) -#define IPT_REG_RD32(g, off) gk20a_readl(g, g->nvlink.ipt_base + (off)) -#define IPT_REG_WR32(g, off, v) gk20a_writel(g, g->nvlink.ipt_base + (off), (v)) -#define TLC_REG_RD32(g, id, off) gk20a_readl(g, g->nvlink.links[(id)].tl_base + (off)) -#define TLC_REG_WR32(g, id, off, v) gk20a_writel(g, g->nvlink.links[(id)].tl_base + (off), (v)) -#define DLPL_REG_RD32(g, id, off) gk20a_readl(g, g->nvlink.links[(id)].dlpl_base + (off)) -#define DLPL_REG_WR32(g, id, off, v) gk20a_writel(g, g->nvlink.links[(id)].dlpl_base + (off), (v)) +#define MINION_REG_RD32(g, off) gk20a_readl(g, (g)->nvlink.minion_base + (off)) +#define MINION_REG_WR32(g, off, v) gk20a_writel(g, (g)->nvlink.minion_base + (off), (v)) +#define IOCTRL_REG_RD32(g, off) gk20a_readl(g, (g)->nvlink.ioctrl_base + (off)) +#define IOCTRL_REG_WR32(g, off, v) gk20a_writel(g, (g)->nvlink.ioctrl_base + (off), (v)) +#define MIF_REG_RD32(g, id, off) gk20a_readl(g, (g)->nvlink.links[(id)].mif_base + (off)) +#define MIF_REG_WR32(g, id, off, v) gk20a_writel(g, (g)->nvlink.links[(id)].mif_base + (off), (v)) +#define IPT_REG_RD32(g, off) gk20a_readl(g, (g)->nvlink.ipt_base + (off)) +#define IPT_REG_WR32(g, off, v) gk20a_writel(g, (g)->nvlink.ipt_base + (off), (v)) +#define TLC_REG_RD32(g, id, off) gk20a_readl(g, (g)->nvlink.links[(id)].tl_base + (off)) +#define TLC_REG_WR32(g, id, off, v) gk20a_writel(g, (g)->nvlink.links[(id)].tl_base + (off), (v)) +#define DLPL_REG_RD32(g, id, off) gk20a_readl(g, (g)->nvlink.links[(id)].dlpl_base + (off)) +#define DLPL_REG_WR32(g, id, off, v) gk20a_writel(g, (g)->nvlink.links[(id)].dlpl_base + (off), (v)) struct gk20a; struct nvgpu_firmware;