diff --git a/drivers/gpu/nvgpu/tu104/gr_tu104.c b/drivers/gpu/nvgpu/tu104/gr_tu104.c
index 8e89ab2d9..14df5bf8e 100644
--- a/drivers/gpu/nvgpu/tu104/gr_tu104.c
+++ b/drivers/gpu/nvgpu/tu104/gr_tu104.c
@@ -489,3 +489,18 @@ int gr_tu104_handle_sw_method(struct gk20a *g, u32 addr,
 fail:
 	return -EINVAL;
 }
+
+void gr_tu104_init_sm_dsm_reg_info(void)
+{
+	return;
+}
+
+void gr_tu104_get_sm_dsm_perf_ctrl_regs(struct gk20a *g,
+				        u32 *num_sm_dsm_perf_ctrl_regs,
+				        u32 **sm_dsm_perf_ctrl_regs,
+				        u32 *ctrl_register_stride)
+{
+	*num_sm_dsm_perf_ctrl_regs = 0;
+	*sm_dsm_perf_ctrl_regs = NULL;
+	*ctrl_register_stride = 0;
+}
diff --git a/drivers/gpu/nvgpu/tu104/gr_tu104.h b/drivers/gpu/nvgpu/tu104/gr_tu104.h
index 157f6c16f..0a0d8d9ba 100644
--- a/drivers/gpu/nvgpu/tu104/gr_tu104.h
+++ b/drivers/gpu/nvgpu/tu104/gr_tu104.h
@@ -88,4 +88,8 @@ int gr_tu104_get_offset_in_gpccs_segment(struct gk20a *g,
 int gr_tu104_handle_sw_method(struct gk20a *g, u32 addr,
 			      u32 class_num, u32 offset, u32 data);
 
+void gr_tu104_init_sm_dsm_reg_info(void);
+void gr_tu104_get_sm_dsm_perf_ctrl_regs(struct gk20a *g,
+	u32 *num_sm_dsm_perf_ctrl_regs, u32 **sm_dsm_perf_ctrl_regs,
+	u32 *ctrl_register_stride);
 #endif
diff --git a/drivers/gpu/nvgpu/tu104/hal_tu104.c b/drivers/gpu/nvgpu/tu104/hal_tu104.c
index eed4f376a..ba52ec06d 100644
--- a/drivers/gpu/nvgpu/tu104/hal_tu104.c
+++ b/drivers/gpu/nvgpu/tu104/hal_tu104.c
@@ -362,7 +362,7 @@ static const struct gpu_ops tu104_ops = {
 		.is_valid_gfx_class = gr_tu104_is_valid_gfx_class,
 		.is_valid_compute_class = gr_tu104_is_valid_compute_class,
 		.get_sm_dsm_perf_regs = gv11b_gr_get_sm_dsm_perf_regs,
-		.get_sm_dsm_perf_ctrl_regs = gv11b_gr_get_sm_dsm_perf_ctrl_regs,
+		.get_sm_dsm_perf_ctrl_regs = gr_tu104_get_sm_dsm_perf_ctrl_regs,
 		.init_fs_state = gr_gv11b_init_fs_state,
 		.set_hww_esr_report_mask = gv11b_gr_set_hww_esr_report_mask,
 		.falcon_load_ucode = gr_gm20b_load_ctxsw_ucode_segments,
@@ -399,7 +399,7 @@ static const struct gpu_ops tu104_ops = {
 		.get_max_lts_per_ltc = gr_gm20b_get_max_lts_per_ltc,
 		.get_rop_l2_en_mask = gr_gm20b_rop_l2_en_mask,
 		.get_max_fbps_count = gr_gm20b_get_max_fbps_count,
-		.init_sm_dsm_reg_info = gv11b_gr_init_sm_dsm_reg_info,
+		.init_sm_dsm_reg_info = gr_tu104_init_sm_dsm_reg_info,
 		.wait_empty = gr_gv11b_wait_empty,
 		.init_cyclestats = gr_gm20b_init_cyclestats,
 		.set_sm_debug_mode = gv11b_gr_set_sm_debug_mode,