gpu: nvgpu: Add MC APIs for reset masks

Add API for querying reset mask corresponding to a unit. The reset
masks need to be read from MC HW header, and we do not want all
units to access Mc HW headers themselves.

JIRA NVGPU-954

Change-Id: I49ebbd891569de634bfc71afcecc8cd2358805c0
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1823384
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

drivers/gpu/nvgpu/common/fb/fb_gv100.c

@@ -39,11 +39,11 @@
 #include <nvgpu/utils.h>
 #include <nvgpu/timers.h>
 #include <nvgpu/gk20a.h>
+#include <nvgpu/unit.h>
 
 #include "fb_gv100.h"
 
 #include <nvgpu/hw/gv100/hw_fb_gv100.h>
-#include <nvgpu/hw/gv100/hw_mc_gv100.h>
 
 #define HW_SCRUB_TIMEOUT_DEFAULT	100 /* usec */
 #define HW_SCRUB_TIMEOUT_MAX		2000000 /* usec */
@@ -160,7 +160,7 @@ int gv100_fb_memory_unlock(struct gk20a *g)
 	}
 
 	/* Enable nvdec */
-	g->ops.mc.enable(g, mc_enable_nvdec_enabled_f());
+	g->ops.mc.enable(g, g->ops.mc.reset_mask(g, NVGPU_UNIT_NVDEC));
 
 	/* nvdec falcon reset */
 	nvgpu_flcn_reset(&g->nvdec_flcn);

drivers/gpu/nvgpu/common/fb/fb_gv11b.c

@@ -46,7 +46,6 @@
 #include "fb_gv11b.h"
 
 #include <nvgpu/hw/gv11b/hw_fb_gv11b.h>
-#include <nvgpu/hw/gv11b/hw_mc_gv11b.h>
 #include <nvgpu/hw/gv11b/hw_gmmu_gv11b.h>
 
 static int gv11b_fb_fix_page_fault(struct gk20a *g,

drivers/gpu/nvgpu/common/mc/mc_gm20b.c

@@ -28,6 +28,7 @@
 #include <nvgpu/io.h>
 #include <nvgpu/mc.h>
 #include <nvgpu/gk20a.h>
+#include <nvgpu/bug.h>
 
 #include "mc_gm20b.h"
 
@@ -292,3 +293,51 @@ void gm20b_mc_log_pending_intrs(struct gk20a *g)
 	}
 }
 
+u32 gm20b_mc_reset_mask(struct gk20a *g, enum nvgpu_unit unit)
+{
+	u32 mask = 0;
+
+	switch(unit) {
+	case NVGPU_UNIT_FIFO:
+		mask = mc_enable_pfifo_enabled_f();
+		break;
+	case NVGPU_UNIT_PERFMON:
+		mask = mc_enable_perfmon_enabled_f();
+		break;
+	case NVGPU_UNIT_GRAPH:
+		mask = mc_enable_pgraph_enabled_f();
+		break;
+	case NVGPU_UNIT_BLG:
+		mask = mc_enable_blg_enabled_f();
+		break;
+	case NVGPU_UNIT_PWR:
+		mask = mc_enable_pwr_enabled_f();
+		break;
+	default:
+		nvgpu_err(g, "unknown reset unit %d", unit);
+		BUG();
+		break;
+	}
+
+	return mask;
+}
+
+bool gm20b_mc_is_enabled(struct gk20a *g, enum nvgpu_unit unit)
+{
+	u32 mask = g->ops.mc.reset_mask(g, unit);
+
+	return (nvgpu_readl(g, mc_enable_r()) & mask) != 0U;
+}
+
+void gm20b_mc_fb_reset(struct gk20a *g)
+{
+	u32 val;
+
+	nvgpu_log_info(g, "reset gk20a fb");
+
+	val = gk20a_readl(g, mc_elpg_enable_r());
+	val |= mc_elpg_enable_xbar_enabled_f()
+		| mc_elpg_enable_pfb_enabled_f()
+		| mc_elpg_enable_hub_enabled_f();
+	gk20a_writel(g, mc_elpg_enable_r(), val);
+}

drivers/gpu/nvgpu/common/mc/mc_gm20b.h

@@ -47,5 +47,8 @@ bool gm20b_mc_is_intr1_pending(struct gk20a *g,
 		enum nvgpu_unit unit, u32 mc_intr_1);
 void gm20b_mc_log_pending_intrs(struct gk20a *g);
 void gm20b_mc_handle_intr_nonstall(struct gk20a *g, u32 ops);
+u32 gm20b_mc_reset_mask(struct gk20a *g, enum nvgpu_unit unit);
+bool gm20b_mc_is_enabled(struct gk20a *g, enum nvgpu_unit unit);
+void gm20b_mc_fb_reset(struct gk20a *g);
 
 #endif /* NVGPU_MC_GM20B_H */

drivers/gpu/nvgpu/common/mc/mc_gv100.c

@@ -26,6 +26,8 @@
 #include <nvgpu/io.h>
 #include <nvgpu/mc.h>
 #include <nvgpu/gk20a.h>
+#include <nvgpu/unit.h>
+#include <nvgpu/bug.h>
 
 #include "mc_gp10b.h"
 #include "mc_gv100.h"
@@ -88,3 +90,35 @@ bool gv100_mc_is_stall_and_eng_intr_pending(struct gk20a *g, u32 act_eng_id,
 
 	return (mc_intr_0 & (eng_intr_mask | stall_intr)) != 0U;
 }
+
+u32 gv100_mc_reset_mask(struct gk20a *g, enum nvgpu_unit unit)
+{
+	u32 mask = 0;
+
+	switch(unit) {
+	case NVGPU_UNIT_FIFO:
+		mask = mc_enable_pfifo_enabled_f();
+		break;
+	case NVGPU_UNIT_PERFMON:
+		mask = mc_enable_perfmon_enabled_f();
+		break;
+	case NVGPU_UNIT_GRAPH:
+		mask = mc_enable_pgraph_enabled_f();
+		break;
+	case NVGPU_UNIT_BLG:
+		mask = mc_enable_blg_enabled_f();
+		break;
+	case NVGPU_UNIT_PWR:
+		mask = mc_enable_pwr_enabled_f();
+		break;
+	case NVGPU_UNIT_NVDEC:
+		mask = mc_enable_nvdec_enabled_f();
+		break;
+	default:
+		nvgpu_err(g, "unknown reset unit %d", unit);
+		BUG();
+		break;
+	}
+
+	return mask;
+}

drivers/gpu/nvgpu/common/mc/mc_gv100.h

@@ -31,4 +31,6 @@ void mc_gv100_intr_enable(struct gk20a *g);
 bool gv100_mc_is_intr_nvlink_pending(struct gk20a *g, u32 mc_intr_0);
 bool gv100_mc_is_stall_and_eng_intr_pending(struct gk20a *g, u32 act_eng_id,
 			u32 *eng_intr_pending);
+u32 gv100_mc_reset_mask(struct gk20a *g, enum nvgpu_unit unit);
+
 #endif

drivers/gpu/nvgpu/gk20a/ce2_gk20a.c

@@ -39,7 +39,6 @@
 #include <nvgpu/hw/gk20a/hw_ccsr_gk20a.h>
 #include <nvgpu/hw/gk20a/hw_ram_gk20a.h>
 #include <nvgpu/hw/gk20a/hw_top_gk20a.h>
-#include <nvgpu/hw/gk20a/hw_mc_gk20a.h>
 #include <nvgpu/hw/gk20a/hw_gr_gk20a.h>
 #include <nvgpu/barrier.h>
 

drivers/gpu/nvgpu/gk20a/css_gr_gk20a.c

@@ -34,12 +34,12 @@
 #include <nvgpu/io.h>
 #include <nvgpu/utils.h>
 #include <nvgpu/channel.h>
+#include <nvgpu/unit.h>
 
 #include "gk20a.h"
 #include "css_gr_gk20a.h"
 
 #include <nvgpu/hw/gk20a/hw_perf_gk20a.h>
-#include <nvgpu/hw/gk20a/hw_mc_gk20a.h>
 
 /* check client for pointed perfmon ownership */
 #define CONTAINS_PERFMON(cl, pm)				\
@@ -89,7 +89,7 @@ static void css_hw_reset_streaming(struct gk20a *g)
 	u32 engine_status;
 
 	/* reset the perfmon */
-	g->ops.mc.reset(g, mc_enable_perfmon_enabled_f());
+	g->ops.mc.reset(g, g->ops.mc.reset_mask(g, NVGPU_UNIT_PERFMON));
 
 	/* RBUFEMPTY must be set -- otherwise we'll pick up */
 	/* snapshot that have been queued up from earlier   */

drivers/gpu/nvgpu/gk20a/dbg_gpu_gk20a.c

@@ -31,6 +31,7 @@
 #include <nvgpu/io.h>
 #include <nvgpu/utils.h>
 #include <nvgpu/channel.h>
+#include <nvgpu/unit.h>
 
 #include "gk20a.h"
 #include "gr_gk20a.h"
@@ -39,14 +40,13 @@
 
 #include <nvgpu/hw/gk20a/hw_gr_gk20a.h>
 #include <nvgpu/hw/gk20a/hw_perf_gk20a.h>
-#include <nvgpu/hw/gk20a/hw_mc_gk20a.h>
 
 static void gk20a_perfbuf_reset_streaming(struct gk20a *g)
 {
 	u32 engine_status;
 	u32 num_unread_bytes;
 
-	g->ops.mc.reset(g, mc_enable_perfmon_enabled_f());
+	g->ops.mc.reset(g, g->ops.mc.reset_mask(g, NVGPU_UNIT_PERFMON));
 
 	engine_status = gk20a_readl(g, perf_pmasys_enginestatus_r());
 	WARN_ON(0u ==

drivers/gpu/nvgpu/gk20a/fifo_gk20a.c

@@ -44,6 +44,7 @@
 #include <nvgpu/io.h>
 #include <nvgpu/utils.h>
 #include <nvgpu/channel.h>
+#include <nvgpu/unit.h>
 
 #include "gk20a.h"
 #include "mm_gk20a.h"
@@ -53,7 +54,6 @@
 #include <nvgpu/hw/gk20a/hw_ccsr_gk20a.h>
 #include <nvgpu/hw/gk20a/hw_ram_gk20a.h>
 #include <nvgpu/hw/gk20a/hw_top_gk20a.h>
-#include <nvgpu/hw/gk20a/hw_mc_gk20a.h>
 #include <nvgpu/hw/gk20a/hw_gr_gk20a.h>
 
 #define FECS_METHOD_WFI_RESTORE 0x80000
@@ -822,7 +822,7 @@ int gk20a_init_fifo_reset_enable_hw(struct gk20a *g)
 	nvgpu_log_fn(g, " ");
 
 	/* enable pmc pfifo */
-	g->ops.mc.reset(g, mc_enable_pfifo_enabled_f());
+	g->ops.mc.reset(g, g->ops.mc.reset_mask(g, NVGPU_UNIT_FIFO));
 
 	if (g->ops.clock_gating.slcg_fifo_load_gating_prod) {
 		g->ops.clock_gating.slcg_fifo_load_gating_prod(g,

drivers/gpu/nvgpu/gk20a/gr_gk20a.c

@@ -42,6 +42,7 @@
 #include <nvgpu/io.h>
 #include <nvgpu/utils.h>
 #include <nvgpu/channel.h>
+#include <nvgpu/unit.h>
 
 #include "gk20a.h"
 #include "gr_gk20a.h"
@@ -4708,9 +4709,9 @@ static int gk20a_init_gr_prepare(struct gk20a *g)
 	u32 err = 0;
 
 	/* reset gr engine */
-	g->ops.mc.reset(g, mc_enable_pgraph_enabled_f() |
+	g->ops.mc.reset(g, g->ops.mc.reset_mask(g, NVGPU_UNIT_GRAPH) |
-			mc_enable_blg_enabled_f() |
+			g->ops.mc.reset_mask(g, NVGPU_UNIT_BLG) |
-			mc_enable_perfmon_enabled_f());
+			g->ops.mc.reset_mask(g, NVGPU_UNIT_PERFMON));
 
 	gr_gk20a_load_gating_prod(g);
 

drivers/gpu/nvgpu/gk20a/mm_gk20a.c

@@ -51,7 +51,6 @@
 #include <nvgpu/hw/gk20a/hw_gmmu_gk20a.h>
 #include <nvgpu/hw/gk20a/hw_ram_gk20a.h>
 #include <nvgpu/hw/gk20a/hw_pram_gk20a.h>
-#include <nvgpu/hw/gk20a/hw_mc_gk20a.h>
 #include <nvgpu/hw/gk20a/hw_flush_gk20a.h>
 
 /*

drivers/gpu/nvgpu/gk20a/pmu_gk20a.c

@@ -34,6 +34,7 @@
 #include <nvgpu/io.h>
 #include <nvgpu/clk_arb.h>
 #include <nvgpu/utils.h>
+#include <nvgpu/unit.h>
 
 #include "gk20a.h"
 #include "gr_gk20a.h"
@@ -497,24 +498,21 @@ void gk20a_write_dmatrfbase(struct gk20a *g, u32 addr)
 
 bool gk20a_pmu_is_engine_in_reset(struct gk20a *g)
 {
-	u32 pmc_enable;
 	bool status = false;
 
-	pmc_enable = gk20a_readl(g, mc_enable_r());
+	status = g->ops.mc.is_enabled(g, NVGPU_UNIT_PWR);
-	if (mc_enable_pwr_v(pmc_enable) ==
-			mc_enable_pwr_disabled_v()) {
-		status = true;
-	}
 
 	return status;
 }
 
 int gk20a_pmu_engine_reset(struct gk20a *g, bool do_reset)
 {
+	u32 reset_mask = g->ops.mc.reset_mask(g, NVGPU_UNIT_PWR);
+
 	if (do_reset) {
-		g->ops.mc.enable(g, mc_enable_pwr_enabled_f());
+		g->ops.mc.enable(g, reset_mask);
 	} else {
-		g->ops.mc.disable(g, mc_enable_pwr_enabled_f());
+		g->ops.mc.disable(g, reset_mask);
 	}
 
 	return 0;
@@ -659,8 +657,6 @@ void gk20a_pmu_dump_falcon_stats(struct nvgpu_pmu *pmu)
 			pwr_falcon_exterrstat_valid_true_v()) {
 		nvgpu_err(g, "pwr_falcon_exterraddr_r : 0x%x",
 			gk20a_readl(g, pwr_falcon_exterraddr_r()));
-		nvgpu_err(g, "pmc_enable : 0x%x",
-			gk20a_readl(g, mc_enable_r()));
 	}
 
 	/* Print PMU F/W debug prints */

drivers/gpu/nvgpu/gm20b/hal_gm20b.c

@@ -592,6 +592,8 @@ static const struct gpu_ops gm20b_ops = {
 		.reset = gm20b_mc_reset,
 		.is_intr1_pending = gm20b_mc_is_intr1_pending,
 		.log_pending_intrs = gm20b_mc_log_pending_intrs,
+		.reset_mask = gm20b_mc_reset_mask,
+		.is_enabled = gm20b_mc_is_enabled,
 	},
 	.debug = {
 		.show_dump = gk20a_debug_show_dump,

drivers/gpu/nvgpu/gp106/bios_gp106.c

@@ -34,7 +34,6 @@
 #include "gp106/mclk_gp106.h"
 
 #include <nvgpu/hw/gp106/hw_pwr_gp106.h>
-#include <nvgpu/hw/gp106/hw_mc_gp106.h>
 #include <nvgpu/hw/gp106/hw_top_gp106.h>
 
 #define PMU_BOOT_TIMEOUT_DEFAULT	100 /* usec */

drivers/gpu/nvgpu/gp106/hal_gp106.c

@@ -720,6 +720,8 @@ static const struct gpu_ops gp106_ops = {
 		.reset = gm20b_mc_reset,
 		.is_intr1_pending = mc_gp10b_is_intr1_pending,
 		.log_pending_intrs = mc_gp10b_log_pending_intrs,
+		.reset_mask = gm20b_mc_reset_mask,
+		.is_enabled = gm20b_mc_is_enabled,
 	},
 	.debug = {
 		.show_dump = gk20a_debug_show_dump,

drivers/gpu/nvgpu/gp106/pmu_gp106.c

@@ -40,7 +40,6 @@
 #include "lpwr/rppg.h"
 
 #include <nvgpu/hw/gp106/hw_psec_gp106.h>
-#include <nvgpu/hw/gp106/hw_mc_gp106.h>
 #include <nvgpu/hw/gp106/hw_pwr_gp106.h>
 
 bool gp106_is_pmu_supported(struct gk20a *g)

drivers/gpu/nvgpu/gp10b/hal_gp10b.c

@@ -654,6 +654,8 @@ static const struct gpu_ops gp10b_ops = {
 		.reset = gm20b_mc_reset,
 		.is_intr1_pending = mc_gp10b_is_intr1_pending,
 		.log_pending_intrs = mc_gp10b_log_pending_intrs,
+		.reset_mask = gm20b_mc_reset_mask,
+		.is_enabled = gm20b_mc_is_enabled,
 	},
 	.debug = {
 		.show_dump = gk20a_debug_show_dump,

drivers/gpu/nvgpu/gv100/hal_gv100.c

@@ -817,6 +817,8 @@ static const struct gpu_ops gv100_ops = {
 		.is_intr_nvlink_pending = gv100_mc_is_intr_nvlink_pending,
 		.is_stall_and_eng_intr_pending =
 					gv100_mc_is_stall_and_eng_intr_pending,
+		.reset_mask = gv100_mc_reset_mask,
+		.is_enabled = gm20b_mc_is_enabled,
 	},
 	.debug = {
 		.show_dump = gk20a_debug_show_dump,

drivers/gpu/nvgpu/gv100/nvlink_gv100.c

@@ -45,8 +45,6 @@
 #include <nvgpu/hw/gv100/hw_trim_gv100.h>
 #include <nvgpu/hw/gv100/hw_nvtlc_gv100.h>
 
-#include <nvgpu/hw/gv100/hw_mc_gv100.h>
-
 #define NVLINK_PLL_ON_TIMEOUT_MS	30
 #define NVLINK_SUBLINK_TIMEOUT_MS	200
 /*

drivers/gpu/nvgpu/gv11b/css_gr_gv11b.c

@@ -37,12 +37,12 @@
 #include <nvgpu/utils.h>
 #include <nvgpu/gk20a.h>
 #include <nvgpu/channel.h>
+#include <nvgpu/unit.h>
 
 #include "gk20a/css_gr_gk20a.h"
 #include "css_gr_gv11b.h"
 
 #include <nvgpu/hw/gv11b/hw_perf_gv11b.h>
-#include <nvgpu/hw/gv11b/hw_mc_gv11b.h>
 
 
 /* reports whether the hw queue overflowed */
@@ -65,7 +65,7 @@ static void gv11b_css_hw_reset_streaming(struct gk20a *g)
 	u32 engine_status;
 
 	/* reset the perfmon */
-	g->ops.mc.reset(g, mc_enable_perfmon_enabled_f());
+	g->ops.mc.reset(g, g->ops.mc.reset_mask(g, NVGPU_UNIT_PERFMON));
 
 	/* RBUFEMPTY must be set -- otherwise we'll pick up */
 	/* snapshot that have been queued up from earlier   */

drivers/gpu/nvgpu/gv11b/dbg_gpu_gv11b.c

@@ -26,10 +26,10 @@
 #include <nvgpu/io.h>
 #include <nvgpu/utils.h>
 #include <nvgpu/gk20a.h>
+#include <nvgpu/unit.h>
 
 #include "gv11b/dbg_gpu_gv11b.h"
 #include <nvgpu/hw/gv11b/hw_perf_gv11b.h>
-#include <nvgpu/hw/gv11b/hw_mc_gv11b.h>
 #include <nvgpu/bug.h>
 
 static void gv11b_perfbuf_reset_streaming(struct gk20a *g)
@@ -37,7 +37,7 @@ static void gv11b_perfbuf_reset_streaming(struct gk20a *g)
 	u32 engine_status;
 	u32 num_unread_bytes;
 
-	g->ops.mc.reset(g, mc_enable_perfmon_enabled_f());
+	g->ops.mc.reset(g, g->ops.mc.reset_mask(g, NVGPU_UNIT_PERFMON));
 
 	engine_status = gk20a_readl(g, perf_pmasys_enginestatus_r());
 	WARN_ON(0u ==

drivers/gpu/nvgpu/gv11b/fifo_gv11b.c

@@ -41,6 +41,7 @@
 #include <nvgpu/utils.h>
 #include <nvgpu/gk20a.h>
 #include <nvgpu/channel.h>
+#include <nvgpu/unit.h>
 
 #include "gk20a/fifo_gk20a.h"
 
@@ -53,7 +54,6 @@
 #include <nvgpu/hw/gv11b/hw_usermode_gv11b.h>
 #include <nvgpu/hw/gv11b/hw_top_gv11b.h>
 #include <nvgpu/hw/gv11b/hw_gmmu_gv11b.h>
-#include <nvgpu/hw/gv11b/hw_mc_gv11b.h>
 #include <nvgpu/hw/gv11b/hw_gr_gv11b.h>
 
 #include "fifo_gv11b.h"
@@ -1281,7 +1281,7 @@ int gv11b_init_fifo_reset_enable_hw(struct gk20a *g)
 	nvgpu_log_fn(g, " ");
 
 	/* enable pmc pfifo */
-	g->ops.mc.reset(g, mc_enable_pfifo_enabled_f());
+	g->ops.mc.reset(g, g->ops.mc.reset_mask(g, NVGPU_UNIT_FIFO));
 
 	if (g->ops.clock_gating.slcg_ce2_load_gating_prod) {
 		g->ops.clock_gating.slcg_ce2_load_gating_prod(g,

drivers/gpu/nvgpu/gv11b/hal_gv11b.c

@@ -759,6 +759,8 @@ static const struct gpu_ops gv11b_ops = {
 		.is_intr_hub_pending = gv11b_mc_is_intr_hub_pending,
 		.is_stall_and_eng_intr_pending =
 					gv11b_mc_is_stall_and_eng_intr_pending,
+		.reset_mask = gm20b_mc_reset_mask,
+		.is_enabled = gm20b_mc_is_enabled,
 	},
 	.debug = {
 		.show_dump = gk20a_debug_show_dump,

drivers/gpu/nvgpu/include/nvgpu/gk20a.h

@@ -1156,7 +1156,7 @@ struct gpu_ops {
 		void (*intr_mask)(struct gk20a *g);
 		void (*intr_enable)(struct gk20a *g);
 		void (*intr_unit_config)(struct gk20a *g,
-				bool enable, bool is_stalling, u32 unit);
+				bool enable, bool is_stalling, u32 mask);
 		void (*isr_stall)(struct gk20a *g);
 		bool (*is_intr_hub_pending)(struct gk20a *g, u32 mc_intr);
 		bool (*is_intr_nvlink_pending)(struct gk20a *g, u32 mc_intr);
@@ -1172,9 +1172,11 @@ struct gpu_ops {
 		void (*enable)(struct gk20a *g, u32 units);
 		void (*disable)(struct gk20a *g, u32 units);
 		void (*reset)(struct gk20a *g, u32 units);
+		bool (*is_enabled)(struct gk20a *g, enum nvgpu_unit unit);
 		bool (*is_intr1_pending)(struct gk20a *g, enum nvgpu_unit unit, u32 mc_intr_1);
 		void (*log_pending_intrs)(struct gk20a *g);
 		void (*fbpa_isr)(struct gk20a *g);
+		u32 (*reset_mask)(struct gk20a *g, enum nvgpu_unit unit);
 	} mc;
 	struct {
 		void (*show_dump)(struct gk20a *g,

drivers/gpu/nvgpu/include/nvgpu/unit.h

@@ -31,6 +31,11 @@
  */
 enum nvgpu_unit {
 	NVGPU_UNIT_FIFO,
+	NVGPU_UNIT_PERFMON,
+	NVGPU_UNIT_GRAPH,
+	NVGPU_UNIT_BLG,
+	NVGPU_UNIT_PWR,
+	NVGPU_UNIT_NVDEC,
 };
 
 #endif /* NVGPU_UNIT_H */

drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c

@@ -493,6 +493,9 @@ static const struct gpu_ops vgpu_gp10b_ops = {
 		.reset = NULL,
 		.is_intr1_pending = NULL,
 		.log_pending_intrs = NULL,
+		.reset_mask = NULL,
+		.is_enabled = NULL,
+		.fb_reset = NULL,
 	},
 	.debug = {
 		.show_dump = NULL,

drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c

@@ -566,6 +566,9 @@ static const struct gpu_ops vgpu_gv11b_ops = {
 		.is_intr1_pending = NULL,
 		.is_intr_hub_pending = NULL,
 		.log_pending_intrs = NULL	,
+		.reset_mask = NULL,
+		.is_enabled = NULL,
+		.fb_reset = NULL,
 	},
 	.debug = {
 		.show_dump = NULL,