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gpu: nvgpu: add doxygen comments for common.ecc unit
Add doxygen style comments for common.ecc unit. Jira NVGPU-2475 Change-Id: Ie31f27a5fb253ac33e7b1b795c7268fd4a626a32 Signed-off-by: Antony Clince Alex <aalex@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2217455 Reviewed-by: Rajesh Devaraj <rdevaraj@nvidia.com> Reviewed-by: Philip Elcan <pelcan@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Ankur Kishore <ankkishore@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Antony Clince Alex
committed by
Alex Waterman
Alex Waterman
parent
6336c78c40
commit
e469c9cd98
@@ -23,6 +23,58 @@
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#ifndef NVGPU_ECC_H
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#define NVGPU_ECC_H
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/**
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* @file
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* @page unit-ecc Unit ECC(Error Control Codes)
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*
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* Acronyms
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* ========
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* ECC - Error Control Codes
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* SEC - Single Error Correction
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* SEC-DED - Standard single-error correction with double-error detection
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* SED - Single Error Detection
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*
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* Overview
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* ========
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* The memories within the GPU are protected using data integrity protection
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* mechanism like ecc or parity. This unit is responsible for allocating,
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* initializing and maintaining error counters for all memories which support
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* ecc/parity protection.
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*
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* + Initialization:
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* This unit allocates and initializes error counters (corrected and
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* uncorrected) for each memory and concatenates them into a list.
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*
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* Data Structures
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* ===============
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*
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* The data structures exposed by the ECC unit, conveys to the user information
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* regarding the corrected, uncorrected errors encountered in the constituent
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* memories in the GPU hardware units like (gr, ltc, pmu, etc).
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*
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* The following are the list of data structures:
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*
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* + struct nvgpu_ecc_stat
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*
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*
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* + struct nvgpu_ecc
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*
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*
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* Static Design
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* =============
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*
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* TODO
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*
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* Dynamic Design
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* =============
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*
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* TODO
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*
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* External APIs
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* -------------
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*
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*/
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#include <nvgpu/types.h>
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#include <nvgpu/list.h>
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@@ -30,12 +82,32 @@
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struct gk20a;
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/**
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* This struct holds the ecc/parity error information associated with each
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* memory. The error information includes a string that can be used to
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* uniquely identity the memory, error type. In addition it has a 32 bit
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* counter to track the number of instances of the errors.
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*/
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struct nvgpu_ecc_stat {
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/** The unique name associated with error */
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char name[NVGPU_ECC_STAT_NAME_MAX_SIZE];
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/** The 32-bit error counter */
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u32 counter;
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/**
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* The embedded list element, this is used to link the counters into
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* linked list.
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*/
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struct nvgpu_list_node node;
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};
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/**
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* @brief Helper function to get struct nvgpu_ecc_stat from list node.
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*
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* @param node [in] List element node.
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*
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* @return Pointer to struct nvgpu_ecc_stat.
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*
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*/
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static inline struct nvgpu_ecc_stat *nvgpu_ecc_stat_from_node(
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struct nvgpu_list_node *node)
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{
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@@ -44,85 +116,166 @@ static inline struct nvgpu_ecc_stat *nvgpu_ecc_stat_from_node(
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);
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}
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/**
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* The structure contains the error statistics assocaited with constituent
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* memories within each gpu hardware unit. All statistics are linked together
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* into a list, the head of this list is stored in stats_list.
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*/
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struct nvgpu_ecc {
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/**
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* Contains error statistics for each memory contained within the gr
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* unit.
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*/
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struct {
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/* stats per tpc */
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/** SM register file SEC count. */
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struct nvgpu_ecc_stat **sm_lrf_ecc_single_err_count;
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/** SM register file DED count. */
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struct nvgpu_ecc_stat **sm_lrf_ecc_double_err_count;
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/** SM shared memory SEC count. */
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struct nvgpu_ecc_stat **sm_shm_ecc_sec_count;
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/** SM shared memory SED count. */
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struct nvgpu_ecc_stat **sm_shm_ecc_sed_count;
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/** SM shared memory DED count. */
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struct nvgpu_ecc_stat **sm_shm_ecc_ded_count;
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/** TEX pipe0 total SEC count. */
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struct nvgpu_ecc_stat **tex_ecc_total_sec_pipe0_count;
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/** TEX pipe0 total DED count. */
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struct nvgpu_ecc_stat **tex_ecc_total_ded_pipe0_count;
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/** TEX pipe0 unique SEC count. */
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struct nvgpu_ecc_stat **tex_unique_ecc_sec_pipe0_count;
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/** TEX pipe0 unique DED count. */
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struct nvgpu_ecc_stat **tex_unique_ecc_ded_pipe0_count;
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/** TEX pipe1 total SEC count. */
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struct nvgpu_ecc_stat **tex_ecc_total_sec_pipe1_count;
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/** TEX pipe1 total DED count. */
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struct nvgpu_ecc_stat **tex_ecc_total_ded_pipe1_count;
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/** TEX pipe1 unique SEC count. */
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struct nvgpu_ecc_stat **tex_unique_ecc_sec_pipe1_count;
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/** TEX pipe1 unique DED count. */
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struct nvgpu_ecc_stat **tex_unique_ecc_ded_pipe1_count;
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/** SM l1-tag correct error count. */
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struct nvgpu_ecc_stat **sm_l1_tag_ecc_corrected_err_count;
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/** SM l1-tag uncorrected error count. */
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struct nvgpu_ecc_stat **sm_l1_tag_ecc_uncorrected_err_count;
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/** SM CBU corrected error count. */
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struct nvgpu_ecc_stat **sm_cbu_ecc_corrected_err_count;
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/** SM CBU uncorrected error count. */
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struct nvgpu_ecc_stat **sm_cbu_ecc_uncorrected_err_count;
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/** SM l1-data corrected error count. */
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struct nvgpu_ecc_stat **sm_l1_data_ecc_corrected_err_count;
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/** SM l1-data uncorrected error count. */
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struct nvgpu_ecc_stat **sm_l1_data_ecc_uncorrected_err_count;
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/** SM icache corrected error count. */
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struct nvgpu_ecc_stat **sm_icache_ecc_corrected_err_count;
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/** SM icache uncorrected error count. */
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struct nvgpu_ecc_stat **sm_icache_ecc_uncorrected_err_count;
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/* stats per gpc */
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/** GCC l1.5-cache corrected error count. */
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struct nvgpu_ecc_stat *gcc_l15_ecc_corrected_err_count;
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/** GCC l1.5-cache uncorrected error count. */
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struct nvgpu_ecc_stat *gcc_l15_ecc_uncorrected_err_count;
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/** GPCCS falcon i-mem, d-mem corrected error count. */
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struct nvgpu_ecc_stat *gpccs_ecc_corrected_err_count;
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/** GPCCS falcone i-mem, d-mem uncorrected error count. */
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struct nvgpu_ecc_stat *gpccs_ecc_uncorrected_err_count;
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/** GMMU l1tlb corrected error count. */
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struct nvgpu_ecc_stat *mmu_l1tlb_ecc_corrected_err_count;
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/** GMMU l1tlb uncorrected error count. */
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struct nvgpu_ecc_stat *mmu_l1tlb_ecc_uncorrected_err_count;
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/* stats per device */
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/** FECS falcon i-mem, d-mem corrected error count. */
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struct nvgpu_ecc_stat *fecs_ecc_corrected_err_count;
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/** FECS falcon i-mem, d-mem uncorrected error count. */
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struct nvgpu_ecc_stat *fecs_ecc_uncorrected_err_count;
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} gr;
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/**
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* Contains error statistics for each memory contained within the ltc
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* unit.
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*/
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struct {
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/* stats per lts */
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/** ltc-lts sec count. */
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struct nvgpu_ecc_stat **ecc_sec_count;
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/** ltc-lts ded count. */
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struct nvgpu_ecc_stat **ecc_ded_count;
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} ltc;
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/**
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* Contains error statistics for each memory contained within the fb
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* unit.
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*/
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struct {
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/* stats per device */
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/** hubmmu l2tlb corrected error count. */
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struct nvgpu_ecc_stat *mmu_l2tlb_ecc_corrected_err_count;
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/** hubmmu l2tlb uncorrected error count. */
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struct nvgpu_ecc_stat *mmu_l2tlb_ecc_uncorrected_err_count;
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/** hubmmu hubtlb corrected error count. */
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struct nvgpu_ecc_stat *mmu_hubtlb_ecc_corrected_err_count;
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/** hubmmu hubtlb uncorrected error count. */
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struct nvgpu_ecc_stat *mmu_hubtlb_ecc_uncorrected_err_count;
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/** hubmmu fillunit corrected error count. */
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struct nvgpu_ecc_stat *mmu_fillunit_ecc_corrected_err_count;
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/** hubmmu fillunit uncorrected error count. */
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struct nvgpu_ecc_stat *mmu_fillunit_ecc_uncorrected_err_count;
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} fb;
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/**
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* Contains error statistics for each memory contained within the pmu
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* unit.
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*/
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struct {
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/* stats per device */
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/** PMU falcon imem, dmem corrected error count. */
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struct nvgpu_ecc_stat *pmu_ecc_corrected_err_count;
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/** PMU falcon imem, dmem uncorrected error count. */
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struct nvgpu_ecc_stat *pmu_ecc_uncorrected_err_count;
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} pmu;
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/**
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* Contains error statistics for each memory contained within the fbpa
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* unit.
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*/
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struct {
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/* stats per fbpa */
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/** fbpa sec count. */
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struct nvgpu_ecc_stat *fbpa_ecc_sec_err_count;
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/** fbpa ded count. */
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struct nvgpu_ecc_stat *fbpa_ecc_ded_err_count;
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} fbpa;
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/** Contains the head to the list of error statistics. */
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struct nvgpu_list_node stats_list;
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/** Contains the number of error statistics. */
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int stats_count;
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/** Flag stores the initialization status of ECC unit. */
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bool initialized;
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};
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/**
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* @brief Allocate and initialize error counter specified by name for all
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* gpc-tpc instances.
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*
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* @param g [in] The GPU driver struct.
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* @param stat [out] Pointer to array of pointers of error counters.
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* @param name [in] Unique name for error counter.
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*
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* Calculates the total number of tpcs across all gpcs within the gr unit.
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* Then allocates, initializes memory to hold error counters associated with all
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* tpcs, which is then added to the stats_list in struct nvgpu_ecc.
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*
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* @return 0 in case of success, less than 0 for failure.
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*/
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int nvgpu_ecc_counter_init_per_tpc(struct gk20a *g,
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struct nvgpu_ecc_stat ***stat, const char *name);
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/*
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* @brief Allocate and initalize counter for memories common across a TPC.
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*
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* @param stat [in] Address of pointer to struct nvgpu_ecc_stat.
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*
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*/
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#define NVGPU_ECC_COUNTER_INIT_PER_TPC(stat) \
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do { \
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int err = 0; \
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@@ -133,38 +286,145 @@ int nvgpu_ecc_counter_init_per_tpc(struct gk20a *g,
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} \
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} while (false)
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/**
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* @brief Allocate and initialize error counter specified by name for all gpc
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* instances.
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*
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* @param g [in] The GPU driver struct.
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* @param stat [out] Pointer to array of tpc error counters.
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* @param name [in] Unique name for error counter.
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*
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* Calculates the total number of gpcs within the gr unit. Then allocates,
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* initializes memory to hold error counters associated with all gpcs, which is
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* then added to the stats_list in struct nvgpu_ecc.
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*
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* @return 0 in case of success, less than 0 for failure.
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*/
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int nvgpu_ecc_counter_init_per_gpc(struct gk20a *g,
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struct nvgpu_ecc_stat **stat, const char *name);
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/*
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* @brief Allocate and initalize counters for memories shared across a GPC.
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*
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* @param stat [in] Address of pointer to struct nvgpu_ecc_stat.
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*
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*/
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#define NVGPU_ECC_COUNTER_INIT_PER_GPC(stat) \
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nvgpu_ecc_counter_init_per_gpc(g, &g->ecc.gr.stat, #stat)
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/**
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* @brief Allocates, initializes an error counter with specified name.
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*
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* @param g [in] The GPU driver struct.
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* @param stat [out] Pointer to array of tpc error counters.
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* @param name [in] Unique name for error counter.
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*
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* Allocate memory for one error counter, initializes the counter with 0 and the
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* specified string identifier. Finally the counter is added to the status_list
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* of struct nvgpu_ecc.
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*
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* @return 0 in case of success, less than 0 for failure.
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*/
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int nvgpu_ecc_counter_init(struct gk20a *g,
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struct nvgpu_ecc_stat **stat, const char *name);
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/*
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* @brief Allocate and initalize counters for memories shared within GR.
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*
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* @param stat [in] Address of pointer to struct nvgpu_ecc_stat.
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*
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*/
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#define NVGPU_ECC_COUNTER_INIT_GR(stat) \
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nvgpu_ecc_counter_init(g, &g->ecc.gr.stat, #stat)
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/*
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* @brief Allocate and initalize counters for memories within FB.
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*
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* @param stat [in] Address of pointer to struct nvgpu_ecc_stat.
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*
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*/
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#define NVGPU_ECC_COUNTER_INIT_FB(stat) \
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nvgpu_ecc_counter_init(g, &g->ecc.fb.stat, #stat)
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/*
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* @brief Allocate and initalize counter for memories within PMU.
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*
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* @param stat [in] Address of pointer to struct nvgpu_ecc_stat.
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*
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*/
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#define NVGPU_ECC_COUNTER_INIT_PMU(stat) \
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nvgpu_ecc_counter_init(g, &g->ecc.pmu.stat, #stat)
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/**
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* @brief Allocate and initialize a error counters for all ltc-lts instances.
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*
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* @param g [in] The GPU driver struct.
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* @param stat [out] Pointer to array of tpc error counters.
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* @param name [in] Unique name for error counter.
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*
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* Calculates the total number of ltc-lts instances, allocates memory for each
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* instance of error counter, initializes the counter with 0 and the specified
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* string identifier. Finally the counter is added to the stats_list of
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* struct nvgpu_ecc.
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*
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* @return 0 in case of success, less than 0 for failure.
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*/
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int nvgpu_ecc_counter_init_per_lts(struct gk20a *g,
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struct nvgpu_ecc_stat ***stat, const char *name);
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/*
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* @brief Allocate and initalize counters for memories within ltc-lts
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*
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* @param stat [in] Address of pointer to struct nvgpu_ecc_stat.
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*
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*/
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#define NVGPU_ECC_COUNTER_INIT_PER_LTS(stat) \
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nvgpu_ecc_counter_init_per_lts(g, &g->ecc.ltc.stat, #stat)
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/**
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* @brief Allocate and initialize error counters for all fbpa instances.
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*
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* @param g [in] The GPU driver struct.
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* @param stat [out] Pointer to array of tpc error counters.
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* @param name [in] Unique name for error counter.
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*
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* Calculates the total number of fbpa instances, allocates memory for each
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* instance of error counter, initializes the counter with 0 and the specified
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* string identifier. Finally the counter is added to the stats_list of
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* struct nvgpu_ecc.
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*
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* @return 0 in case of success, less than 0 for failure.
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*/
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int nvgpu_ecc_counter_init_per_fbpa(struct gk20a *g,
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struct nvgpu_ecc_stat **stat, const char *name);
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#define NVGPU_ECC_COUNTER_INIT_PER_FBPA(stat) \
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nvgpu_ecc_counter_init_per_fbpa(g, &g->ecc.fbpa.stat, #stat)
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/**
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* @brief Release memory associated with all error counters.
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*
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* @param g [in] The GPU driver struct.
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*
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* Releases memory associated with all error counters associated with a hardware
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* unit, this is done for every instance of the hardware unit.
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*/
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void nvgpu_ecc_free(struct gk20a *g);
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/**
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* @brief Allocates and initializes error counters for memories within gpu
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* hardware units.
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*
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* @param g [in] The GPU driver struct.
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*
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* @return 0 in case of success, less than 0 for failure.
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*/
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int nvgpu_ecc_init_support(struct gk20a *g);
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/**
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* @brief Destroys, frees up memory allocated to ecc/parity error counters.
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*
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* @param g [in] The GPU driver struct.
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*/
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void nvgpu_ecc_remove_support(struct gk20a *g);
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/* OSes to implement */
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#ifdef CONFIG_NVGPU_SYSFS
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int nvgpu_ecc_sysfs_init(struct gk20a *g);
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void nvgpu_ecc_sysfs_remove(struct gk20a *g);
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#endif
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#endif
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