gpu: nvgpu: Linux specific GPU characteristics flags

Make GPU characteristics flags specific to Linux code only. The
rest of driver is moved to using nvgpu_is_enabled() API.

JIRA NVGPU-259

Change-Id: I2faf46ef64c964361c267887b28c9d19806d6d51
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1583876
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

drivers/gpu/nvgpu/common/linux/ioctl_channel.c

@@ -28,6 +28,7 @@
 #include <nvgpu/log.h>
 #include <nvgpu/list.h>
 #include <nvgpu/debug.h>
+#include <nvgpu/enabled.h>
 
 #include "gk20a/gk20a.h"
 #include "gk20a/ctxsw_trace_gk20a.h"
@@ -99,8 +100,7 @@ static int gk20a_channel_cycle_stats(struct channel_gk20a *ch,
 	void *virtual_address;
 
 	/* is it allowed to handle calls for current GPU? */
-	if (0 == (ch->g->gpu_characteristics.flags &
+	if (!nvgpu_is_enabled(ch->g, NVGPU_SUPPORT_CYCLE_STATS))
-			NVGPU_GPU_FLAGS_SUPPORT_CYCLE_STATS))
 		return -ENOSYS;
 
 	if (args->dmabuf_fd && !ch->cyclestate.cyclestate_buffer_handler) {
@@ -176,8 +176,7 @@ static int gk20a_channel_cycle_stats_snapshot(struct channel_gk20a *ch,
 	int ret;
 
 	/* is it allowed to handle calls for current GPU? */
-	if (0 == (ch->g->gpu_characteristics.flags &
+	if (!nvgpu_is_enabled(ch->g, NVGPU_SUPPORT_CYCLE_STATS_SNAPSHOT))
-			NVGPU_GPU_FLAGS_SUPPORT_CYCLE_STATS_SNAPSHOT))
 		return -ENOSYS;
 
 	if (!args->dmabuf_fd)

drivers/gpu/nvgpu/common/linux/ioctl_ctrl.c

@@ -20,6 +20,7 @@
 #include <linux/anon_inodes.h>
 #include <linux/fs.h>
 #include <uapi/linux/nvgpu.h>
+#include <uapi/linux/nvgpu-t18x.h>
 
 #include <nvgpu/bitops.h>
 #include <nvgpu/kmem.h>
@@ -27,10 +28,14 @@
 #include <nvgpu/bus.h>
 #include <nvgpu/vidmem.h>
 #include <nvgpu/log.h>
+#include <nvgpu/enabled.h>
 
 #include <nvgpu/linux/vidmem.h>
 
 #include "ioctl_ctrl.h"
+#ifdef CONFIG_TEGRA_19x_GPU
+#include "common/linux/ioctl_ctrl_t19x.h"
+#endif
 #include "ioctl_tsg.h"
 #include "ioctl_channel.h"
 #include "gk20a/gk20a.h"
@@ -113,6 +118,77 @@ int gk20a_ctrl_dev_release(struct inode *inode, struct file *filp)
 	return 0;
 }
 
+struct nvgpu_flags_mapping {
+	u64 ioctl_flag;
+	int enabled_flag;
+};
+
+static struct nvgpu_flags_mapping flags_mapping[] = {
+	{NVGPU_GPU_FLAGS_HAS_SYNCPOINTS,
+		NVGPU_HAS_SYNCPOINTS},
+	{NVGPU_GPU_FLAGS_SUPPORT_PARTIAL_MAPPINGS,
+		NVGPU_SUPPORT_PARTIAL_MAPPINGS},
+	{NVGPU_GPU_FLAGS_SUPPORT_SPARSE_ALLOCS,
+		NVGPU_SUPPORT_SPARSE_ALLOCS},
+	{NVGPU_GPU_FLAGS_SUPPORT_SYNC_FENCE_FDS,
+		NVGPU_SUPPORT_SYNC_FENCE_FDS},
+	{NVGPU_GPU_FLAGS_SUPPORT_CYCLE_STATS,
+		NVGPU_SUPPORT_CYCLE_STATS},
+	{NVGPU_GPU_FLAGS_SUPPORT_CYCLE_STATS_SNAPSHOT,
+		NVGPU_SUPPORT_CYCLE_STATS_SNAPSHOT},
+	{NVGPU_GPU_FLAGS_SUPPORT_USERSPACE_MANAGED_AS,
+		NVGPU_SUPPORT_USERSPACE_MANAGED_AS},
+	{NVGPU_GPU_FLAGS_SUPPORT_TSG,
+		NVGPU_SUPPORT_TSG},
+	{NVGPU_GPU_FLAGS_SUPPORT_CLOCK_CONTROLS,
+		NVGPU_SUPPORT_CLOCK_CONTROLS},
+	{NVGPU_GPU_FLAGS_SUPPORT_GET_VOLTAGE,
+		NVGPU_SUPPORT_GET_VOLTAGE},
+	{NVGPU_GPU_FLAGS_SUPPORT_GET_CURRENT,
+		NVGPU_SUPPORT_GET_CURRENT},
+	{NVGPU_GPU_FLAGS_SUPPORT_GET_POWER,
+		NVGPU_SUPPORT_GET_POWER},
+	{NVGPU_GPU_FLAGS_SUPPORT_GET_TEMPERATURE,
+		NVGPU_SUPPORT_GET_TEMPERATURE},
+	{NVGPU_GPU_FLAGS_SUPPORT_SET_THERM_ALERT_LIMIT,
+		NVGPU_SUPPORT_SET_THERM_ALERT_LIMIT},
+	{NVGPU_GPU_FLAGS_SUPPORT_DEVICE_EVENTS,
+		NVGPU_SUPPORT_DEVICE_EVENTS},
+	{NVGPU_GPU_FLAGS_SUPPORT_FECS_CTXSW_TRACE,
+		NVGPU_SUPPORT_FECS_CTXSW_TRACE},
+	{NVGPU_GPU_FLAGS_SUPPORT_DETERMINISTIC_SUBMIT_NO_JOBTRACKING,
+		NVGPU_SUPPORT_DETERMINISTIC_SUBMIT_NO_JOBTRACKING},
+	{NVGPU_GPU_FLAGS_SUPPORT_DETERMINISTIC_SUBMIT_FULL,
+		NVGPU_SUPPORT_DETERMINISTIC_SUBMIT_FULL},
+	{NVGPU_GPU_FLAGS_SUPPORT_IO_COHERENCE,
+		NVGPU_SUPPORT_IO_COHERENCE},
+	{NVGPU_GPU_FLAGS_SUPPORT_RESCHEDULE_RUNLIST,
+		NVGPU_SUPPORT_RESCHEDULE_RUNLIST},
+	{NVGPU_GPU_FLAGS_SUPPORT_MAP_DIRECT_KIND_CTRL,
+		NVGPU_SUPPORT_MAP_DIRECT_KIND_CTRL},
+	{NVGPU_GPU_FLAGS_ECC_ENABLED_SM_LRF,
+		NVGPU_ECC_ENABLED_SM_LRF},
+	{NVGPU_GPU_FLAGS_ECC_ENABLED_SM_SHM,
+		NVGPU_ECC_ENABLED_SM_SHM},
+	{NVGPU_GPU_FLAGS_ECC_ENABLED_TEX,
+		NVGPU_ECC_ENABLED_TEX},
+	{NVGPU_GPU_FLAGS_ECC_ENABLED_LTC,
+		NVGPU_ECC_ENABLED_LTC},
+};
+
+static u64 nvgpu_ctrl_ioctl_gpu_characteristics_flags(struct gk20a *g)
+{
+	unsigned int i;
+	u64 ioctl_flags = 0;
+
+	for (i = 0; i < sizeof(flags_mapping)/sizeof(*flags_mapping); i++) {
+		if (nvgpu_is_enabled(g, flags_mapping[i].enabled_flag))
+			ioctl_flags |= flags_mapping[i].ioctl_flag;
+	}
+
+	return ioctl_flags;
+}
+
 static long
 gk20a_ctrl_ioctl_gpu_characteristics(
 	struct gk20a *g,
@@ -121,6 +197,11 @@ gk20a_ctrl_ioctl_gpu_characteristics(
 	struct nvgpu_gpu_characteristics *pgpu = &g->gpu_characteristics;
 	long err = 0;
 
+	pgpu->flags = nvgpu_ctrl_ioctl_gpu_characteristics_flags(g);
+#ifdef CONFIG_TEGRA_19x_GPU
+	pgpu->flags |= nvgpu_ctrl_ioctl_gpu_characteristics_flags_t19x(g);
+#endif
+
 	if (request->gpu_characteristics_buf_size > 0) {
 		size_t write_size = sizeof(*pgpu);
 
@@ -1108,7 +1189,7 @@ static int nvgpu_gpu_get_voltage(struct gk20a *g,
 	if (args->reserved)
 		return -EINVAL;
 
-	if (!(g->gpu_characteristics.flags & NVGPU_GPU_FLAGS_SUPPORT_GET_VOLTAGE))
+	if (!nvgpu_is_enabled(g, NVGPU_SUPPORT_GET_VOLTAGE))
 		return -EINVAL;
 
 	err = gk20a_busy(g);
@@ -1144,7 +1225,7 @@ static int nvgpu_gpu_get_current(struct gk20a *g,
 	if (args->reserved[0] || args->reserved[1] || args->reserved[2])
 		return -EINVAL;
 
-	if (!(g->gpu_characteristics.flags & NVGPU_GPU_FLAGS_SUPPORT_GET_CURRENT))
+	if (!nvgpu_is_enabled(g, NVGPU_SUPPORT_GET_CURRENT))
 		return -EINVAL;
 
 	err = gk20a_busy(g);
@@ -1168,7 +1249,7 @@ static int nvgpu_gpu_get_power(struct gk20a *g,
 	if (args->reserved[0] || args->reserved[1] || args->reserved[2])
 		return -EINVAL;
 
-	if (!(g->gpu_characteristics.flags & NVGPU_GPU_FLAGS_SUPPORT_GET_POWER))
+	if (!nvgpu_is_enabled(g, NVGPU_SUPPORT_GET_POWER))
 		return -EINVAL;
 
 	err = gk20a_busy(g);

drivers/gpu/nvgpu/common/mm/vm.c

@@ -175,7 +175,7 @@ static int nvgpu_init_sema_pool(struct vm_gk20a *vm)
 	/*
 	 * Don't waste the memory on semaphores if we don't need them.
 	 */
-	if (g->gpu_characteristics.flags & NVGPU_GPU_FLAGS_HAS_SYNCPOINTS)
+	if (nvgpu_is_enabled(g, NVGPU_HAS_SYNCPOINTS))
 		return 0;
 
 	if (vm->sema_pool)
@@ -520,7 +520,7 @@ static void __nvgpu_vm_remove(struct vm_gk20a *vm)
 	 * pool involves unmapping a GMMU mapping which means aquiring the
 	 * update_gmmu_lock.
 	 */
-	if (!(g->gpu_characteristics.flags & NVGPU_GPU_FLAGS_HAS_SYNCPOINTS)) {
+	if (!nvgpu_is_enabled(g, NVGPU_HAS_SYNCPOINTS)) {
 		if (vm->sema_pool) {
 			nvgpu_semaphore_pool_unmap(vm->sema_pool, vm);
 			nvgpu_semaphore_pool_put(vm->sema_pool);

drivers/gpu/nvgpu/gk20a/fecs_trace_gk20a.c

@@ -33,6 +33,7 @@
 #include <nvgpu/thread.h>
 #include <nvgpu/barrier.h>
 #include <nvgpu/mm.h>
+#include <nvgpu/enabled.h>
 
 #include "ctxsw_trace_gk20a.h"
 #include "fecs_trace_gk20a.h"
@@ -594,8 +595,7 @@ int gk20a_fecs_trace_init(struct gk20a *g)
 
 	hash_init(trace->pid_hash_table);
 
-	g->gpu_characteristics.flags |=
+	__nvgpu_set_enabled(g, NVGPU_SUPPORT_FECS_CTXSW_TRACE, true);
-		NVGPU_GPU_FLAGS_SUPPORT_FECS_CTXSW_TRACE;
 
 	gk20a_fecs_trace_debugfs_init(g);
 

drivers/gpu/nvgpu/gk20a/gk20a.c

@@ -417,24 +417,26 @@ int gk20a_init_gpu_characteristics(struct gk20a *g)
 			gpu->available_big_page_sizes |= g->ops.mm.get_big_page_sizes();
 	}
 
-	gpu->flags = NVGPU_GPU_FLAGS_SUPPORT_PARTIAL_MAPPINGS |
+	__nvgpu_set_enabled(g, NVGPU_SUPPORT_PARTIAL_MAPPINGS, true);
-		NVGPU_GPU_FLAGS_SUPPORT_MAP_DIRECT_KIND_CTRL;
+	__nvgpu_set_enabled(g, NVGPU_SUPPORT_MAP_DIRECT_KIND_CTRL, true);
 
 	if (IS_ENABLED(CONFIG_SYNC))
-		gpu->flags |= NVGPU_GPU_FLAGS_SUPPORT_SYNC_FENCE_FDS;
+		__nvgpu_set_enabled(g, NVGPU_SUPPORT_SYNC_FENCE_FDS, true);
 
 	if (g->ops.mm.support_sparse && g->ops.mm.support_sparse(g))
-		gpu->flags |= NVGPU_GPU_FLAGS_SUPPORT_SPARSE_ALLOCS;
+		__nvgpu_set_enabled(g, NVGPU_SUPPORT_SPARSE_ALLOCS, true);
 
 	if (gk20a_platform_has_syncpoints(g))
-		gpu->flags |= NVGPU_GPU_FLAGS_HAS_SYNCPOINTS;
+		__nvgpu_set_enabled(g, NVGPU_HAS_SYNCPOINTS, true);
 
 	/*
 	 * Fast submits are supported as long as the user doesn't request
 	 * anything that depends on job tracking. (Here, fast means strictly no
 	 * metadata, just the gpfifo contents are copied and gp_put updated).
 	 */
-	gpu->flags |= NVGPU_GPU_FLAGS_SUPPORT_DETERMINISTIC_SUBMIT_NO_JOBTRACKING;
+	__nvgpu_set_enabled(g,
+			NVGPU_SUPPORT_DETERMINISTIC_SUBMIT_NO_JOBTRACKING,
+			true);
 
 	/*
 	 * Sync framework requires deferred job cleanup, wrapping syncs in FDs,
@@ -443,13 +445,15 @@ int gk20a_init_gpu_characteristics(struct gk20a *g)
 	 * that depends on deferred cleanup.
 	 */
 	if (!gk20a_channel_sync_needs_sync_framework(g))
-		gpu->flags |= NVGPU_GPU_FLAGS_SUPPORT_DETERMINISTIC_SUBMIT_FULL;
+		__nvgpu_set_enabled(g,
+				NVGPU_SUPPORT_DETERMINISTIC_SUBMIT_FULL,
+				true);
 
-	gpu->flags |= NVGPU_GPU_FLAGS_SUPPORT_USERSPACE_MANAGED_AS;
+	__nvgpu_set_enabled(g, NVGPU_SUPPORT_USERSPACE_MANAGED_AS, true);
-	gpu->flags |= NVGPU_GPU_FLAGS_SUPPORT_TSG;
+	__nvgpu_set_enabled(g, NVGPU_SUPPORT_TSG, true);
 
 	if (g->ops.clk_arb.get_arbiter_clk_domains)
-		gpu->flags |= NVGPU_GPU_FLAGS_SUPPORT_CLOCK_CONTROLS;
+		__nvgpu_set_enabled(g, NVGPU_SUPPORT_CLOCK_CONTROLS, true);
 
 	gpu->gpc_mask = (1 << g->gr.gpc_count)-1;
 

drivers/gpu/nvgpu/gm20b/gr_gm20b.c

@@ -1126,10 +1126,8 @@ u32 gr_gm20b_get_max_fbps_count(struct gk20a *g)
 void gr_gm20b_init_cyclestats(struct gk20a *g)
 {
 #if defined(CONFIG_GK20A_CYCLE_STATS)
-	g->gpu_characteristics.flags |=
+	__nvgpu_set_enabled(g, NVGPU_SUPPORT_CYCLE_STATS, true);
-		NVGPU_GPU_FLAGS_SUPPORT_CYCLE_STATS;
+	__nvgpu_set_enabled(g, NVGPU_SUPPORT_CYCLE_STATS_SNAPSHOT, true);
-	g->gpu_characteristics.flags |=
-		NVGPU_GPU_FLAGS_SUPPORT_CYCLE_STATS_SNAPSHOT;
 	g->gpu_characteristics.max_css_buffer_size = 0xffffffff;
 #else
 	(void)g;

drivers/gpu/nvgpu/gp106/hal_gp106.c

@@ -189,26 +189,24 @@ static int gp106_get_litter_value(struct gk20a *g, int value)
 
 static int gp106_init_gpu_characteristics(struct gk20a *g)
 {
-	struct nvgpu_gpu_characteristics *gpu = &g->gpu_characteristics;
-
 	int err;
 
 	err = gk20a_init_gpu_characteristics(g);
 	if (err)
 		return err;
 
-	gpu->flags |= NVGPU_GPU_FLAGS_SUPPORT_GET_VOLTAGE |
+	__nvgpu_set_enabled(g, NVGPU_SUPPORT_GET_VOLTAGE, true);
-			NVGPU_GPU_FLAGS_SUPPORT_GET_CURRENT |
+	__nvgpu_set_enabled(g, NVGPU_SUPPORT_GET_CURRENT, true);
-			NVGPU_GPU_FLAGS_SUPPORT_GET_POWER |
+	__nvgpu_set_enabled(g, NVGPU_SUPPORT_GET_POWER, true);
-			NVGPU_GPU_FLAGS_SUPPORT_GET_TEMPERATURE |
+	__nvgpu_set_enabled(g, NVGPU_SUPPORT_GET_TEMPERATURE, true);
-			NVGPU_GPU_FLAGS_SUPPORT_DEVICE_EVENTS |
+	__nvgpu_set_enabled(g, NVGPU_SUPPORT_DEVICE_EVENTS, true);
-			NVGPU_GPU_FLAGS_SUPPORT_SET_THERM_ALERT_LIMIT;
+	__nvgpu_set_enabled(g, NVGPU_SUPPORT_SET_THERM_ALERT_LIMIT, true);
 
 	/* WAR for missing INA3221 on HW2.5 RevA */
 	if (g->power_sensor_missing) {
-		gpu->flags &= ~(NVGPU_GPU_FLAGS_SUPPORT_GET_VOLTAGE |
+		__nvgpu_set_enabled(g, NVGPU_SUPPORT_GET_VOLTAGE, false);
-				NVGPU_GPU_FLAGS_SUPPORT_GET_CURRENT |
+		__nvgpu_set_enabled(g, NVGPU_SUPPORT_GET_CURRENT, false);
-				NVGPU_GPU_FLAGS_SUPPORT_GET_POWER);
+		__nvgpu_set_enabled(g, NVGPU_SUPPORT_GET_POWER, false);
 	}
 
 	return 0;

drivers/gpu/nvgpu/gp10b/gp10b.c

@@ -24,14 +24,15 @@
 
 #include "gk20a/gk20a.h"
 
+#include <nvgpu/enabled.h>
+
 #include "gp10b.h"
 
 #include <nvgpu/hw/gp10b/hw_fuse_gp10b.h>
 #include <nvgpu/hw/gp10b/hw_gr_gp10b.h>
 
-static u64 gp10b_detect_ecc_enabled_units(struct gk20a *g)
+static void gp10b_detect_ecc_enabled_units(struct gk20a *g)
 {
-	u64 ecc_enabled_units = 0;
 	u32 opt_ecc_en = gk20a_readl(g, fuse_opt_ecc_en_r());
 	u32 opt_feature_fuses_override_disable =
 			gk20a_readl(g,
@@ -41,23 +42,25 @@ static u64 gp10b_detect_ecc_enabled_units(struct gk20a *g)
 					gr_fecs_feature_override_ecc_r());
 
 	if (opt_feature_fuses_override_disable) {
-		if (opt_ecc_en)
+		if (opt_ecc_en) {
-			ecc_enabled_units = NVGPU_GPU_FLAGS_ALL_ECC_ENABLED;
+			__nvgpu_set_enabled(g, NVGPU_ECC_ENABLED_SM_LRF, true);
-		else
+			__nvgpu_set_enabled(g, NVGPU_ECC_ENABLED_SM_SHM, true);
-			ecc_enabled_units = 0;
+			__nvgpu_set_enabled(g, NVGPU_ECC_ENABLED_TEX, true);
+			__nvgpu_set_enabled(g, NVGPU_ECC_ENABLED_LTC, true);
+		}
 	} else {
 		/* SM LRF */
 		if (gr_fecs_feature_override_ecc_sm_lrf_override_v(
 						fecs_feature_override_ecc)) {
 			if (gr_fecs_feature_override_ecc_sm_lrf_v(
 						fecs_feature_override_ecc)) {
-				ecc_enabled_units |=
+				__nvgpu_set_enabled(g,
-					NVGPU_GPU_FLAGS_ECC_ENABLED_SM_LRF;
+						NVGPU_ECC_ENABLED_SM_LRF, true);
 			}
 		} else {
 			if (opt_ecc_en) {
-				ecc_enabled_units |=
+				__nvgpu_set_enabled(g,
-					NVGPU_GPU_FLAGS_ECC_ENABLED_SM_LRF;
+						NVGPU_ECC_ENABLED_SM_LRF, true);
 			}
 		}
 
@@ -66,13 +69,13 @@ static u64 gp10b_detect_ecc_enabled_units(struct gk20a *g)
 						fecs_feature_override_ecc)) {
 			if (gr_fecs_feature_override_ecc_sm_shm_v(
 						fecs_feature_override_ecc)) {
-				ecc_enabled_units |=
+				__nvgpu_set_enabled(g,
-					NVGPU_GPU_FLAGS_ECC_ENABLED_SM_SHM;
+						NVGPU_ECC_ENABLED_SM_SHM, true);
 			}
 		} else {
 			if (opt_ecc_en) {
-				ecc_enabled_units |=
+				__nvgpu_set_enabled(g,
-					NVGPU_GPU_FLAGS_ECC_ENABLED_SM_SHM;
+						NVGPU_ECC_ENABLED_SM_SHM, true);
 			}
 		}
 
@@ -81,13 +84,13 @@ static u64 gp10b_detect_ecc_enabled_units(struct gk20a *g)
 						fecs_feature_override_ecc)) {
 			if (gr_fecs_feature_override_ecc_tex_v(
 						fecs_feature_override_ecc)) {
-				ecc_enabled_units |=
+				__nvgpu_set_enabled(g,
-					NVGPU_GPU_FLAGS_ECC_ENABLED_TEX;
+						NVGPU_ECC_ENABLED_TEX, true);
 			}
 		} else {
 			if (opt_ecc_en) {
-				ecc_enabled_units |=
+				__nvgpu_set_enabled(g,
-					NVGPU_GPU_FLAGS_ECC_ENABLED_TEX;
+						NVGPU_ECC_ENABLED_TEX, true);
 			}
 		}
 
@@ -96,25 +99,22 @@ static u64 gp10b_detect_ecc_enabled_units(struct gk20a *g)
 						fecs_feature_override_ecc)) {
 			if (gr_fecs_feature_override_ecc_ltc_v(
 						fecs_feature_override_ecc)) {
-				ecc_enabled_units |=
+				__nvgpu_set_enabled(g,
-					NVGPU_GPU_FLAGS_ECC_ENABLED_LTC;
+						NVGPU_ECC_ENABLED_LTC, true);
 			}
 		} else {
 			if (opt_ecc_en) {
-				ecc_enabled_units |=
+				__nvgpu_set_enabled(g,
-					NVGPU_GPU_FLAGS_ECC_ENABLED_LTC;
+						NVGPU_ECC_ENABLED_LTC, true);
 			}
 		}
 	}
-
-	return ecc_enabled_units;
 }
 
 int gp10b_init_gpu_characteristics(struct gk20a *g)
 {
 	gk20a_init_gpu_characteristics(g);
-	g->gpu_characteristics.flags |= gp10b_detect_ecc_enabled_units(g);
+	gp10b_detect_ecc_enabled_units(g);
-	g->gpu_characteristics.flags |=
+	__nvgpu_set_enabled(g, NVGPU_SUPPORT_RESCHEDULE_RUNLIST, true);
-		NVGPU_GPU_FLAGS_SUPPORT_RESCHEDULE_RUNLIST;
 	return 0;
 }

drivers/gpu/nvgpu/gp10b/gr_gp10b.c

@@ -32,6 +32,7 @@
 #include <nvgpu/bug.h>
 #include <nvgpu/debug.h>
 #include <nvgpu/fuse.h>
+#include <nvgpu/enabled.h>
 
 #include "gk20a/gk20a.h"
 #include "gk20a/gr_gk20a.h"

drivers/gpu/nvgpu/include/nvgpu/enabled.h

@@ -34,6 +34,18 @@ struct gk20a;
 #define NVGPU_IS_FMODEL				1
 #define NVGPU_DRIVER_IS_DYING			2
 #define NVGPU_GR_USE_DMA_FOR_FW_BOOTSTRAP 3
+
+/*
+ * ECC flags
+ */
+/* SM LRF ECC is enabled */
+#define NVGPU_ECC_ENABLED_SM_LRF		8
+/* SM SHM ECC is enabled */
+#define NVGPU_ECC_ENABLED_SM_SHM		9
+/* TEX ECC is enabled */
+#define NVGPU_ECC_ENABLED_TEX			10
+/* L2 ECC is enabled */
+#define NVGPU_ECC_ENABLED_LTC			11
 /*
  * MM flags.
  */
@@ -44,13 +56,47 @@ struct gk20a;
 #define NVGPU_MM_UNIFIED_MEMORY			18
 /* kernel mode ce vidmem clearing channels need to be in a tsg */
 #define NVGPU_MM_CE_TSG_REQUIRED		19
+/* User-space managed address spaces support */
+#define NVGPU_SUPPORT_USERSPACE_MANAGED_AS	20
+/* IO coherence support is available */
+#define NVGPU_SUPPORT_IO_COHERENCE		21
+/* MAP_BUFFER_EX with partial mappings */
+#define NVGPU_SUPPORT_PARTIAL_MAPPINGS		22
+/* MAP_BUFFER_EX with sparse allocations */
+#define NVGPU_SUPPORT_SPARSE_ALLOCS		23
+/* Direct PTE kind control is supported (map_buffer_ex) */
+#define NVGPU_SUPPORT_MAP_DIRECT_KIND_CTRL	24
+
+/*
+ * Host flags
+ */
+#define NVGPU_HAS_SYNCPOINTS			30
+/* sync fence FDs are available in, e.g., submit_gpfifo */
+#define NVGPU_SUPPORT_SYNC_FENCE_FDS		31
+/* NVGPU_IOCTL_CHANNEL_CYCLE_STATS is available */
+#define NVGPU_SUPPORT_CYCLE_STATS		32
+/* NVGPU_IOCTL_CHANNEL_CYCLE_STATS_SNAPSHOT is available */
+#define NVGPU_SUPPORT_CYCLE_STATS_SNAPSHOT	33
+/* Both gpu driver and device support TSG */
+#define NVGPU_SUPPORT_TSG			33
+/* Fast deterministic submits with no job tracking are supported */
+#define NVGPU_SUPPORT_DETERMINISTIC_SUBMIT_NO_JOBTRACKING 34
+/* Deterministic submits are supported even with job tracking */
+#define NVGPU_SUPPORT_DETERMINISTIC_SUBMIT_FULL	35
+/* NVGPU_SUBMIT_GPFIFO_FLAGS_RESCHEDULE_RUNLIST is available */
+#define NVGPU_SUPPORT_RESCHEDULE_RUNLIST	36
+
+/* NVGPU_GPU_IOCTL_GET_EVENT_FD is available */
+#define NVGPU_SUPPORT_DEVICE_EVENTS		37
+/* FECS context switch tracing is available */
+#define NVGPU_SUPPORT_FECS_CTXSW_TRACE		38
 
 /*
  * Security flags
  */
 
-#define NVGPU_SEC_SECUREGPCCS			32
+#define NVGPU_SEC_SECUREGPCCS			40
-#define NVGPU_SEC_PRIVSECURITY			33
+#define NVGPU_SEC_PRIVSECURITY			41
 
 /*
  * PMU flags.
@@ -63,9 +109,21 @@ struct gk20a;
 #define NVGPU_GPU_CAN_BLCG                              52
 #define NVGPU_GPU_CAN_SLCG                              53
 #define NVGPU_GPU_CAN_ELCG                              54
+/* Clock control support */
+#define NVGPU_SUPPORT_CLOCK_CONTROLS		55
+/* NVGPU_GPU_IOCTL_GET_VOLTAGE is available */
+#define NVGPU_SUPPORT_GET_VOLTAGE		56
+/* NVGPU_GPU_IOCTL_GET_CURRENT is available */
+#define NVGPU_SUPPORT_GET_CURRENT		57
+/* NVGPU_GPU_IOCTL_GET_POWER is available */
+#define NVGPU_SUPPORT_GET_POWER			58
+/* NVGPU_GPU_IOCTL_GET_TEMPERATURE is available */
+#define NVGPU_SUPPORT_GET_TEMPERATURE		59
+/* NVGPU_GPU_IOCTL_SET_THERM_ALERT_LIMIT is available */
+#define NVGPU_SUPPORT_SET_THERM_ALERT_LIMIT	60
 
 /* whether to run PREOS binary on dGPUs */
-#define NVGPU_PMU_RUN_PREOS			52
+#define NVGPU_PMU_RUN_PREOS			61
 
 /*
  * Must be greater than the largest bit offset in the above list.

drivers/gpu/nvgpu/vgpu/fecs_trace_vgpu.c

@@ -26,6 +26,7 @@
 
 #include <nvgpu/kmem.h>
 #include <nvgpu/bug.h>
+#include <nvgpu/enabled.h>
 
 #include "gk20a/gk20a.h"
 #include "gk20a/ctxsw_trace_gk20a.h"
@@ -63,8 +64,7 @@ int vgpu_fecs_trace_init(struct gk20a *g)
 		dev_info(dev_from_gk20a(g), "does not support fecs trace\n");
 		goto fail;
 	}
-	g->gpu_characteristics.flags |=
+	__nvgpu_set_enabled(g, NVGPU_SUPPORT_FECS_CTXSW_TRACE, true);
-		NVGPU_GPU_FLAGS_SUPPORT_FECS_CTXSW_TRACE;
 
 	hv_np = args.np;
 	mempool = args.args[0];

drivers/gpu/nvgpu/vgpu/vgpu.c

@@ -370,10 +370,8 @@ int vgpu_init_gpu_characteristics(struct gk20a *g)
 	g->gpu_characteristics.map_buffer_batch_limit = 0;
 
 	/* features vgpu does not support */
-	g->gpu_characteristics.flags &= ~NVGPU_GPU_FLAGS_SUPPORT_CYCLE_STATS;
+	__nvgpu_set_enabled(g, NVGPU_SUPPORT_CYCLE_STATS, false);
-	g->gpu_characteristics.flags &= ~NVGPU_GPU_FLAGS_SUPPORT_MAP_COMPBITS;
+	__nvgpu_set_enabled(g, NVGPU_SUPPORT_RESCHEDULE_RUNLIST, false);
-	g->gpu_characteristics.flags &=
-		~NVGPU_GPU_FLAGS_SUPPORT_RESCHEDULE_RUNLIST;
 
 	return 0;
 }