diff --git a/drivers/gpu/nvgpu/common/fifo/engines.c b/drivers/gpu/nvgpu/common/fifo/engines.c
index cbb5e8817..2e91d6c22 100644
--- a/drivers/gpu/nvgpu/common/fifo/engines.c
+++ b/drivers/gpu/nvgpu/common/fifo/engines.c
@@ -527,6 +527,9 @@ void nvgpu_engine_reset(struct gk20a *g, u32 engine_id)
 	 * Simple case first: reset a copy engine.
 	 */
 	if (nvgpu_device_is_ce(g, dev)) {
+		if (g->ops.ce.halt_engine != NULL) {
+			g->ops.ce.halt_engine(g, dev);
+		}
 		err = nvgpu_mc_reset_dev(g, dev);
 		if (g->ops.ce.request_idle != NULL) {
 			/*
diff --git a/drivers/gpu/nvgpu/hal/ce/ce_gv11b.h b/drivers/gpu/nvgpu/hal/ce/ce_gv11b.h
index a27e77269..4d2d1b307 100644
--- a/drivers/gpu/nvgpu/hal/ce/ce_gv11b.h
+++ b/drivers/gpu/nvgpu/hal/ce/ce_gv11b.h
@@ -2,7 +2,7 @@
  *
  * Volta GPU series copy engine
  *
- * Copyright (c) 2016-2019, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2016-2022, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -26,10 +26,11 @@
 #define NVGPU_CE_GV11B_H
 
 struct gk20a;
+struct nvgpu_device;
 
 void gv11b_ce_mthd_buffer_fault_in_bar2_fault(struct gk20a *g);
 u32 gv11b_ce_get_num_pce(struct gk20a *g);
 void gv11b_ce_stall_isr(struct gk20a *g, u32 inst_id, u32 pri_base);
 void gv11b_ce_init_prod_values(struct gk20a *g);
-
+void gv11b_ce_halt_engine(struct gk20a *g, const struct nvgpu_device *dev);
 #endif /* NVGPU_CE_GV11B_H */
diff --git a/drivers/gpu/nvgpu/hal/ce/ce_gv11b_fusa.c b/drivers/gpu/nvgpu/hal/ce/ce_gv11b_fusa.c
index 2c5da90b9..1dbaf3caa 100644
--- a/drivers/gpu/nvgpu/hal/ce/ce_gv11b_fusa.c
+++ b/drivers/gpu/nvgpu/hal/ce/ce_gv11b_fusa.c
@@ -25,6 +25,7 @@
 #include <nvgpu/io.h>
 #include <nvgpu/log.h>
 #include <nvgpu/bitops.h>
+#include <nvgpu/device.h>
 #include <nvgpu/gk20a.h>
 #include <nvgpu/nvgpu_err.h>
 
@@ -118,3 +119,18 @@ void gv11b_ce_init_prod_values(struct gk20a *g)
 		nvgpu_writel(g, ce_lce_opt_r(lce), reg_val);
 	}
 }
+
+void gv11b_ce_halt_engine(struct gk20a *g, const struct nvgpu_device *dev)
+{
+	u32 reg_val;
+
+	reg_val = nvgpu_readl(g, ce_lce_engctl_r(dev->inst_id));
+	reg_val |= ce_lce_engctl_stallreq_true_f();
+	nvgpu_writel(g, ce_lce_engctl_r(dev->inst_id), reg_val);
+
+	reg_val = nvgpu_readl(g, ce_lce_engctl_r(dev->inst_id));
+	if ((reg_val & ce_lce_engctl_stallack_true_f()) == 0U) {
+		nvgpu_err(g, "The CE engine %u is not idle"
+					"while reset", dev->inst_id);
+	}
+}
diff --git a/drivers/gpu/nvgpu/hal/init/hal_ga100.c b/drivers/gpu/nvgpu/hal/init/hal_ga100.c
index ad9d30521..98c621505 100644
--- a/drivers/gpu/nvgpu/hal/init/hal_ga100.c
+++ b/drivers/gpu/nvgpu/hal/init/hal_ga100.c
@@ -429,6 +429,7 @@ static const struct gops_ce ga100_ops_ce = {
 	.get_num_pce = gv11b_ce_get_num_pce,
 	.mthd_buffer_fault_in_bar2_fault = gv11b_ce_mthd_buffer_fault_in_bar2_fault,
 	.init_prod_values = gv11b_ce_init_prod_values,
+	.halt_engine = gv11b_ce_halt_engine,
 	.request_idle = NULL,
 };
 
diff --git a/drivers/gpu/nvgpu/hal/init/hal_ga10b.c b/drivers/gpu/nvgpu/hal/init/hal_ga10b.c
index c3b7d4de2..278d2042a 100644
--- a/drivers/gpu/nvgpu/hal/init/hal_ga10b.c
+++ b/drivers/gpu/nvgpu/hal/init/hal_ga10b.c
@@ -403,6 +403,7 @@ static const struct gops_ce ga10b_ops_ce = {
 	.get_num_pce = gv11b_ce_get_num_pce,
 	.mthd_buffer_fault_in_bar2_fault = gv11b_ce_mthd_buffer_fault_in_bar2_fault,
 	.init_prod_values = gv11b_ce_init_prod_values,
+	.halt_engine = gv11b_ce_halt_engine,
 	.request_idle = ga10b_ce_request_idle,
 };
 
diff --git a/drivers/gpu/nvgpu/hal/init/hal_gv11b.c b/drivers/gpu/nvgpu/hal/init/hal_gv11b.c
index 38bc3ba7e..5cb233bd0 100644
--- a/drivers/gpu/nvgpu/hal/init/hal_gv11b.c
+++ b/drivers/gpu/nvgpu/hal/init/hal_gv11b.c
@@ -316,6 +316,7 @@ static const struct gops_ce gv11b_ops_ce = {
 	.get_num_pce = gv11b_ce_get_num_pce,
 	.mthd_buffer_fault_in_bar2_fault = gv11b_ce_mthd_buffer_fault_in_bar2_fault,
 	.init_prod_values = gv11b_ce_init_prod_values,
+	.halt_engine = gv11b_ce_halt_engine,
 	.request_idle = NULL,
 };
 
diff --git a/drivers/gpu/nvgpu/hal/init/hal_tu104.c b/drivers/gpu/nvgpu/hal/init/hal_tu104.c
index 2f9297e9e..4b1567695 100644
--- a/drivers/gpu/nvgpu/hal/init/hal_tu104.c
+++ b/drivers/gpu/nvgpu/hal/init/hal_tu104.c
@@ -365,6 +365,7 @@ static const struct gops_ce tu104_ops_ce = {
 	.get_num_pce = gv11b_ce_get_num_pce,
 	.mthd_buffer_fault_in_bar2_fault = gv11b_ce_mthd_buffer_fault_in_bar2_fault,
 	.init_prod_values = gv11b_ce_init_prod_values,
+	.halt_engine = gv11b_ce_halt_engine,
 	.request_idle = NULL,
 };
 
diff --git a/drivers/gpu/nvgpu/include/nvgpu/gops/ce.h b/drivers/gpu/nvgpu/include/nvgpu/gops/ce.h
index e7d88e8c0..35acf060c 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/gops/ce.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/gops/ce.h
@@ -30,7 +30,7 @@
  * CE HAL interface.
  */
 struct gk20a;
-
+struct nvgpu_device;
 /**
  * CE HAL operations.
  *
@@ -132,6 +132,7 @@ struct gops_ce {
 	int (*ce_init_support)(struct gk20a *g);
 	void (*set_pce2lce_mapping)(struct gk20a *g);
 	void (*init_prod_values)(struct gk20a *g);
+	void (*halt_engine)(struct gk20a *g, const struct nvgpu_device *dev);
 	void (*request_idle)(struct gk20a *g);
 
 	/*