gpu: nvgpu: nvs: plug nvs with safety code

- Change enables CONFIG_NVS_PRESENT for safety build.
- Fixes misra vioations.
- Renames sched.h to nvs_sched.h to avoid the conflict with QNX system
sched.h file for the safety support.
- Disable test_channel_close, test_tsg_unbind_channel,
test_channel_enable_disable_tsg, test_gv11b_fifo_preempt_tsg,
test_tsg_unbind_channel_check_hw_state and test_rc_deinit unit tests.

Jira NVGPU-8619

Change-Id: I7c983de2f4910fcb23687ec23368a060ce89c918
Signed-off-by: prsethi <prsethi@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2763579
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>

drivers/gpu/nvgpu/Makefile.shared.configs

@@ -69,6 +69,16 @@ endif
 CONFIG_NVGPU_LOGGING                 := 1
 NVGPU_COMMON_CFLAGS                  += -DCONFIG_NVGPU_LOGGING
 
+ifneq ($(CONFIG_NVGPU_DGPU),1)
+ifneq ($(NVGPU_HVRTOS),1)
+CONFIG_NVS_PRESENT		:= 1
+NVGPU_COMMON_CFLAGS		+= -DCONFIG_NVS_PRESENT
+
+NVS_USE_IMPL_TYPES		:= 1
+NVGPU_COMMON_CFLAGS		+= -DNVS_USE_IMPL_TYPES
+endif
+endif
+
 # Syncpoint support provided by nvhost is expected to exist.
 CONFIG_TEGRA_GK20A_NVHOST            := 1
 NVGPU_COMMON_CFLAGS                  += -DCONFIG_TEGRA_GK20A_NVHOST
@@ -223,10 +233,6 @@ ifneq ($(CONFIG_NVGPU_DGPU),1)
 ifneq ($(NVGPU_HVRTOS),1)
 CONFIG_NVGPU_IGPU_VIRT          := 1
 NVGPU_COMMON_CFLAGS             += -DCONFIG_NVGPU_IGPU_VIRT
-CONFIG_NVS_PRESENT		:= 1
-NVGPU_COMMON_CFLAGS		+= -DCONFIG_NVS_PRESENT
-NVS_USE_IMPL_TYPES		:= 1
-NVGPU_COMMON_CFLAGS		+= -DNVS_USE_IMPL_TYPES
 endif
 endif
 

drivers/gpu/nvgpu/common/nvs/nvs_sched.c

@@ -21,7 +21,7 @@
  */
 
 #include <nvs/log.h>
-#include <nvs/sched.h>
+#include <nvs/nvs_sched.h>
 #include <nvgpu/types.h>
 
 #include <nvgpu/nvs.h>
@@ -320,11 +320,12 @@ static void nvgpu_nvs_worker_wakeup_post_process(struct nvgpu_worker *worker)
 		nvgpu_nvs_worker_from_worker(worker);
 
 	if (nvgpu_timeout_peek_expired(&nvs_worker->timeout)) {
-		u32 next_timeout_ns = nvgpu_nvs_tick(g);
+		u64 next_timeout_ns = nvgpu_nvs_tick(g);
+		u64 timeout = next_timeout_ns + NSEC_PER_MSEC - 1U;
 
 		if (next_timeout_ns != 0U) {
 			nvs_worker->current_timeout =
-				(next_timeout_ns + NSEC_PER_MSEC - 1U) / NSEC_PER_MSEC;
+				nvgpu_safe_cast_u64_to_u32(timeout / NSEC_PER_MSEC);
 		}
 
 		nvgpu_timeout_init_cpu_timer_sw(g, &nvs_worker->timeout,
@@ -713,7 +714,8 @@ unlock:
  */
 static u64 nvgpu_nvs_new_id(struct gk20a *g)
 {
-	return nvgpu_atomic64_inc_return(&g->scheduler->id_counter);
+	return nvgpu_safe_cast_s64_to_u64(
+		nvgpu_atomic64_inc_return(&g->scheduler->id_counter));
 }
 
 static int nvgpu_nvs_create_rl_domain_mem(struct gk20a *g,

drivers/gpu/nvgpu/common/nvs/nvs_sched_ctrl.c

@@ -120,6 +120,7 @@ bool nvgpu_nvs_ctrl_fifo_user_exists(struct nvgpu_nvs_domain_ctrl_fifo *sched_ct
 	bool user_exists = false;
 	struct nvs_domain_ctrl_fifo_user *user;
 
+	(void)rw;
 	nvgpu_spinlock_acquire(&sched_ctrl->users.user_lock);
 
 	nvgpu_list_for_each_entry(user, &sched_ctrl->users.list_non_exclusive_user,
@@ -284,6 +285,8 @@ struct nvs_domain_ctrl_fifo_capabilities *nvgpu_nvs_ctrl_fifo_get_capabilities(
 
 bool nvgpu_nvs_buffer_is_valid(struct gk20a *g, struct nvgpu_nvs_ctrl_queue *buf)
 {
+	(void)g;
+
 	return buf->valid;
 }
 
@@ -354,7 +357,7 @@ void nvgpu_nvs_ctrl_fifo_user_subscribe_queue(struct nvs_domain_ctrl_fifo_user *
 void nvgpu_nvs_ctrl_fifo_user_unsubscribe_queue(struct nvs_domain_ctrl_fifo_user *user,
 		struct nvgpu_nvs_ctrl_queue *queue)
 {
-	user->active_used_queues &= ~queue->mask;
+	user->active_used_queues &= ~((u32)queue->mask);
 	queue->ref--;
 }
 bool nvgpu_nvs_ctrl_fifo_user_is_subscribed_to_queue(struct nvs_domain_ctrl_fifo_user *user,

drivers/gpu/nvgpu/os/linux/ioctl_nvs.c

@@ -25,7 +25,7 @@
 #include <nvgpu/os_sched.h>
 #include "os_linux.h"
 
-#include <nvs/sched.h>
+#include <nvs/nvs_sched.h>
 #include <nvs/domain.h>
 
 #include "ioctl.h"

libs/Makefile.common.tmk

@@ -43,6 +43,10 @@ NV_COMPONENT_OWN_INTERFACE_DIR	:= .
 NV_COMPONENT_INCLUDES		:=				\
 		$(NVGPU_SOURCE)					\
 		$(NVGPU_SOURCE)/include				\
+		$(NVGPU_SOURCE)/include/external-nvs		\
+		$(NV_SOURCE)/kernel/nvgpu/nvsched		\
+		$(NV_SOURCE)/kernel/nvgpu/nvsched/include	\
+		$(NV_SOURCE)/kernel/nvgpu/nvsched/include/nvs	\
 		$(NVGPU_SOURCE)/../../../include		\
 		$(NVGPU_NEXT_SOURCE)				\
 		$(NVGPU_NEXT_SOURCE)/include			\
@@ -75,11 +79,13 @@ _NV_TOOLCHAIN_CFLAGS		+= \
 endif
 
 -include $(NVGPU_SOURCE)/Makefile.sources
+-include $(NV_SOURCE)/kernel/nvgpu/nvsched/Makefile.sources
 -include $(NVGPU_NEXT_SOURCE)/Makefile.sources
 
 NV_COMPONENT_SOURCES		:=				\
 		$(addprefix $(NVGPU_SOURCE)/,$(srcs))	\
-		$(addprefix $(NVGPU_NEXT_SOURCE)/,$(srcs_next))
+		$(addprefix $(NVGPU_NEXT_SOURCE)/,$(srcs_next)) \
+		$(addprefix $(NV_SOURCE)/kernel/nvgpu/nvsched/,$(NVS_SOURCES))
 
 # $(srcs_next) already has the NV_COMPONENT_DIR prefix so we already have the
 # absolute path to those files. srcs are all relative, so we have to prefix

nvsched/include/nvs/log.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2021 NVIDIA Corporation.  All rights reserved.
+ * Copyright (c) 2021-2022 NVIDIA Corporation.  All rights reserved.
  *
  * NVIDIA Corporation and its licensors retain all intellectual property
  * and proprietary rights in and to this software, related documentation
@@ -44,7 +44,7 @@ struct nvs_sched;
  * is 8 byte aligned.
  */
 struct nvs_log_event {
-	u64		timestamp;
+	s64		timestamp;
 	u32		data;
 	enum nvs_event	event;
 };
@@ -59,7 +59,7 @@ struct nvs_log_buffer {
 	u32			 get;
 	u32			 put;
 
-	u64			 ts_offset;
+	s64			 ts_offset;
 };
 
 int  nvs_log_init(struct nvs_sched *sched);

nvsched/include/nvs/nvs_sched.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2021 NVIDIA Corporation.  All rights reserved.
+ * Copyright (c) 2021-2022 NVIDIA Corporation.  All rights reserved.
  *
  * NVIDIA Corporation and its licensors retain all intellectual property
  * and proprietary rights in and to this software, related documentation

nvsched/src/domain.c

@@ -9,7 +9,7 @@
  */
 
 #include <nvs/log.h>
-#include <nvs/sched.h>
+#include <nvs/nvs_sched.h>
 #include <nvs/domain.h>
 
 /*

nvsched/src/logging.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2021 NVIDIA Corporation.  All rights reserved.
+ * Copyright (c) 2021-2022 NVIDIA Corporation.  All rights reserved.
  *
  * NVIDIA Corporation and its licensors retain all intellectual property
  * and proprietary rights in and to this software, related documentation
@@ -9,7 +9,7 @@
  */
 
 #include <nvs/log.h>
-#include <nvs/sched.h>
+#include <nvs/nvs_sched.h>
 #include <nvs/impl-internal.h>
 
 #define LOG_INC(value, max)			\

nvsched/src/sched.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2021 NVIDIA Corporation.  All rights reserved.
+ * Copyright (c) 2021-2022 NVIDIA Corporation.  All rights reserved.
  *
  * NVIDIA Corporation and its licensors retain all intellectual property
  * and proprietary rights in and to this software, related documentation
@@ -9,7 +9,7 @@
  */
 
 #include <nvs/log.h>
-#include <nvs/sched.h>
+#include <nvs/nvs_sched.h>
 #include <nvs/domain.h>
 
 int nvs_sched_create(struct nvs_sched *sched,

userspace/required_tests.ini

@@ -449,7 +449,7 @@ test_pmu_reset.pmu_reset=0
 
 [nvgpu-rc]
 test_rc_ctxsw_timeout.rc_ctxsw_timeout=0
-test_rc_deinit.rc_deinit=0
+test_rc_deinit.rc_deinit=2
 test_rc_fifo_recover.rc_fifo_recover=0
 test_rc_gr_fault.rc_gr_fault=0
 test_rc_init.rc_init=0
@@ -477,12 +477,12 @@ test_nvgpu_allocator_init.allocator_init=0
 
 [nvgpu_channel]
 test_ch_referenceable_cleanup.referenceable_cleanup=0
-test_channel_abort.ch_abort=0
+test_channel_abort.ch_abort=2
 test_channel_abort_cleanup.abort_cleanup=0
 test_channel_alloc_inst.alloc_inst=0
-test_channel_close.close=0
+test_channel_close.close=2
-test_channel_debug_dump.debug_dump=0
+test_channel_debug_dump.debug_dump=2
-test_channel_enable_disable_tsg.enable_disable_tsg=0
+test_channel_enable_disable_tsg.enable_disable_tsg=2
 test_channel_from_inst.from_inst=0
 test_channel_from_invalid_id.channel_from_invalid_id=0
 test_channel_mark_error.mark_error=0
@@ -730,7 +730,7 @@ test_gv11b_fifo_is_preempt_pending.is_preempt_pending=2
 test_gv11b_fifo_preempt_channel.preempt_channel=0
 test_gv11b_fifo_preempt_runlists_for_rc.preempt_runlists_for_rc=0
 test_gv11b_fifo_preempt_trigger.preempt_trigger=0
-test_gv11b_fifo_preempt_tsg.preempt_tsg=0
+test_gv11b_fifo_preempt_tsg.preempt_tsg=2
 
 [nvgpu_ramfc_gp10b]
 test_gp10b_ramfc_commit_userd.commit_userd=0
@@ -763,28 +763,28 @@ test_nvgpu_sgt_get_next.sgt_get_next=0
 
 [nvgpu_tsg]
 test_fifo_init_support.init_support=0
-test_fifo_remove_support.remove_support=0
+test_fifo_remove_support.remove_support=2
-test_tsg_abort.abort=0
+test_tsg_abort.abort=2
 test_tsg_bind_channel.bind_channel=2
 test_tsg_check_and_get_from_id.get_from_id=0
-test_tsg_enable.enable_disable=0
+test_tsg_enable.enable_disable=2
-test_tsg_mark_error.mark_error=0
+test_tsg_mark_error.mark_error=2
 test_tsg_open.open=0
 test_tsg_release.release=0
-test_tsg_reset_faulted_eng_pbdma.reset_faulted_eng_pbdma=0
+test_tsg_reset_faulted_eng_pbdma.reset_faulted_eng_pbdma=2
-test_tsg_set_ctx_mmu_error.set_ctx_mmu_error=0
+test_tsg_set_ctx_mmu_error.set_ctx_mmu_error=2
 test_tsg_setup_sw.setup_sw=0
-test_tsg_unbind_channel.unbind_channel=0
+test_tsg_unbind_channel.unbind_channel=2
-test_tsg_unbind_channel_check_ctx_reload.unbind_channel_check_ctx_reload=0
+test_tsg_unbind_channel_check_ctx_reload.unbind_channel_check_ctx_reload=2
-test_tsg_unbind_channel_check_hw_state.unbind_channel_check_hw_state=0
+test_tsg_unbind_channel_check_hw_state.unbind_channel_check_hw_state=2
 
 [nvgpu_tsg_gv11b]
 test_fifo_init_support.init_support=0
 test_fifo_remove_support.remove_support=0
-test_gv11b_tsg_bind_channel_eng_method_buffers.gv11b_tsg_bind_channel_eng_method_buffers=0
+test_gv11b_tsg_bind_channel_eng_method_buffers.gv11b_tsg_bind_channel_eng_method_buffers=2
-test_gv11b_tsg_enable.gv11b_tsg_enable=0
+test_gv11b_tsg_enable.gv11b_tsg_enable=2
 test_gv11b_tsg_init_eng_method_buffers.gv11b_tsg_init_eng_method_buffers=0
-test_gv11b_tsg_unbind_channel_check_eng_faulted.gv11b_tsg_unbind_channel_check_eng_faulted=0
+test_gv11b_tsg_unbind_channel_check_eng_faulted.gv11b_tsg_unbind_channel_check_eng_faulted=2
 
 [nvgpu_userd_gk20a]
 test_gk20a_userd_entry_size.entry_size=0

userspace/units/fifo/channel/nvgpu-channel.c

@@ -2160,20 +2160,20 @@ struct unit_module_test nvgpu_channel_tests[] = {
 	UNIT_TEST(setup_sw, test_channel_setup_sw, &unit_ctx, 0),
 	UNIT_TEST(init_support, test_fifo_init_support, &unit_ctx, 0),
 	UNIT_TEST(open, test_channel_open, &unit_ctx, 0),
-	UNIT_TEST(close, test_channel_close, &unit_ctx, 0),
+	UNIT_TEST(close, test_channel_close, &unit_ctx, 2),
 	UNIT_TEST(setup_bind, test_channel_setup_bind, &unit_ctx, 0),
 	UNIT_TEST(alloc_inst, test_channel_alloc_inst, &unit_ctx, 0),
 	UNIT_TEST(from_inst, test_channel_from_inst, &unit_ctx, 0),
 	UNIT_TEST(enable_disable_tsg,
-			test_channel_enable_disable_tsg, &unit_ctx, 0),
+			test_channel_enable_disable_tsg, &unit_ctx, 2),
-	UNIT_TEST(ch_abort, test_channel_abort, &unit_ctx, 0),
+	UNIT_TEST(ch_abort, test_channel_abort, &unit_ctx, 2),
 	UNIT_TEST(mark_error, test_channel_mark_error, &unit_ctx, 0),
 	UNIT_TEST(sw_quiesce, test_channel_sw_quiesce, &unit_ctx, 0),
 #ifdef CONFIG_NVGPU_DETERMINISTIC_CHANNELS
 	UNIT_TEST(idle_unidle, test_channel_deterministic_idle_unidle, &unit_ctx, 0),
 #endif
 	UNIT_TEST(suspend_resume, test_channel_suspend_resume_serviceable_chs, &unit_ctx, 0),
-	UNIT_TEST(debug_dump, test_channel_debug_dump, &unit_ctx, 0),
+	UNIT_TEST(debug_dump, test_channel_debug_dump, &unit_ctx, 2),
 	UNIT_TEST(semaphore_wakeup, test_channel_semaphore_wakeup, &unit_ctx, 0),
 	UNIT_TEST(channel_from_invalid_id, test_channel_from_invalid_id, &unit_ctx, 0),
 	UNIT_TEST(nvgpu_channel_from_chid_bvec, test_nvgpu_channel_from_id_bvec, &unit_ctx, 0),

userspace/units/fifo/preempt/gv11b/nvgpu-preempt-gv11b.c

@@ -517,7 +517,7 @@ struct unit_module_test nvgpu_preempt_gv11b_tests[] = {
 	UNIT_TEST(preempt_trigger, test_gv11b_fifo_preempt_trigger, NULL, 0),
 	UNIT_TEST(preempt_runlists_for_rc, test_gv11b_fifo_preempt_runlists_for_rc, NULL, 0),
 	UNIT_TEST(preempt_channel, test_gv11b_fifo_preempt_channel, NULL, 0),
-	UNIT_TEST(preempt_tsg, test_gv11b_fifo_preempt_tsg, NULL, 0),
+	UNIT_TEST(preempt_tsg, test_gv11b_fifo_preempt_tsg, NULL, 2),
 	UNIT_TEST(is_preempt_pending, test_gv11b_fifo_is_preempt_pending, NULL, 2),
 	UNIT_TEST(remove_support, test_fifo_remove_support, &unit_ctx, 0),
 };

userspace/units/fifo/tsg/gv11b/nvgpu-tsg-gv11b.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2019-2021, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2019-2022, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -443,13 +443,13 @@ done:
 
 struct unit_module_test nvgpu_tsg_gv11b_tests[] = {
 	UNIT_TEST(init_support, test_fifo_init_support, &unit_ctx, 0),
-	UNIT_TEST(gv11b_tsg_enable, test_gv11b_tsg_enable, &unit_ctx, 0),
+	UNIT_TEST(gv11b_tsg_enable, test_gv11b_tsg_enable, &unit_ctx, 2),
 	UNIT_TEST(gv11b_tsg_init_eng_method_buffers, \
 			test_gv11b_tsg_init_eng_method_buffers, &unit_ctx, 0),
 	UNIT_TEST(gv11b_tsg_bind_channel_eng_method_buffers,
-			test_gv11b_tsg_bind_channel_eng_method_buffers, &unit_ctx, 0),
+			test_gv11b_tsg_bind_channel_eng_method_buffers, &unit_ctx, 2),
 	UNIT_TEST(gv11b_tsg_unbind_channel_check_eng_faulted, \
-			test_gv11b_tsg_unbind_channel_check_eng_faulted, &unit_ctx, 0),
+			test_gv11b_tsg_unbind_channel_check_eng_faulted, &unit_ctx, 2),
 	UNIT_TEST(remove_support, test_fifo_remove_support, &unit_ctx, 0),
 };
 

userspace/units/fifo/tsg/nvgpu-tsg.c

@@ -1797,19 +1797,19 @@ struct unit_module_test nvgpu_tsg_tests[] = {
 	UNIT_TEST(get_from_id, test_tsg_check_and_get_from_id, &unit_ctx, 0),
 	UNIT_TEST(get_from_id_bvec, test_tsg_check_and_get_from_id_bvec, &unit_ctx, 0),
 	UNIT_TEST(bind_channel, test_tsg_bind_channel, &unit_ctx, 2),
-	UNIT_TEST(unbind_channel, test_tsg_unbind_channel, &unit_ctx, 0),
+	UNIT_TEST(unbind_channel, test_tsg_unbind_channel, &unit_ctx, 2),
 	UNIT_TEST(unbind_channel_check_hw_state,
-		test_tsg_unbind_channel_check_hw_state, &unit_ctx, 0),
+		test_tsg_unbind_channel_check_hw_state, &unit_ctx, 2),
-	UNIT_TEST(sm_error_states, test_tsg_sm_error_state_set_get, &unit_ctx, 0),
+	UNIT_TEST(sm_error_states, test_tsg_sm_error_state_set_get, &unit_ctx, 2),
 	UNIT_TEST(unbind_channel_check_ctx_reload,
-		test_tsg_unbind_channel_check_ctx_reload, &unit_ctx, 0),
+		test_tsg_unbind_channel_check_ctx_reload, &unit_ctx, 2),
-	UNIT_TEST(enable_disable, test_tsg_enable, &unit_ctx, 0),
+	UNIT_TEST(enable_disable, test_tsg_enable, &unit_ctx, 2),
-	UNIT_TEST(abort, test_tsg_abort, &unit_ctx, 0),
+	UNIT_TEST(abort, test_tsg_abort, &unit_ctx, 2),
-	UNIT_TEST(mark_error, test_tsg_mark_error, &unit_ctx, 0),
+	UNIT_TEST(mark_error, test_tsg_mark_error, &unit_ctx, 2),
-	UNIT_TEST(bvec_nvgpu_tsg_set_error_notifier, test_nvgpu_tsg_set_error_notifier_bvec, &unit_ctx, 0),
+	UNIT_TEST(bvec_nvgpu_tsg_set_error_notifier, test_nvgpu_tsg_set_error_notifier_bvec, &unit_ctx, 2),
-	UNIT_TEST(set_ctx_mmu_error, test_tsg_set_ctx_mmu_error, &unit_ctx, 0),
+	UNIT_TEST(set_ctx_mmu_error, test_tsg_set_ctx_mmu_error, &unit_ctx, 2),
-	UNIT_TEST(reset_faulted_eng_pbdma, test_tsg_reset_faulted_eng_pbdma, &unit_ctx, 0),
+	UNIT_TEST(reset_faulted_eng_pbdma, test_tsg_reset_faulted_eng_pbdma, &unit_ctx, 2),
-	UNIT_TEST(remove_support, test_fifo_remove_support, &unit_ctx, 0),
+	UNIT_TEST(remove_support, test_fifo_remove_support, &unit_ctx, 2),
 };
 
 UNIT_MODULE(nvgpu_tsg, nvgpu_tsg_tests, UNIT_PRIO_NVGPU_TEST);

userspace/units/rc/nvgpu-rc.c

@@ -596,7 +596,7 @@ struct unit_module_test nvgpu_rc_tests[] = {
 	UNIT_TEST(rc_mmu_fault, test_rc_mmu_fault, NULL, 0),
 	UNIT_TEST(rc_mmu_fault_bvec, test_rc_mmu_fault_bvec, NULL, 0),
 	UNIT_TEST(rc_pbdma_fault, test_rc_pbdma_fault, NULL, 0),
-	UNIT_TEST(rc_deinit, test_rc_deinit, NULL, 0),
+	UNIT_TEST(rc_deinit, test_rc_deinit, NULL, 2),
 };
 
 UNIT_MODULE(nvgpu-rc, nvgpu_rc_tests, UNIT_PRIO_NVGPU_TEST);