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gpu: nvgpu: Initialize clk counters for dGPU clocks

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Initialize the clock counters for GPCCLK, XBARCLK, SYSCLK.
This INIT was done in PMU before, but now disabled from TU10A profile.
Hence the initialization is moved into nvgpu.

This patch does the following.
1. Move clock files from GV100 to TU104.
2. Add the Counter HW Registers.
3. Initialize the counter registers for gpc, xbar and sysclk.
4. Change the debug fs node from gv100 to tu104.
5. Update in yaml file with new file names.

Bug 200536091

Change-Id: I436019a18f5c4c73979977666d0c04ce4c569047
Signed-off-by: Abdul Salam <absalam@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2155298
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: Mahantesh Kumbar <mkumbar@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Abdul Salam
2019-07-25 11:53:01 +05:30
committed by mobile promotions
parent 1551e7ea3d
commit e58e00b0fb
12 changed files with 179 additions and 51 deletions
Download Patch File Download Diff File Expand all files Collapse all files

255
drivers/gpu/nvgpu/os/linux/debug_clk_tu104.c Normal file
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@@ -0,0 +1,255 @@
/*
* Copyright (c) 2018-2019, NVIDIA Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
#include <linux/debugfs.h>
#include <linux/seq_file.h>
#include "os_linux.h"
#include <nvgpu/clk.h>
#include <nvgpu/boardobj.h>
#include <nvgpu/boardobjgrp_e32.h>
#include <nvgpu/boardobjgrp_e255.h>
#include <nvgpu/pmu/clk/clk_freq_controller.h>
#include <nvgpu/pmu/clk/clk_vf_point.h>
#include <nvgpu/pmu/clk/clk_fll.h>
#include <nvgpu/pmu/clk/clk.h>
#include "hal/clk/clk_tu104.h"
#include "common/pmu/clk/clk_freq_controller.h"
void nvgpu_clk_arb_pstate_change_lock(struct gk20a *g, bool lock);
static int tu104_get_rate_show(void *data , u64 *val)
{
struct namemap_cfg *c = (struct namemap_cfg *)data;
struct gk20a *g = c->g;
if (!g->ops.clk.get_rate_cntr)
return -EINVAL;
*val = c->is_counter ? (u64)c->scale * g->ops.clk.get_rate_cntr(g, c) :
0 /* TODO PLL read */;
return 0;
}
DEFINE_SIMPLE_ATTRIBUTE(get_rate_fops, tu104_get_rate_show, NULL, "%llu\n");
static int sys_cfc_read(void *data , u64 *val)
{
struct gk20a *g = (struct gk20a *)data;
bool bload = nvgpu_boardobjgrpmask_bit_get(
&g->pmu->clk_pmu->clk_freq_controllers->
freq_ctrl_load_mask.super,
CTRL_CLK_CLK_FREQ_CONTROLLER_ID_SYS);
/* val = 1 implies CLFC is loaded or enabled */
*val = bload ? 1 : 0;
return 0;
}
static int sys_cfc_write(void *data , u64 val)
{
struct gk20a *g = (struct gk20a *)data;
int status;
/* val = 1 implies load or enable the CLFC */
bool bload = val ? true : false;
nvgpu_clk_arb_pstate_change_lock(g, true);
status = nvgpu_clk_pmu_freq_controller_load(g, bload,
CTRL_CLK_CLK_FREQ_CONTROLLER_ID_SYS);
nvgpu_clk_arb_pstate_change_lock(g, false);
return status;
}
DEFINE_SIMPLE_ATTRIBUTE(sys_cfc_fops, sys_cfc_read, sys_cfc_write, "%llu\n");
static int ltc_cfc_read(void *data , u64 *val)
{
struct gk20a *g = (struct gk20a *)data;
bool bload = nvgpu_boardobjgrpmask_bit_get(
&g->pmu->clk_pmu->clk_freq_controllers->
freq_ctrl_load_mask.super,
CTRL_CLK_CLK_FREQ_CONTROLLER_ID_LTC);
/* val = 1 implies CLFC is loaded or enabled */
*val = bload ? 1 : 0;
return 0;
}
static int ltc_cfc_write(void *data , u64 val)
{
struct gk20a *g = (struct gk20a *)data;
int status;
/* val = 1 implies load or enable the CLFC */
bool bload = val ? true : false;
nvgpu_clk_arb_pstate_change_lock(g, true);
status = nvgpu_clk_pmu_freq_controller_load(g, bload,
CTRL_CLK_CLK_FREQ_CONTROLLER_ID_LTC);
nvgpu_clk_arb_pstate_change_lock(g, false);
return status;
}
DEFINE_SIMPLE_ATTRIBUTE(ltc_cfc_fops, ltc_cfc_read, ltc_cfc_write, "%llu\n");
static int xbar_cfc_read(void *data , u64 *val)
{
struct gk20a *g = (struct gk20a *)data;
bool bload = nvgpu_boardobjgrpmask_bit_get(
&g->pmu->clk_pmu->clk_freq_controllers->
freq_ctrl_load_mask.super,
CTRL_CLK_CLK_FREQ_CONTROLLER_ID_XBAR);
/* val = 1 implies CLFC is loaded or enabled */
*val = bload ? 1 : 0;
return 0;
}
static int xbar_cfc_write(void *data , u64 val)
{
struct gk20a *g = (struct gk20a *)data;
int status;
/* val = 1 implies load or enable the CLFC */
bool bload = val ? true : false;
nvgpu_clk_arb_pstate_change_lock(g, true);
status = nvgpu_clk_pmu_freq_controller_load(g, bload,
CTRL_CLK_CLK_FREQ_CONTROLLER_ID_XBAR);
nvgpu_clk_arb_pstate_change_lock(g, false);
return status;
}
DEFINE_SIMPLE_ATTRIBUTE(xbar_cfc_fops, xbar_cfc_read,
xbar_cfc_write, "%llu\n");
static int gpc_cfc_read(void *data , u64 *val)
{
struct gk20a *g = (struct gk20a *)data;
bool bload = nvgpu_boardobjgrpmask_bit_get(
&g->pmu->clk_pmu->clk_freq_controllers->
freq_ctrl_load_mask.super,
CTRL_CLK_CLK_FREQ_CONTROLLER_ID_GPC0);
/* val = 1 implies CLFC is loaded or enabled */
*val = bload ? 1 : 0;
return 0;
}
static int gpc_cfc_write(void *data , u64 val)
{
struct gk20a *g = (struct gk20a *)data;
int status;
/* val = 1 implies load or enable the CLFC */
bool bload = val ? true : false;
nvgpu_clk_arb_pstate_change_lock(g, true);
status = nvgpu_clk_pmu_freq_controller_load(g, bload,
CTRL_CLK_CLK_FREQ_CONTROLLER_ID_GPC0);
nvgpu_clk_arb_pstate_change_lock(g, false);
return status;
}
DEFINE_SIMPLE_ATTRIBUTE(gpc_cfc_fops, gpc_cfc_read, gpc_cfc_write, "%llu\n");
static int vftable_show(struct seq_file *s, void *unused)
{
struct gk20a *g = s->private;
int status;
u8 index;
u32 voltage_min_uv, voltage_step_size_uv;
u32 gpcclk_clkmhz = 0, gpcclk_voltuv = 0;
voltage_min_uv = g->pmu->clk_pmu->avfs_fllobjs->lut_min_voltage_uv;
voltage_step_size_uv = g->pmu->clk_pmu->avfs_fllobjs->lut_step_size_uv;
for (index = 0; index < CTRL_CLK_LUT_NUM_ENTRIES_GV10x; index++) {
gpcclk_voltuv = voltage_min_uv + index * voltage_step_size_uv;
status = nvgpu_clk_domain_volt_to_freq(g, 0, &gpcclk_clkmhz,
&gpcclk_voltuv, CTRL_VOLT_DOMAIN_LOGIC);
if (status != 0) {
nvgpu_err(g, "Failed to get freq for requested volt");
return status;
}
seq_printf(s, "Voltage: %duV Frequency: %dMHz\n",
gpcclk_voltuv, gpcclk_clkmhz);
}
return 0;
}
static int vftable_open(struct inode *inode, struct file *file)
{
return single_open(file, vftable_show, inode->i_private);
}
static const struct file_operations vftable_fops = {
.open = vftable_open,
.read = seq_read,
.llseek = seq_lseek,
.release = single_release,
};
int tu104_clk_init_debugfs(struct gk20a *g)
{
struct nvgpu_os_linux *l = nvgpu_os_linux_from_gk20a(g);
struct dentry *gpu_root = l->debugfs;
struct dentry *clocks_root, *clk_freq_ctlr_root;
struct dentry *d;
unsigned int i;
if (NULL == (clocks_root = debugfs_create_dir("clocks", gpu_root)))
return -ENOMEM;
clk_freq_ctlr_root = debugfs_create_dir("clk_freq_ctlr", gpu_root);
if (clk_freq_ctlr_root == NULL)
return -ENOMEM;
d = debugfs_create_file("sys", S_IRUGO | S_IWUSR, clk_freq_ctlr_root,
g, &sys_cfc_fops);
d = debugfs_create_file("ltc", S_IRUGO | S_IWUSR, clk_freq_ctlr_root,
g, &ltc_cfc_fops);
d = debugfs_create_file("xbar", S_IRUGO | S_IWUSR, clk_freq_ctlr_root,
g, &xbar_cfc_fops);
d = debugfs_create_file("gpc", S_IRUGO | S_IWUSR, clk_freq_ctlr_root,
g, &gpc_cfc_fops);
nvgpu_log(g, gpu_dbg_info, "g=%p", g);
for (i = 0; i < g->clk.namemap_num; i++) {
if (g->clk.clk_namemap[i].is_enable) {
d = debugfs_create_file(
g->clk.clk_namemap[i].name,
S_IRUGO,
clocks_root,
&g->clk.clk_namemap[i],
&get_rate_fops);
if (!d)
goto err_out;
}
}
d = debugfs_create_file("vftable", S_IRUGO,
clocks_root, g, &vftable_fops);
if (!d)
goto err_out;
return 0;
err_out:
pr_err("%s: Failed to make debugfs node\n", __func__);
debugfs_remove_recursive(clocks_root);
return -ENOMEM;
}