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gpu: nvgpu: Initialize clk counters for dGPU clocks

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Initialize the clock counters for GPCCLK, XBARCLK, SYSCLK.
This INIT was done in PMU before, but now disabled from TU10A profile.
Hence the initialization is moved into nvgpu.

This patch does the following.
1. Move clock files from GV100 to TU104.
2. Add the Counter HW Registers.
3. Initialize the counter registers for gpc, xbar and sysclk.
4. Change the debug fs node from gv100 to tu104.
5. Update in yaml file with new file names.

Bug 200536091

Change-Id: I436019a18f5c4c73979977666d0c04ce4c569047
Signed-off-by: Abdul Salam <absalam@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2155298
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: Mahantesh Kumbar <mkumbar@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Abdul Salam
2019-07-25 11:53:01 +05:30
committed by mobile promotions
parent 1551e7ea3d
commit e58e00b0fb
12 changed files with 179 additions and 51 deletions
Download Patch File Download Diff File Expand all files Collapse all files

4
arch/nvgpu-hal-new.yaml
View File

@@ -116,8 +116,8 @@ clk:
sources: [ hal/clk/clk_gk20a.h, sources: [ hal/clk/clk_gk20a.h,
hal/clk/clk_gm20b.c, hal/clk/clk_gm20b.c,
hal/clk/clk_gm20b.h, hal/clk/clk_gm20b.h,
hal/clk/clk_gv100.c, hal/clk/clk_tu104.c,
hal/clk/clk_gv100.h ] hal/clk/clk_tu104.h ]
fifo: fifo:

4
arch/nvgpu-linux.yaml
View File

@@ -55,8 +55,8 @@ debug:
os/linux/debug_ce.h, os/linux/debug_ce.h,
os/linux/debug_clk_gm20b.c, os/linux/debug_clk_gm20b.c,
os/linux/debug_clk_gm20b.h, os/linux/debug_clk_gm20b.h,
os/linux/debug_clk_gv100.c, os/linux/debug_clk_tu104.c,
os/linux/debug_clk_gv100.h, os/linux/debug_clk_tu104.h,
os/linux/debug_fecs_trace.c, os/linux/debug_fecs_trace.c,
os/linux/debug_fecs_trace.h, os/linux/debug_fecs_trace.h,
os/linux/debug_fifo.c, os/linux/debug_fifo.c,

4
drivers/gpu/nvgpu/Makefile
View File

@@ -191,7 +191,7 @@ nvgpu-y += \
hal/class/class_gm20b.o \ hal/class/class_gm20b.o \
hal/class/class_tu104.o \ hal/class/class_tu104.o \
hal/clk/clk_gm20b.o \ hal/clk/clk_gm20b.o \
hal/clk/clk_gv100.o \ hal/clk/clk_tu104.o \
hal/gr/ecc/ecc_gp10b.o \ hal/gr/ecc/ecc_gp10b.o \
hal/gr/ecc/ecc_tu104.o \ hal/gr/ecc/ecc_tu104.o \
hal/gr/zcull/zcull_gm20b.o \ hal/gr/zcull/zcull_gm20b.o \
@@ -381,7 +381,7 @@ nvgpu-$(CONFIG_DEBUG_FS) += \
os/linux/debug_bios.o \ os/linux/debug_bios.o \
os/linux/debug_ltc.o \ os/linux/debug_ltc.o \
os/linux/debug_xve.o \ os/linux/debug_xve.o \
os/linux/debug_clk_gv100.o \ os/linux/debug_clk_tu104.o \
os/linux/debug_volt.o \ os/linux/debug_volt.o \
os/linux/debug_s_param.o os/linux/debug_s_param.o

2
drivers/gpu/nvgpu/Makefile.sources
View File

@@ -582,7 +582,7 @@ srcs += common/sec2/sec2.c \
hal/bus/bus_tu104.c \ hal/bus/bus_tu104.c \
hal/ce/ce_tu104.c \ hal/ce/ce_tu104.c \
hal/class/class_tu104.c \ hal/class/class_tu104.c \
hal/clk/clk_gv100.c \ hal/clk/clk_tu104.c \
hal/gr/ecc/ecc_tu104.c \ hal/gr/ecc/ecc_tu104.c \
hal/gr/init/gr_init_gv100.c \ hal/gr/init/gr_init_gv100.c \
hal/gr/init/gr_init_tu104.c \ hal/gr/init/gr_init_tu104.c \

118
drivers/gpu/nvgpu/hal/clk/clk_gv100.c → drivers/gpu/nvgpu/hal/clk/clk_tu104.c
View File

@@ -1,5 +1,5 @@
/* /*
* GV100 Clocks * TU104 Clocks
* *
* Copyright (c) 2016-2019, NVIDIA CORPORATION. All rights reserved. * Copyright (c) 2016-2019, NVIDIA CORPORATION. All rights reserved.
* *
@@ -37,9 +37,9 @@
#include <nvgpu/clk_arb.h> #include <nvgpu/clk_arb.h>
#include <nvgpu/pmu/clk/clk.h> #include <nvgpu/pmu/clk/clk.h>
#include <nvgpu/pmu/clk/clk_domain.h> #include <nvgpu/pmu/clk/clk_domain.h>
#include <nvgpu/hw/gv100/hw_trim_gv100.h> #include <nvgpu/hw/tu104/hw_trim_tu104.h>
#include "clk_gv100.h" #include "clk_tu104.h"
@@ -58,12 +58,12 @@
#define XTAL4X_KHZ 108000 #define XTAL4X_KHZ 108000
#define BOOT_GPCCLK_MHZ 645U #define BOOT_GPCCLK_MHZ 645U
u32 gv100_crystal_clk_hz(struct gk20a *g) u32 tu104_crystal_clk_hz(struct gk20a *g)
{ {
return (XTAL4X_KHZ * 1000); return (XTAL4X_KHZ * 1000);
} }
unsigned long gv100_clk_measure_freq(struct gk20a *g, u32 api_domain) unsigned long tu104_clk_measure_freq(struct gk20a *g, u32 api_domain)
{ {
struct clk_gk20a *clk = &g->clk; struct clk_gk20a *clk = &g->clk;
u32 freq_khz; u32 freq_khz;
@@ -81,7 +81,7 @@ unsigned long gv100_clk_measure_freq(struct gk20a *g, u32 api_domain)
return 0; return 0;
} }
if (c->is_counter != 0U) { if (c->is_counter != 0U) {
freq_khz = c->scale * gv100_get_rate_cntr(g, c); freq_khz = c->scale * tu104_get_rate_cntr(g, c);
} else { } else {
freq_khz = 0U; freq_khz = 0U;
/* TODO: PLL read */ /* TODO: PLL read */
@@ -91,10 +91,94 @@ unsigned long gv100_clk_measure_freq(struct gk20a *g, u32 api_domain)
return (freq_khz * 1000UL); return (freq_khz * 1000UL);
} }
int gv100_init_clk_support(struct gk20a *g) static void nvgpu_gpu_gpcclk_counter_init(struct gk20a *g)
{
u32 data;
data = gk20a_readl(g, trim_gpc_bcast_fr_clk_cntr_ncgpcclk_cfg_r());
data |= trim_gpc_bcast_fr_clk_cntr_ncgpcclk_cfg_update_cycle_init_f() |
trim_gpc_bcast_fr_clk_cntr_ncgpcclk_cfg_cont_update_enabled_f() |
trim_gpc_bcast_fr_clk_cntr_ncgpcclk_cfg_start_count_disabled_f() |
trim_gpc_bcast_fr_clk_cntr_ncgpcclk_cfg_reset_asserted_f() |
trim_gpc_bcast_fr_clk_cntr_ncgpcclk_cfg_source_gpcclk_noeg_f();
gk20a_writel(g,trim_gpc_bcast_fr_clk_cntr_ncgpcclk_cfg_r(), data);
/*
* Based on the clock counter design, it takes 16 clock cycles of the
* "counted clock" for the counter to completely reset. Considering
* 27MHz as the slowest clock during boot time, delay of 16/27us (~1us)
* should be sufficient. See Bug 1953217.
*/
nvgpu_udelay(1);
data = gk20a_readl(g, trim_gpc_bcast_fr_clk_cntr_ncgpcclk_cfg_r());
data = set_field(data, trim_gpc_bcast_fr_clk_cntr_ncgpcclk_cfg_reset_m(),
trim_gpc_bcast_fr_clk_cntr_ncgpcclk_cfg_reset_deasserted_f());
gk20a_writel(g,trim_gpc_bcast_fr_clk_cntr_ncgpcclk_cfg_r(), data);
/*
* Enable clock counter.
* Note : Need to write un-reset and enable signal in different
* register writes as the source (register block) and destination
* (FR counter) are on the same clock and far away from each other,
* so the signals can not reach in the same clock cycle hence some
* delay is required between signals.
*/
data = gk20a_readl(g, trim_gpc_bcast_fr_clk_cntr_ncgpcclk_cfg_r());
data |= trim_gpc_bcast_fr_clk_cntr_ncgpcclk_cfg_start_count_enabled_f();
gk20a_writel(g,trim_gpc_bcast_fr_clk_cntr_ncgpcclk_cfg_r(), data);
}
static void nvgpu_gpu_sysclk_counter_init(struct gk20a *g)
{
u32 data;
data = gk20a_readl(g, trim_sys_fr_clk_cntr_sysclk_cfg_r());
data |= trim_sys_fr_clk_cntr_sysclk_cfg_update_cycle_init_f() |
trim_sys_fr_clk_cntr_sysclk_cfg_cont_update_enabled_f() |
trim_sys_fr_clk_cntr_sysclk_cfg_start_count_disabled_f() |
trim_sys_fr_clk_cntr_sysclk_cfg_reset_asserted_f() |
trim_sys_fr_clk_cntr_sysclk_cfg_source_sys_noeg_f();
gk20a_writel(g,trim_sys_fr_clk_cntr_sysclk_cfg_r(), data);
nvgpu_udelay(1);
data = gk20a_readl(g, trim_sys_fr_clk_cntr_sysclk_cfg_r());
data = set_field(data, trim_sys_fr_clk_cntr_sysclk_cfg_reset_m(),
trim_sys_fr_clk_cntr_sysclk_cfg_reset_deasserted_f());
gk20a_writel(g,trim_sys_fr_clk_cntr_sysclk_cfg_r(), data);
data = gk20a_readl(g, trim_sys_fr_clk_cntr_sysclk_cfg_r());
data |= trim_sys_fr_clk_cntr_sysclk_cfg_start_count_enabled_f();
gk20a_writel(g,trim_sys_fr_clk_cntr_sysclk_cfg_r(), data);
}
static void nvgpu_gpu_xbarclk_counter_init(struct gk20a *g)
{
u32 data;
data = gk20a_readl(g, trim_sys_fll_fr_clk_cntr_xbarclk_cfg_r());
data |= trim_sys_fll_fr_clk_cntr_xbarclk_cfg_update_cycle_init_f() |
trim_sys_fll_fr_clk_cntr_xbarclk_cfg_cont_update_enabled_f() |
trim_sys_fll_fr_clk_cntr_xbarclk_cfg_start_count_disabled_f() |
trim_sys_fll_fr_clk_cntr_xbarclk_cfg_reset_asserted_f() |
trim_sys_fll_fr_clk_cntr_xbarclk_cfg_source_xbar_nobg_f();
gk20a_writel(g,trim_sys_fll_fr_clk_cntr_xbarclk_cfg_r(), data);
nvgpu_udelay(1);
data = gk20a_readl(g, trim_sys_fll_fr_clk_cntr_xbarclk_cfg_r());
data = set_field(data, trim_sys_fll_fr_clk_cntr_xbarclk_cfg_reset_m(),
trim_sys_fll_fr_clk_cntr_xbarclk_cfg_reset_deasserted_f());
gk20a_writel(g,trim_sys_fll_fr_clk_cntr_xbarclk_cfg_r(), data);
data = gk20a_readl(g, trim_sys_fll_fr_clk_cntr_xbarclk_cfg_r());
data |= trim_sys_fll_fr_clk_cntr_xbarclk_cfg_start_count_enabled_f();
gk20a_writel(g,trim_sys_fll_fr_clk_cntr_xbarclk_cfg_r(), data);
}
int tu104_init_clk_support(struct gk20a *g)
{ {
struct clk_gk20a *clk = &g->clk; struct clk_gk20a *clk = &g->clk;
nvgpu_log_fn(g, " "); nvgpu_log_fn(g, " ");
nvgpu_mutex_init(&clk->clk_mutex); nvgpu_mutex_init(&clk->clk_mutex);
@@ -122,13 +206,15 @@ int gv100_init_clk_support(struct gk20a *g)
.g = g, .g = g,
.cntr = { .cntr = {
.reg_ctrl_addr = trim_gpc_bcast_fr_clk_cntr_ncgpcclk_cfg_r(), .reg_ctrl_addr = trim_gpc_bcast_fr_clk_cntr_ncgpcclk_cfg_r(),
.reg_ctrl_idx = trim_gpc_bcast_fr_clk_cntr_ncgpcclk_cfg_source_gpcclk_f(), .reg_ctrl_idx = trim_gpc_bcast_fr_clk_cntr_ncgpcclk_cfg_source_gpcclk_noeg_f(),
.reg_cntr_addr[0] = trim_gpc_bcast_fr_clk_cntr_ncgpcclk_cnt0_r(), .reg_cntr_addr[0] = trim_gpc_bcast_fr_clk_cntr_ncgpcclk_cnt0_r(),
.reg_cntr_addr[1] = trim_gpc_bcast_fr_clk_cntr_ncgpcclk_cnt1_r() .reg_cntr_addr[1] = trim_gpc_bcast_fr_clk_cntr_ncgpcclk_cnt1_r()
}, },
.name = "gpcclk", .name = "gpcclk",
.scale = 1 .scale = 1
}; };
nvgpu_gpu_gpcclk_counter_init(g);
clk->namemap_xlat_table[0] = CTRL_CLK_DOMAIN_GPCCLK; clk->namemap_xlat_table[0] = CTRL_CLK_DOMAIN_GPCCLK;
clk->clk_namemap[1] = (struct namemap_cfg) { clk->clk_namemap[1] = (struct namemap_cfg) {
@@ -138,13 +224,15 @@ int gv100_init_clk_support(struct gk20a *g)
.g = g, .g = g,
.cntr = { .cntr = {
.reg_ctrl_addr = trim_sys_fr_clk_cntr_sysclk_cfg_r(), .reg_ctrl_addr = trim_sys_fr_clk_cntr_sysclk_cfg_r(),
.reg_ctrl_idx = trim_sys_fr_clk_cntr_sysclk_cfg_source_sysclk_f(), .reg_ctrl_idx = trim_sys_fr_clk_cntr_sysclk_cfg_source_sys_noeg_f(),
.reg_cntr_addr[0] = trim_sys_fr_clk_cntr_sysclk_cntr0_r(), .reg_cntr_addr[0] = trim_sys_fr_clk_cntr_sysclk_cntr0_r(),
.reg_cntr_addr[1] = trim_sys_fr_clk_cntr_sysclk_cntr1_r() .reg_cntr_addr[1] = trim_sys_fr_clk_cntr_sysclk_cntr1_r()
}, },
.name = "sysclk", .name = "sysclk",
.scale = 1 .scale = 1
}; };
nvgpu_gpu_sysclk_counter_init(g);
clk->namemap_xlat_table[1] = CTRL_CLK_DOMAIN_SYSCLK; clk->namemap_xlat_table[1] = CTRL_CLK_DOMAIN_SYSCLK;
clk->clk_namemap[2] = (struct namemap_cfg) { clk->clk_namemap[2] = (struct namemap_cfg) {
@@ -154,13 +242,15 @@ int gv100_init_clk_support(struct gk20a *g)
.g = g, .g = g,
.cntr = { .cntr = {
.reg_ctrl_addr = trim_sys_fll_fr_clk_cntr_xbarclk_cfg_r(), .reg_ctrl_addr = trim_sys_fll_fr_clk_cntr_xbarclk_cfg_r(),
.reg_ctrl_idx = trim_sys_fll_fr_clk_cntr_xbarclk_cfg_source_xbarclk_f(), .reg_ctrl_idx = trim_sys_fll_fr_clk_cntr_xbarclk_cfg_source_xbar_nobg_f(),
.reg_cntr_addr[0] = trim_sys_fll_fr_clk_cntr_xbarclk_cntr0_r(), .reg_cntr_addr[0] = trim_sys_fll_fr_clk_cntr_xbarclk_cntr0_r(),
.reg_cntr_addr[1] = trim_sys_fll_fr_clk_cntr_xbarclk_cntr1_r() .reg_cntr_addr[1] = trim_sys_fll_fr_clk_cntr_xbarclk_cntr1_r()
}, },
.name = "xbarclk", .name = "xbarclk",
.scale = 1 .scale = 1
}; };
nvgpu_gpu_xbarclk_counter_init(g);
clk->namemap_xlat_table[2] = CTRL_CLK_DOMAIN_XBARCLK; clk->namemap_xlat_table[2] = CTRL_CLK_DOMAIN_XBARCLK;
clk->namemap_num = NUM_NAMEMAPS; clk->namemap_num = NUM_NAMEMAPS;
@@ -170,7 +260,7 @@ int gv100_init_clk_support(struct gk20a *g)
return 0; return 0;
} }
u32 gv100_get_rate_cntr(struct gk20a *g, struct namemap_cfg *c) { u32 tu104_get_rate_cntr(struct gk20a *g, struct namemap_cfg *c) {
u32 cntr = 0; u32 cntr = 0;
u64 cntr_start = 0; u64 cntr_start = 0;
u64 cntr_stop = 0; u64 cntr_stop = 0;
@@ -224,7 +314,7 @@ u32 gv100_get_rate_cntr(struct gk20a *g, struct namemap_cfg *c) {
return -EBUSY; return -EBUSY;
} }
int gv100_clk_domain_get_f_points( int tu104_clk_domain_get_f_points(
struct gk20a *g, struct gk20a *g,
u32 clkapidomain, u32 clkapidomain,
u32 *pfpointscount, u32 *pfpointscount,
@@ -253,12 +343,12 @@ int gv100_clk_domain_get_f_points(
} }
return status; return status;
} }
void gv100_suspend_clk_support(struct gk20a *g) void tu104_suspend_clk_support(struct gk20a *g)
{ {
nvgpu_mutex_destroy(&g->clk.clk_mutex); nvgpu_mutex_destroy(&g->clk.clk_mutex);
} }
unsigned long gv100_clk_maxrate(struct gk20a *g, u32 api_domain) unsigned long tu104_clk_maxrate(struct gk20a *g, u32 api_domain)
{ {
u16 min_mhz = 0, max_mhz = 0; u16 min_mhz = 0, max_mhz = 0;
int status; int status;

20
drivers/gpu/nvgpu/hal/clk/clk_gv100.h → drivers/gpu/nvgpu/hal/clk/clk_tu104.h
View File

@@ -19,21 +19,21 @@
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE. * DEALINGS IN THE SOFTWARE.
*/ */
#ifndef CLK_GV100_H #ifndef CLK_TU104_H
#define CLK_GV100_H #define CLK_TU104_H
#include <nvgpu/lock.h> #include <nvgpu/lock.h>
#include <nvgpu/gk20a.h> #include <nvgpu/gk20a.h>
u32 gv100_get_rate_cntr(struct gk20a *g, struct namemap_cfg *c); u32 tu104_get_rate_cntr(struct gk20a *g, struct namemap_cfg *c);
int gv100_init_clk_support(struct gk20a *g); int tu104_init_clk_support(struct gk20a *g);
u32 gv100_crystal_clk_hz(struct gk20a *g); u32 tu104_crystal_clk_hz(struct gk20a *g);
unsigned long gv100_clk_measure_freq(struct gk20a *g, u32 api_domain); unsigned long tu104_clk_measure_freq(struct gk20a *g, u32 api_domain);
void gv100_suspend_clk_support(struct gk20a *g); void tu104_suspend_clk_support(struct gk20a *g);
int gv100_clk_domain_get_f_points( int tu104_clk_domain_get_f_points(
struct gk20a *g, struct gk20a *g,
u32 clkapidomain, u32 clkapidomain,
u32 *pfpointscount, u32 *pfpointscount,
u16 *pfreqpointsinmhz); u16 *pfreqpointsinmhz);
unsigned long gv100_clk_maxrate(struct gk20a *g, u32 api_domain); unsigned long tu104_clk_maxrate(struct gk20a *g, u32 api_domain);
#endif /* CLK_GV100_H */ #endif /* CLK_TU104_H */

16
drivers/gpu/nvgpu/hal/init/hal_tu104.c
View File

@@ -176,7 +176,7 @@
#include "hal/fifo/channel_gv100.h" #include "hal/fifo/channel_gv100.h"
#include "common/clk_arb/clk_arb_gv100.h" #include "common/clk_arb/clk_arb_gv100.h"
#include "hal/clk/clk_gv100.h" #include "hal/clk/clk_tu104.h"
#include "hal/fbpa/fbpa_tu104.h" #include "hal/fbpa/fbpa_tu104.h"
#include "hal_tu104.h" #include "hal_tu104.h"
@@ -1153,14 +1153,14 @@ static const struct gpu_ops tu104_ops = {
gm20b_clear_pmu_bar0_host_err_status, gm20b_clear_pmu_bar0_host_err_status,
}, },
.clk = { .clk = {
.init_clk_support = gv100_init_clk_support, .init_clk_support = tu104_init_clk_support,
.get_crystal_clk_hz = gv100_crystal_clk_hz, .get_crystal_clk_hz = tu104_crystal_clk_hz,
.get_rate_cntr = gv100_get_rate_cntr, .get_rate_cntr = tu104_get_rate_cntr,
.measure_freq = gv100_clk_measure_freq, .measure_freq = tu104_clk_measure_freq,
.suspend_clk_support = gv100_suspend_clk_support, .suspend_clk_support = tu104_suspend_clk_support,
.perf_pmu_vfe_load = nvgpu_perf_pmu_vfe_load_ps35, .perf_pmu_vfe_load = nvgpu_perf_pmu_vfe_load_ps35,
.clk_domain_get_f_points = gv100_clk_domain_get_f_points, .clk_domain_get_f_points = tu104_clk_domain_get_f_points,
.get_maxrate = gv100_clk_maxrate, .get_maxrate = tu104_clk_maxrate,
}, },
#ifdef CONFIG_NVGPU_CLK_ARB #ifdef CONFIG_NVGPU_CLK_ARB
.clk_arb = { .clk_arb = {

38
drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_trim_tu104.h
View File

@@ -99,4 +99,42 @@
#define trim_sys_nvl_common_clk_alt_switch_finalsel_miscclk_f() (0x2U) #define trim_sys_nvl_common_clk_alt_switch_finalsel_miscclk_f() (0x2U)
#define trim_sys_nvl_common_clk_alt_switch_finalsel_onesrcclk_v() (0x00000003U) #define trim_sys_nvl_common_clk_alt_switch_finalsel_onesrcclk_v() (0x00000003U)
#define trim_sys_nvl_common_clk_alt_switch_finalsel_onesrcclk_f() (0x3U) #define trim_sys_nvl_common_clk_alt_switch_finalsel_onesrcclk_f() (0x3U)
#define trim_gpc_bcast_fr_clk_cntr_ncgpcclk_cfg_r() (0x00132a70U)
#define trim_gpc_bcast_fr_clk_cntr_ncgpcclk_cfg_update_cycle_init_f() (0x0U)
#define trim_gpc_bcast_fr_clk_cntr_ncgpcclk_cfg_cont_update_enabled_f()\
(0x8000000U)
#define trim_gpc_bcast_fr_clk_cntr_ncgpcclk_cfg_start_count_disabled_f() (0x0U)
#define trim_gpc_bcast_fr_clk_cntr_ncgpcclk_cfg_start_count_enabled_f()\
(0x2000000U)
#define trim_gpc_bcast_fr_clk_cntr_ncgpcclk_cfg_reset_m() (U32(0x1U) << 24U)
#define trim_gpc_bcast_fr_clk_cntr_ncgpcclk_cfg_reset_asserted_f() (0x1000000U)
#define trim_gpc_bcast_fr_clk_cntr_ncgpcclk_cfg_reset_deasserted_f() (0x0U)
#define trim_gpc_bcast_fr_clk_cntr_ncgpcclk_cfg_source_gpcclk_noeg_f()\
(0x20000000U)
#define trim_gpc_bcast_fr_clk_cntr_ncgpcclk_cnt0_r() (0x00132a74U)
#define trim_gpc_bcast_fr_clk_cntr_ncgpcclk_cnt1_r() (0x00132a78U)
#define trim_sys_fll_fr_clk_cntr_xbarclk_cfg_r() (0x00136470U)
#define trim_sys_fll_fr_clk_cntr_xbarclk_cfg_update_cycle_init_f() (0x0U)
#define trim_sys_fll_fr_clk_cntr_xbarclk_cfg_cont_update_enabled_f()\
(0x8000000U)
#define trim_sys_fll_fr_clk_cntr_xbarclk_cfg_start_count_disabled_f() (0x0U)
#define trim_sys_fll_fr_clk_cntr_xbarclk_cfg_start_count_enabled_f()\
(0x2000000U)
#define trim_sys_fll_fr_clk_cntr_xbarclk_cfg_reset_m() (U32(0x1U) << 24U)
#define trim_sys_fll_fr_clk_cntr_xbarclk_cfg_reset_asserted_f() (0x1000000U)
#define trim_sys_fll_fr_clk_cntr_xbarclk_cfg_reset_deasserted_f() (0x0U)
#define trim_sys_fll_fr_clk_cntr_xbarclk_cfg_source_xbar_nobg_f() (0x0U)
#define trim_sys_fll_fr_clk_cntr_xbarclk_cntr0_r() (0x00136474U)
#define trim_sys_fll_fr_clk_cntr_xbarclk_cntr1_r() (0x00136478U)
#define trim_sys_fr_clk_cntr_sysclk_cfg_r() (0x0013762cU)
#define trim_sys_fr_clk_cntr_sysclk_cfg_update_cycle_init_f() (0x0U)
#define trim_sys_fr_clk_cntr_sysclk_cfg_cont_update_enabled_f() (0x8000000U)
#define trim_sys_fr_clk_cntr_sysclk_cfg_start_count_disabled_f() (0x0U)
#define trim_sys_fr_clk_cntr_sysclk_cfg_start_count_enabled_f() (0x2000000U)
#define trim_sys_fr_clk_cntr_sysclk_cfg_reset_m() (U32(0x1U) << 24U)
#define trim_sys_fr_clk_cntr_sysclk_cfg_reset_asserted_f() (0x1000000U)
#define trim_sys_fr_clk_cntr_sysclk_cfg_reset_deasserted_f() (0x0U)
#define trim_sys_fr_clk_cntr_sysclk_cfg_source_sys_noeg_f() (0x0U)
#define trim_sys_fr_clk_cntr_sysclk_cntr0_r() (0x00137630U)
#define trim_sys_fr_clk_cntr_sysclk_cntr1_r() (0x00137634U)
#endif #endif

8
drivers/gpu/nvgpu/os/linux/debug_clk_gv100.c → drivers/gpu/nvgpu/os/linux/debug_clk_tu104.c
View File

@@ -28,12 +28,12 @@
#include <nvgpu/pmu/clk/clk_fll.h> #include <nvgpu/pmu/clk/clk_fll.h>
#include <nvgpu/pmu/clk/clk.h> #include <nvgpu/pmu/clk/clk.h>
#include "hal/clk/clk_gv100.h" #include "hal/clk/clk_tu104.h"
#include "common/pmu/clk/clk_freq_controller.h" #include "common/pmu/clk/clk_freq_controller.h"
void nvgpu_clk_arb_pstate_change_lock(struct gk20a *g, bool lock); void nvgpu_clk_arb_pstate_change_lock(struct gk20a *g, bool lock);
static int gv100_get_rate_show(void *data , u64 *val) static int tu104_get_rate_show(void *data , u64 *val)
{ {
struct namemap_cfg *c = (struct namemap_cfg *)data; struct namemap_cfg *c = (struct namemap_cfg *)data;
struct gk20a *g = c->g; struct gk20a *g = c->g;
@@ -46,7 +46,7 @@ static int gv100_get_rate_show(void *data , u64 *val)
return 0; return 0;
} }
DEFINE_SIMPLE_ATTRIBUTE(get_rate_fops, gv100_get_rate_show, NULL, "%llu\n"); DEFINE_SIMPLE_ATTRIBUTE(get_rate_fops, tu104_get_rate_show, NULL, "%llu\n");
static int sys_cfc_read(void *data , u64 *val) static int sys_cfc_read(void *data , u64 *val)
{ {
@@ -203,7 +203,7 @@ static const struct file_operations vftable_fops = {
.release = single_release, .release = single_release,
}; };
int gv100_clk_init_debugfs(struct gk20a *g) int tu104_clk_init_debugfs(struct gk20a *g)
{ {
struct nvgpu_os_linux *l = nvgpu_os_linux_from_gk20a(g); struct nvgpu_os_linux *l = nvgpu_os_linux_from_gk20a(g);
struct dentry *gpu_root = l->debugfs; struct dentry *gpu_root = l->debugfs;

8
drivers/gpu/nvgpu/os/linux/debug_clk_gv100.h → drivers/gpu/nvgpu/os/linux/debug_clk_tu104.h
View File

@@ -14,13 +14,13 @@
* along with this program. If not, see <http://www.gnu.org/licenses/>. * along with this program. If not, see <http://www.gnu.org/licenses/>.
*/ */
#ifndef __DEBUG_CLK_GV100_H #ifndef __DEBUG_CLK_TU104_H
#define __DEBUG_CLK_GV100_H #define __DEBUG_CLK_TU104_H
#ifdef CONFIG_DEBUG_FS #ifdef CONFIG_DEBUG_FS
int gv100_clk_init_debugfs(struct gk20a *g); int tu104_clk_init_debugfs(struct gk20a *g);
#else #else
static inline int gv100_clk_init_debugfs(struct gk20a *g) static inline int tu104_clk_init_debugfs(struct gk20a *g)
{ {
return 0; return 0;
} }

4
drivers/gpu/nvgpu/os/linux/os_ops_gv100.c
View File

@@ -16,13 +16,13 @@
#include "os_linux.h" #include "os_linux.h"
#include "debug_clk_gv100.h" #include "debug_clk_tu104.h"
#include "debug_therm_tu104.h" #include "debug_therm_tu104.h"
#include "debug_fecs_trace.h" #include "debug_fecs_trace.h"
static struct nvgpu_os_linux_ops gv100_os_linux_ops = { static struct nvgpu_os_linux_ops gv100_os_linux_ops = {
.clk = { .clk = {
.init_debugfs = gv100_clk_init_debugfs, .init_debugfs = tu104_clk_init_debugfs,
}, },
.therm = { .therm = {
.init_debugfs = tu104_therm_init_debugfs, .init_debugfs = tu104_therm_init_debugfs,

4
drivers/gpu/nvgpu/os/linux/os_ops_tu104.c
View File

@@ -17,7 +17,7 @@
#include "os/linux/os_linux.h" #include "os/linux/os_linux.h"
#include "os/linux/debug_therm_tu104.h" #include "os/linux/debug_therm_tu104.h"
#include "os/linux/debug_clk_gv100.h" #include "os/linux/debug_clk_tu104.h"
#include "os/linux/debug_volt.h" #include "os/linux/debug_volt.h"
#include "os/linux/debug_s_param.h" #include "os/linux/debug_s_param.h"
@@ -26,7 +26,7 @@ static struct nvgpu_os_linux_ops tu104_os_linux_ops = {
.init_debugfs = tu104_therm_init_debugfs, .init_debugfs = tu104_therm_init_debugfs,
}, },
.clk = { .clk = {
.init_debugfs = gv100_clk_init_debugfs, .init_debugfs = tu104_clk_init_debugfs,
}, },
.volt = { .volt = {
.init_debugfs = nvgpu_volt_init_debugfs, .init_debugfs = nvgpu_volt_init_debugfs,