diff --git a/drivers/gpu/nvgpu/ctrl/ctrlpmgr.h b/drivers/gpu/nvgpu/ctrl/ctrlpmgr.h
index ba55e4a5c..514422dc6 100644
--- a/drivers/gpu/nvgpu/ctrl/ctrlpmgr.h
+++ b/drivers/gpu/nvgpu/ctrl/ctrlpmgr.h
@@ -28,6 +28,7 @@
 
 #define CTRL_PMGR_PWR_POLICY_TABLE_VERSION_3X                        0x30
 #define CTRL_PMGR_PWR_POLICY_TYPE_HW_THRESHOLD                       0x04
+#define CTRL_PMGR_PWR_POLICY_TYPE_SW_THRESHOLD                       0x0C
 
 #define CTRL_PMGR_PWR_POLICY_MAX_LIMIT_INPUTS                       0x8
 #define CTRL_PMGR_PWR_POLICY_IDX_NUM_INDEXES                         0x08
diff --git a/drivers/gpu/nvgpu/pmuif/gpmuifpmgr.h b/drivers/gpu/nvgpu/pmuif/gpmuifpmgr.h
index 613dcea6c..b985b0154 100644
--- a/drivers/gpu/nvgpu/pmuif/gpmuifpmgr.h
+++ b/drivers/gpu/nvgpu/pmuif/gpmuifpmgr.h
@@ -212,6 +212,15 @@ struct nv_pmu_pmgr_pwr_policy_hw_threshold {
 	u16 low_threshold_value;
 };
 
+struct nv_pmu_pmgr_pwr_policy_sw_threshold {
+	struct nv_pmu_pmgr_pwr_policy super;
+	u8 threshold_idx;
+	u8 low_threshold_idx;
+	bool b_use_low_threshold;
+	u16 low_threshold_value;
+	u8 event_id;
+};
+
 struct nv_pmu_pmgr_pwr_policy_pmu_compactible {
 	u8 pmu_compactible_data[68];
 };
@@ -220,6 +229,7 @@ union nv_pmu_pmgr_pwr_policy_union {
 	struct nv_pmu_boardobj board_obj;
 	struct nv_pmu_pmgr_pwr_policy pwr_policy;
 	struct nv_pmu_pmgr_pwr_policy_hw_threshold hw_threshold;
+	struct nv_pmu_pmgr_pwr_policy_sw_threshold sw_threshold;
 	struct nv_pmu_pmgr_pwr_policy_pmu_compactible pmu_pwr_policy;
 };