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synced 2025-12-22 17:36:20 +03:00
gpu: nvgpu: add internal CONFIG_SYNC wrapper
The sync file support in Linux has been stabilized and the new config is called CONFIG_SYNC_FILE. Even if maybe not so intended, both the stabilized version and the legacy CONFIG_SYNC can coexist; to begin with supporting the stabilized version, add CONFIG_NVGPU_SYNCFD_ANDROID and CONFIG_NVGPU_SYNCFD_NONE as choice configs of which one will be set. A later patch will extend this with a choice for CONFIG_SYNC_FILE. Jira NVGPU-5353 Change-Id: I67582b68d700b16c46e1cd090f1b938067a364e3 Signed-off-by: Konsta Hölttä <kholtta@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2336118 Tested-by: mobile promotions <svcmobile_promotions@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
committed by
Alex Waterman
parent
068e00749b
commit
e5b23f33b9
@@ -233,3 +233,29 @@ config NVGPU_TEGRA_FUSE
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default y
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help
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Support Tegra fuse
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choice
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prompt "Supported sync fence backend"
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default NVGPU_SYNCFD_ANDROID
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depends on GK20A
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help
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GPU job synchronization (fences before and after submits) can use raw
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syncpoints if available and sync fds if chosen. Without syncpoints,
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nvgpu also provides semaphore-backed sync fds to userspace.
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Select which kernel-provided API is used for sync fds. Matching
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support is required for the userspace drivers too.
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config NVGPU_SYNCFD_ANDROID
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bool "Android SYNC"
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depends on SYNC
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help
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Select CONFIG_SYNC, the legacy synchronization framework provided by
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Android (and deprecated in Linux 4.9+ in favor of dma fences and the
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stabilized SYNC_FILE).
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config NVGPU_SYNCFD_NONE
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bool "Nothing"
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help
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Do not build in support for sync fences.
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endchoice
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@@ -439,13 +439,13 @@ nvgpu-$(CONFIG_NVGPU_TEGRA_FUSE) += os/linux/fuse.o \
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os/linux/soc.o
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endif
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nvgpu-$(CONFIG_SYNC) += \
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nvgpu-$(CONFIG_NVGPU_SYNCFD_ANDROID) += \
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os/linux/sync_sema_android.o \
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os/linux/os_fence_android.o \
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os/linux/os_fence_android_sema.o
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ifeq ($(CONFIG_TEGRA_GK20A_NVHOST), y)
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nvgpu-$(CONFIG_SYNC) += \
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nvgpu-$(CONFIG_NVGPU_SYNCFD_ANDROID) += \
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os/linux/os_fence_android_syncpt.o
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nvgpu-y += common/sync/channel_sync_syncpt.o
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endif
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@@ -64,6 +64,9 @@ NVGPU_COMMON_CFLAGS += \
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CONFIG_NVGPU_LOGGING := 1
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NVGPU_COMMON_CFLAGS += -DCONFIG_NVGPU_LOGGING
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CONFIG_NVGPU_SYNCFD_NONE := 1
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NVGPU_COMMON_CFLAGS += -DCONFIG_NVGPU_SYNCFD_NONE
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ifeq ($(profile),$(filter $(profile),safety_debug safety_release))
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# Enable golden context verification only for safety debug/release build
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@@ -56,6 +56,7 @@ nvgpu_channel_sync_semaphore_from_base(struct nvgpu_channel_sync *base)
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offsetof(struct nvgpu_channel_sync_semaphore, base));
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}
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#ifndef CONFIG_NVGPU_SYNCFD_NONE
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static void add_sema_wait_cmd(struct gk20a *g, struct nvgpu_channel *c,
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struct nvgpu_semaphore *s, struct priv_cmd_entry *cmd)
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{
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@@ -73,6 +74,24 @@ static void add_sema_wait_cmd(struct gk20a *g, struct nvgpu_channel *c,
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va, cmd);
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}
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static void channel_sync_semaphore_gen_wait_cmd(struct nvgpu_channel *c,
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struct nvgpu_semaphore *sema, struct priv_cmd_entry *wait_cmd,
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u32 wait_cmd_size)
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{
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bool has_incremented;
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if (sema == NULL) {
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/* came from an expired sync fence */
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nvgpu_priv_cmdbuf_append_zeros(c->g, wait_cmd, wait_cmd_size);
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} else {
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has_incremented = nvgpu_semaphore_can_wait(sema);
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nvgpu_assert(has_incremented);
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add_sema_wait_cmd(c->g, c, sema, wait_cmd);
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nvgpu_semaphore_put(sema);
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}
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}
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#endif
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static void add_sema_incr_cmd(struct gk20a *g, struct nvgpu_channel *c,
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struct nvgpu_semaphore *s, struct priv_cmd_entry *cmd,
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bool wfi)
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@@ -95,27 +114,11 @@ static void add_sema_incr_cmd(struct gk20a *g, struct nvgpu_channel *c,
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va, cmd);
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}
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static void channel_sync_semaphore_gen_wait_cmd(struct nvgpu_channel *c,
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struct nvgpu_semaphore *sema, struct priv_cmd_entry *wait_cmd,
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u32 wait_cmd_size)
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{
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bool has_incremented;
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if (sema == NULL) {
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/* came from an expired sync fence */
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nvgpu_priv_cmdbuf_append_zeros(c->g, wait_cmd, wait_cmd_size);
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} else {
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has_incremented = nvgpu_semaphore_can_wait(sema);
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nvgpu_assert(has_incremented);
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add_sema_wait_cmd(c->g, c, sema, wait_cmd);
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nvgpu_semaphore_put(sema);
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}
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}
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static int channel_sync_semaphore_wait_fd(
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struct nvgpu_channel_sync *s, int fd,
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struct priv_cmd_entry **entry, u32 max_wait_cmds)
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{
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#ifndef CONFIG_NVGPU_SYNCFD_NONE
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struct nvgpu_channel_sync_semaphore *sema =
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nvgpu_channel_sync_semaphore_from_base(s);
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struct nvgpu_channel *c = sema->c;
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@@ -164,6 +167,14 @@ static int channel_sync_semaphore_wait_fd(
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cleanup:
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os_fence.ops->drop_ref(&os_fence);
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return err;
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#else
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struct nvgpu_channel_sync_semaphore *sema =
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nvgpu_channel_sync_semaphore_from_base(s);
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nvgpu_err(sema->c->g,
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"trying to use sync fds with CONFIG_NVGPU_SYNCFD_NONE");
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return -ENODEV;
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#endif
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}
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static int channel_sync_semaphore_incr_common(
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@@ -246,7 +257,7 @@ static int channel_sync_semaphore_incr_user(
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bool need_sync_fence,
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bool register_irq)
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{
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#ifdef CONFIG_SYNC
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#ifndef CONFIG_NVGPU_SYNCFD_NONE
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int err;
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err = channel_sync_semaphore_incr_common(s, wfi, entry, fence,
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@@ -259,8 +270,9 @@ static int channel_sync_semaphore_incr_user(
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#else
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struct nvgpu_channel_sync_semaphore *sema =
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nvgpu_channel_sync_semaphore_from_base(s);
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nvgpu_err(sema->c->g,
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"trying to use sync fds with CONFIG_SYNC disabled");
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"trying to use sync fds with CONFIG_NVGPU_SYNCFD_NONE");
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return -ENODEV;
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#endif
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}
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@@ -241,7 +241,7 @@ u32 nvgpu_nvhost_get_syncpt_client_managed(struct nvgpu_nvhost_dev
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*nvgpu_syncpt_dev,
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const char *syncpt_name);
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#ifdef CONFIG_SYNC
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#ifdef CONFIG_NVGPU_SYNCFD_ANDROID
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u32 nvgpu_nvhost_sync_pt_id(struct sync_pt *pt);
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u32 nvgpu_nvhost_sync_pt_thresh(struct sync_pt *pt);
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int nvgpu_nvhost_sync_num_pts(struct sync_fence *fence);
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@@ -250,7 +250,7 @@ struct sync_fence *nvgpu_nvhost_sync_fdget(int fd);
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struct sync_fence *nvgpu_nvhost_sync_create_fence(
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struct nvgpu_nvhost_dev *nvgpu_syncpt_dev,
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u32 id, u32 thresh, const char *name);
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#endif /* CONFIG_SYNC */
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#endif /* CONFIG_NVGPU_SYNCFD_ANDROID */
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#ifdef CONFIG_TEGRA_T19X_GRHOST
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@@ -1,7 +1,7 @@
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/*
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* nvgpu os fence
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*
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* Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved.
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* Copyright (c) 2018-2020, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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@@ -79,7 +79,7 @@ static inline bool nvgpu_os_fence_is_initialized(struct nvgpu_os_fence *fence)
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return (fence->ops != NULL);
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}
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#ifdef CONFIG_SYNC
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#ifndef CONFIG_NVGPU_SYNCFD_NONE
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int nvgpu_os_fence_sema_create(
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struct nvgpu_os_fence *fence_out,
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@@ -106,9 +106,9 @@ static inline int nvgpu_os_fence_fdget(
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return -ENOSYS;
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}
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#endif /* CONFIG_SYNC */
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#endif /* !CONFIG_NVGPU_SYNCFD_NONE */
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#if defined(CONFIG_TEGRA_GK20A_NVHOST) && defined(CONFIG_SYNC)
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#if defined(CONFIG_TEGRA_GK20A_NVHOST) && !defined(CONFIG_NVGPU_SYNCFD_NONE)
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int nvgpu_os_fence_syncpt_create(struct nvgpu_os_fence *fence_out,
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struct nvgpu_channel *c, struct nvgpu_nvhost_dev *nvhost_dev,
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@@ -124,6 +124,6 @@ static inline int nvgpu_os_fence_syncpt_create(
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return -ENOSYS;
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}
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#endif /* CONFIG_TEGRA_GK20A_NVHOST && CONFIG_SYNC */
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#endif /* CONFIG_TEGRA_GK20A_NVHOST && !CONFIG_NVGPU_SYNCFD_NONE */
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#endif /* NVGPU_OS_FENCE_H */
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@@ -1,7 +1,7 @@
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/*
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* nvgpu os fence semas
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*
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* Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved.
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* Copyright (c) 2018-2020, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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@@ -32,7 +32,7 @@ struct nvgpu_os_fence_sema {
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struct nvgpu_os_fence *fence;
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};
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#ifdef CONFIG_SYNC
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#if !defined(CONFIG_NVGPU_SYNCFD_NONE)
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/*
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* Return a struct of nvgpu_os_fence_sema only if the underlying os_fence
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* object is backed by semaphore, else return empty object.
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@@ -79,6 +79,6 @@ static inline u32 nvgpu_os_fence_sema_get_num_semaphores(
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return 0;
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}
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#endif
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#endif /* !CONFIG_NVGPU_SYNCFD_NONE */
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#endif /* NVGPU_OS_FENCE_SEMAS_H */
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#endif /* NVGPU_OS_FENCE_SEMAS_H */
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@@ -1,7 +1,7 @@
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/*
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* nvgpu os fence syncpts
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*
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* Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved.
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* Copyright (c) 2018-2020, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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@@ -31,7 +31,7 @@ struct nvgpu_os_fence_syncpt {
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struct nvgpu_os_fence *fence;
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};
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#if defined(CONFIG_TEGRA_GK20A_NVHOST) && defined(CONFIG_SYNC)
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#if defined(CONFIG_TEGRA_GK20A_NVHOST) && !defined(CONFIG_NVGPU_SYNCFD_NONE)
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/*
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* Return a struct of nvgpu_os_fence_syncpt only if the underlying os_fence
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* object is backed by syncpoints, else return empty object.
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@@ -80,4 +80,4 @@ static inline u32 nvgpu_os_fence_syncpt_get_num_syncpoints(
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#endif
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#endif /* NVGPU_OS_FENCE_SYNPT_H */
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#endif /* NVGPU_OS_FENCE_SYNPT_H */
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@@ -810,7 +810,7 @@ static int gk20a_ioctl_channel_submit_gpfifo(
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return -ETIMEDOUT;
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}
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#ifndef CONFIG_SYNC
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#ifdef CONFIG_NVGPU_SYNCFD_NONE
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if (flag_sync_fence) {
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return -EINVAL;
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}
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@@ -291,7 +291,7 @@ static int nvgpu_channel_alloc_linux(struct gk20a *g, struct nvgpu_channel *ch)
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ch->os_priv = priv;
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priv->ch = ch;
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#ifdef CONFIG_SYNC
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#ifndef CONFIG_NVGPU_SYNCFD_NONE
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ch->has_os_fence_framework_support = true;
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#endif
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@@ -311,7 +311,7 @@ static void nvgpu_channel_free_linux(struct gk20a *g, struct nvgpu_channel *ch)
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ch->os_priv = NULL;
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#ifdef CONFIG_SYNC
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#ifndef CONFIG_NVGPU_SYNCFD_NONE
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ch->has_os_fence_framework_support = false;
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#endif
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}
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@@ -317,7 +317,7 @@ void gk20a_init_linux_characteristics(struct gk20a *g)
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nvgpu_set_enabled(g, NVGPU_SUPPORT_DETERMINISTIC_OPTS, true);
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nvgpu_set_enabled(g, NVGPU_SUPPORT_USERSPACE_MANAGED_AS, true);
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if (IS_ENABLED(CONFIG_SYNC)) {
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if (!IS_ENABLED(CONFIG_NVGPU_SYNCFD_NONE)) {
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nvgpu_set_enabled(g, NVGPU_SUPPORT_SYNC_FENCE_FDS, true);
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}
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}
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@@ -226,7 +226,7 @@ void nvgpu_nvhost_remove_symlink(struct gk20a *g)
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}
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}
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#ifdef CONFIG_SYNC
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#ifndef CONFIG_NVGPU_SYNCFD_NONE
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u32 nvgpu_nvhost_sync_pt_id(struct sync_pt *pt)
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{
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return nvhost_sync_pt_id(pt);
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@@ -258,7 +258,7 @@ struct sync_fence *nvgpu_nvhost_sync_create_fence(
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return nvhost_sync_create_fence(nvhost_dev->host1x_pdev, &pt, 1, name);
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}
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#endif /* CONFIG_SYNC */
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#endif /* !CONFIG_NVGPU_SYNCFD_NONE */
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#ifdef CONFIG_TEGRA_T19X_GRHOST
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int nvgpu_nvhost_get_syncpt_aperture(
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@@ -1,7 +1,7 @@
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/*
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* Semaphore Sync Framework Integration
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*
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* Copyright (c) 2017-2018, NVIDIA Corporation. All rights reserved.
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* Copyright (c) 2017-2020, NVIDIA Corporation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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@@ -25,7 +25,7 @@ struct sync_pt;
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struct nvgpu_semaphore;
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struct fence;
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#ifdef CONFIG_SYNC
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#ifdef CONFIG_NVGPU_SYNCFD_ANDROID
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struct sync_timeline *gk20a_sync_timeline_create(const char *name);
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void gk20a_sync_timeline_destroy(struct sync_timeline *);
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void gk20a_sync_timeline_signal(struct sync_timeline *);
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